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cb849fc5 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
fa236a7e KD |
2 | /* |
3 | * Driver for Broadcom BRCMSTB, NSP, NS2, Cygnus SPI Controllers | |
4 | * | |
5 | * Copyright 2016 Broadcom | |
fa236a7e KD |
6 | */ |
7 | ||
8 | #include <linux/clk.h> | |
9 | #include <linux/delay.h> | |
10 | #include <linux/device.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/io.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/module.h> | |
fa236a7e KD |
17 | #include <linux/of.h> |
18 | #include <linux/of_irq.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/slab.h> | |
21 | #include <linux/spi/spi.h> | |
5f195ee7 | 22 | #include <linux/spi/spi-mem.h> |
fa236a7e KD |
23 | #include <linux/sysfs.h> |
24 | #include <linux/types.h> | |
25 | #include "spi-bcm-qspi.h" | |
26 | ||
27 | #define DRIVER_NAME "bcm_qspi" | |
28 | ||
4e3b2d23 KD |
29 | |
30 | /* BSPI register offsets */ | |
31 | #define BSPI_REVISION_ID 0x000 | |
32 | #define BSPI_SCRATCH 0x004 | |
33 | #define BSPI_MAST_N_BOOT_CTRL 0x008 | |
34 | #define BSPI_BUSY_STATUS 0x00c | |
35 | #define BSPI_INTR_STATUS 0x010 | |
36 | #define BSPI_B0_STATUS 0x014 | |
37 | #define BSPI_B0_CTRL 0x018 | |
38 | #define BSPI_B1_STATUS 0x01c | |
39 | #define BSPI_B1_CTRL 0x020 | |
40 | #define BSPI_STRAP_OVERRIDE_CTRL 0x024 | |
41 | #define BSPI_FLEX_MODE_ENABLE 0x028 | |
42 | #define BSPI_BITS_PER_CYCLE 0x02c | |
43 | #define BSPI_BITS_PER_PHASE 0x030 | |
44 | #define BSPI_CMD_AND_MODE_BYTE 0x034 | |
45 | #define BSPI_BSPI_FLASH_UPPER_ADDR_BYTE 0x038 | |
46 | #define BSPI_BSPI_XOR_VALUE 0x03c | |
47 | #define BSPI_BSPI_XOR_ENABLE 0x040 | |
48 | #define BSPI_BSPI_PIO_MODE_ENABLE 0x044 | |
49 | #define BSPI_BSPI_PIO_IODIR 0x048 | |
50 | #define BSPI_BSPI_PIO_DATA 0x04c | |
51 | ||
52 | /* RAF register offsets */ | |
53 | #define BSPI_RAF_START_ADDR 0x100 | |
54 | #define BSPI_RAF_NUM_WORDS 0x104 | |
55 | #define BSPI_RAF_CTRL 0x108 | |
56 | #define BSPI_RAF_FULLNESS 0x10c | |
57 | #define BSPI_RAF_WATERMARK 0x110 | |
58 | #define BSPI_RAF_STATUS 0x114 | |
59 | #define BSPI_RAF_READ_DATA 0x118 | |
60 | #define BSPI_RAF_WORD_CNT 0x11c | |
61 | #define BSPI_RAF_CURR_ADDR 0x120 | |
62 | ||
63 | /* Override mode masks */ | |
64 | #define BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE BIT(0) | |
65 | #define BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL BIT(1) | |
66 | #define BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE BIT(2) | |
67 | #define BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD BIT(3) | |
68 | #define BSPI_STRAP_OVERRIDE_CTRL_ENDAIN_MODE BIT(4) | |
69 | ||
70 | #define BSPI_ADDRLEN_3BYTES 3 | |
71 | #define BSPI_ADDRLEN_4BYTES 4 | |
72 | ||
73 | #define BSPI_RAF_STATUS_FIFO_EMPTY_MASK BIT(1) | |
74 | ||
75 | #define BSPI_RAF_CTRL_START_MASK BIT(0) | |
76 | #define BSPI_RAF_CTRL_CLEAR_MASK BIT(1) | |
77 | ||
78 | #define BSPI_BPP_MODE_SELECT_MASK BIT(8) | |
79 | #define BSPI_BPP_ADDR_SELECT_MASK BIT(16) | |
80 | ||
940ec770 | 81 | #define BSPI_READ_LENGTH 256 |
4e3b2d23 | 82 | |
fa236a7e KD |
83 | /* MSPI register offsets */ |
84 | #define MSPI_SPCR0_LSB 0x000 | |
85 | #define MSPI_SPCR0_MSB 0x004 | |
86 | #define MSPI_SPCR1_LSB 0x008 | |
87 | #define MSPI_SPCR1_MSB 0x00c | |
88 | #define MSPI_NEWQP 0x010 | |
89 | #define MSPI_ENDQP 0x014 | |
90 | #define MSPI_SPCR2 0x018 | |
91 | #define MSPI_MSPI_STATUS 0x020 | |
92 | #define MSPI_CPTQP 0x024 | |
93 | #define MSPI_SPCR3 0x028 | |
94 | #define MSPI_TXRAM 0x040 | |
95 | #define MSPI_RXRAM 0x0c0 | |
96 | #define MSPI_CDRAM 0x140 | |
97 | #define MSPI_WRITE_LOCK 0x180 | |
98 | ||
99 | #define MSPI_MASTER_BIT BIT(7) | |
100 | ||
101 | #define MSPI_NUM_CDRAM 16 | |
102 | #define MSPI_CDRAM_CONT_BIT BIT(7) | |
103 | #define MSPI_CDRAM_BITSE_BIT BIT(6) | |
104 | #define MSPI_CDRAM_PCS 0xf | |
105 | ||
106 | #define MSPI_SPCR2_SPE BIT(6) | |
107 | #define MSPI_SPCR2_CONT_AFTER_CMD BIT(7) | |
108 | ||
109 | #define MSPI_MSPI_STATUS_SPIF BIT(0) | |
110 | ||
111 | #define INTR_BASE_BIT_SHIFT 0x02 | |
112 | #define INTR_COUNT 0x07 | |
113 | ||
114 | #define NUM_CHIPSELECT 4 | |
115 | #define QSPI_SPBR_MIN 8U | |
116 | #define QSPI_SPBR_MAX 255U | |
117 | ||
118 | #define OPCODE_DIOR 0xBB | |
119 | #define OPCODE_QIOR 0xEB | |
120 | #define OPCODE_DIOR_4B 0xBC | |
121 | #define OPCODE_QIOR_4B 0xEC | |
122 | ||
123 | #define MAX_CMD_SIZE 6 | |
124 | ||
125 | #define ADDR_4MB_MASK GENMASK(22, 0) | |
126 | ||
127 | /* stop at end of transfer, no other reason */ | |
128 | #define TRANS_STATUS_BREAK_NONE 0 | |
129 | /* stop at end of spi_message */ | |
130 | #define TRANS_STATUS_BREAK_EOM 1 | |
131 | /* stop at end of spi_transfer if delay */ | |
132 | #define TRANS_STATUS_BREAK_DELAY 2 | |
133 | /* stop at end of spi_transfer if cs_change */ | |
134 | #define TRANS_STATUS_BREAK_CS_CHANGE 4 | |
135 | /* stop if we run out of bytes */ | |
136 | #define TRANS_STATUS_BREAK_NO_BYTES 8 | |
137 | ||
138 | /* events that make us stop filling TX slots */ | |
139 | #define TRANS_STATUS_BREAK_TX (TRANS_STATUS_BREAK_EOM | \ | |
140 | TRANS_STATUS_BREAK_DELAY | \ | |
141 | TRANS_STATUS_BREAK_CS_CHANGE) | |
142 | ||
143 | /* events that make us deassert CS */ | |
144 | #define TRANS_STATUS_BREAK_DESELECT (TRANS_STATUS_BREAK_EOM | \ | |
145 | TRANS_STATUS_BREAK_CS_CHANGE) | |
146 | ||
147 | struct bcm_qspi_parms { | |
148 | u32 speed_hz; | |
149 | u8 mode; | |
150 | u8 bits_per_word; | |
151 | }; | |
152 | ||
4e3b2d23 KD |
153 | struct bcm_xfer_mode { |
154 | bool flex_mode; | |
155 | unsigned int width; | |
156 | unsigned int addrlen; | |
157 | unsigned int hp; | |
158 | }; | |
159 | ||
fa236a7e KD |
160 | enum base_type { |
161 | MSPI, | |
4e3b2d23 | 162 | BSPI, |
fa236a7e KD |
163 | CHIP_SELECT, |
164 | BASEMAX, | |
165 | }; | |
166 | ||
cc20a386 KD |
167 | enum irq_source { |
168 | SINGLE_L2, | |
169 | MUXED_L1, | |
170 | }; | |
171 | ||
fa236a7e KD |
172 | struct bcm_qspi_irq { |
173 | const char *irq_name; | |
174 | const irq_handler_t irq_handler; | |
cc20a386 | 175 | int irq_source; |
fa236a7e KD |
176 | u32 mask; |
177 | }; | |
178 | ||
179 | struct bcm_qspi_dev_id { | |
180 | const struct bcm_qspi_irq *irqp; | |
181 | void *dev; | |
182 | }; | |
183 | ||
81ab52fd | 184 | |
fa236a7e KD |
185 | struct qspi_trans { |
186 | struct spi_transfer *trans; | |
187 | int byte; | |
81ab52fd | 188 | bool mspi_last_trans; |
fa236a7e KD |
189 | }; |
190 | ||
191 | struct bcm_qspi { | |
192 | struct platform_device *pdev; | |
193 | struct spi_master *master; | |
194 | struct clk *clk; | |
195 | u32 base_clk; | |
196 | u32 max_speed_hz; | |
197 | void __iomem *base[BASEMAX]; | |
cc20a386 KD |
198 | |
199 | /* Some SoCs provide custom interrupt status register(s) */ | |
200 | struct bcm_qspi_soc_intc *soc_intc; | |
201 | ||
fa236a7e KD |
202 | struct bcm_qspi_parms last_parms; |
203 | struct qspi_trans trans_pos; | |
204 | int curr_cs; | |
4e3b2d23 KD |
205 | int bspi_maj_rev; |
206 | int bspi_min_rev; | |
207 | int bspi_enabled; | |
5f195ee7 BB |
208 | const struct spi_mem_op *bspi_rf_op; |
209 | u32 bspi_rf_op_idx; | |
210 | u32 bspi_rf_op_len; | |
211 | u32 bspi_rf_op_status; | |
4e3b2d23 | 212 | struct bcm_xfer_mode xfer_mode; |
fa236a7e | 213 | u32 s3_strap_override_ctrl; |
4e3b2d23 | 214 | bool bspi_mode; |
fa236a7e KD |
215 | bool big_endian; |
216 | int num_irqs; | |
217 | struct bcm_qspi_dev_id *dev_ids; | |
218 | struct completion mspi_done; | |
4e3b2d23 | 219 | struct completion bspi_done; |
fa236a7e KD |
220 | }; |
221 | ||
4e3b2d23 KD |
222 | static inline bool has_bspi(struct bcm_qspi *qspi) |
223 | { | |
224 | return qspi->bspi_mode; | |
225 | } | |
226 | ||
fa236a7e KD |
227 | /* Read qspi controller register*/ |
228 | static inline u32 bcm_qspi_read(struct bcm_qspi *qspi, enum base_type type, | |
229 | unsigned int offset) | |
230 | { | |
231 | return bcm_qspi_readl(qspi->big_endian, qspi->base[type] + offset); | |
232 | } | |
233 | ||
234 | /* Write qspi controller register*/ | |
235 | static inline void bcm_qspi_write(struct bcm_qspi *qspi, enum base_type type, | |
236 | unsigned int offset, unsigned int data) | |
237 | { | |
238 | bcm_qspi_writel(qspi->big_endian, data, qspi->base[type] + offset); | |
239 | } | |
240 | ||
4e3b2d23 KD |
241 | /* BSPI helpers */ |
242 | static int bcm_qspi_bspi_busy_poll(struct bcm_qspi *qspi) | |
243 | { | |
244 | int i; | |
245 | ||
246 | /* this should normally finish within 10us */ | |
247 | for (i = 0; i < 1000; i++) { | |
248 | if (!(bcm_qspi_read(qspi, BSPI, BSPI_BUSY_STATUS) & 1)) | |
249 | return 0; | |
250 | udelay(1); | |
251 | } | |
252 | dev_warn(&qspi->pdev->dev, "timeout waiting for !busy_status\n"); | |
253 | return -EIO; | |
254 | } | |
255 | ||
256 | static inline bool bcm_qspi_bspi_ver_three(struct bcm_qspi *qspi) | |
257 | { | |
258 | if (qspi->bspi_maj_rev < 4) | |
259 | return true; | |
260 | return false; | |
261 | } | |
262 | ||
263 | static void bcm_qspi_bspi_flush_prefetch_buffers(struct bcm_qspi *qspi) | |
264 | { | |
265 | bcm_qspi_bspi_busy_poll(qspi); | |
266 | /* Force rising edge for the b0/b1 'flush' field */ | |
267 | bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 1); | |
268 | bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 1); | |
269 | bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0); | |
270 | bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0); | |
271 | } | |
272 | ||
273 | static int bcm_qspi_bspi_lr_is_fifo_empty(struct bcm_qspi *qspi) | |
274 | { | |
275 | return (bcm_qspi_read(qspi, BSPI, BSPI_RAF_STATUS) & | |
276 | BSPI_RAF_STATUS_FIFO_EMPTY_MASK); | |
277 | } | |
278 | ||
279 | static inline u32 bcm_qspi_bspi_lr_read_fifo(struct bcm_qspi *qspi) | |
280 | { | |
281 | u32 data = bcm_qspi_read(qspi, BSPI, BSPI_RAF_READ_DATA); | |
282 | ||
283 | /* BSPI v3 LR is LE only, convert data to host endianness */ | |
284 | if (bcm_qspi_bspi_ver_three(qspi)) | |
285 | data = le32_to_cpu(data); | |
286 | ||
287 | return data; | |
288 | } | |
289 | ||
290 | static inline void bcm_qspi_bspi_lr_start(struct bcm_qspi *qspi) | |
291 | { | |
292 | bcm_qspi_bspi_busy_poll(qspi); | |
293 | bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL, | |
294 | BSPI_RAF_CTRL_START_MASK); | |
295 | } | |
296 | ||
297 | static inline void bcm_qspi_bspi_lr_clear(struct bcm_qspi *qspi) | |
298 | { | |
299 | bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL, | |
300 | BSPI_RAF_CTRL_CLEAR_MASK); | |
301 | bcm_qspi_bspi_flush_prefetch_buffers(qspi); | |
302 | } | |
303 | ||
304 | static void bcm_qspi_bspi_lr_data_read(struct bcm_qspi *qspi) | |
305 | { | |
5f195ee7 | 306 | u32 *buf = (u32 *)qspi->bspi_rf_op->data.buf.in; |
4e3b2d23 KD |
307 | u32 data = 0; |
308 | ||
5f195ee7 BB |
309 | dev_dbg(&qspi->pdev->dev, "xfer %p rx %p rxlen %d\n", qspi->bspi_rf_op, |
310 | qspi->bspi_rf_op->data.buf.in, qspi->bspi_rf_op_len); | |
4e3b2d23 KD |
311 | while (!bcm_qspi_bspi_lr_is_fifo_empty(qspi)) { |
312 | data = bcm_qspi_bspi_lr_read_fifo(qspi); | |
5f195ee7 | 313 | if (likely(qspi->bspi_rf_op_len >= 4) && |
4e3b2d23 | 314 | IS_ALIGNED((uintptr_t)buf, 4)) { |
5f195ee7 BB |
315 | buf[qspi->bspi_rf_op_idx++] = data; |
316 | qspi->bspi_rf_op_len -= 4; | |
4e3b2d23 KD |
317 | } else { |
318 | /* Read out remaining bytes, make sure*/ | |
5f195ee7 | 319 | u8 *cbuf = (u8 *)&buf[qspi->bspi_rf_op_idx]; |
4e3b2d23 KD |
320 | |
321 | data = cpu_to_le32(data); | |
5f195ee7 | 322 | while (qspi->bspi_rf_op_len) { |
4e3b2d23 KD |
323 | *cbuf++ = (u8)data; |
324 | data >>= 8; | |
5f195ee7 | 325 | qspi->bspi_rf_op_len--; |
4e3b2d23 KD |
326 | } |
327 | } | |
328 | } | |
329 | } | |
330 | ||
331 | static void bcm_qspi_bspi_set_xfer_params(struct bcm_qspi *qspi, u8 cmd_byte, | |
332 | int bpp, int bpc, int flex_mode) | |
333 | { | |
334 | bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 0); | |
335 | bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_CYCLE, bpc); | |
336 | bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_PHASE, bpp); | |
337 | bcm_qspi_write(qspi, BSPI, BSPI_CMD_AND_MODE_BYTE, cmd_byte); | |
338 | bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, flex_mode); | |
339 | } | |
340 | ||
054e532f | 341 | static int bcm_qspi_bspi_set_flex_mode(struct bcm_qspi *qspi, |
5f195ee7 | 342 | const struct spi_mem_op *op, int hp) |
4e3b2d23 KD |
343 | { |
344 | int bpc = 0, bpp = 0; | |
5f195ee7 BB |
345 | u8 command = op->cmd.opcode; |
346 | int width = op->cmd.buswidth ? op->cmd.buswidth : SPI_NBITS_SINGLE; | |
0976eda7 | 347 | int addrlen = op->addr.nbytes; |
054e532f | 348 | int flex_mode = 1; |
4e3b2d23 KD |
349 | |
350 | dev_dbg(&qspi->pdev->dev, "set flex mode w %x addrlen %x hp %d\n", | |
351 | width, addrlen, hp); | |
352 | ||
054e532f | 353 | if (addrlen == BSPI_ADDRLEN_4BYTES) |
4e3b2d23 | 354 | bpp = BSPI_BPP_ADDR_SELECT_MASK; |
4e3b2d23 | 355 | |
5f195ee7 | 356 | bpp |= (op->dummy.nbytes * 8) / op->dummy.buswidth; |
4e3b2d23 KD |
357 | |
358 | switch (width) { | |
359 | case SPI_NBITS_SINGLE: | |
360 | if (addrlen == BSPI_ADDRLEN_3BYTES) | |
361 | /* default mode, does not need flex_cmd */ | |
362 | flex_mode = 0; | |
4e3b2d23 KD |
363 | break; |
364 | case SPI_NBITS_DUAL: | |
365 | bpc = 0x00000001; | |
366 | if (hp) { | |
367 | bpc |= 0x00010100; /* address and mode are 2-bit */ | |
368 | bpp = BSPI_BPP_MODE_SELECT_MASK; | |
4e3b2d23 KD |
369 | } |
370 | break; | |
371 | case SPI_NBITS_QUAD: | |
372 | bpc = 0x00000002; | |
373 | if (hp) { | |
374 | bpc |= 0x00020200; /* address and mode are 4-bit */ | |
054e532f | 375 | bpp |= BSPI_BPP_MODE_SELECT_MASK; |
4e3b2d23 KD |
376 | } |
377 | break; | |
378 | default: | |
054e532f | 379 | return -EINVAL; |
4e3b2d23 KD |
380 | } |
381 | ||
054e532f | 382 | bcm_qspi_bspi_set_xfer_params(qspi, command, bpp, bpc, flex_mode); |
4e3b2d23 | 383 | |
054e532f | 384 | return 0; |
4e3b2d23 KD |
385 | } |
386 | ||
054e532f | 387 | static int bcm_qspi_bspi_set_override(struct bcm_qspi *qspi, |
5f195ee7 | 388 | const struct spi_mem_op *op, int hp) |
4e3b2d23 | 389 | { |
5f195ee7 BB |
390 | int width = op->data.buswidth ? op->data.buswidth : SPI_NBITS_SINGLE; |
391 | int addrlen = op->addr.nbytes; | |
4e3b2d23 KD |
392 | u32 data = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL); |
393 | ||
394 | dev_dbg(&qspi->pdev->dev, "set override mode w %x addrlen %x hp %d\n", | |
395 | width, addrlen, hp); | |
396 | ||
397 | switch (width) { | |
398 | case SPI_NBITS_SINGLE: | |
399 | /* clear quad/dual mode */ | |
400 | data &= ~(BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD | | |
401 | BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL); | |
402 | break; | |
4e3b2d23 KD |
403 | case SPI_NBITS_QUAD: |
404 | /* clear dual mode and set quad mode */ | |
405 | data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL; | |
406 | data |= BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD; | |
407 | break; | |
408 | case SPI_NBITS_DUAL: | |
409 | /* clear quad mode set dual mode */ | |
410 | data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD; | |
411 | data |= BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL; | |
412 | break; | |
413 | default: | |
414 | return -EINVAL; | |
415 | } | |
416 | ||
417 | if (addrlen == BSPI_ADDRLEN_4BYTES) | |
418 | /* set 4byte mode*/ | |
419 | data |= BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE; | |
420 | else | |
421 | /* clear 4 byte mode */ | |
422 | data &= ~BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE; | |
423 | ||
424 | /* set the override mode */ | |
425 | data |= BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE; | |
426 | bcm_qspi_write(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL, data); | |
5f195ee7 | 427 | bcm_qspi_bspi_set_xfer_params(qspi, op->cmd.opcode, 0, 0, 0); |
4e3b2d23 KD |
428 | |
429 | return 0; | |
430 | } | |
431 | ||
432 | static int bcm_qspi_bspi_set_mode(struct bcm_qspi *qspi, | |
5f195ee7 | 433 | const struct spi_mem_op *op, int hp) |
4e3b2d23 KD |
434 | { |
435 | int error = 0; | |
5f195ee7 BB |
436 | int width = op->data.buswidth ? op->data.buswidth : SPI_NBITS_SINGLE; |
437 | int addrlen = op->addr.nbytes; | |
4e3b2d23 KD |
438 | |
439 | /* default mode */ | |
440 | qspi->xfer_mode.flex_mode = true; | |
441 | ||
442 | if (!bcm_qspi_bspi_ver_three(qspi)) { | |
443 | u32 val, mask; | |
444 | ||
445 | val = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL); | |
446 | mask = BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE; | |
447 | if (val & mask || qspi->s3_strap_override_ctrl & mask) { | |
448 | qspi->xfer_mode.flex_mode = false; | |
054e532f | 449 | bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 0); |
5f195ee7 | 450 | error = bcm_qspi_bspi_set_override(qspi, op, hp); |
4e3b2d23 KD |
451 | } |
452 | } | |
453 | ||
454 | if (qspi->xfer_mode.flex_mode) | |
5f195ee7 | 455 | error = bcm_qspi_bspi_set_flex_mode(qspi, op, hp); |
4e3b2d23 KD |
456 | |
457 | if (error) { | |
458 | dev_warn(&qspi->pdev->dev, | |
459 | "INVALID COMBINATION: width=%d addrlen=%d hp=%d\n", | |
460 | width, addrlen, hp); | |
461 | } else if (qspi->xfer_mode.width != width || | |
462 | qspi->xfer_mode.addrlen != addrlen || | |
463 | qspi->xfer_mode.hp != hp) { | |
464 | qspi->xfer_mode.width = width; | |
465 | qspi->xfer_mode.addrlen = addrlen; | |
466 | qspi->xfer_mode.hp = hp; | |
467 | dev_dbg(&qspi->pdev->dev, | |
468 | "cs:%d %d-lane output, %d-byte address%s\n", | |
469 | qspi->curr_cs, | |
470 | qspi->xfer_mode.width, | |
471 | qspi->xfer_mode.addrlen, | |
472 | qspi->xfer_mode.hp != -1 ? ", hp mode" : ""); | |
473 | } | |
474 | ||
475 | return error; | |
476 | } | |
477 | ||
478 | static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi) | |
479 | { | |
602805fb | 480 | if (!has_bspi(qspi)) |
4e3b2d23 KD |
481 | return; |
482 | ||
483 | qspi->bspi_enabled = 1; | |
484 | if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1) == 0) | |
485 | return; | |
486 | ||
487 | bcm_qspi_bspi_flush_prefetch_buffers(qspi); | |
488 | udelay(1); | |
489 | bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 0); | |
490 | udelay(1); | |
491 | } | |
492 | ||
493 | static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi) | |
494 | { | |
602805fb | 495 | if (!has_bspi(qspi)) |
4e3b2d23 KD |
496 | return; |
497 | ||
498 | qspi->bspi_enabled = 0; | |
499 | if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1)) | |
500 | return; | |
501 | ||
502 | bcm_qspi_bspi_busy_poll(qspi); | |
503 | bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 1); | |
504 | udelay(1); | |
505 | } | |
506 | ||
fa236a7e KD |
507 | static void bcm_qspi_chip_select(struct bcm_qspi *qspi, int cs) |
508 | { | |
5eb9a07a KD |
509 | u32 rd = 0; |
510 | u32 wr = 0; | |
fa236a7e | 511 | |
fa236a7e | 512 | if (qspi->base[CHIP_SELECT]) { |
5eb9a07a KD |
513 | rd = bcm_qspi_read(qspi, CHIP_SELECT, 0); |
514 | wr = (rd & ~0xff) | (1 << cs); | |
515 | if (rd == wr) | |
516 | return; | |
517 | bcm_qspi_write(qspi, CHIP_SELECT, 0, wr); | |
fa236a7e KD |
518 | usleep_range(10, 20); |
519 | } | |
5eb9a07a KD |
520 | |
521 | dev_dbg(&qspi->pdev->dev, "using cs:%d\n", cs); | |
fa236a7e KD |
522 | qspi->curr_cs = cs; |
523 | } | |
524 | ||
525 | /* MSPI helpers */ | |
526 | static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi, | |
527 | const struct bcm_qspi_parms *xp) | |
528 | { | |
529 | u32 spcr, spbr = 0; | |
530 | ||
531 | if (xp->speed_hz) | |
532 | spbr = qspi->base_clk / (2 * xp->speed_hz); | |
533 | ||
534 | spcr = clamp_val(spbr, QSPI_SPBR_MIN, QSPI_SPBR_MAX); | |
535 | bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spcr); | |
536 | ||
537 | spcr = MSPI_MASTER_BIT; | |
538 | /* for 16 bit the data should be zero */ | |
539 | if (xp->bits_per_word != 16) | |
540 | spcr |= xp->bits_per_word << 2; | |
541 | spcr |= xp->mode & 3; | |
542 | bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr); | |
543 | ||
544 | qspi->last_parms = *xp; | |
545 | } | |
546 | ||
547 | static void bcm_qspi_update_parms(struct bcm_qspi *qspi, | |
548 | struct spi_device *spi, | |
549 | struct spi_transfer *trans) | |
550 | { | |
551 | struct bcm_qspi_parms xp; | |
552 | ||
553 | xp.speed_hz = trans->speed_hz; | |
554 | xp.bits_per_word = trans->bits_per_word; | |
555 | xp.mode = spi->mode; | |
556 | ||
557 | bcm_qspi_hw_set_parms(qspi, &xp); | |
558 | } | |
559 | ||
560 | static int bcm_qspi_setup(struct spi_device *spi) | |
561 | { | |
562 | struct bcm_qspi_parms *xp; | |
563 | ||
564 | if (spi->bits_per_word > 16) | |
565 | return -EINVAL; | |
566 | ||
567 | xp = spi_get_ctldata(spi); | |
568 | if (!xp) { | |
569 | xp = kzalloc(sizeof(*xp), GFP_KERNEL); | |
570 | if (!xp) | |
571 | return -ENOMEM; | |
572 | spi_set_ctldata(spi, xp); | |
573 | } | |
574 | xp->speed_hz = spi->max_speed_hz; | |
575 | xp->mode = spi->mode; | |
576 | ||
577 | if (spi->bits_per_word) | |
578 | xp->bits_per_word = spi->bits_per_word; | |
579 | else | |
580 | xp->bits_per_word = 8; | |
581 | ||
582 | return 0; | |
583 | } | |
584 | ||
81ab52fd KD |
585 | static bool bcm_qspi_mspi_transfer_is_last(struct bcm_qspi *qspi, |
586 | struct qspi_trans *qt) | |
587 | { | |
588 | if (qt->mspi_last_trans && | |
589 | spi_transfer_is_last(qspi->master, qt->trans)) | |
590 | return true; | |
591 | else | |
592 | return false; | |
593 | } | |
594 | ||
fa236a7e KD |
595 | static int update_qspi_trans_byte_count(struct bcm_qspi *qspi, |
596 | struct qspi_trans *qt, int flags) | |
597 | { | |
598 | int ret = TRANS_STATUS_BREAK_NONE; | |
599 | ||
600 | /* count the last transferred bytes */ | |
601 | if (qt->trans->bits_per_word <= 8) | |
602 | qt->byte++; | |
603 | else | |
604 | qt->byte += 2; | |
605 | ||
606 | if (qt->byte >= qt->trans->len) { | |
607 | /* we're at the end of the spi_transfer */ | |
fa236a7e KD |
608 | /* in TX mode, need to pause for a delay or CS change */ |
609 | if (qt->trans->delay_usecs && | |
610 | (flags & TRANS_STATUS_BREAK_DELAY)) | |
611 | ret |= TRANS_STATUS_BREAK_DELAY; | |
612 | if (qt->trans->cs_change && | |
613 | (flags & TRANS_STATUS_BREAK_CS_CHANGE)) | |
614 | ret |= TRANS_STATUS_BREAK_CS_CHANGE; | |
615 | if (ret) | |
616 | goto done; | |
617 | ||
618 | dev_dbg(&qspi->pdev->dev, "advance msg exit\n"); | |
81ab52fd | 619 | if (bcm_qspi_mspi_transfer_is_last(qspi, qt)) |
fa236a7e KD |
620 | ret = TRANS_STATUS_BREAK_EOM; |
621 | else | |
622 | ret = TRANS_STATUS_BREAK_NO_BYTES; | |
623 | ||
624 | qt->trans = NULL; | |
625 | } | |
626 | ||
627 | done: | |
628 | dev_dbg(&qspi->pdev->dev, "trans %p len %d byte %d ret %x\n", | |
629 | qt->trans, qt->trans ? qt->trans->len : 0, qt->byte, ret); | |
630 | return ret; | |
631 | } | |
632 | ||
633 | static inline u8 read_rxram_slot_u8(struct bcm_qspi *qspi, int slot) | |
634 | { | |
635 | u32 slot_offset = MSPI_RXRAM + (slot << 3) + 0x4; | |
636 | ||
637 | /* mask out reserved bits */ | |
638 | return bcm_qspi_read(qspi, MSPI, slot_offset) & 0xff; | |
639 | } | |
640 | ||
641 | static inline u16 read_rxram_slot_u16(struct bcm_qspi *qspi, int slot) | |
642 | { | |
643 | u32 reg_offset = MSPI_RXRAM; | |
644 | u32 lsb_offset = reg_offset + (slot << 3) + 0x4; | |
645 | u32 msb_offset = reg_offset + (slot << 3); | |
646 | ||
647 | return (bcm_qspi_read(qspi, MSPI, lsb_offset) & 0xff) | | |
648 | ((bcm_qspi_read(qspi, MSPI, msb_offset) & 0xff) << 8); | |
649 | } | |
650 | ||
651 | static void read_from_hw(struct bcm_qspi *qspi, int slots) | |
652 | { | |
653 | struct qspi_trans tp; | |
654 | int slot; | |
655 | ||
4e3b2d23 KD |
656 | bcm_qspi_disable_bspi(qspi); |
657 | ||
fa236a7e KD |
658 | if (slots > MSPI_NUM_CDRAM) { |
659 | /* should never happen */ | |
660 | dev_err(&qspi->pdev->dev, "%s: too many slots!\n", __func__); | |
661 | return; | |
662 | } | |
663 | ||
664 | tp = qspi->trans_pos; | |
665 | ||
666 | for (slot = 0; slot < slots; slot++) { | |
667 | if (tp.trans->bits_per_word <= 8) { | |
668 | u8 *buf = tp.trans->rx_buf; | |
669 | ||
670 | if (buf) | |
671 | buf[tp.byte] = read_rxram_slot_u8(qspi, slot); | |
672 | dev_dbg(&qspi->pdev->dev, "RD %02x\n", | |
673 | buf ? buf[tp.byte] : 0xff); | |
674 | } else { | |
675 | u16 *buf = tp.trans->rx_buf; | |
676 | ||
677 | if (buf) | |
678 | buf[tp.byte / 2] = read_rxram_slot_u16(qspi, | |
679 | slot); | |
680 | dev_dbg(&qspi->pdev->dev, "RD %04x\n", | |
681 | buf ? buf[tp.byte] : 0xffff); | |
682 | } | |
683 | ||
684 | update_qspi_trans_byte_count(qspi, &tp, | |
685 | TRANS_STATUS_BREAK_NONE); | |
686 | } | |
687 | ||
688 | qspi->trans_pos = tp; | |
689 | } | |
690 | ||
691 | static inline void write_txram_slot_u8(struct bcm_qspi *qspi, int slot, | |
692 | u8 val) | |
693 | { | |
694 | u32 reg_offset = MSPI_TXRAM + (slot << 3); | |
695 | ||
696 | /* mask out reserved bits */ | |
697 | bcm_qspi_write(qspi, MSPI, reg_offset, val); | |
698 | } | |
699 | ||
700 | static inline void write_txram_slot_u16(struct bcm_qspi *qspi, int slot, | |
701 | u16 val) | |
702 | { | |
703 | u32 reg_offset = MSPI_TXRAM; | |
704 | u32 msb_offset = reg_offset + (slot << 3); | |
705 | u32 lsb_offset = reg_offset + (slot << 3) + 0x4; | |
706 | ||
707 | bcm_qspi_write(qspi, MSPI, msb_offset, (val >> 8)); | |
708 | bcm_qspi_write(qspi, MSPI, lsb_offset, (val & 0xff)); | |
709 | } | |
710 | ||
711 | static inline u32 read_cdram_slot(struct bcm_qspi *qspi, int slot) | |
712 | { | |
713 | return bcm_qspi_read(qspi, MSPI, MSPI_CDRAM + (slot << 2)); | |
714 | } | |
715 | ||
716 | static inline void write_cdram_slot(struct bcm_qspi *qspi, int slot, u32 val) | |
717 | { | |
718 | bcm_qspi_write(qspi, MSPI, (MSPI_CDRAM + (slot << 2)), val); | |
719 | } | |
720 | ||
721 | /* Return number of slots written */ | |
722 | static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi) | |
723 | { | |
724 | struct qspi_trans tp; | |
725 | int slot = 0, tstatus = 0; | |
726 | u32 mspi_cdram = 0; | |
727 | ||
4e3b2d23 | 728 | bcm_qspi_disable_bspi(qspi); |
fa236a7e KD |
729 | tp = qspi->trans_pos; |
730 | bcm_qspi_update_parms(qspi, spi, tp.trans); | |
731 | ||
732 | /* Run until end of transfer or reached the max data */ | |
733 | while (!tstatus && slot < MSPI_NUM_CDRAM) { | |
734 | if (tp.trans->bits_per_word <= 8) { | |
735 | const u8 *buf = tp.trans->tx_buf; | |
736 | u8 val = buf ? buf[tp.byte] : 0xff; | |
737 | ||
738 | write_txram_slot_u8(qspi, slot, val); | |
739 | dev_dbg(&qspi->pdev->dev, "WR %02x\n", val); | |
740 | } else { | |
741 | const u16 *buf = tp.trans->tx_buf; | |
742 | u16 val = buf ? buf[tp.byte / 2] : 0xffff; | |
743 | ||
744 | write_txram_slot_u16(qspi, slot, val); | |
745 | dev_dbg(&qspi->pdev->dev, "WR %04x\n", val); | |
746 | } | |
747 | mspi_cdram = MSPI_CDRAM_CONT_BIT; | |
5eb9a07a KD |
748 | |
749 | if (has_bspi(qspi)) | |
750 | mspi_cdram &= ~1; | |
751 | else | |
752 | mspi_cdram |= (~(1 << spi->chip_select) & | |
753 | MSPI_CDRAM_PCS); | |
754 | ||
fa236a7e KD |
755 | mspi_cdram |= ((tp.trans->bits_per_word <= 8) ? 0 : |
756 | MSPI_CDRAM_BITSE_BIT); | |
757 | ||
758 | write_cdram_slot(qspi, slot, mspi_cdram); | |
759 | ||
760 | tstatus = update_qspi_trans_byte_count(qspi, &tp, | |
761 | TRANS_STATUS_BREAK_TX); | |
762 | slot++; | |
763 | } | |
764 | ||
765 | if (!slot) { | |
766 | dev_err(&qspi->pdev->dev, "%s: no data to send?", __func__); | |
767 | goto done; | |
768 | } | |
769 | ||
770 | dev_dbg(&qspi->pdev->dev, "submitting %d slots\n", slot); | |
771 | bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0); | |
772 | bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1); | |
773 | ||
774 | if (tstatus & TRANS_STATUS_BREAK_DESELECT) { | |
775 | mspi_cdram = read_cdram_slot(qspi, slot - 1) & | |
776 | ~MSPI_CDRAM_CONT_BIT; | |
777 | write_cdram_slot(qspi, slot - 1, mspi_cdram); | |
778 | } | |
779 | ||
4e3b2d23 KD |
780 | if (has_bspi(qspi)) |
781 | bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 1); | |
782 | ||
fa236a7e KD |
783 | /* Must flush previous writes before starting MSPI operation */ |
784 | mb(); | |
785 | /* Set cont | spe | spifie */ | |
786 | bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0xe0); | |
787 | ||
788 | done: | |
789 | return slot; | |
790 | } | |
791 | ||
5f195ee7 BB |
792 | static int bcm_qspi_bspi_exec_mem_op(struct spi_device *spi, |
793 | const struct spi_mem_op *op) | |
4e3b2d23 KD |
794 | { |
795 | struct bcm_qspi *qspi = spi_master_get_devdata(spi->master); | |
5f195ee7 | 796 | u32 addr = 0, len, rdlen, len_words, from = 0; |
4e3b2d23 KD |
797 | int ret = 0; |
798 | unsigned long timeo = msecs_to_jiffies(100); | |
cc20a386 | 799 | struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc; |
4e3b2d23 KD |
800 | |
801 | if (bcm_qspi_bspi_ver_three(qspi)) | |
5f195ee7 | 802 | if (op->addr.nbytes == BSPI_ADDRLEN_4BYTES) |
4e3b2d23 KD |
803 | return -EIO; |
804 | ||
5f195ee7 | 805 | from = op->addr.val; |
4e3b2d23 KD |
806 | bcm_qspi_chip_select(qspi, spi->chip_select); |
807 | bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0); | |
808 | ||
809 | /* | |
345309fa | 810 | * when using flex mode we need to send |
4e3b2d23 KD |
811 | * the upper address byte to bspi |
812 | */ | |
813 | if (bcm_qspi_bspi_ver_three(qspi) == false) { | |
5f195ee7 | 814 | addr = from & 0xff000000; |
4e3b2d23 KD |
815 | bcm_qspi_write(qspi, BSPI, |
816 | BSPI_BSPI_FLASH_UPPER_ADDR_BYTE, addr); | |
817 | } | |
818 | ||
819 | if (!qspi->xfer_mode.flex_mode) | |
5f195ee7 | 820 | addr = from; |
4e3b2d23 | 821 | else |
5f195ee7 | 822 | addr = from & 0x00ffffff; |
4e3b2d23 | 823 | |
4e3b2d23 KD |
824 | if (bcm_qspi_bspi_ver_three(qspi) == true) |
825 | addr = (addr + 0xc00000) & 0xffffff; | |
826 | ||
345309fa KD |
827 | /* |
828 | * read into the entire buffer by breaking the reads | |
829 | * into RAF buffer read lengths | |
830 | */ | |
5f195ee7 BB |
831 | len = op->data.nbytes; |
832 | qspi->bspi_rf_op_idx = 0; | |
4e3b2d23 | 833 | |
345309fa KD |
834 | do { |
835 | if (len > BSPI_READ_LENGTH) | |
836 | rdlen = BSPI_READ_LENGTH; | |
837 | else | |
838 | rdlen = len; | |
839 | ||
840 | reinit_completion(&qspi->bspi_done); | |
841 | bcm_qspi_enable_bspi(qspi); | |
842 | len_words = (rdlen + 3) >> 2; | |
5f195ee7 BB |
843 | qspi->bspi_rf_op = op; |
844 | qspi->bspi_rf_op_status = 0; | |
845 | qspi->bspi_rf_op_len = rdlen; | |
345309fa KD |
846 | dev_dbg(&qspi->pdev->dev, |
847 | "bspi xfr addr 0x%x len 0x%x", addr, rdlen); | |
848 | bcm_qspi_write(qspi, BSPI, BSPI_RAF_START_ADDR, addr); | |
849 | bcm_qspi_write(qspi, BSPI, BSPI_RAF_NUM_WORDS, len_words); | |
850 | bcm_qspi_write(qspi, BSPI, BSPI_RAF_WATERMARK, 0); | |
851 | if (qspi->soc_intc) { | |
852 | /* | |
853 | * clear soc MSPI and BSPI interrupts and enable | |
854 | * BSPI interrupts. | |
855 | */ | |
856 | soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_BSPI_DONE); | |
857 | soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE, true); | |
858 | } | |
4e3b2d23 | 859 | |
345309fa KD |
860 | /* Must flush previous writes before starting BSPI operation */ |
861 | mb(); | |
862 | bcm_qspi_bspi_lr_start(qspi); | |
863 | if (!wait_for_completion_timeout(&qspi->bspi_done, timeo)) { | |
864 | dev_err(&qspi->pdev->dev, "timeout waiting for BSPI\n"); | |
865 | ret = -ETIMEDOUT; | |
866 | break; | |
867 | } | |
868 | ||
869 | /* set msg return length */ | |
345309fa KD |
870 | addr += rdlen; |
871 | len -= rdlen; | |
872 | } while (len); | |
4e3b2d23 KD |
873 | |
874 | return ret; | |
875 | } | |
876 | ||
81ab52fd KD |
877 | static int bcm_qspi_transfer_one(struct spi_master *master, |
878 | struct spi_device *spi, | |
879 | struct spi_transfer *trans) | |
880 | { | |
881 | struct bcm_qspi *qspi = spi_master_get_devdata(master); | |
882 | int slots; | |
883 | unsigned long timeo = msecs_to_jiffies(100); | |
884 | ||
885 | bcm_qspi_chip_select(qspi, spi->chip_select); | |
886 | qspi->trans_pos.trans = trans; | |
887 | qspi->trans_pos.byte = 0; | |
888 | ||
889 | while (qspi->trans_pos.byte < trans->len) { | |
890 | reinit_completion(&qspi->mspi_done); | |
891 | ||
892 | slots = write_to_hw(qspi, spi); | |
893 | if (!wait_for_completion_timeout(&qspi->mspi_done, timeo)) { | |
894 | dev_err(&qspi->pdev->dev, "timeout waiting for MSPI\n"); | |
895 | return -ETIMEDOUT; | |
896 | } | |
897 | ||
898 | read_from_hw(qspi, slots); | |
cc20a386 KD |
899 | } |
900 | ||
81ab52fd KD |
901 | return 0; |
902 | } | |
4e3b2d23 | 903 | |
5f195ee7 BB |
904 | static int bcm_qspi_mspi_exec_mem_op(struct spi_device *spi, |
905 | const struct spi_mem_op *op) | |
81ab52fd | 906 | { |
5f195ee7 BB |
907 | struct spi_master *master = spi->master; |
908 | struct bcm_qspi *qspi = spi_master_get_devdata(master); | |
81ab52fd | 909 | struct spi_transfer t[2]; |
5f195ee7 BB |
910 | u8 cmd[6] = { }; |
911 | int ret, i; | |
81ab52fd KD |
912 | |
913 | memset(cmd, 0, sizeof(cmd)); | |
914 | memset(t, 0, sizeof(t)); | |
915 | ||
916 | /* tx */ | |
917 | /* opcode is in cmd[0] */ | |
5f195ee7 BB |
918 | cmd[0] = op->cmd.opcode; |
919 | for (i = 0; i < op->addr.nbytes; i++) | |
920 | cmd[1 + i] = op->addr.val >> (8 * (op->addr.nbytes - i - 1)); | |
921 | ||
81ab52fd | 922 | t[0].tx_buf = cmd; |
5f195ee7 | 923 | t[0].len = op->addr.nbytes + op->dummy.nbytes + 1; |
81ab52fd | 924 | t[0].bits_per_word = spi->bits_per_word; |
5f195ee7 | 925 | t[0].tx_nbits = op->cmd.buswidth; |
81ab52fd KD |
926 | /* lets mspi know that this is not last transfer */ |
927 | qspi->trans_pos.mspi_last_trans = false; | |
5f195ee7 | 928 | ret = bcm_qspi_transfer_one(master, spi, &t[0]); |
81ab52fd KD |
929 | |
930 | /* rx */ | |
931 | qspi->trans_pos.mspi_last_trans = true; | |
932 | if (!ret) { | |
933 | /* rx */ | |
5f195ee7 BB |
934 | t[1].rx_buf = op->data.buf.in; |
935 | t[1].len = op->data.nbytes; | |
936 | t[1].rx_nbits = op->data.buswidth; | |
81ab52fd | 937 | t[1].bits_per_word = spi->bits_per_word; |
5f195ee7 | 938 | ret = bcm_qspi_transfer_one(master, spi, &t[1]); |
4e3b2d23 KD |
939 | } |
940 | ||
941 | return ret; | |
942 | } | |
943 | ||
b6456057 | 944 | static int bcm_qspi_exec_mem_op(struct spi_mem *mem, |
5f195ee7 | 945 | const struct spi_mem_op *op) |
4e3b2d23 | 946 | { |
b6456057 | 947 | struct spi_device *spi = mem->spi; |
4e3b2d23 KD |
948 | struct bcm_qspi *qspi = spi_master_get_devdata(spi->master); |
949 | int ret = 0; | |
950 | bool mspi_read = false; | |
5f195ee7 | 951 | u32 addr = 0, len; |
4e3b2d23 KD |
952 | u_char *buf; |
953 | ||
5f195ee7 BB |
954 | if (!op->data.nbytes || !op->addr.nbytes || op->addr.nbytes > 4 || |
955 | op->data.dir != SPI_MEM_DATA_IN) | |
956 | return -ENOTSUPP; | |
957 | ||
958 | buf = op->data.buf.in; | |
959 | addr = op->addr.val; | |
960 | len = op->data.nbytes; | |
4e3b2d23 KD |
961 | |
962 | if (bcm_qspi_bspi_ver_three(qspi) == true) { | |
963 | /* | |
964 | * The address coming into this function is a raw flash offset. | |
965 | * But for BSPI <= V3, we need to convert it to a remapped BSPI | |
966 | * address. If it crosses a 4MB boundary, just revert back to | |
967 | * using MSPI. | |
968 | */ | |
969 | addr = (addr + 0xc00000) & 0xffffff; | |
970 | ||
971 | if ((~ADDR_4MB_MASK & addr) ^ | |
972 | (~ADDR_4MB_MASK & (addr + len - 1))) | |
973 | mspi_read = true; | |
974 | } | |
975 | ||
976 | /* non-aligned and very short transfers are handled by MSPI */ | |
977 | if (!IS_ALIGNED((uintptr_t)addr, 4) || !IS_ALIGNED((uintptr_t)buf, 4) || | |
978 | len < 4) | |
979 | mspi_read = true; | |
980 | ||
981 | if (mspi_read) | |
5f195ee7 | 982 | return bcm_qspi_mspi_exec_mem_op(spi, op); |
4e3b2d23 | 983 | |
5f195ee7 | 984 | ret = bcm_qspi_bspi_set_mode(qspi, op, -1); |
4e3b2d23 KD |
985 | |
986 | if (!ret) | |
5f195ee7 BB |
987 | ret = bcm_qspi_bspi_exec_mem_op(spi, op); |
988 | ||
989 | return ret; | |
990 | } | |
991 | ||
fa236a7e KD |
992 | static void bcm_qspi_cleanup(struct spi_device *spi) |
993 | { | |
994 | struct bcm_qspi_parms *xp = spi_get_ctldata(spi); | |
995 | ||
996 | kfree(xp); | |
997 | } | |
998 | ||
999 | static irqreturn_t bcm_qspi_mspi_l2_isr(int irq, void *dev_id) | |
1000 | { | |
1001 | struct bcm_qspi_dev_id *qspi_dev_id = dev_id; | |
1002 | struct bcm_qspi *qspi = qspi_dev_id->dev; | |
1003 | u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS); | |
1004 | ||
1005 | if (status & MSPI_MSPI_STATUS_SPIF) { | |
cc20a386 | 1006 | struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc; |
fa236a7e KD |
1007 | /* clear interrupt */ |
1008 | status &= ~MSPI_MSPI_STATUS_SPIF; | |
1009 | bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status); | |
cc20a386 KD |
1010 | if (qspi->soc_intc) |
1011 | soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_DONE); | |
fa236a7e KD |
1012 | complete(&qspi->mspi_done); |
1013 | return IRQ_HANDLED; | |
fa236a7e | 1014 | } |
4e3b2d23 KD |
1015 | |
1016 | return IRQ_NONE; | |
1017 | } | |
1018 | ||
1019 | static irqreturn_t bcm_qspi_bspi_lr_l2_isr(int irq, void *dev_id) | |
1020 | { | |
1021 | struct bcm_qspi_dev_id *qspi_dev_id = dev_id; | |
1022 | struct bcm_qspi *qspi = qspi_dev_id->dev; | |
cc20a386 KD |
1023 | struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc; |
1024 | u32 status = qspi_dev_id->irqp->mask; | |
4e3b2d23 | 1025 | |
5f195ee7 | 1026 | if (qspi->bspi_enabled && qspi->bspi_rf_op) { |
4e3b2d23 | 1027 | bcm_qspi_bspi_lr_data_read(qspi); |
5f195ee7 BB |
1028 | if (qspi->bspi_rf_op_len == 0) { |
1029 | qspi->bspi_rf_op = NULL; | |
cc20a386 KD |
1030 | if (qspi->soc_intc) { |
1031 | /* disable soc BSPI interrupt */ | |
1032 | soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE, | |
1033 | false); | |
1034 | /* indicate done */ | |
1035 | status = INTR_BSPI_LR_SESSION_DONE_MASK; | |
1036 | } | |
1037 | ||
5f195ee7 | 1038 | if (qspi->bspi_rf_op_status) |
4e3b2d23 KD |
1039 | bcm_qspi_bspi_lr_clear(qspi); |
1040 | else | |
1041 | bcm_qspi_bspi_flush_prefetch_buffers(qspi); | |
1042 | } | |
cc20a386 KD |
1043 | |
1044 | if (qspi->soc_intc) | |
1045 | /* clear soc BSPI interrupt */ | |
1046 | soc_intc->bcm_qspi_int_ack(soc_intc, BSPI_DONE); | |
4e3b2d23 KD |
1047 | } |
1048 | ||
cc20a386 | 1049 | status &= INTR_BSPI_LR_SESSION_DONE_MASK; |
5f195ee7 | 1050 | if (qspi->bspi_enabled && status && qspi->bspi_rf_op_len == 0) |
4e3b2d23 KD |
1051 | complete(&qspi->bspi_done); |
1052 | ||
1053 | return IRQ_HANDLED; | |
1054 | } | |
1055 | ||
1056 | static irqreturn_t bcm_qspi_bspi_lr_err_l2_isr(int irq, void *dev_id) | |
1057 | { | |
1058 | struct bcm_qspi_dev_id *qspi_dev_id = dev_id; | |
1059 | struct bcm_qspi *qspi = qspi_dev_id->dev; | |
cc20a386 | 1060 | struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc; |
4e3b2d23 KD |
1061 | |
1062 | dev_err(&qspi->pdev->dev, "BSPI INT error\n"); | |
5f195ee7 | 1063 | qspi->bspi_rf_op_status = -EIO; |
cc20a386 KD |
1064 | if (qspi->soc_intc) |
1065 | /* clear soc interrupt */ | |
1066 | soc_intc->bcm_qspi_int_ack(soc_intc, BSPI_ERR); | |
1067 | ||
4e3b2d23 KD |
1068 | complete(&qspi->bspi_done); |
1069 | return IRQ_HANDLED; | |
fa236a7e KD |
1070 | } |
1071 | ||
cc20a386 KD |
1072 | static irqreturn_t bcm_qspi_l1_isr(int irq, void *dev_id) |
1073 | { | |
1074 | struct bcm_qspi_dev_id *qspi_dev_id = dev_id; | |
1075 | struct bcm_qspi *qspi = qspi_dev_id->dev; | |
1076 | struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc; | |
1077 | irqreturn_t ret = IRQ_NONE; | |
1078 | ||
1079 | if (soc_intc) { | |
1080 | u32 status = soc_intc->bcm_qspi_get_int_status(soc_intc); | |
1081 | ||
1082 | if (status & MSPI_DONE) | |
1083 | ret = bcm_qspi_mspi_l2_isr(irq, dev_id); | |
1084 | else if (status & BSPI_DONE) | |
1085 | ret = bcm_qspi_bspi_lr_l2_isr(irq, dev_id); | |
1086 | else if (status & BSPI_ERR) | |
1087 | ret = bcm_qspi_bspi_lr_err_l2_isr(irq, dev_id); | |
1088 | } | |
1089 | ||
1090 | return ret; | |
1091 | } | |
1092 | ||
fa236a7e | 1093 | static const struct bcm_qspi_irq qspi_irq_tab[] = { |
4e3b2d23 KD |
1094 | { |
1095 | .irq_name = "spi_lr_fullness_reached", | |
1096 | .irq_handler = bcm_qspi_bspi_lr_l2_isr, | |
1097 | .mask = INTR_BSPI_LR_FULLNESS_REACHED_MASK, | |
1098 | }, | |
1099 | { | |
1100 | .irq_name = "spi_lr_session_aborted", | |
1101 | .irq_handler = bcm_qspi_bspi_lr_err_l2_isr, | |
1102 | .mask = INTR_BSPI_LR_SESSION_ABORTED_MASK, | |
1103 | }, | |
1104 | { | |
1105 | .irq_name = "spi_lr_impatient", | |
1106 | .irq_handler = bcm_qspi_bspi_lr_err_l2_isr, | |
1107 | .mask = INTR_BSPI_LR_IMPATIENT_MASK, | |
1108 | }, | |
1109 | { | |
1110 | .irq_name = "spi_lr_session_done", | |
1111 | .irq_handler = bcm_qspi_bspi_lr_l2_isr, | |
1112 | .mask = INTR_BSPI_LR_SESSION_DONE_MASK, | |
1113 | }, | |
1114 | #ifdef QSPI_INT_DEBUG | |
1115 | /* this interrupt is for debug purposes only, dont request irq */ | |
1116 | { | |
1117 | .irq_name = "spi_lr_overread", | |
1118 | .irq_handler = bcm_qspi_bspi_lr_err_l2_isr, | |
1119 | .mask = INTR_BSPI_LR_OVERREAD_MASK, | |
1120 | }, | |
1121 | #endif | |
fa236a7e KD |
1122 | { |
1123 | .irq_name = "mspi_done", | |
1124 | .irq_handler = bcm_qspi_mspi_l2_isr, | |
1125 | .mask = INTR_MSPI_DONE_MASK, | |
1126 | }, | |
1127 | { | |
1128 | .irq_name = "mspi_halted", | |
1129 | .irq_handler = bcm_qspi_mspi_l2_isr, | |
1130 | .mask = INTR_MSPI_HALTED_MASK, | |
1131 | }, | |
cc20a386 KD |
1132 | { |
1133 | /* single muxed L1 interrupt source */ | |
1134 | .irq_name = "spi_l1_intr", | |
1135 | .irq_handler = bcm_qspi_l1_isr, | |
1136 | .irq_source = MUXED_L1, | |
1137 | .mask = QSPI_INTERRUPTS_ALL, | |
1138 | }, | |
fa236a7e KD |
1139 | }; |
1140 | ||
4e3b2d23 KD |
1141 | static void bcm_qspi_bspi_init(struct bcm_qspi *qspi) |
1142 | { | |
1143 | u32 val = 0; | |
1144 | ||
1145 | val = bcm_qspi_read(qspi, BSPI, BSPI_REVISION_ID); | |
1146 | qspi->bspi_maj_rev = (val >> 8) & 0xff; | |
1147 | qspi->bspi_min_rev = val & 0xff; | |
1148 | if (!(bcm_qspi_bspi_ver_three(qspi))) { | |
1149 | /* Force mapping of BSPI address -> flash offset */ | |
1150 | bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_VALUE, 0); | |
1151 | bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_ENABLE, 1); | |
1152 | } | |
1153 | qspi->bspi_enabled = 1; | |
1154 | bcm_qspi_disable_bspi(qspi); | |
1155 | bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0); | |
1156 | bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0); | |
1157 | } | |
1158 | ||
fa236a7e KD |
1159 | static void bcm_qspi_hw_init(struct bcm_qspi *qspi) |
1160 | { | |
1161 | struct bcm_qspi_parms parms; | |
1162 | ||
1163 | bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 0); | |
1164 | bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_MSB, 0); | |
1165 | bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0); | |
1166 | bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, 0); | |
1167 | bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0x20); | |
1168 | ||
1169 | parms.mode = SPI_MODE_3; | |
1170 | parms.bits_per_word = 8; | |
1171 | parms.speed_hz = qspi->max_speed_hz; | |
1172 | bcm_qspi_hw_set_parms(qspi, &parms); | |
4e3b2d23 KD |
1173 | |
1174 | if (has_bspi(qspi)) | |
1175 | bcm_qspi_bspi_init(qspi); | |
fa236a7e KD |
1176 | } |
1177 | ||
1178 | static void bcm_qspi_hw_uninit(struct bcm_qspi *qspi) | |
1179 | { | |
1180 | bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0); | |
4e3b2d23 KD |
1181 | if (has_bspi(qspi)) |
1182 | bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0); | |
1183 | ||
fa236a7e KD |
1184 | } |
1185 | ||
5f195ee7 | 1186 | static const struct spi_controller_mem_ops bcm_qspi_mem_ops = { |
b6456057 | 1187 | .exec_op = bcm_qspi_exec_mem_op, |
5f195ee7 BB |
1188 | }; |
1189 | ||
fa236a7e KD |
1190 | static const struct of_device_id bcm_qspi_of_match[] = { |
1191 | { .compatible = "brcm,spi-bcm-qspi" }, | |
1192 | {}, | |
1193 | }; | |
1194 | MODULE_DEVICE_TABLE(of, bcm_qspi_of_match); | |
1195 | ||
1196 | int bcm_qspi_probe(struct platform_device *pdev, | |
4e3b2d23 | 1197 | struct bcm_qspi_soc_intc *soc_intc) |
fa236a7e KD |
1198 | { |
1199 | struct device *dev = &pdev->dev; | |
1200 | struct bcm_qspi *qspi; | |
1201 | struct spi_master *master; | |
1202 | struct resource *res; | |
1203 | int irq, ret = 0, num_ints = 0; | |
1204 | u32 val; | |
1205 | const char *name = NULL; | |
1206 | int num_irqs = ARRAY_SIZE(qspi_irq_tab); | |
1207 | ||
1208 | /* We only support device-tree instantiation */ | |
1209 | if (!dev->of_node) | |
1210 | return -ENODEV; | |
1211 | ||
1212 | if (!of_match_node(bcm_qspi_of_match, dev->of_node)) | |
1213 | return -ENODEV; | |
1214 | ||
1215 | master = spi_alloc_master(dev, sizeof(struct bcm_qspi)); | |
1216 | if (!master) { | |
1217 | dev_err(dev, "error allocating spi_master\n"); | |
1218 | return -ENOMEM; | |
1219 | } | |
1220 | ||
1221 | qspi = spi_master_get_devdata(master); | |
1222 | qspi->pdev = pdev; | |
1223 | qspi->trans_pos.trans = NULL; | |
1224 | qspi->trans_pos.byte = 0; | |
81ab52fd | 1225 | qspi->trans_pos.mspi_last_trans = true; |
fa236a7e KD |
1226 | qspi->master = master; |
1227 | ||
1228 | master->bus_num = -1; | |
1229 | master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_RX_DUAL | SPI_RX_QUAD; | |
1230 | master->setup = bcm_qspi_setup; | |
1231 | master->transfer_one = bcm_qspi_transfer_one; | |
5f195ee7 | 1232 | master->mem_ops = &bcm_qspi_mem_ops; |
fa236a7e KD |
1233 | master->cleanup = bcm_qspi_cleanup; |
1234 | master->dev.of_node = dev->of_node; | |
1235 | master->num_chipselect = NUM_CHIPSELECT; | |
1236 | ||
1237 | qspi->big_endian = of_device_is_big_endian(dev->of_node); | |
1238 | ||
1239 | if (!of_property_read_u32(dev->of_node, "num-cs", &val)) | |
1240 | master->num_chipselect = val; | |
1241 | ||
1242 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hif_mspi"); | |
1243 | if (!res) | |
1244 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
1245 | "mspi"); | |
1246 | ||
1247 | if (res) { | |
1248 | qspi->base[MSPI] = devm_ioremap_resource(dev, res); | |
1249 | if (IS_ERR(qspi->base[MSPI])) { | |
1250 | ret = PTR_ERR(qspi->base[MSPI]); | |
bc3cc752 | 1251 | goto qspi_resource_err; |
fa236a7e KD |
1252 | } |
1253 | } else { | |
c0368e4d | 1254 | goto qspi_resource_err; |
fa236a7e KD |
1255 | } |
1256 | ||
4e3b2d23 KD |
1257 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bspi"); |
1258 | if (res) { | |
1259 | qspi->base[BSPI] = devm_ioremap_resource(dev, res); | |
1260 | if (IS_ERR(qspi->base[BSPI])) { | |
1261 | ret = PTR_ERR(qspi->base[BSPI]); | |
bc3cc752 | 1262 | goto qspi_resource_err; |
4e3b2d23 KD |
1263 | } |
1264 | qspi->bspi_mode = true; | |
1265 | } else { | |
1266 | qspi->bspi_mode = false; | |
1267 | } | |
1268 | ||
1269 | dev_info(dev, "using %smspi mode\n", qspi->bspi_mode ? "bspi-" : ""); | |
1270 | ||
fa236a7e KD |
1271 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs_reg"); |
1272 | if (res) { | |
1273 | qspi->base[CHIP_SELECT] = devm_ioremap_resource(dev, res); | |
1274 | if (IS_ERR(qspi->base[CHIP_SELECT])) { | |
1275 | ret = PTR_ERR(qspi->base[CHIP_SELECT]); | |
c0368e4d | 1276 | goto qspi_resource_err; |
fa236a7e KD |
1277 | } |
1278 | } | |
1279 | ||
1280 | qspi->dev_ids = kcalloc(num_irqs, sizeof(struct bcm_qspi_dev_id), | |
1281 | GFP_KERNEL); | |
3bf3eb2b WY |
1282 | if (!qspi->dev_ids) { |
1283 | ret = -ENOMEM; | |
c0368e4d | 1284 | goto qspi_resource_err; |
fa236a7e KD |
1285 | } |
1286 | ||
1287 | for (val = 0; val < num_irqs; val++) { | |
1288 | irq = -1; | |
1289 | name = qspi_irq_tab[val].irq_name; | |
cc20a386 KD |
1290 | if (qspi_irq_tab[val].irq_source == SINGLE_L2) { |
1291 | /* get the l2 interrupts */ | |
1292 | irq = platform_get_irq_byname(pdev, name); | |
1293 | } else if (!num_ints && soc_intc) { | |
1294 | /* all mspi, bspi intrs muxed to one L1 intr */ | |
1295 | irq = platform_get_irq(pdev, 0); | |
1296 | } | |
fa236a7e KD |
1297 | |
1298 | if (irq >= 0) { | |
1299 | ret = devm_request_irq(&pdev->dev, irq, | |
1300 | qspi_irq_tab[val].irq_handler, 0, | |
1301 | name, | |
1302 | &qspi->dev_ids[val]); | |
1303 | if (ret < 0) { | |
1304 | dev_err(&pdev->dev, "IRQ %s not found\n", name); | |
1305 | goto qspi_probe_err; | |
1306 | } | |
1307 | ||
1308 | qspi->dev_ids[val].dev = qspi; | |
1309 | qspi->dev_ids[val].irqp = &qspi_irq_tab[val]; | |
1310 | num_ints++; | |
1311 | dev_dbg(&pdev->dev, "registered IRQ %s %d\n", | |
1312 | qspi_irq_tab[val].irq_name, | |
1313 | irq); | |
1314 | } | |
1315 | } | |
1316 | ||
1317 | if (!num_ints) { | |
1318 | dev_err(&pdev->dev, "no IRQs registered, cannot init driver\n"); | |
71b8f350 | 1319 | ret = -EINVAL; |
fa236a7e KD |
1320 | goto qspi_probe_err; |
1321 | } | |
1322 | ||
cc20a386 KD |
1323 | /* |
1324 | * Some SoCs integrate spi controller (e.g., its interrupt bits) | |
1325 | * in specific ways | |
1326 | */ | |
1327 | if (soc_intc) { | |
1328 | qspi->soc_intc = soc_intc; | |
1329 | soc_intc->bcm_qspi_int_set(soc_intc, MSPI_DONE, true); | |
1330 | } else { | |
1331 | qspi->soc_intc = NULL; | |
1332 | } | |
1333 | ||
fa236a7e KD |
1334 | qspi->clk = devm_clk_get(&pdev->dev, NULL); |
1335 | if (IS_ERR(qspi->clk)) { | |
1336 | dev_warn(dev, "unable to get clock\n"); | |
71b8f350 | 1337 | ret = PTR_ERR(qspi->clk); |
fa236a7e KD |
1338 | goto qspi_probe_err; |
1339 | } | |
1340 | ||
1341 | ret = clk_prepare_enable(qspi->clk); | |
1342 | if (ret) { | |
1343 | dev_err(dev, "failed to prepare clock\n"); | |
1344 | goto qspi_probe_err; | |
1345 | } | |
1346 | ||
1347 | qspi->base_clk = clk_get_rate(qspi->clk); | |
1348 | qspi->max_speed_hz = qspi->base_clk / (QSPI_SPBR_MIN * 2); | |
1349 | ||
1350 | bcm_qspi_hw_init(qspi); | |
1351 | init_completion(&qspi->mspi_done); | |
4e3b2d23 | 1352 | init_completion(&qspi->bspi_done); |
fa236a7e KD |
1353 | qspi->curr_cs = -1; |
1354 | ||
1355 | platform_set_drvdata(pdev, qspi); | |
4e3b2d23 KD |
1356 | |
1357 | qspi->xfer_mode.width = -1; | |
1358 | qspi->xfer_mode.addrlen = -1; | |
1359 | qspi->xfer_mode.hp = -1; | |
1360 | ||
fa236a7e KD |
1361 | ret = devm_spi_register_master(&pdev->dev, master); |
1362 | if (ret < 0) { | |
1363 | dev_err(dev, "can't register master\n"); | |
1364 | goto qspi_reg_err; | |
1365 | } | |
1366 | ||
1367 | return 0; | |
1368 | ||
1369 | qspi_reg_err: | |
1370 | bcm_qspi_hw_uninit(qspi); | |
1371 | clk_disable_unprepare(qspi->clk); | |
1372 | qspi_probe_err: | |
fa236a7e | 1373 | kfree(qspi->dev_ids); |
c0368e4d FF |
1374 | qspi_resource_err: |
1375 | spi_master_put(master); | |
fa236a7e KD |
1376 | return ret; |
1377 | } | |
1378 | /* probe function to be called by SoC specific platform driver probe */ | |
1379 | EXPORT_SYMBOL_GPL(bcm_qspi_probe); | |
1380 | ||
1381 | int bcm_qspi_remove(struct platform_device *pdev) | |
1382 | { | |
1383 | struct bcm_qspi *qspi = platform_get_drvdata(pdev); | |
1384 | ||
fa236a7e KD |
1385 | bcm_qspi_hw_uninit(qspi); |
1386 | clk_disable_unprepare(qspi->clk); | |
1387 | kfree(qspi->dev_ids); | |
1388 | spi_unregister_master(qspi->master); | |
1389 | ||
1390 | return 0; | |
1391 | } | |
1392 | /* function to be called by SoC specific platform driver remove() */ | |
1393 | EXPORT_SYMBOL_GPL(bcm_qspi_remove); | |
1394 | ||
a0319f8b | 1395 | static int __maybe_unused bcm_qspi_suspend(struct device *dev) |
fa236a7e KD |
1396 | { |
1397 | struct bcm_qspi *qspi = dev_get_drvdata(dev); | |
1398 | ||
054e532f KD |
1399 | /* store the override strap value */ |
1400 | if (!bcm_qspi_bspi_ver_three(qspi)) | |
1401 | qspi->s3_strap_override_ctrl = | |
1402 | bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL); | |
1403 | ||
fa236a7e KD |
1404 | spi_master_suspend(qspi->master); |
1405 | clk_disable(qspi->clk); | |
1406 | bcm_qspi_hw_uninit(qspi); | |
1407 | ||
1408 | return 0; | |
1409 | }; | |
1410 | ||
a0319f8b | 1411 | static int __maybe_unused bcm_qspi_resume(struct device *dev) |
fa236a7e KD |
1412 | { |
1413 | struct bcm_qspi *qspi = dev_get_drvdata(dev); | |
1414 | int ret = 0; | |
1415 | ||
1416 | bcm_qspi_hw_init(qspi); | |
1417 | bcm_qspi_chip_select(qspi, qspi->curr_cs); | |
cc20a386 KD |
1418 | if (qspi->soc_intc) |
1419 | /* enable MSPI interrupt */ | |
1420 | qspi->soc_intc->bcm_qspi_int_set(qspi->soc_intc, MSPI_DONE, | |
1421 | true); | |
1422 | ||
fa236a7e KD |
1423 | ret = clk_enable(qspi->clk); |
1424 | if (!ret) | |
1425 | spi_master_resume(qspi->master); | |
1426 | ||
1427 | return ret; | |
1428 | } | |
fa236a7e | 1429 | |
a0319f8b AB |
1430 | SIMPLE_DEV_PM_OPS(bcm_qspi_pm_ops, bcm_qspi_suspend, bcm_qspi_resume); |
1431 | ||
fa236a7e KD |
1432 | /* pm_ops to be called by SoC specific platform driver */ |
1433 | EXPORT_SYMBOL_GPL(bcm_qspi_pm_ops); | |
1434 | ||
1435 | MODULE_AUTHOR("Kamal Dasu"); | |
1436 | MODULE_DESCRIPTION("Broadcom QSPI driver"); | |
1437 | MODULE_LICENSE("GPL v2"); | |
1438 | MODULE_ALIAS("platform:" DRIVER_NAME); |