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fda8d26e | 1 | // SPDX-License-Identifier: GPL-2.0-only |
b1353d1c LPC |
2 | /* |
3 | * SPI-Engine SPI controller driver | |
4 | * Copyright 2015 Analog Devices Inc. | |
5 | * Author: Lars-Peter Clausen <lars@metafoo.de> | |
b1353d1c LPC |
6 | */ |
7 | ||
8 | #include <linux/clk.h> | |
9 | #include <linux/interrupt.h> | |
10 | #include <linux/io.h> | |
11 | #include <linux/of.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/spi/spi.h> | |
15 | ||
16 | #define SPI_ENGINE_VERSION_MAJOR(x) ((x >> 16) & 0xff) | |
17 | #define SPI_ENGINE_VERSION_MINOR(x) ((x >> 8) & 0xff) | |
18 | #define SPI_ENGINE_VERSION_PATCH(x) (x & 0xff) | |
19 | ||
20 | #define SPI_ENGINE_REG_VERSION 0x00 | |
21 | ||
22 | #define SPI_ENGINE_REG_RESET 0x40 | |
23 | ||
24 | #define SPI_ENGINE_REG_INT_ENABLE 0x80 | |
25 | #define SPI_ENGINE_REG_INT_PENDING 0x84 | |
26 | #define SPI_ENGINE_REG_INT_SOURCE 0x88 | |
27 | ||
28 | #define SPI_ENGINE_REG_SYNC_ID 0xc0 | |
29 | ||
30 | #define SPI_ENGINE_REG_CMD_FIFO_ROOM 0xd0 | |
31 | #define SPI_ENGINE_REG_SDO_FIFO_ROOM 0xd4 | |
32 | #define SPI_ENGINE_REG_SDI_FIFO_LEVEL 0xd8 | |
33 | ||
34 | #define SPI_ENGINE_REG_CMD_FIFO 0xe0 | |
35 | #define SPI_ENGINE_REG_SDO_DATA_FIFO 0xe4 | |
36 | #define SPI_ENGINE_REG_SDI_DATA_FIFO 0xe8 | |
37 | #define SPI_ENGINE_REG_SDI_DATA_FIFO_PEEK 0xec | |
38 | ||
39 | #define SPI_ENGINE_INT_CMD_ALMOST_EMPTY BIT(0) | |
40 | #define SPI_ENGINE_INT_SDO_ALMOST_EMPTY BIT(1) | |
41 | #define SPI_ENGINE_INT_SDI_ALMOST_FULL BIT(2) | |
42 | #define SPI_ENGINE_INT_SYNC BIT(3) | |
43 | ||
44 | #define SPI_ENGINE_CONFIG_CPHA BIT(0) | |
45 | #define SPI_ENGINE_CONFIG_CPOL BIT(1) | |
46 | #define SPI_ENGINE_CONFIG_3WIRE BIT(2) | |
47 | ||
48 | #define SPI_ENGINE_INST_TRANSFER 0x0 | |
49 | #define SPI_ENGINE_INST_ASSERT 0x1 | |
50 | #define SPI_ENGINE_INST_WRITE 0x2 | |
51 | #define SPI_ENGINE_INST_MISC 0x3 | |
52 | ||
53 | #define SPI_ENGINE_CMD_REG_CLK_DIV 0x0 | |
54 | #define SPI_ENGINE_CMD_REG_CONFIG 0x1 | |
55 | ||
56 | #define SPI_ENGINE_MISC_SYNC 0x0 | |
57 | #define SPI_ENGINE_MISC_SLEEP 0x1 | |
58 | ||
59 | #define SPI_ENGINE_TRANSFER_WRITE 0x1 | |
60 | #define SPI_ENGINE_TRANSFER_READ 0x2 | |
61 | ||
62 | #define SPI_ENGINE_CMD(inst, arg1, arg2) \ | |
63 | (((inst) << 12) | ((arg1) << 8) | (arg2)) | |
64 | ||
65 | #define SPI_ENGINE_CMD_TRANSFER(flags, n) \ | |
66 | SPI_ENGINE_CMD(SPI_ENGINE_INST_TRANSFER, (flags), (n)) | |
67 | #define SPI_ENGINE_CMD_ASSERT(delay, cs) \ | |
68 | SPI_ENGINE_CMD(SPI_ENGINE_INST_ASSERT, (delay), (cs)) | |
69 | #define SPI_ENGINE_CMD_WRITE(reg, val) \ | |
70 | SPI_ENGINE_CMD(SPI_ENGINE_INST_WRITE, (reg), (val)) | |
71 | #define SPI_ENGINE_CMD_SLEEP(delay) \ | |
72 | SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, SPI_ENGINE_MISC_SLEEP, (delay)) | |
73 | #define SPI_ENGINE_CMD_SYNC(id) \ | |
74 | SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, SPI_ENGINE_MISC_SYNC, (id)) | |
75 | ||
76 | struct spi_engine_program { | |
77 | unsigned int length; | |
78 | uint16_t instructions[]; | |
79 | }; | |
80 | ||
81 | struct spi_engine { | |
82 | struct clk *clk; | |
83 | struct clk *ref_clk; | |
84 | ||
85 | spinlock_t lock; | |
86 | ||
87 | void __iomem *base; | |
88 | ||
89 | struct spi_message *msg; | |
90 | struct spi_engine_program *p; | |
91 | unsigned cmd_length; | |
92 | const uint16_t *cmd_buf; | |
93 | ||
94 | struct spi_transfer *tx_xfer; | |
95 | unsigned int tx_length; | |
96 | const uint8_t *tx_buf; | |
97 | ||
98 | struct spi_transfer *rx_xfer; | |
99 | unsigned int rx_length; | |
100 | uint8_t *rx_buf; | |
101 | ||
102 | unsigned int sync_id; | |
103 | unsigned int completed_id; | |
104 | ||
105 | unsigned int int_enable; | |
106 | }; | |
107 | ||
108 | static void spi_engine_program_add_cmd(struct spi_engine_program *p, | |
109 | bool dry, uint16_t cmd) | |
110 | { | |
111 | if (!dry) | |
112 | p->instructions[p->length] = cmd; | |
113 | p->length++; | |
114 | } | |
115 | ||
116 | static unsigned int spi_engine_get_config(struct spi_device *spi) | |
117 | { | |
118 | unsigned int config = 0; | |
119 | ||
120 | if (spi->mode & SPI_CPOL) | |
121 | config |= SPI_ENGINE_CONFIG_CPOL; | |
122 | if (spi->mode & SPI_CPHA) | |
123 | config |= SPI_ENGINE_CONFIG_CPHA; | |
124 | if (spi->mode & SPI_3WIRE) | |
125 | config |= SPI_ENGINE_CONFIG_3WIRE; | |
126 | ||
127 | return config; | |
128 | } | |
129 | ||
130 | static unsigned int spi_engine_get_clk_div(struct spi_engine *spi_engine, | |
131 | struct spi_device *spi, struct spi_transfer *xfer) | |
132 | { | |
133 | unsigned int clk_div; | |
134 | ||
135 | clk_div = DIV_ROUND_UP(clk_get_rate(spi_engine->ref_clk), | |
136 | xfer->speed_hz * 2); | |
137 | if (clk_div > 255) | |
138 | clk_div = 255; | |
139 | else if (clk_div > 0) | |
140 | clk_div -= 1; | |
141 | ||
142 | return clk_div; | |
143 | } | |
144 | ||
145 | static void spi_engine_gen_xfer(struct spi_engine_program *p, bool dry, | |
146 | struct spi_transfer *xfer) | |
147 | { | |
148 | unsigned int len = xfer->len; | |
149 | ||
150 | while (len) { | |
151 | unsigned int n = min(len, 256U); | |
152 | unsigned int flags = 0; | |
153 | ||
154 | if (xfer->tx_buf) | |
155 | flags |= SPI_ENGINE_TRANSFER_WRITE; | |
156 | if (xfer->rx_buf) | |
157 | flags |= SPI_ENGINE_TRANSFER_READ; | |
158 | ||
159 | spi_engine_program_add_cmd(p, dry, | |
160 | SPI_ENGINE_CMD_TRANSFER(flags, n - 1)); | |
161 | len -= n; | |
162 | } | |
163 | } | |
164 | ||
165 | static void spi_engine_gen_sleep(struct spi_engine_program *p, bool dry, | |
166 | struct spi_engine *spi_engine, unsigned int clk_div, unsigned int delay) | |
167 | { | |
168 | unsigned int spi_clk = clk_get_rate(spi_engine->ref_clk); | |
169 | unsigned int t; | |
170 | ||
171 | if (delay == 0) | |
172 | return; | |
173 | ||
174 | t = DIV_ROUND_UP(delay * spi_clk, (clk_div + 1) * 2); | |
175 | while (t) { | |
176 | unsigned int n = min(t, 256U); | |
177 | ||
178 | spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_SLEEP(n - 1)); | |
179 | t -= n; | |
180 | } | |
181 | } | |
182 | ||
183 | static void spi_engine_gen_cs(struct spi_engine_program *p, bool dry, | |
184 | struct spi_device *spi, bool assert) | |
185 | { | |
186 | unsigned int mask = 0xff; | |
187 | ||
188 | if (assert) | |
189 | mask ^= BIT(spi->chip_select); | |
190 | ||
191 | spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_ASSERT(1, mask)); | |
192 | } | |
193 | ||
194 | static int spi_engine_compile_message(struct spi_engine *spi_engine, | |
195 | struct spi_message *msg, bool dry, struct spi_engine_program *p) | |
196 | { | |
197 | struct spi_device *spi = msg->spi; | |
198 | struct spi_transfer *xfer; | |
199 | int clk_div, new_clk_div; | |
200 | bool cs_change = true; | |
201 | ||
202 | clk_div = -1; | |
203 | ||
204 | spi_engine_program_add_cmd(p, dry, | |
205 | SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CONFIG, | |
206 | spi_engine_get_config(spi))); | |
207 | ||
208 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | |
209 | new_clk_div = spi_engine_get_clk_div(spi_engine, spi, xfer); | |
210 | if (new_clk_div != clk_div) { | |
211 | clk_div = new_clk_div; | |
212 | spi_engine_program_add_cmd(p, dry, | |
213 | SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CLK_DIV, | |
214 | clk_div)); | |
215 | } | |
216 | ||
217 | if (cs_change) | |
218 | spi_engine_gen_cs(p, dry, spi, true); | |
219 | ||
220 | spi_engine_gen_xfer(p, dry, xfer); | |
221 | spi_engine_gen_sleep(p, dry, spi_engine, clk_div, | |
222 | xfer->delay_usecs); | |
223 | ||
224 | cs_change = xfer->cs_change; | |
225 | if (list_is_last(&xfer->transfer_list, &msg->transfers)) | |
226 | cs_change = !cs_change; | |
227 | ||
228 | if (cs_change) | |
229 | spi_engine_gen_cs(p, dry, spi, false); | |
230 | } | |
231 | ||
232 | return 0; | |
233 | } | |
234 | ||
235 | static void spi_engine_xfer_next(struct spi_engine *spi_engine, | |
236 | struct spi_transfer **_xfer) | |
237 | { | |
238 | struct spi_message *msg = spi_engine->msg; | |
239 | struct spi_transfer *xfer = *_xfer; | |
240 | ||
241 | if (!xfer) { | |
242 | xfer = list_first_entry(&msg->transfers, | |
243 | struct spi_transfer, transfer_list); | |
244 | } else if (list_is_last(&xfer->transfer_list, &msg->transfers)) { | |
245 | xfer = NULL; | |
246 | } else { | |
247 | xfer = list_next_entry(xfer, transfer_list); | |
248 | } | |
249 | ||
250 | *_xfer = xfer; | |
251 | } | |
252 | ||
253 | static void spi_engine_tx_next(struct spi_engine *spi_engine) | |
254 | { | |
255 | struct spi_transfer *xfer = spi_engine->tx_xfer; | |
256 | ||
257 | do { | |
258 | spi_engine_xfer_next(spi_engine, &xfer); | |
259 | } while (xfer && !xfer->tx_buf); | |
260 | ||
261 | spi_engine->tx_xfer = xfer; | |
262 | if (xfer) { | |
263 | spi_engine->tx_length = xfer->len; | |
264 | spi_engine->tx_buf = xfer->tx_buf; | |
265 | } else { | |
266 | spi_engine->tx_buf = NULL; | |
267 | } | |
268 | } | |
269 | ||
270 | static void spi_engine_rx_next(struct spi_engine *spi_engine) | |
271 | { | |
272 | struct spi_transfer *xfer = spi_engine->rx_xfer; | |
273 | ||
274 | do { | |
275 | spi_engine_xfer_next(spi_engine, &xfer); | |
276 | } while (xfer && !xfer->rx_buf); | |
277 | ||
278 | spi_engine->rx_xfer = xfer; | |
279 | if (xfer) { | |
280 | spi_engine->rx_length = xfer->len; | |
281 | spi_engine->rx_buf = xfer->rx_buf; | |
282 | } else { | |
283 | spi_engine->rx_buf = NULL; | |
284 | } | |
285 | } | |
286 | ||
287 | static bool spi_engine_write_cmd_fifo(struct spi_engine *spi_engine) | |
288 | { | |
289 | void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_CMD_FIFO; | |
290 | unsigned int n, m, i; | |
291 | const uint16_t *buf; | |
292 | ||
293 | n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_CMD_FIFO_ROOM); | |
294 | while (n && spi_engine->cmd_length) { | |
295 | m = min(n, spi_engine->cmd_length); | |
296 | buf = spi_engine->cmd_buf; | |
297 | for (i = 0; i < m; i++) | |
298 | writel_relaxed(buf[i], addr); | |
299 | spi_engine->cmd_buf += m; | |
300 | spi_engine->cmd_length -= m; | |
301 | n -= m; | |
302 | } | |
303 | ||
304 | return spi_engine->cmd_length != 0; | |
305 | } | |
306 | ||
307 | static bool spi_engine_write_tx_fifo(struct spi_engine *spi_engine) | |
308 | { | |
309 | void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_SDO_DATA_FIFO; | |
310 | unsigned int n, m, i; | |
311 | const uint8_t *buf; | |
312 | ||
313 | n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_SDO_FIFO_ROOM); | |
314 | while (n && spi_engine->tx_length) { | |
315 | m = min(n, spi_engine->tx_length); | |
316 | buf = spi_engine->tx_buf; | |
317 | for (i = 0; i < m; i++) | |
318 | writel_relaxed(buf[i], addr); | |
319 | spi_engine->tx_buf += m; | |
320 | spi_engine->tx_length -= m; | |
321 | n -= m; | |
322 | if (spi_engine->tx_length == 0) | |
323 | spi_engine_tx_next(spi_engine); | |
324 | } | |
325 | ||
326 | return spi_engine->tx_length != 0; | |
327 | } | |
328 | ||
329 | static bool spi_engine_read_rx_fifo(struct spi_engine *spi_engine) | |
330 | { | |
331 | void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_SDI_DATA_FIFO; | |
332 | unsigned int n, m, i; | |
333 | uint8_t *buf; | |
334 | ||
335 | n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_SDI_FIFO_LEVEL); | |
336 | while (n && spi_engine->rx_length) { | |
337 | m = min(n, spi_engine->rx_length); | |
338 | buf = spi_engine->rx_buf; | |
339 | for (i = 0; i < m; i++) | |
340 | buf[i] = readl_relaxed(addr); | |
341 | spi_engine->rx_buf += m; | |
342 | spi_engine->rx_length -= m; | |
343 | n -= m; | |
344 | if (spi_engine->rx_length == 0) | |
345 | spi_engine_rx_next(spi_engine); | |
346 | } | |
347 | ||
348 | return spi_engine->rx_length != 0; | |
349 | } | |
350 | ||
351 | static irqreturn_t spi_engine_irq(int irq, void *devid) | |
352 | { | |
353 | struct spi_master *master = devid; | |
354 | struct spi_engine *spi_engine = spi_master_get_devdata(master); | |
355 | unsigned int disable_int = 0; | |
356 | unsigned int pending; | |
357 | ||
358 | pending = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_INT_PENDING); | |
359 | ||
360 | if (pending & SPI_ENGINE_INT_SYNC) { | |
361 | writel_relaxed(SPI_ENGINE_INT_SYNC, | |
362 | spi_engine->base + SPI_ENGINE_REG_INT_PENDING); | |
363 | spi_engine->completed_id = readl_relaxed( | |
364 | spi_engine->base + SPI_ENGINE_REG_SYNC_ID); | |
365 | } | |
366 | ||
367 | spin_lock(&spi_engine->lock); | |
368 | ||
369 | if (pending & SPI_ENGINE_INT_CMD_ALMOST_EMPTY) { | |
370 | if (!spi_engine_write_cmd_fifo(spi_engine)) | |
371 | disable_int |= SPI_ENGINE_INT_CMD_ALMOST_EMPTY; | |
372 | } | |
373 | ||
374 | if (pending & SPI_ENGINE_INT_SDO_ALMOST_EMPTY) { | |
375 | if (!spi_engine_write_tx_fifo(spi_engine)) | |
376 | disable_int |= SPI_ENGINE_INT_SDO_ALMOST_EMPTY; | |
377 | } | |
378 | ||
379 | if (pending & (SPI_ENGINE_INT_SDI_ALMOST_FULL | SPI_ENGINE_INT_SYNC)) { | |
380 | if (!spi_engine_read_rx_fifo(spi_engine)) | |
381 | disable_int |= SPI_ENGINE_INT_SDI_ALMOST_FULL; | |
382 | } | |
383 | ||
384 | if (pending & SPI_ENGINE_INT_SYNC) { | |
385 | if (spi_engine->msg && | |
386 | spi_engine->completed_id == spi_engine->sync_id) { | |
387 | struct spi_message *msg = spi_engine->msg; | |
388 | ||
389 | kfree(spi_engine->p); | |
390 | msg->status = 0; | |
391 | msg->actual_length = msg->frame_length; | |
392 | spi_engine->msg = NULL; | |
393 | spi_finalize_current_message(master); | |
394 | disable_int |= SPI_ENGINE_INT_SYNC; | |
395 | } | |
396 | } | |
397 | ||
398 | if (disable_int) { | |
399 | spi_engine->int_enable &= ~disable_int; | |
400 | writel_relaxed(spi_engine->int_enable, | |
401 | spi_engine->base + SPI_ENGINE_REG_INT_ENABLE); | |
402 | } | |
403 | ||
404 | spin_unlock(&spi_engine->lock); | |
405 | ||
406 | return IRQ_HANDLED; | |
407 | } | |
408 | ||
409 | static int spi_engine_transfer_one_message(struct spi_master *master, | |
410 | struct spi_message *msg) | |
411 | { | |
412 | struct spi_engine_program p_dry, *p; | |
413 | struct spi_engine *spi_engine = spi_master_get_devdata(master); | |
414 | unsigned int int_enable = 0; | |
415 | unsigned long flags; | |
416 | size_t size; | |
417 | ||
418 | p_dry.length = 0; | |
419 | spi_engine_compile_message(spi_engine, msg, true, &p_dry); | |
420 | ||
421 | size = sizeof(*p->instructions) * (p_dry.length + 1); | |
422 | p = kzalloc(sizeof(*p) + size, GFP_KERNEL); | |
423 | if (!p) | |
424 | return -ENOMEM; | |
425 | spi_engine_compile_message(spi_engine, msg, false, p); | |
426 | ||
427 | spin_lock_irqsave(&spi_engine->lock, flags); | |
428 | spi_engine->sync_id = (spi_engine->sync_id + 1) & 0xff; | |
429 | spi_engine_program_add_cmd(p, false, | |
430 | SPI_ENGINE_CMD_SYNC(spi_engine->sync_id)); | |
431 | ||
432 | spi_engine->msg = msg; | |
433 | spi_engine->p = p; | |
434 | ||
435 | spi_engine->cmd_buf = p->instructions; | |
436 | spi_engine->cmd_length = p->length; | |
437 | if (spi_engine_write_cmd_fifo(spi_engine)) | |
438 | int_enable |= SPI_ENGINE_INT_CMD_ALMOST_EMPTY; | |
439 | ||
440 | spi_engine_tx_next(spi_engine); | |
441 | if (spi_engine_write_tx_fifo(spi_engine)) | |
442 | int_enable |= SPI_ENGINE_INT_SDO_ALMOST_EMPTY; | |
443 | ||
444 | spi_engine_rx_next(spi_engine); | |
445 | if (spi_engine->rx_length != 0) | |
446 | int_enable |= SPI_ENGINE_INT_SDI_ALMOST_FULL; | |
447 | ||
448 | int_enable |= SPI_ENGINE_INT_SYNC; | |
449 | ||
450 | writel_relaxed(int_enable, | |
451 | spi_engine->base + SPI_ENGINE_REG_INT_ENABLE); | |
452 | spi_engine->int_enable = int_enable; | |
453 | spin_unlock_irqrestore(&spi_engine->lock, flags); | |
454 | ||
455 | return 0; | |
456 | } | |
457 | ||
458 | static int spi_engine_probe(struct platform_device *pdev) | |
459 | { | |
460 | struct spi_engine *spi_engine; | |
461 | struct spi_master *master; | |
462 | unsigned int version; | |
463 | struct resource *res; | |
464 | int irq; | |
465 | int ret; | |
466 | ||
467 | irq = platform_get_irq(pdev, 0); | |
468 | if (irq <= 0) | |
469 | return -ENXIO; | |
470 | ||
471 | spi_engine = devm_kzalloc(&pdev->dev, sizeof(*spi_engine), GFP_KERNEL); | |
472 | if (!spi_engine) | |
473 | return -ENOMEM; | |
474 | ||
475 | master = spi_alloc_master(&pdev->dev, 0); | |
476 | if (!master) | |
477 | return -ENOMEM; | |
478 | ||
479 | spi_master_set_devdata(master, spi_engine); | |
480 | ||
481 | spin_lock_init(&spi_engine->lock); | |
482 | ||
483 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
484 | spi_engine->base = devm_ioremap_resource(&pdev->dev, res); | |
485 | if (IS_ERR(spi_engine->base)) { | |
486 | ret = PTR_ERR(spi_engine->base); | |
487 | goto err_put_master; | |
488 | } | |
489 | ||
490 | version = readl(spi_engine->base + SPI_ENGINE_REG_VERSION); | |
491 | if (SPI_ENGINE_VERSION_MAJOR(version) != 1) { | |
492 | dev_err(&pdev->dev, "Unsupported peripheral version %u.%u.%c\n", | |
493 | SPI_ENGINE_VERSION_MAJOR(version), | |
494 | SPI_ENGINE_VERSION_MINOR(version), | |
495 | SPI_ENGINE_VERSION_PATCH(version)); | |
9620ca90 CJ |
496 | ret = -ENODEV; |
497 | goto err_put_master; | |
b1353d1c LPC |
498 | } |
499 | ||
500 | spi_engine->clk = devm_clk_get(&pdev->dev, "s_axi_aclk"); | |
501 | if (IS_ERR(spi_engine->clk)) { | |
502 | ret = PTR_ERR(spi_engine->clk); | |
503 | goto err_put_master; | |
504 | } | |
505 | ||
506 | spi_engine->ref_clk = devm_clk_get(&pdev->dev, "spi_clk"); | |
507 | if (IS_ERR(spi_engine->ref_clk)) { | |
508 | ret = PTR_ERR(spi_engine->ref_clk); | |
509 | goto err_put_master; | |
510 | } | |
511 | ||
512 | ret = clk_prepare_enable(spi_engine->clk); | |
513 | if (ret) | |
514 | goto err_put_master; | |
515 | ||
516 | ret = clk_prepare_enable(spi_engine->ref_clk); | |
517 | if (ret) | |
518 | goto err_clk_disable; | |
519 | ||
520 | writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_RESET); | |
521 | writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING); | |
522 | writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_INT_ENABLE); | |
523 | ||
524 | ret = request_irq(irq, spi_engine_irq, 0, pdev->name, master); | |
525 | if (ret) | |
526 | goto err_ref_clk_disable; | |
527 | ||
b1353d1c LPC |
528 | master->dev.of_node = pdev->dev.of_node; |
529 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_3WIRE; | |
530 | master->bits_per_word_mask = SPI_BPW_MASK(8); | |
531 | master->max_speed_hz = clk_get_rate(spi_engine->ref_clk) / 2; | |
532 | master->transfer_one_message = spi_engine_transfer_one_message; | |
533 | master->num_chipselect = 8; | |
534 | ||
535 | ret = spi_register_master(master); | |
536 | if (ret) | |
537 | goto err_free_irq; | |
538 | ||
539 | platform_set_drvdata(pdev, master); | |
540 | ||
541 | return 0; | |
542 | err_free_irq: | |
543 | free_irq(irq, master); | |
544 | err_ref_clk_disable: | |
545 | clk_disable_unprepare(spi_engine->ref_clk); | |
546 | err_clk_disable: | |
547 | clk_disable_unprepare(spi_engine->clk); | |
548 | err_put_master: | |
549 | spi_master_put(master); | |
550 | return ret; | |
551 | } | |
552 | ||
553 | static int spi_engine_remove(struct platform_device *pdev) | |
554 | { | |
4d5e0689 | 555 | struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); |
b1353d1c LPC |
556 | struct spi_engine *spi_engine = spi_master_get_devdata(master); |
557 | int irq = platform_get_irq(pdev, 0); | |
558 | ||
559 | spi_unregister_master(master); | |
560 | ||
561 | free_irq(irq, master); | |
562 | ||
4d5e0689 JH |
563 | spi_master_put(master); |
564 | ||
b1353d1c LPC |
565 | writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING); |
566 | writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_INT_ENABLE); | |
567 | writel_relaxed(0x01, spi_engine->base + SPI_ENGINE_REG_RESET); | |
568 | ||
569 | clk_disable_unprepare(spi_engine->ref_clk); | |
570 | clk_disable_unprepare(spi_engine->clk); | |
571 | ||
572 | return 0; | |
573 | } | |
574 | ||
575 | static const struct of_device_id spi_engine_match_table[] = { | |
576 | { .compatible = "adi,axi-spi-engine-1.00.a" }, | |
577 | { }, | |
578 | }; | |
01affe23 | 579 | MODULE_DEVICE_TABLE(of, spi_engine_match_table); |
b1353d1c LPC |
580 | |
581 | static struct platform_driver spi_engine_driver = { | |
582 | .probe = spi_engine_probe, | |
583 | .remove = spi_engine_remove, | |
584 | .driver = { | |
585 | .name = "spi-engine", | |
586 | .of_match_table = spi_engine_match_table, | |
587 | }, | |
588 | }; | |
589 | module_platform_driver(spi_engine_driver); | |
590 | ||
591 | MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); | |
592 | MODULE_DESCRIPTION("Analog Devices SPI engine peripheral driver"); | |
593 | MODULE_LICENSE("GPL"); |