[linux-block.git] / drivers / spi / spi-ath79.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
 *
 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
 *
 * This driver has been based on the spi-gpio.c:
 *	Copyright (C) 2006,2008 David Brownell
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/platform_data/spi-ath79.h>

#define DRV_NAME	"ath79-spi"

#define ATH79_SPI_RRW_DELAY_FACTOR	12000
#define MHZ				(1000 * 1000)

#define AR71XX_SPI_REG_FS		0x00	/* Function Select */
#define AR71XX_SPI_REG_CTRL		0x04	/* SPI Control */
#define AR71XX_SPI_REG_IOC		0x08	/* SPI I/O Control */
#define AR71XX_SPI_REG_RDS		0x0c	/* Read Data Shift */

#define AR71XX_SPI_FS_GPIO		BIT(0)	/* Enable GPIO mode */

#define AR71XX_SPI_IOC_DO		BIT(0)	/* Data Out pin */
#define AR71XX_SPI_IOC_CLK		BIT(8)	/* CLK pin */
#define AR71XX_SPI_IOC_CS(n)		BIT(16 + (n))

struct ath79_spi {
	struct spi_bitbang	bitbang;
	u32			ioc_base;
	u32			reg_ctrl;
	void __iomem		*base;
	struct clk		*clk;
	unsigned int		rrw_delay;
};

static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned int reg)
{
	return ioread32(sp->base + reg);
}

static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned int reg, u32 val)
{
	iowrite32(val, sp->base + reg);
}

static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
{
	return spi_master_get_devdata(spi->master);
}

static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned int nsecs)
{
	if (nsecs > sp->rrw_delay)
		ndelay(nsecs - sp->rrw_delay);
}

static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
{
	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
	int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
	u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);

	if (cs_high)
		sp->ioc_base |= cs_bit;
	else
		sp->ioc_base &= ~cs_bit;

	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
}

static void ath79_spi_enable(struct ath79_spi *sp)
{
	/* enable GPIO mode */
	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);

	/* save CTRL register */
	sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
	sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);

	/* clear clk and mosi in the base state */
	sp->ioc_base &= ~(AR71XX_SPI_IOC_DO | AR71XX_SPI_IOC_CLK);

	/* TODO: setup speed? */
	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
}

static void ath79_spi_disable(struct ath79_spi *sp)
{
	/* restore CTRL register */
	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
	/* disable GPIO mode */
	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
}

static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned int nsecs,
			       u32 word, u8 bits, unsigned flags)
{
	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
	u32 ioc = sp->ioc_base;

	/* clock starts at inactive polarity */
	for (word <<= (32 - bits); likely(bits); bits--) {
		u32 out;

		if (word & (1 << 31))
			out = ioc | AR71XX_SPI_IOC_DO;
		else
			out = ioc & ~AR71XX_SPI_IOC_DO;

		/* setup MSB (to slave) on trailing edge */
		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
		ath79_spi_delay(sp, nsecs);
		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
		ath79_spi_delay(sp, nsecs);
		if (bits == 1)
			ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);

		word <<= 1;
	}

	return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
}

static int ath79_spi_probe(struct platform_device *pdev)
{
	struct spi_master *master;
	struct ath79_spi *sp;
	struct ath79_spi_platform_data *pdata;
	struct resource	*r;
	unsigned long rate;
	int ret;

	master = spi_alloc_master(&pdev->dev, sizeof(*sp));
	if (master == NULL) {
		dev_err(&pdev->dev, "failed to allocate spi master\n");
		return -ENOMEM;
	}

	sp = spi_master_get_devdata(master);
	master->dev.of_node = pdev->dev.of_node;
	platform_set_drvdata(pdev, sp);

	pdata = dev_get_platdata(&pdev->dev);

	master->use_gpio_descriptors = true;
	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
	master->setup = spi_bitbang_setup;
	master->cleanup = spi_bitbang_cleanup;
	if (pdata) {
		master->bus_num = pdata->bus_num;
		master->num_chipselect = pdata->num_chipselect;
	}

	sp->bitbang.master = master;
	sp->bitbang.chipselect = ath79_spi_chipselect;
	sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
	sp->bitbang.flags = SPI_CS_HIGH;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	sp->base = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(sp->base)) {
		ret = PTR_ERR(sp->base);
		goto err_put_master;
	}

	sp->clk = devm_clk_get(&pdev->dev, "ahb");
	if (IS_ERR(sp->clk)) {
		ret = PTR_ERR(sp->clk);
		goto err_put_master;
	}

	ret = clk_prepare_enable(sp->clk);
	if (ret)
		goto err_put_master;

	rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
	if (!rate) {
		ret = -EINVAL;
		goto err_clk_disable;
	}

	sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
	dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
		sp->rrw_delay);

	ath79_spi_enable(sp);
	ret = spi_bitbang_start(&sp->bitbang);
	if (ret)
		goto err_disable;

	return 0;

err_disable:
	ath79_spi_disable(sp);
err_clk_disable:
	clk_disable_unprepare(sp->clk);
err_put_master:
	spi_master_put(sp->bitbang.master);

	return ret;
}

static int ath79_spi_remove(struct platform_device *pdev)
{
	struct ath79_spi *sp = platform_get_drvdata(pdev);

	spi_bitbang_stop(&sp->bitbang);
	ath79_spi_disable(sp);
	clk_disable_unprepare(sp->clk);
	spi_master_put(sp->bitbang.master);

	return 0;
}

static void ath79_spi_shutdown(struct platform_device *pdev)
{
	ath79_spi_remove(pdev);
}

static const struct of_device_id ath79_spi_of_match[] = {
	{ .compatible = "qca,ar7100-spi", },
	{ },
};
MODULE_DEVICE_TABLE(of, ath79_spi_of_match);

static struct platform_driver ath79_spi_driver = {
	.probe		= ath79_spi_probe,
	.remove		= ath79_spi_remove,
	.shutdown	= ath79_spi_shutdown,
	.driver		= {
		.name	= DRV_NAME,
		.of_match_table = ath79_spi_of_match,
	},
};
module_platform_driver(ath79_spi_driver);

MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
8efaef4d GJ	2	/*
	3	* SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
	4	*
	5	* Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
	6	*
	7	* This driver has been based on the spi-gpio.c:
	8	* Copyright (C) 2006,2008 David Brownell
8efaef4d GJ	9	*/
	10
	11	#include <linux/kernel.h>
807cc4b1	12	#include <linux/module.h>
8efaef4d GJ	13	#include <linux/delay.h>
8efaef4d GJ	14	#include <linux/spinlock.h>
8efaef4d GJ	15	#include <linux/platform_device.h>
	16	#include <linux/io.h>
	17	#include <linux/spi/spi.h>
	18	#include <linux/spi/spi_bitbang.h>
	19	#include <linux/bitops.h>
440114fd GJ	20	#include <linux/clk.h>
440114fd GJ	21	#include <linux/err.h>
b172fd0c	22	#include <linux/platform_data/spi-ath79.h>
8efaef4d GJ	23
	24	#define DRV_NAME "ath79-spi"
	25
440114fd GJ	26	#define ATH79_SPI_RRW_DELAY_FACTOR 12000
	27	#define MHZ (1000 * 1000)
	28
b172fd0c AB	29	#define AR71XX_SPI_REG_FS 0x00 /* Function Select */
	30	#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */
	31	#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */
	32	#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */
	33
	34	#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
	35
	36	#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */
	37	#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */
	38	#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n))
	39
8efaef4d GJ	40	struct ath79_spi {
	41	struct spi_bitbang bitbang;
	42	u32 ioc_base;
	43	u32 reg_ctrl;
	44	void __iomem *base;
440114fd	45	struct clk *clk;
da470d6a	46	unsigned int rrw_delay;
8efaef4d GJ	47	};
8efaef4d GJ	48
da470d6a	49	static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned int reg)
8efaef4d GJ	50	{
	51	return ioread32(sp->base + reg);
	52	}
	53
da470d6a	54	static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned int reg, u32 val)
8efaef4d GJ	55	{
	56	iowrite32(val, sp->base + reg);
	57	}
	58
	59	static inline struct ath79_spi ath79_spidev_to_sp(struct spi_device spi)
	60	{
	61	return spi_master_get_devdata(spi->master);
	62	}
	63
da470d6a	64	static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned int nsecs)
440114fd GJ	65	{
	66	if (nsecs > sp->rrw_delay)
	67	ndelay(nsecs - sp->rrw_delay);
	68	}
	69
8efaef4d GJ	70	static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
	71	{
	72	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
	73	int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
797622d7	74	u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
8efaef4d	75
797622d7 AB	76	if (cs_high)
	77	sp->ioc_base \|= cs_bit;
	78	else
	79	sp->ioc_base &= ~cs_bit;
8efaef4d	80
797622d7	81	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
8efaef4d GJ	82	}
8efaef4d GJ	83
c4a31f43	84	static void ath79_spi_enable(struct ath79_spi *sp)
8efaef4d	85	{
8efaef4d GJ	86	/* enable GPIO mode */
	87	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
	88
	89	/* save CTRL register */
	90	sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
	91	sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
	92
797622d7 AB	93	/* clear clk and mosi in the base state */
	94	sp->ioc_base &= ~(AR71XX_SPI_IOC_DO \| AR71XX_SPI_IOC_CLK);
	95
8efaef4d GJ	96	/* TODO: setup speed? */
8efaef4d GJ	97	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
c4a31f43 GJ	98	}
	99
	100	static void ath79_spi_disable(struct ath79_spi *sp)
	101	{
	102	/* restore CTRL register */
	103	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
	104	/* disable GPIO mode */
	105	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
	106	}
	107
da470d6a	108	static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned int nsecs,
304d3436	109	u32 word, u8 bits, unsigned flags)
8efaef4d GJ	110	{
	111	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
	112	u32 ioc = sp->ioc_base;
	113
	114	/* clock starts at inactive polarity */
	115	for (word <<= (32 - bits); likely(bits); bits--) {
	116	u32 out;
	117
	118	if (word & (1 << 31))
	119	out = ioc \| AR71XX_SPI_IOC_DO;
	120	else
	121	out = ioc & ~AR71XX_SPI_IOC_DO;
	122
	123	/* setup MSB (to slave) on trailing edge */
	124	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
440114fd	125	ath79_spi_delay(sp, nsecs);
8efaef4d	126	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out \| AR71XX_SPI_IOC_CLK);
440114fd	127	ath79_spi_delay(sp, nsecs);
72611db0 GJ	128	if (bits == 1)
72611db0 GJ	129	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
8efaef4d GJ	130
	131	word <<= 1;
	132	}
	133
	134	return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
	135	}
	136
fd4a319b	137	static int ath79_spi_probe(struct platform_device *pdev)
8efaef4d GJ	138	{
	139	struct spi_master *master;
	140	struct ath79_spi *sp;
	141	struct ath79_spi_platform_data *pdata;
	142	struct resource *r;
440114fd	143	unsigned long rate;
8efaef4d GJ	144	int ret;
	145
	146	master = spi_alloc_master(&pdev->dev, sizeof(*sp));
	147	if (master == NULL) {
	148	dev_err(&pdev->dev, "failed to allocate spi master\n");
	149	return -ENOMEM;
	150	}
	151
	152	sp = spi_master_get_devdata(master);
85f62476	153	master->dev.of_node = pdev->dev.of_node;
8efaef4d GJ	154	platform_set_drvdata(pdev, sp);
8efaef4d GJ	155
8074cf06	156	pdata = dev_get_platdata(&pdev->dev);
8efaef4d	157
8db79547	158	master->use_gpio_descriptors = true;
24778be2	159	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
f1b2c1c8 AB	160	master->setup = spi_bitbang_setup;
f1b2c1c8 AB	161	master->cleanup = spi_bitbang_cleanup;
8efaef4d GJ	162	if (pdata) {
	163	master->bus_num = pdata->bus_num;
	164	master->num_chipselect = pdata->num_chipselect;
8efaef4d GJ	165	}
8efaef4d GJ	166
94c69f76	167	sp->bitbang.master = master;
8efaef4d GJ	168	sp->bitbang.chipselect = ath79_spi_chipselect;
8efaef4d GJ	169	sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
8efaef4d GJ	170	sp->bitbang.flags = SPI_CS_HIGH;
	171
	172	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b7a2a1c0 HK	173	sp->base = devm_ioremap_resource(&pdev->dev, r);
	174	if (IS_ERR(sp->base)) {
	175	ret = PTR_ERR(sp->base);
8efaef4d GJ	176	goto err_put_master;
	177	}
	178
a6f4c8e0	179	sp->clk = devm_clk_get(&pdev->dev, "ahb");
440114fd GJ	180	if (IS_ERR(sp->clk)) {
440114fd GJ	181	ret = PTR_ERR(sp->clk);
a6f4c8e0	182	goto err_put_master;
440114fd GJ	183	}
440114fd GJ	184
3e19acdc	185	ret = clk_prepare_enable(sp->clk);
440114fd	186	if (ret)
a6f4c8e0	187	goto err_put_master;
440114fd GJ	188
	189	rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
	190	if (!rate) {
	191	ret = -EINVAL;
	192	goto err_clk_disable;
	193	}
	194
	195	sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
	196	dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
	197	sp->rrw_delay);
	198
c4a31f43	199	ath79_spi_enable(sp);
8efaef4d GJ	200	ret = spi_bitbang_start(&sp->bitbang);
8efaef4d GJ	201	if (ret)
c4a31f43	202	goto err_disable;
8efaef4d GJ	203
	204	return 0;
	205
c4a31f43 GJ	206	err_disable:
c4a31f43 GJ	207	ath79_spi_disable(sp);
440114fd	208	err_clk_disable:
3e19acdc	209	clk_disable_unprepare(sp->clk);
8efaef4d	210	err_put_master:
8efaef4d GJ	211	spi_master_put(sp->bitbang.master);
	212
	213	return ret;
	214	}
	215
fd4a319b	216	static int ath79_spi_remove(struct platform_device *pdev)
8efaef4d GJ	217	{
	218	struct ath79_spi *sp = platform_get_drvdata(pdev);
	219
	220	spi_bitbang_stop(&sp->bitbang);
c4a31f43	221	ath79_spi_disable(sp);
3e19acdc	222	clk_disable_unprepare(sp->clk);
8efaef4d GJ	223	spi_master_put(sp->bitbang.master);
	224
	225	return 0;
	226	}
	227
7410e848 GJ	228	static void ath79_spi_shutdown(struct platform_device *pdev)
	229	{
	230	ath79_spi_remove(pdev);
	231	}
	232
85f62476 AB	233	static const struct of_device_id ath79_spi_of_match[] = {
	234	{ .compatible = "qca,ar7100-spi", },
	235	{ },
	236	};
d7a32394	237	MODULE_DEVICE_TABLE(of, ath79_spi_of_match);
85f62476	238
8efaef4d GJ	239	static struct platform_driver ath79_spi_driver = {
8efaef4d GJ	240	.probe = ath79_spi_probe,
fd4a319b	241	.remove = ath79_spi_remove,
7410e848	242	.shutdown = ath79_spi_shutdown,
8efaef4d GJ	243	.driver = {
8efaef4d GJ	244	.name = DRV_NAME,
85f62476	245	.of_match_table = ath79_spi_of_match,
8efaef4d GJ	246	},
8efaef4d GJ	247	};
940ab889	248	module_platform_driver(ath79_spi_driver);
8efaef4d GJ	249
	250	MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
	251	MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
	252	MODULE_LICENSE("GPL v2");
	253	MODULE_ALIAS("platform:" DRV_NAME);