[linux-2.6-block.git] / drivers / spi / spi-ath79.c

/*
 * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
 *
 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
 *
 * This driver has been based on the spi-gpio.c:
 *	Copyright (C) 2006,2008 David Brownell
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/platform_data/spi-ath79.h>

#define DRV_NAME	"ath79-spi"

#define ATH79_SPI_RRW_DELAY_FACTOR	12000
#define MHZ				(1000 * 1000)

#define AR71XX_SPI_REG_FS		0x00	/* Function Select */
#define AR71XX_SPI_REG_CTRL		0x04	/* SPI Control */
#define AR71XX_SPI_REG_IOC		0x08	/* SPI I/O Control */
#define AR71XX_SPI_REG_RDS		0x0c	/* Read Data Shift */

#define AR71XX_SPI_FS_GPIO		BIT(0)	/* Enable GPIO mode */

#define AR71XX_SPI_IOC_DO		BIT(0)	/* Data Out pin */
#define AR71XX_SPI_IOC_CLK		BIT(8)	/* CLK pin */
#define AR71XX_SPI_IOC_CS(n)		BIT(16 + (n))

struct ath79_spi {
	struct spi_bitbang	bitbang;
	u32			ioc_base;
	u32			reg_ctrl;
	void __iomem		*base;
	struct clk		*clk;
	unsigned int		rrw_delay;
};

static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned int reg)
{
	return ioread32(sp->base + reg);
}

static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned int reg, u32 val)
{
	iowrite32(val, sp->base + reg);
}

static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
{
	return spi_master_get_devdata(spi->master);
}

static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned int nsecs)
{
	if (nsecs > sp->rrw_delay)
		ndelay(nsecs - sp->rrw_delay);
}

static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
{
	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
	int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
	u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);

	if (cs_high)
		sp->ioc_base |= cs_bit;
	else
		sp->ioc_base &= ~cs_bit;

	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
}

static void ath79_spi_enable(struct ath79_spi *sp)
{
	/* enable GPIO mode */
	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);

	/* save CTRL register */
	sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
	sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);

	/* clear clk and mosi in the base state */
	sp->ioc_base &= ~(AR71XX_SPI_IOC_DO | AR71XX_SPI_IOC_CLK);

	/* TODO: setup speed? */
	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
}

static void ath79_spi_disable(struct ath79_spi *sp)
{
	/* restore CTRL register */
	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
	/* disable GPIO mode */
	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
}

static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned int nsecs,
			       u32 word, u8 bits, unsigned flags)
{
	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
	u32 ioc = sp->ioc_base;

	/* clock starts at inactive polarity */
	for (word <<= (32 - bits); likely(bits); bits--) {
		u32 out;

		if (word & (1 << 31))
			out = ioc | AR71XX_SPI_IOC_DO;
		else
			out = ioc & ~AR71XX_SPI_IOC_DO;

		/* setup MSB (to slave) on trailing edge */
		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
		ath79_spi_delay(sp, nsecs);
		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
		ath79_spi_delay(sp, nsecs);
		if (bits == 1)
			ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);

		word <<= 1;
	}

	return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
}

static int ath79_spi_probe(struct platform_device *pdev)
{
	struct spi_master *master;
	struct ath79_spi *sp;
	struct ath79_spi_platform_data *pdata;
	struct resource	*r;
	unsigned long rate;
	int ret;

	master = spi_alloc_master(&pdev->dev, sizeof(*sp));
	if (master == NULL) {
		dev_err(&pdev->dev, "failed to allocate spi master\n");
		return -ENOMEM;
	}

	sp = spi_master_get_devdata(master);
	master->dev.of_node = pdev->dev.of_node;
	platform_set_drvdata(pdev, sp);

	pdata = dev_get_platdata(&pdev->dev);

	master->use_gpio_descriptors = true;
	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
	master->setup = spi_bitbang_setup;
	master->cleanup = spi_bitbang_cleanup;
	if (pdata) {
		master->bus_num = pdata->bus_num;
		master->num_chipselect = pdata->num_chipselect;
	}

	sp->bitbang.master = master;
	sp->bitbang.chipselect = ath79_spi_chipselect;
	sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
	sp->bitbang.flags = SPI_CS_HIGH;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	sp->base = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(sp->base)) {
		ret = PTR_ERR(sp->base);
		goto err_put_master;
	}

	sp->clk = devm_clk_get(&pdev->dev, "ahb");
	if (IS_ERR(sp->clk)) {
		ret = PTR_ERR(sp->clk);
		goto err_put_master;
	}

	ret = clk_prepare_enable(sp->clk);
	if (ret)
		goto err_put_master;

	rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
	if (!rate) {
		ret = -EINVAL;
		goto err_clk_disable;
	}

	sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
	dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
		sp->rrw_delay);

	ath79_spi_enable(sp);
	ret = spi_bitbang_start(&sp->bitbang);
	if (ret)
		goto err_disable;

	return 0;

err_disable:
	ath79_spi_disable(sp);
err_clk_disable:
	clk_disable_unprepare(sp->clk);
err_put_master:
	spi_master_put(sp->bitbang.master);

	return ret;
}

static int ath79_spi_remove(struct platform_device *pdev)
{
	struct ath79_spi *sp = platform_get_drvdata(pdev);

	spi_bitbang_stop(&sp->bitbang);
	ath79_spi_disable(sp);
	clk_disable_unprepare(sp->clk);
	spi_master_put(sp->bitbang.master);

	return 0;
}

static void ath79_spi_shutdown(struct platform_device *pdev)
{
	ath79_spi_remove(pdev);
}

static const struct of_device_id ath79_spi_of_match[] = {
	{ .compatible = "qca,ar7100-spi", },
	{ },
};
MODULE_DEVICE_TABLE(of, ath79_spi_of_match);

static struct platform_driver ath79_spi_driver = {
	.probe		= ath79_spi_probe,
	.remove		= ath79_spi_remove,
	.shutdown	= ath79_spi_shutdown,
	.driver		= {
		.name	= DRV_NAME,
		.of_match_table = ath79_spi_of_match,
	},
};
module_platform_driver(ath79_spi_driver);

MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
Commit	Line	Data
8efaef4d GJ	1	/*
	2	* SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
	3	*
	4	* Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
	5	*
	6	* This driver has been based on the spi-gpio.c:
	7	* Copyright (C) 2006,2008 David Brownell
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	*/
	14
	15	#include <linux/kernel.h>
807cc4b1	16	#include <linux/module.h>
8efaef4d GJ	17	#include <linux/delay.h>
8efaef4d GJ	18	#include <linux/spinlock.h>
8efaef4d GJ	19	#include <linux/platform_device.h>
	20	#include <linux/io.h>
	21	#include <linux/spi/spi.h>
	22	#include <linux/spi/spi_bitbang.h>
	23	#include <linux/bitops.h>
440114fd GJ	24	#include <linux/clk.h>
440114fd GJ	25	#include <linux/err.h>
b172fd0c	26	#include <linux/platform_data/spi-ath79.h>
8efaef4d GJ	27
	28	#define DRV_NAME "ath79-spi"
	29
440114fd GJ	30	#define ATH79_SPI_RRW_DELAY_FACTOR 12000
	31	#define MHZ (1000 * 1000)
	32
b172fd0c AB	33	#define AR71XX_SPI_REG_FS 0x00 /* Function Select */
	34	#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */
	35	#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */
	36	#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */
	37
	38	#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
	39
	40	#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */
	41	#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */
	42	#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n))
	43
8efaef4d GJ	44	struct ath79_spi {
	45	struct spi_bitbang bitbang;
	46	u32 ioc_base;
	47	u32 reg_ctrl;
	48	void __iomem *base;
440114fd	49	struct clk *clk;
da470d6a	50	unsigned int rrw_delay;
8efaef4d GJ	51	};
8efaef4d GJ	52
da470d6a	53	static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned int reg)
8efaef4d GJ	54	{
	55	return ioread32(sp->base + reg);
	56	}
	57
da470d6a	58	static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned int reg, u32 val)
8efaef4d GJ	59	{
	60	iowrite32(val, sp->base + reg);
	61	}
	62
	63	static inline struct ath79_spi ath79_spidev_to_sp(struct spi_device spi)
	64	{
	65	return spi_master_get_devdata(spi->master);
	66	}
	67
da470d6a	68	static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned int nsecs)
440114fd GJ	69	{
	70	if (nsecs > sp->rrw_delay)
	71	ndelay(nsecs - sp->rrw_delay);
	72	}
	73
8efaef4d GJ	74	static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
	75	{
	76	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
	77	int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
797622d7	78	u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
8efaef4d	79
797622d7 AB	80	if (cs_high)
	81	sp->ioc_base \|= cs_bit;
	82	else
	83	sp->ioc_base &= ~cs_bit;
8efaef4d	84
797622d7	85	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
8efaef4d GJ	86	}
8efaef4d GJ	87
c4a31f43	88	static void ath79_spi_enable(struct ath79_spi *sp)
8efaef4d	89	{
8efaef4d GJ	90	/* enable GPIO mode */
	91	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
	92
	93	/* save CTRL register */
	94	sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
	95	sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
	96
797622d7 AB	97	/* clear clk and mosi in the base state */
	98	sp->ioc_base &= ~(AR71XX_SPI_IOC_DO \| AR71XX_SPI_IOC_CLK);
	99
8efaef4d GJ	100	/* TODO: setup speed? */
8efaef4d GJ	101	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
c4a31f43 GJ	102	}
	103
	104	static void ath79_spi_disable(struct ath79_spi *sp)
	105	{
	106	/* restore CTRL register */
	107	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
	108	/* disable GPIO mode */
	109	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
	110	}
	111
da470d6a	112	static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned int nsecs,
304d3436	113	u32 word, u8 bits, unsigned flags)
8efaef4d GJ	114	{
	115	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
	116	u32 ioc = sp->ioc_base;
	117
	118	/* clock starts at inactive polarity */
	119	for (word <<= (32 - bits); likely(bits); bits--) {
	120	u32 out;
	121
	122	if (word & (1 << 31))
	123	out = ioc \| AR71XX_SPI_IOC_DO;
	124	else
	125	out = ioc & ~AR71XX_SPI_IOC_DO;
	126
	127	/* setup MSB (to slave) on trailing edge */
	128	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
440114fd	129	ath79_spi_delay(sp, nsecs);
8efaef4d	130	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out \| AR71XX_SPI_IOC_CLK);
440114fd	131	ath79_spi_delay(sp, nsecs);
72611db0 GJ	132	if (bits == 1)
72611db0 GJ	133	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
8efaef4d GJ	134
	135	word <<= 1;
	136	}
	137
	138	return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
	139	}
	140
fd4a319b	141	static int ath79_spi_probe(struct platform_device *pdev)
8efaef4d GJ	142	{
	143	struct spi_master *master;
	144	struct ath79_spi *sp;
	145	struct ath79_spi_platform_data *pdata;
	146	struct resource *r;
440114fd	147	unsigned long rate;
8efaef4d GJ	148	int ret;
	149
	150	master = spi_alloc_master(&pdev->dev, sizeof(*sp));
	151	if (master == NULL) {
	152	dev_err(&pdev->dev, "failed to allocate spi master\n");
	153	return -ENOMEM;
	154	}
	155
	156	sp = spi_master_get_devdata(master);
85f62476	157	master->dev.of_node = pdev->dev.of_node;
8efaef4d GJ	158	platform_set_drvdata(pdev, sp);
8efaef4d GJ	159
8074cf06	160	pdata = dev_get_platdata(&pdev->dev);
8efaef4d	161
8db79547	162	master->use_gpio_descriptors = true;
24778be2	163	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
f1b2c1c8 AB	164	master->setup = spi_bitbang_setup;
f1b2c1c8 AB	165	master->cleanup = spi_bitbang_cleanup;
8efaef4d GJ	166	if (pdata) {
	167	master->bus_num = pdata->bus_num;
	168	master->num_chipselect = pdata->num_chipselect;
8efaef4d GJ	169	}
8efaef4d GJ	170
94c69f76	171	sp->bitbang.master = master;
8efaef4d GJ	172	sp->bitbang.chipselect = ath79_spi_chipselect;
8efaef4d GJ	173	sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
8efaef4d GJ	174	sp->bitbang.flags = SPI_CS_HIGH;
	175
	176	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b7a2a1c0 HK	177	sp->base = devm_ioremap_resource(&pdev->dev, r);
	178	if (IS_ERR(sp->base)) {
	179	ret = PTR_ERR(sp->base);
8efaef4d GJ	180	goto err_put_master;
	181	}
	182
a6f4c8e0	183	sp->clk = devm_clk_get(&pdev->dev, "ahb");
440114fd GJ	184	if (IS_ERR(sp->clk)) {
440114fd GJ	185	ret = PTR_ERR(sp->clk);
a6f4c8e0	186	goto err_put_master;
440114fd GJ	187	}
440114fd GJ	188
3e19acdc	189	ret = clk_prepare_enable(sp->clk);
440114fd	190	if (ret)
a6f4c8e0	191	goto err_put_master;
440114fd GJ	192
	193	rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
	194	if (!rate) {
	195	ret = -EINVAL;
	196	goto err_clk_disable;
	197	}
	198
	199	sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
	200	dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
	201	sp->rrw_delay);
	202
c4a31f43	203	ath79_spi_enable(sp);
8efaef4d GJ	204	ret = spi_bitbang_start(&sp->bitbang);
8efaef4d GJ	205	if (ret)
c4a31f43	206	goto err_disable;
8efaef4d GJ	207
	208	return 0;
	209
c4a31f43 GJ	210	err_disable:
c4a31f43 GJ	211	ath79_spi_disable(sp);
440114fd	212	err_clk_disable:
3e19acdc	213	clk_disable_unprepare(sp->clk);
8efaef4d	214	err_put_master:
8efaef4d GJ	215	spi_master_put(sp->bitbang.master);
	216
	217	return ret;
	218	}
	219
fd4a319b	220	static int ath79_spi_remove(struct platform_device *pdev)
8efaef4d GJ	221	{
	222	struct ath79_spi *sp = platform_get_drvdata(pdev);
	223
	224	spi_bitbang_stop(&sp->bitbang);
c4a31f43	225	ath79_spi_disable(sp);
3e19acdc	226	clk_disable_unprepare(sp->clk);
8efaef4d GJ	227	spi_master_put(sp->bitbang.master);
	228
	229	return 0;
	230	}
	231
7410e848 GJ	232	static void ath79_spi_shutdown(struct platform_device *pdev)
	233	{
	234	ath79_spi_remove(pdev);
	235	}
	236
85f62476 AB	237	static const struct of_device_id ath79_spi_of_match[] = {
	238	{ .compatible = "qca,ar7100-spi", },
	239	{ },
	240	};
d7a32394	241	MODULE_DEVICE_TABLE(of, ath79_spi_of_match);
85f62476	242
8efaef4d GJ	243	static struct platform_driver ath79_spi_driver = {
8efaef4d GJ	244	.probe = ath79_spi_probe,
fd4a319b	245	.remove = ath79_spi_remove,
7410e848	246	.shutdown = ath79_spi_shutdown,
8efaef4d GJ	247	.driver = {
8efaef4d GJ	248	.name = DRV_NAME,
85f62476	249	.of_match_table = ath79_spi_of_match,
8efaef4d GJ	250	},
8efaef4d GJ	251	};
940ab889	252	module_platform_driver(ath79_spi_driver);
8efaef4d GJ	253
	254	MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
	255	MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
	256	MODULE_LICENSE("GPL v2");
	257	MODULE_ALIAS("platform:" DRV_NAME);