[linux-2.6-block.git] / drivers / spi / spi-at91-usart.c

// SPDX-License-Identifier: GPL-2.0
//
// Driver for AT91 USART Controllers as SPI
//
// Copyright (C) 2018 Microchip Technology Inc.
//
// Author: Radu Pirea <radu.pirea@microchip.com>

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_gpio.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>

#include <linux/spi/spi.h>

#define US_CR			0x00
#define US_MR			0x04
#define US_IER			0x08
#define US_IDR			0x0C
#define US_CSR			0x14
#define US_RHR			0x18
#define US_THR			0x1C
#define US_BRGR			0x20
#define US_VERSION		0xFC

#define US_CR_RSTRX		BIT(2)
#define US_CR_RSTTX		BIT(3)
#define US_CR_RXEN		BIT(4)
#define US_CR_RXDIS		BIT(5)
#define US_CR_TXEN		BIT(6)
#define US_CR_TXDIS		BIT(7)

#define US_MR_SPI_MASTER	0x0E
#define US_MR_CHRL		GENMASK(7, 6)
#define US_MR_CPHA		BIT(8)
#define US_MR_CPOL		BIT(16)
#define US_MR_CLKO		BIT(18)
#define US_MR_WRDBT		BIT(20)
#define US_MR_LOOP		BIT(15)

#define US_IR_RXRDY		BIT(0)
#define US_IR_TXRDY		BIT(1)
#define US_IR_OVRE		BIT(5)

#define US_BRGR_SIZE		BIT(16)

#define US_MIN_CLK_DIV		0x06
#define US_MAX_CLK_DIV		BIT(16)

#define US_RESET		(US_CR_RSTRX | US_CR_RSTTX)
#define US_DISABLE		(US_CR_RXDIS | US_CR_TXDIS)
#define US_ENABLE		(US_CR_RXEN | US_CR_TXEN)
#define US_OVRE_RXRDY_IRQS	(US_IR_OVRE | US_IR_RXRDY)

#define US_INIT \
	(US_MR_SPI_MASTER | US_MR_CHRL | US_MR_CLKO | US_MR_WRDBT)

/* Register access macros */
#define at91_usart_spi_readl(port, reg) \
	readl_relaxed((port)->regs + US_##reg)
#define at91_usart_spi_writel(port, reg, value) \
	writel_relaxed((value), (port)->regs + US_##reg)

#define at91_usart_spi_readb(port, reg) \
	readb_relaxed((port)->regs + US_##reg)
#define at91_usart_spi_writeb(port, reg, value) \
	writeb_relaxed((value), (port)->regs + US_##reg)

struct at91_usart_spi {
	struct spi_transfer	*current_transfer;
	void __iomem		*regs;
	struct device		*dev;
	struct clk		*clk;

	/*used in interrupt to protect data reading*/
	spinlock_t		lock;

	int			irq;
	unsigned int		current_tx_remaining_bytes;
	unsigned int		current_rx_remaining_bytes;

	u32			spi_clk;
	u32			status;

	bool			xfer_failed;
};

static inline u32 at91_usart_spi_tx_ready(struct at91_usart_spi *aus)
{
	return aus->status & US_IR_TXRDY;
}

static inline u32 at91_usart_spi_rx_ready(struct at91_usart_spi *aus)
{
	return aus->status & US_IR_RXRDY;
}

static inline u32 at91_usart_spi_check_overrun(struct at91_usart_spi *aus)
{
	return aus->status & US_IR_OVRE;
}

static inline u32 at91_usart_spi_read_status(struct at91_usart_spi *aus)
{
	aus->status = at91_usart_spi_readl(aus, CSR);
	return aus->status;
}

static inline void at91_usart_spi_tx(struct at91_usart_spi *aus)
{
	unsigned int len = aus->current_transfer->len;
	unsigned int remaining = aus->current_tx_remaining_bytes;
	const u8  *tx_buf = aus->current_transfer->tx_buf;

	if (!remaining)
		return;

	if (at91_usart_spi_tx_ready(aus)) {
		at91_usart_spi_writeb(aus, THR, tx_buf[len - remaining]);
		aus->current_tx_remaining_bytes--;
	}
}

static inline void at91_usart_spi_rx(struct at91_usart_spi *aus)
{
	int len = aus->current_transfer->len;
	int remaining = aus->current_rx_remaining_bytes;
	u8  *rx_buf = aus->current_transfer->rx_buf;

	if (!remaining)
		return;

	rx_buf[len - remaining] = at91_usart_spi_readb(aus, RHR);
	aus->current_rx_remaining_bytes--;
}

static inline void
at91_usart_spi_set_xfer_speed(struct at91_usart_spi *aus,
			      struct spi_transfer *xfer)
{
	at91_usart_spi_writel(aus, BRGR,
			      DIV_ROUND_UP(aus->spi_clk, xfer->speed_hz));
}

static irqreturn_t at91_usart_spi_interrupt(int irq, void *dev_id)
{
	struct spi_controller *controller = dev_id;
	struct at91_usart_spi *aus = spi_master_get_devdata(controller);

	spin_lock(&aus->lock);
	at91_usart_spi_read_status(aus);

	if (at91_usart_spi_check_overrun(aus)) {
		aus->xfer_failed = true;
		at91_usart_spi_writel(aus, IDR, US_IR_OVRE | US_IR_RXRDY);
		spin_unlock(&aus->lock);
		return IRQ_HANDLED;
	}

	if (at91_usart_spi_rx_ready(aus)) {
		at91_usart_spi_rx(aus);
		spin_unlock(&aus->lock);
		return IRQ_HANDLED;
	}

	spin_unlock(&aus->lock);

	return IRQ_NONE;
}

static int at91_usart_spi_setup(struct spi_device *spi)
{
	struct at91_usart_spi *aus = spi_master_get_devdata(spi->controller);
	u32 *ausd = spi->controller_state;
	unsigned int mr = at91_usart_spi_readl(aus, MR);
	u8 bits = spi->bits_per_word;

	if (bits != 8) {
		dev_dbg(&spi->dev, "Only 8 bits per word are supported\n");
		return -EINVAL;
	}

	if (spi->mode & SPI_CPOL)
		mr |= US_MR_CPOL;
	else
		mr &= ~US_MR_CPOL;

	if (spi->mode & SPI_CPHA)
		mr |= US_MR_CPHA;
	else
		mr &= ~US_MR_CPHA;

	if (spi->mode & SPI_LOOP)
		mr |= US_MR_LOOP;
	else
		mr &= ~US_MR_LOOP;

	if (!ausd) {
		ausd = kzalloc(sizeof(*ausd), GFP_KERNEL);
		if (!ausd)
			return -ENOMEM;

		spi->controller_state = ausd;
	}

	*ausd = mr;

	dev_dbg(&spi->dev,
		"setup: bpw %u mode 0x%x -> mr %d %08x\n",
		bits, spi->mode, spi->chip_select, mr);

	return 0;
}

static int at91_usart_spi_transfer_one(struct spi_controller *ctlr,
				       struct spi_device *spi,
				       struct spi_transfer *xfer)
{
	struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);

	at91_usart_spi_set_xfer_speed(aus, xfer);
	aus->xfer_failed = false;
	aus->current_transfer = xfer;
	aus->current_tx_remaining_bytes = xfer->len;
	aus->current_rx_remaining_bytes = xfer->len;

	while ((aus->current_tx_remaining_bytes ||
		aus->current_rx_remaining_bytes) && !aus->xfer_failed) {
		at91_usart_spi_read_status(aus);
		at91_usart_spi_tx(aus);
		cpu_relax();
	}

	if (aus->xfer_failed) {
		dev_err(aus->dev, "Overrun!\n");
		return -EIO;
	}

	return 0;
}

static int at91_usart_spi_prepare_message(struct spi_controller *ctlr,
					  struct spi_message *message)
{
	struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);
	struct spi_device *spi = message->spi;
	u32 *ausd = spi->controller_state;

	at91_usart_spi_writel(aus, CR, US_ENABLE);
	at91_usart_spi_writel(aus, IER, US_OVRE_RXRDY_IRQS);
	at91_usart_spi_writel(aus, MR, *ausd);

	return 0;
}

static int at91_usart_spi_unprepare_message(struct spi_controller *ctlr,
					    struct spi_message *message)
{
	struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);

	at91_usart_spi_writel(aus, CR, US_RESET | US_DISABLE);
	at91_usart_spi_writel(aus, IDR, US_OVRE_RXRDY_IRQS);

	return 0;
}

static void at91_usart_spi_cleanup(struct spi_device *spi)
{
	struct at91_usart_spi_device *ausd = spi->controller_state;

	spi->controller_state = NULL;
	kfree(ausd);
}

static void at91_usart_spi_init(struct at91_usart_spi *aus)
{
	at91_usart_spi_writel(aus, MR, US_INIT);
	at91_usart_spi_writel(aus, CR, US_RESET | US_DISABLE);
}

static int at91_usart_gpio_setup(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.parent->of_node;
	int i;
	int ret;
	int nb;

	if (!np)
		return -EINVAL;

	nb = of_gpio_named_count(np, "cs-gpios");
	for (i = 0; i < nb; i++) {
		int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);

		if (cs_gpio < 0)
			return cs_gpio;

		if (gpio_is_valid(cs_gpio)) {
			ret = devm_gpio_request_one(&pdev->dev, cs_gpio,
						    GPIOF_DIR_OUT,
						    dev_name(&pdev->dev));
			if (ret)
				return ret;
		}
	}

	return 0;
}

static int at91_usart_spi_probe(struct platform_device *pdev)
{
	struct resource *regs;
	struct spi_controller *controller;
	struct at91_usart_spi *aus;
	struct clk *clk;
	int irq;
	int ret;

	regs = platform_get_resource(to_platform_device(pdev->dev.parent),
				     IORESOURCE_MEM, 0);
	if (!regs)
		return -EINVAL;

	irq = platform_get_irq(to_platform_device(pdev->dev.parent), 0);
	if (irq < 0)
		return irq;

	clk = devm_clk_get(pdev->dev.parent, "usart");
	if (IS_ERR(clk))
		return PTR_ERR(clk);

	ret = -ENOMEM;
	controller = spi_alloc_master(&pdev->dev, sizeof(*aus));
	if (!controller)
		goto at91_usart_spi_probe_fail;

	ret = at91_usart_gpio_setup(pdev);
	if (ret)
		goto at91_usart_spi_probe_fail;

	controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH;
	controller->dev.of_node = pdev->dev.parent->of_node;
	controller->bits_per_word_mask = SPI_BPW_MASK(8);
	controller->setup = at91_usart_spi_setup;
	controller->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
	controller->transfer_one = at91_usart_spi_transfer_one;
	controller->prepare_message = at91_usart_spi_prepare_message;
	controller->unprepare_message = at91_usart_spi_unprepare_message;
	controller->cleanup = at91_usart_spi_cleanup;
	controller->max_speed_hz = DIV_ROUND_UP(clk_get_rate(clk),
						US_MIN_CLK_DIV);
	controller->min_speed_hz = DIV_ROUND_UP(clk_get_rate(clk),
						US_MAX_CLK_DIV);
	platform_set_drvdata(pdev, controller);

	aus = spi_master_get_devdata(controller);

	aus->dev = &pdev->dev;
	aus->regs = devm_ioremap_resource(&pdev->dev, regs);
	if (IS_ERR(aus->regs)) {
		ret = PTR_ERR(aus->regs);
		goto at91_usart_spi_probe_fail;
	}

	aus->irq = irq;
	aus->clk = clk;

	ret = devm_request_irq(&pdev->dev, irq, at91_usart_spi_interrupt, 0,
			       dev_name(&pdev->dev), controller);
	if (ret)
		goto at91_usart_spi_probe_fail;

	ret = clk_prepare_enable(clk);
	if (ret)
		goto at91_usart_spi_probe_fail;

	aus->spi_clk = clk_get_rate(clk);
	at91_usart_spi_init(aus);

	spin_lock_init(&aus->lock);
	ret = devm_spi_register_master(&pdev->dev, controller);
	if (ret)
		goto at91_usart_fail_register_master;

	dev_info(&pdev->dev,
		 "AT91 USART SPI Controller version 0x%x at %pa (irq %d)\n",
		 at91_usart_spi_readl(aus, VERSION),
		 &regs->start, irq);

	return 0;

at91_usart_fail_register_master:
	clk_disable_unprepare(clk);
at91_usart_spi_probe_fail:
	spi_master_put(controller);
	return ret;
}

__maybe_unused static int at91_usart_spi_runtime_suspend(struct device *dev)
{
	struct spi_controller *ctlr = dev_get_drvdata(dev);
	struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);

	clk_disable_unprepare(aus->clk);
	pinctrl_pm_select_sleep_state(dev);

	return 0;
}

__maybe_unused static int at91_usart_spi_runtime_resume(struct device *dev)
{
	struct spi_controller *ctrl = dev_get_drvdata(dev);
	struct at91_usart_spi *aus = spi_master_get_devdata(ctrl);

	pinctrl_pm_select_default_state(dev);

	return clk_prepare_enable(aus->clk);
}

__maybe_unused static int at91_usart_spi_suspend(struct device *dev)
{
	struct spi_controller *ctrl = dev_get_drvdata(dev);
	int ret;

	ret = spi_controller_suspend(ctrl);
	if (ret)
		return ret;

	if (!pm_runtime_suspended(dev))
		at91_usart_spi_runtime_suspend(dev);

	return 0;
}

__maybe_unused static int at91_usart_spi_resume(struct device *dev)
{
	struct spi_controller *ctrl = dev_get_drvdata(dev);
	struct at91_usart_spi *aus = spi_master_get_devdata(ctrl);
	int ret;

	if (!pm_runtime_suspended(dev)) {
		ret = at91_usart_spi_runtime_resume(dev);
		if (ret)
			return ret;
	}

	at91_usart_spi_init(aus);

	return spi_controller_resume(ctrl);
}

static int at91_usart_spi_remove(struct platform_device *pdev)
{
	struct spi_controller *ctlr = platform_get_drvdata(pdev);
	struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);

	clk_disable_unprepare(aus->clk);

	return 0;
}

static const struct dev_pm_ops at91_usart_spi_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(at91_usart_spi_suspend, at91_usart_spi_resume)
	SET_RUNTIME_PM_OPS(at91_usart_spi_runtime_suspend,
			   at91_usart_spi_runtime_resume, NULL)
};

static const struct of_device_id at91_usart_spi_dt_ids[] = {
	{ .compatible = "microchip,at91sam9g45-usart-spi"},
	{ /* sentinel */}
};

MODULE_DEVICE_TABLE(of, at91_usart_spi_dt_ids);

static struct platform_driver at91_usart_spi_driver = {
	.driver = {
		.name = "at91_usart_spi",
		.pm = &at91_usart_spi_pm_ops,
	},
	.probe = at91_usart_spi_probe,
	.remove = at91_usart_spi_remove,
};

module_platform_driver(at91_usart_spi_driver);

MODULE_DESCRIPTION("Microchip AT91 USART SPI Controller driver");
MODULE_AUTHOR("Radu Pirea <radu.pirea@microchip.com>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:at91_usart_spi");
Commit	Line	Data
e1892546 RP	1	// SPDX-License-Identifier: GPL-2.0
	2	//
	3	// Driver for AT91 USART Controllers as SPI
	4	//
	5	// Copyright (C) 2018 Microchip Technology Inc.
	6	//
	7	// Author: Radu Pirea <radu.pirea@microchip.com>
	8
	9	#include <linux/clk.h>
	10	#include <linux/delay.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/kernel.h>
	13	#include <linux/module.h>
	14	#include <linux/of_gpio.h>
c2b142cc	15	#include <linux/pinctrl/consumer.h>
e1892546	16	#include <linux/platform_device.h>
96ed3ecd	17	#include <linux/pm_runtime.h>
e1892546 RP	18
	19	#include <linux/spi/spi.h>
	20
	21	#define US_CR 0x00
	22	#define US_MR 0x04
	23	#define US_IER 0x08
	24	#define US_IDR 0x0C
	25	#define US_CSR 0x14
	26	#define US_RHR 0x18
	27	#define US_THR 0x1C
	28	#define US_BRGR 0x20
	29	#define US_VERSION 0xFC
	30
	31	#define US_CR_RSTRX BIT(2)
	32	#define US_CR_RSTTX BIT(3)
	33	#define US_CR_RXEN BIT(4)
	34	#define US_CR_RXDIS BIT(5)
	35	#define US_CR_TXEN BIT(6)
	36	#define US_CR_TXDIS BIT(7)
	37
	38	#define US_MR_SPI_MASTER 0x0E
	39	#define US_MR_CHRL GENMASK(7, 6)
	40	#define US_MR_CPHA BIT(8)
	41	#define US_MR_CPOL BIT(16)
	42	#define US_MR_CLKO BIT(18)
	43	#define US_MR_WRDBT BIT(20)
	44	#define US_MR_LOOP BIT(15)
	45
	46	#define US_IR_RXRDY BIT(0)
	47	#define US_IR_TXRDY BIT(1)
	48	#define US_IR_OVRE BIT(5)
	49
	50	#define US_BRGR_SIZE BIT(16)
	51
	52	#define US_MIN_CLK_DIV 0x06
	53	#define US_MAX_CLK_DIV BIT(16)
	54
	55	#define US_RESET (US_CR_RSTRX \| US_CR_RSTTX)
	56	#define US_DISABLE (US_CR_RXDIS \| US_CR_TXDIS)
	57	#define US_ENABLE (US_CR_RXEN \| US_CR_TXEN)
	58	#define US_OVRE_RXRDY_IRQS (US_IR_OVRE \| US_IR_RXRDY)
	59
	60	#define US_INIT \
	61	(US_MR_SPI_MASTER \| US_MR_CHRL \| US_MR_CLKO \| US_MR_WRDBT)
	62
	63	/* Register access macros */
	64	#define at91_usart_spi_readl(port, reg) \
	65	readl_relaxed((port)->regs + US_##reg)
	66	#define at91_usart_spi_writel(port, reg, value) \
	67	writel_relaxed((value), (port)->regs + US_##reg)
	68
	69	#define at91_usart_spi_readb(port, reg) \
	70	readb_relaxed((port)->regs + US_##reg)
	71	#define at91_usart_spi_writeb(port, reg, value) \
	72	writeb_relaxed((value), (port)->regs + US_##reg)
	73
	74	struct at91_usart_spi {
	75	struct spi_transfer *current_transfer;
	76	void __iomem *regs;
	77	struct device *dev;
	78	struct clk *clk;
	79
	80	/used in interrupt to protect data reading/
	81	spinlock_t lock;
82
83	int irq;
84	unsigned int current_tx_remaining_bytes;
85	unsigned int current_rx_remaining_bytes;
86
87	u32 spi_clk;
88	u32 status;
89
90	bool xfer_failed;
91	};
92
93	static inline u32 at91_usart_spi_tx_ready(struct at91_usart_spi *aus)
94	{
95	return aus->status & US_IR_TXRDY;
96	}
97
98	static inline u32 at91_usart_spi_rx_ready(struct at91_usart_spi *aus)
99	{
100	return aus->status & US_IR_RXRDY;
101	}
102
103	static inline u32 at91_usart_spi_check_overrun(struct at91_usart_spi *aus)
104	{
105	return aus->status & US_IR_OVRE;
106	}
107
108	static inline u32 at91_usart_spi_read_status(struct at91_usart_spi *aus)
109	{
110	aus->status = at91_usart_spi_readl(aus, CSR);
111	return aus->status;
112	}
113
114	static inline void at91_usart_spi_tx(struct at91_usart_spi *aus)
115	{
116	unsigned int len = aus->current_transfer->len;
117	unsigned int remaining = aus->current_tx_remaining_bytes;
118	const u8 *tx_buf = aus->current_transfer->tx_buf;
119
120	if (!remaining)
121	return;
122
123	if (at91_usart_spi_tx_ready(aus)) {
124	at91_usart_spi_writeb(aus, THR, tx_buf[len - remaining]);
125	aus->current_tx_remaining_bytes--;
126	}
127	}
128
129	static inline void at91_usart_spi_rx(struct at91_usart_spi *aus)
130	{
131	int len = aus->current_transfer->len;
132	int remaining = aus->current_rx_remaining_bytes;
133	u8 *rx_buf = aus->current_transfer->rx_buf;
134
135	if (!remaining)
136	return;
137
138	rx_buf[len - remaining] = at91_usart_spi_readb(aus, RHR);
139	aus->current_rx_remaining_bytes--;
140	}
141
142	static inline void
143	at91_usart_spi_set_xfer_speed(struct at91_usart_spi *aus,
144	struct spi_transfer *xfer)
145	{
146	at91_usart_spi_writel(aus, BRGR,
147	DIV_ROUND_UP(aus->spi_clk, xfer->speed_hz));
148	}
149
150	static irqreturn_t at91_usart_spi_interrupt(int irq, void *dev_id)
151	{
152	struct spi_controller *controller = dev_id;
153	struct at91_usart_spi *aus = spi_master_get_devdata(controller);
154
155	spin_lock(&aus->lock);
156	at91_usart_spi_read_status(aus);
157
158	if (at91_usart_spi_check_overrun(aus)) {
159	aus->xfer_failed = true;
160	at91_usart_spi_writel(aus, IDR, US_IR_OVRE \| US_IR_RXRDY);
161	spin_unlock(&aus->lock);
162	return IRQ_HANDLED;
163	}
164
165	if (at91_usart_spi_rx_ready(aus)) {
166	at91_usart_spi_rx(aus);
167	spin_unlock(&aus->lock);
168	return IRQ_HANDLED;
169	}
170
171	spin_unlock(&aus->lock);
172
173	return IRQ_NONE;
174	}
175
176	static int at91_usart_spi_setup(struct spi_device *spi)
177	{
178	struct at91_usart_spi *aus = spi_master_get_devdata(spi->controller);
179	u32 *ausd = spi->controller_state;
180	unsigned int mr = at91_usart_spi_readl(aus, MR);
181	u8 bits = spi->bits_per_word;
182
183	if (bits != 8) {
184	dev_dbg(&spi->dev, "Only 8 bits per word are supported\n");
185	return -EINVAL;
186	}
187
188	if (spi->mode & SPI_CPOL)
189	mr \|= US_MR_CPOL;
190	else
191	mr &= ~US_MR_CPOL;
192
193	if (spi->mode & SPI_CPHA)
194	mr \|= US_MR_CPHA;
195	else
196	mr &= ~US_MR_CPHA;
197
198	if (spi->mode & SPI_LOOP)
199	mr \|= US_MR_LOOP;
200	else
201	mr &= ~US_MR_LOOP;
202
203	if (!ausd) {
204	ausd = kzalloc(sizeof(*ausd), GFP_KERNEL);
205	if (!ausd)
206	return -ENOMEM;
207
208	spi->controller_state = ausd;
209	}
210
211	*ausd = mr;
212
213	dev_dbg(&spi->dev,
214	"setup: bpw %u mode 0x%x -> mr %d %08x\n",
215	bits, spi->mode, spi->chip_select, mr);
216
217	return 0;
218	}
219
259e0a00 LJ	220	static int at91_usart_spi_transfer_one(struct spi_controller *ctlr,
	221	struct spi_device *spi,
	222	struct spi_transfer *xfer)
e1892546 RP	223	{
	224	struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);
	225
	226	at91_usart_spi_set_xfer_speed(aus, xfer);
	227	aus->xfer_failed = false;
	228	aus->current_transfer = xfer;
	229	aus->current_tx_remaining_bytes = xfer->len;
	230	aus->current_rx_remaining_bytes = xfer->len;
	231
	232	while ((aus->current_tx_remaining_bytes \|\|
	233	aus->current_rx_remaining_bytes) && !aus->xfer_failed) {
	234	at91_usart_spi_read_status(aus);
	235	at91_usart_spi_tx(aus);
	236	cpu_relax();
	237	}
	238
	239	if (aus->xfer_failed) {
	240	dev_err(aus->dev, "Overrun!\n");
	241	return -EIO;
	242	}
	243
	244	return 0;
	245	}
	246
259e0a00 LJ	247	static int at91_usart_spi_prepare_message(struct spi_controller *ctlr,
259e0a00 LJ	248	struct spi_message *message)
e1892546 RP	249	{
	250	struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);
	251	struct spi_device *spi = message->spi;
	252	u32 *ausd = spi->controller_state;
	253
	254	at91_usart_spi_writel(aus, CR, US_ENABLE);
	255	at91_usart_spi_writel(aus, IER, US_OVRE_RXRDY_IRQS);
	256	at91_usart_spi_writel(aus, MR, *ausd);
	257
	258	return 0;
	259	}
	260
259e0a00 LJ	261	static int at91_usart_spi_unprepare_message(struct spi_controller *ctlr,
259e0a00 LJ	262	struct spi_message *message)
e1892546 RP	263	{
	264	struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);
	265
	266	at91_usart_spi_writel(aus, CR, US_RESET \| US_DISABLE);
	267	at91_usart_spi_writel(aus, IDR, US_OVRE_RXRDY_IRQS);
	268
	269	return 0;
	270	}
	271
	272	static void at91_usart_spi_cleanup(struct spi_device *spi)
	273	{
	274	struct at91_usart_spi_device *ausd = spi->controller_state;
	275
	276	spi->controller_state = NULL;
	277	kfree(ausd);
	278	}
	279
	280	static void at91_usart_spi_init(struct at91_usart_spi *aus)
	281	{
	282	at91_usart_spi_writel(aus, MR, US_INIT);
	283	at91_usart_spi_writel(aus, CR, US_RESET \| US_DISABLE);
	284	}
	285
	286	static int at91_usart_gpio_setup(struct platform_device *pdev)
	287	{
	288	struct device_node *np = pdev->dev.parent->of_node;
	289	int i;
	290	int ret;
	291	int nb;
	292
	293	if (!np)
	294	return -EINVAL;
	295
	296	nb = of_gpio_named_count(np, "cs-gpios");
	297	for (i = 0; i < nb; i++) {
	298	int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
	299
	300	if (cs_gpio < 0)
	301	return cs_gpio;
	302
	303	if (gpio_is_valid(cs_gpio)) {
	304	ret = devm_gpio_request_one(&pdev->dev, cs_gpio,
	305	GPIOF_DIR_OUT,
	306	dev_name(&pdev->dev));
	307	if (ret)
	308	return ret;
	309	}
	310	}
	311
	312	return 0;
	313	}
	314
	315	static int at91_usart_spi_probe(struct platform_device *pdev)
	316	{
	317	struct resource *regs;
	318	struct spi_controller *controller;
	319	struct at91_usart_spi *aus;
	320	struct clk *clk;
	321	int irq;
	322	int ret;
	323
	324	regs = platform_get_resource(to_platform_device(pdev->dev.parent),
	325	IORESOURCE_MEM, 0);
	326	if (!regs)
327	return -EINVAL;
328
329	irq = platform_get_irq(to_platform_device(pdev->dev.parent), 0);
330	if (irq < 0)
331	return irq;
332
333	clk = devm_clk_get(pdev->dev.parent, "usart");
334	if (IS_ERR(clk))
335	return PTR_ERR(clk);
336
337	ret = -ENOMEM;
338	controller = spi_alloc_master(&pdev->dev, sizeof(*aus));
339	if (!controller)
340	goto at91_usart_spi_probe_fail;
341
342	ret = at91_usart_gpio_setup(pdev);
343	if (ret)
344	goto at91_usart_spi_probe_fail;
345
346	controller->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_LOOP \| SPI_CS_HIGH;
347	controller->dev.of_node = pdev->dev.parent->of_node;
348	controller->bits_per_word_mask = SPI_BPW_MASK(8);
349	controller->setup = at91_usart_spi_setup;
350	controller->flags = SPI_MASTER_MUST_RX \| SPI_MASTER_MUST_TX;
351	controller->transfer_one = at91_usart_spi_transfer_one;
352	controller->prepare_message = at91_usart_spi_prepare_message;
353	controller->unprepare_message = at91_usart_spi_unprepare_message;
354	controller->cleanup = at91_usart_spi_cleanup;
355	controller->max_speed_hz = DIV_ROUND_UP(clk_get_rate(clk),
356	US_MIN_CLK_DIV);
357	controller->min_speed_hz = DIV_ROUND_UP(clk_get_rate(clk),
358	US_MAX_CLK_DIV);
359	platform_set_drvdata(pdev, controller);
360
361	aus = spi_master_get_devdata(controller);
362
363	aus->dev = &pdev->dev;
364	aus->regs = devm_ioremap_resource(&pdev->dev, regs);
365	if (IS_ERR(aus->regs)) {
366	ret = PTR_ERR(aus->regs);
367	goto at91_usart_spi_probe_fail;
368	}
369
370	aus->irq = irq;
371	aus->clk = clk;
372
373	ret = devm_request_irq(&pdev->dev, irq, at91_usart_spi_interrupt, 0,
374	dev_name(&pdev->dev), controller);
375	if (ret)
376	goto at91_usart_spi_probe_fail;
377
378	ret = clk_prepare_enable(clk);
379	if (ret)
380	goto at91_usart_spi_probe_fail;
381
382	aus->spi_clk = clk_get_rate(clk);
383	at91_usart_spi_init(aus);
384
385	spin_lock_init(&aus->lock);
386	ret = devm_spi_register_master(&pdev->dev, controller);
387	if (ret)
388	goto at91_usart_fail_register_master;
389
390	dev_info(&pdev->dev,
391	"AT91 USART SPI Controller version 0x%x at %pa (irq %d)\n",
392	at91_usart_spi_readl(aus, VERSION),
393	&regs->start, irq);
394
395	return 0;
396
397	at91_usart_fail_register_master:
398	clk_disable_unprepare(clk);
399	at91_usart_spi_probe_fail:
400	spi_master_put(controller);
401	return ret;
402	}
403
96ed3ecd RP	404	__maybe_unused static int at91_usart_spi_runtime_suspend(struct device *dev)
	405	{
	406	struct spi_controller *ctlr = dev_get_drvdata(dev);
	407	struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);
	408
	409	clk_disable_unprepare(aus->clk);
	410	pinctrl_pm_select_sleep_state(dev);
	411
	412	return 0;
	413	}
	414
	415	__maybe_unused static int at91_usart_spi_runtime_resume(struct device *dev)
	416	{
	417	struct spi_controller *ctrl = dev_get_drvdata(dev);
	418	struct at91_usart_spi *aus = spi_master_get_devdata(ctrl);
	419
	420	pinctrl_pm_select_default_state(dev);
	421
	422	return clk_prepare_enable(aus->clk);
	423	}
	424
	425	__maybe_unused static int at91_usart_spi_suspend(struct device *dev)
	426	{
	427	struct spi_controller *ctrl = dev_get_drvdata(dev);
	428	int ret;
	429
	430	ret = spi_controller_suspend(ctrl);
	431	if (ret)
	432	return ret;
	433
	434	if (!pm_runtime_suspended(dev))
	435	at91_usart_spi_runtime_suspend(dev);
	436
	437	return 0;
	438	}
	439
	440	__maybe_unused static int at91_usart_spi_resume(struct device *dev)
	441	{
	442	struct spi_controller *ctrl = dev_get_drvdata(dev);
	443	struct at91_usart_spi *aus = spi_master_get_devdata(ctrl);
	444	int ret;
	445
	446	if (!pm_runtime_suspended(dev)) {
	447	ret = at91_usart_spi_runtime_resume(dev);
	448	if (ret)
	449	return ret;
	450	}
	451
	452	at91_usart_spi_init(aus);
	453
	454	return spi_controller_resume(ctrl);
	455	}
	456
e1892546 RP	457	static int at91_usart_spi_remove(struct platform_device *pdev)
	458	{
	459	struct spi_controller *ctlr = platform_get_drvdata(pdev);
	460	struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);
	461
	462	clk_disable_unprepare(aus->clk);
	463
	464	return 0;
	465	}
	466
96ed3ecd RP	467	static const struct dev_pm_ops at91_usart_spi_pm_ops = {
	468	SET_SYSTEM_SLEEP_PM_OPS(at91_usart_spi_suspend, at91_usart_spi_resume)
	469	SET_RUNTIME_PM_OPS(at91_usart_spi_runtime_suspend,
	470	at91_usart_spi_runtime_resume, NULL)
	471	};
	472
e1892546 RP	473	static const struct of_device_id at91_usart_spi_dt_ids[] = {
	474	{ .compatible = "microchip,at91sam9g45-usart-spi"},
	475	{ /* sentinel */}
	476	};
	477
	478	MODULE_DEVICE_TABLE(of, at91_usart_spi_dt_ids);
	479
	480	static struct platform_driver at91_usart_spi_driver = {
	481	.driver = {
	482	.name = "at91_usart_spi",
96ed3ecd	483	.pm = &at91_usart_spi_pm_ops,
e1892546 RP	484	},
	485	.probe = at91_usart_spi_probe,
	486	.remove = at91_usart_spi_remove,
	487	};
	488
	489	module_platform_driver(at91_usart_spi_driver);
	490
	491	MODULE_DESCRIPTION("Microchip AT91 USART SPI Controller driver");
	492	MODULE_AUTHOR("Radu Pirea <radu.pirea@microchip.com>");
	493	MODULE_LICENSE("GPL v2");
	494	MODULE_ALIAS("platform:at91_usart_spi");