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spi: aspeed: Adjust direct mapping to device size
[linux-2.6-block.git] / drivers / spi / spi-aspeed-smc.c
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e3228ed9
CLG		 1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * ASPEED FMC/SPI Memory Controller Driver
4 *
5 * Copyright (c) 2015-2022, IBM Corporation.
6 * Copyright (c) 2020, ASPEED Corporation.
7 */
8
9#include <linux/clk.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/of_platform.h>
13#include <linux/platform_device.h>
14#include <linux/spi/spi.h>
15#include <linux/spi/spi-mem.h>
16
17#define DEVICE_NAME "spi-aspeed-smc"
18
19/* Type setting Register */
20#define CONFIG_REG 0x0
21#define CONFIG_TYPE_SPI 0x2
22
23/* CE Control Register */
24#define CE_CTRL_REG 0x4
25
26/* CEx Control Register */
27#define CE0_CTRL_REG 0x10
28#define CTRL_IO_MODE_MASK GENMASK(30, 28)
29#define CTRL_IO_SINGLE_DATA 0x0
30#define CTRL_IO_DUAL_DATA BIT(29)
31#define CTRL_IO_QUAD_DATA BIT(30)
32#define CTRL_COMMAND_SHIFT 16
33#define CTRL_IO_DUMMY_SET(dummy) \
34 (((((dummy) >> 2) & 0x1) << 14) | (((dummy) & 0x3) << 6))
35#define CTRL_CE_STOP_ACTIVE BIT(2)
36#define CTRL_IO_MODE_CMD_MASK GENMASK(1, 0)
37#define CTRL_IO_MODE_NORMAL 0x0
38#define CTRL_IO_MODE_READ 0x1
39#define CTRL_IO_MODE_WRITE 0x2
40#define CTRL_IO_MODE_USER 0x3
41
42#define CTRL_IO_CMD_MASK 0xf0ff40c3
43
44/* CEx Address Decoding Range Register */
45#define CE0_SEGMENT_ADDR_REG 0x30
46
47enum aspeed_spi_ctl_reg_value {
48 ASPEED_SPI_BASE,
49 ASPEED_SPI_READ,
50 ASPEED_SPI_WRITE,
51 ASPEED_SPI_MAX,
52};
53
54struct aspeed_spi;
55
56struct aspeed_spi_chip {
57 struct aspeed_spi *aspi;
58 u32 cs;
59 void __iomem *ctl;
60 void __iomem *ahb_base;
61 u32 ahb_window_size;
62 u32 ctl_val[ASPEED_SPI_MAX];
63 u32 clk_freq;
64};
65
66struct aspeed_spi_data {
67 u32 ctl0;
68 u32 max_cs;
69 bool hastype;
70 u32 mode_bits;
71 u32 we0;
72
73 u32 (*segment_start)(struct aspeed_spi *aspi, u32 reg);
74 u32 (*segment_end)(struct aspeed_spi *aspi, u32 reg);
75 u32 (*segment_reg)(struct aspeed_spi *aspi, u32 start, u32 end);
76};
77
78#define ASPEED_SPI_MAX_NUM_CS 5
79
80struct aspeed_spi {
81 const struct aspeed_spi_data *data;
82
83 void __iomem *regs;
84 void __iomem *ahb_base;
85 u32 ahb_base_phy;
86 u32 ahb_window_size;
87 struct device *dev;
88
89 struct clk *clk;
90 u32 clk_freq;
91
92 struct aspeed_spi_chip chips[ASPEED_SPI_MAX_NUM_CS];
93};
94
95static u32 aspeed_spi_get_io_mode(const struct spi_mem_op *op)
96{
97 switch (op->data.buswidth) {
98 case 1:
99 return CTRL_IO_SINGLE_DATA;
100 case 2:
101 return CTRL_IO_DUAL_DATA;
102 case 4:
103 return CTRL_IO_QUAD_DATA;
104 default:
105 return CTRL_IO_SINGLE_DATA;
106 }
107}
108
109static void aspeed_spi_set_io_mode(struct aspeed_spi_chip *chip, u32 io_mode)
110{
111 u32 ctl;
112
113 if (io_mode > 0) {
114 ctl = readl(chip->ctl) & ~CTRL_IO_MODE_MASK;
115 ctl |= io_mode;
116 writel(ctl, chip->ctl);
117 }
118}
119
120static void aspeed_spi_start_user(struct aspeed_spi_chip *chip)
121{
122 u32 ctl = chip->ctl_val[ASPEED_SPI_BASE];
123
124 ctl |= CTRL_IO_MODE_USER | CTRL_CE_STOP_ACTIVE;
125 writel(ctl, chip->ctl);
126
127 ctl &= ~CTRL_CE_STOP_ACTIVE;
128 writel(ctl, chip->ctl);
129}
130
131static void aspeed_spi_stop_user(struct aspeed_spi_chip *chip)
132{
133 u32 ctl = chip->ctl_val[ASPEED_SPI_READ] |
134 CTRL_IO_MODE_USER | CTRL_CE_STOP_ACTIVE;
135
136 writel(ctl, chip->ctl);
137
138 /* Restore defaults */
139 writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
140}
141
142static int aspeed_spi_read_from_ahb(void *buf, void __iomem *src, size_t len)
143{
144 size_t offset = 0;
145
146 if (IS_ALIGNED((uintptr_t)src, sizeof(uintptr_t)) &&
147 IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) {
148 ioread32_rep(src, buf, len >> 2);
149 offset = len & ~0x3;
150 len -= offset;
151 }
152 ioread8_rep(src, (u8 *)buf + offset, len);
153 return 0;
154}
155
156static int aspeed_spi_write_to_ahb(void __iomem *dst, const void *buf, size_t len)
157{
158 size_t offset = 0;
159
160 if (IS_ALIGNED((uintptr_t)dst, sizeof(uintptr_t)) &&
161 IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) {
162 iowrite32_rep(dst, buf, len >> 2);
163 offset = len & ~0x3;
164 len -= offset;
165 }
166 iowrite8_rep(dst, (const u8 *)buf + offset, len);
167 return 0;
168}
169
170static int aspeed_spi_send_cmd_addr(struct aspeed_spi_chip *chip, u8 addr_nbytes,
171 u64 offset, u32 opcode)
172{
173 __be32 temp;
174 u32 cmdaddr;
175
176 switch (addr_nbytes) {
177 case 3:
178 cmdaddr = offset & 0xFFFFFF;
179 cmdaddr |= opcode << 24;
180
181 temp = cpu_to_be32(cmdaddr);
182 aspeed_spi_write_to_ahb(chip->ahb_base, &temp, 4);
183 break;
184 case 4:
185 temp = cpu_to_be32(offset);
186 aspeed_spi_write_to_ahb(chip->ahb_base, &opcode, 1);
187 aspeed_spi_write_to_ahb(chip->ahb_base, &temp, 4);
188 break;
189 default:
190 WARN_ONCE(1, "Unexpected address width %u", addr_nbytes);
191 return -EOPNOTSUPP;
192 }
193 return 0;
194}
195
196static int aspeed_spi_read_reg(struct aspeed_spi_chip *chip,
197 const struct spi_mem_op *op)
198{
199 aspeed_spi_start_user(chip);
200 aspeed_spi_write_to_ahb(chip->ahb_base, &op->cmd.opcode, 1);
201 aspeed_spi_read_from_ahb(op->data.buf.in,
202 chip->ahb_base, op->data.nbytes);
203 aspeed_spi_stop_user(chip);
204 return 0;
205}
206
207static int aspeed_spi_write_reg(struct aspeed_spi_chip *chip,
208 const struct spi_mem_op *op)
209{
210 aspeed_spi_start_user(chip);
211 aspeed_spi_write_to_ahb(chip->ahb_base, &op->cmd.opcode, 1);
212 aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out,
213 op->data.nbytes);
214 aspeed_spi_stop_user(chip);
215 return 0;
216}
217
218static ssize_t aspeed_spi_read_user(struct aspeed_spi_chip *chip,
219 const struct spi_mem_op *op,
220 u64 offset, size_t len, void *buf)
221{
222 int io_mode = aspeed_spi_get_io_mode(op);
223 u8 dummy = 0xFF;
224 int i;
225 int ret;
226
227 aspeed_spi_start_user(chip);
228
229 ret = aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, offset, op->cmd.opcode);
230 if (ret < 0)
231 return ret;
232
233 if (op->dummy.buswidth && op->dummy.nbytes) {
234 for (i = 0; i < op->dummy.nbytes / op->dummy.buswidth; i++)
235 aspeed_spi_write_to_ahb(chip->ahb_base, &dummy, sizeof(dummy));
236 }
237
238 aspeed_spi_set_io_mode(chip, io_mode);
239
240 aspeed_spi_read_from_ahb(buf, chip->ahb_base, len);
241 aspeed_spi_stop_user(chip);
242 return 0;
243}
244
245static ssize_t aspeed_spi_write_user(struct aspeed_spi_chip *chip,
246 const struct spi_mem_op *op)
247{
248 int ret;
249
250 aspeed_spi_start_user(chip);
251 ret = aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, op->addr.val, op->cmd.opcode);
252 if (ret < 0)
253 return ret;
254 aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out, op->data.nbytes);
255 aspeed_spi_stop_user(chip);
256 return 0;
257}
258
259/* support for 1-1-1, 1-1-2 or 1-1-4 */
260static bool aspeed_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
261{
262 if (op->cmd.buswidth > 1)
263 return false;
264
265 if (op->addr.nbytes != 0) {
266 if (op->addr.buswidth > 1)
267 return false;
268 if (op->addr.nbytes < 3 || op->addr.nbytes > 4)
269 return false;
270 }
271
272 if (op->dummy.nbytes != 0) {
273 if (op->dummy.buswidth > 1 || op->dummy.nbytes > 7)
274 return false;
275 }
276
277 if (op->data.nbytes != 0 && op->data.buswidth > 4)
278 return false;
279
280 return spi_mem_default_supports_op(mem, op);
281}
282
283static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
284{
285 struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
286 struct aspeed_spi_chip *chip = &aspi->chips[mem->spi->chip_select];
287 u32 addr_mode, addr_mode_backup;
288 u32 ctl_val;
289 int ret = 0;
290
291 dev_dbg(aspi->dev,
292 "CE%d %s OP %#x mode:%d.%d.%d.%d naddr:%#x ndummies:%#x len:%#x",
293 chip->cs, op->data.dir == SPI_MEM_DATA_IN ? "read" : "write",
294 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
295 op->dummy.buswidth, op->data.buswidth,
296 op->addr.nbytes, op->dummy.nbytes, op->data.nbytes);
297
298 addr_mode = readl(aspi->regs + CE_CTRL_REG);
299 addr_mode_backup = addr_mode;
300
301 ctl_val = chip->ctl_val[ASPEED_SPI_BASE];
302 ctl_val &= ~CTRL_IO_CMD_MASK;
303
304 ctl_val |= op->cmd.opcode << CTRL_COMMAND_SHIFT;
305
306 /* 4BYTE address mode */
307 if (op->addr.nbytes) {
308 if (op->addr.nbytes == 4)
309 addr_mode |= (0x11 << chip->cs);
310 else
311 addr_mode &= ~(0x11 << chip->cs);
312 }
313
314 if (op->dummy.nbytes)
315 ctl_val |= CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth);
316
317 if (op->data.nbytes)
318 ctl_val |= aspeed_spi_get_io_mode(op);
319
320 if (op->data.dir == SPI_MEM_DATA_OUT)
321 ctl_val |= CTRL_IO_MODE_WRITE;
322 else
323 ctl_val |= CTRL_IO_MODE_READ;
324
325 if (addr_mode != addr_mode_backup)
326 writel(addr_mode, aspi->regs + CE_CTRL_REG);
327 writel(ctl_val, chip->ctl);
328
329 if (op->data.dir == SPI_MEM_DATA_IN) {
330 if (!op->addr.nbytes)
331 ret = aspeed_spi_read_reg(chip, op);
332 else
333 ret = aspeed_spi_read_user(chip, op, op->addr.val,
334 op->data.nbytes, op->data.buf.in);
335 } else {
336 if (!op->addr.nbytes)
337 ret = aspeed_spi_write_reg(chip, op);
338 else
339 ret = aspeed_spi_write_user(chip, op);
340 }
341
342 /* Restore defaults */
343 if (addr_mode != addr_mode_backup)
344 writel(addr_mode_backup, aspi->regs + CE_CTRL_REG);
345 writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
346 return ret;
347}
348
349static int aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
350{
351 int ret;
352
353 ret = do_aspeed_spi_exec_op(mem, op);
354 if (ret)
355 dev_err(&mem->spi->dev, "operation failed: %d\n", ret);
356 return ret;
357}
358
359static const char *aspeed_spi_get_name(struct spi_mem *mem)
360{
361 struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
362 struct device *dev = aspi->dev;
363
364 return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select);
365}
366
367struct aspeed_spi_window {
368 u32 cs;
369 u32 offset;
370 u32 size;
371};
372
373static void aspeed_spi_get_windows(struct aspeed_spi *aspi,
374 struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS])
375{
376 const struct aspeed_spi_data *data = aspi->data;
377 u32 reg_val;
378 u32 cs;
379
380 for (cs = 0; cs < aspi->data->max_cs; cs++) {
381 reg_val = readl(aspi->regs + CE0_SEGMENT_ADDR_REG + cs * 4);
382 windows[cs].cs = cs;
383 windows[cs].size = data->segment_end(aspi, reg_val) -
384 data->segment_start(aspi, reg_val);
385 windows[cs].offset = cs ? windows[cs - 1].offset + windows[cs - 1].size : 0;
386 dev_vdbg(aspi->dev, "CE%d offset=0x%.8x size=0x%x\n", cs,
387 windows[cs].offset, windows[cs].size);
388 }
389}
390
391/*
392 * On the AST2600, some CE windows are closed by default at reset but
393 * U-Boot should open all.
394 */
395static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip)
396{
397 struct aspeed_spi *aspi = chip->aspi;
398 struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 };
399 struct aspeed_spi_window *win = &windows[chip->cs];
400
401 aspeed_spi_get_windows(aspi, windows);
402
403 chip->ahb_base = aspi->ahb_base + win->offset;
404 chip->ahb_window_size = win->size;
405
406 dev_dbg(aspi->dev, "CE%d default window [ 0x%.8x - 0x%.8x ] %dMB",
407 chip->cs, aspi->ahb_base_phy + win->offset,
408 aspi->ahb_base_phy + win->offset + win->size - 1,
409 win->size >> 20);
410
411 return chip->ahb_window_size ? 0 : -1;
412}
413
bb084f94
CLG		 414static int aspeed_spi_set_window(struct aspeed_spi *aspi,
415 const struct aspeed_spi_window *win)
416{
417 u32 start = aspi->ahb_base_phy + win->offset;
418 u32 end = start + win->size;
419 void __iomem *seg_reg = aspi->regs + CE0_SEGMENT_ADDR_REG + win->cs * 4;
420 u32 seg_val_backup = readl(seg_reg);
421 u32 seg_val = aspi->data->segment_reg(aspi, start, end);
422
423 if (seg_val == seg_val_backup)
424 return 0;
425
426 writel(seg_val, seg_reg);
427
428 /*
429 * Restore initial value if something goes wrong else we could
430 * loose access to the chip.
431 */
432 if (seg_val != readl(seg_reg)) {
433 dev_err(aspi->dev, "CE%d invalid window [ 0x%.8x - 0x%.8x ] %dMB",
434 win->cs, start, end - 1, win->size >> 20);
435 writel(seg_val_backup, seg_reg);
436 return -EIO;
437 }
438
439 if (win->size)
440 dev_dbg(aspi->dev, "CE%d new window [ 0x%.8x - 0x%.8x ] %dMB",
441 win->cs, start, end - 1, win->size >> 20);
442 else
443 dev_dbg(aspi->dev, "CE%d window closed", win->cs);
444
445 return 0;
446}
447
448/*
449 * Yet to be done when possible :
450 * - Align mappings on flash size (we don't have the info)
451 * - ioremap each window, not strictly necessary since the overall window
452 * is correct.
453 */
454static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
455 u32 local_offset, u32 size)
456{
457 struct aspeed_spi *aspi = chip->aspi;
458 struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 };
459 struct aspeed_spi_window *win = &windows[chip->cs];
460 int ret;
461
462 aspeed_spi_get_windows(aspi, windows);
463
464 /* Adjust this chip window */
465 win->offset += local_offset;
466 win->size = size;
467
468 if (win->offset + win->size > aspi->ahb_window_size) {
469 win->size = aspi->ahb_window_size - win->offset;
470 dev_warn(aspi->dev, "CE%d window resized to %dMB", chip->cs, win->size >> 20);
471 }
472
473 ret = aspeed_spi_set_window(aspi, win);
474 if (ret)
475 return ret;
476
477 /* Update chip mapping info */
478 chip->ahb_base = aspi->ahb_base + win->offset;
479 chip->ahb_window_size = win->size;
480
481 /*
482 * Also adjust next chip window to make sure that it does not
483 * overlap with the current window.
484 */
485 if (chip->cs < aspi->data->max_cs - 1) {
486 struct aspeed_spi_window *next = &windows[chip->cs + 1];
487
488 /* Change offset and size to keep the same end address */
489 if ((next->offset + next->size) > (win->offset + win->size))
490 next->size = (next->offset + next->size) - (win->offset + win->size);
491 else
492 next->size = 0;
493 next->offset = win->offset + win->size;
494
495 aspeed_spi_set_window(aspi, next);
496 }
497 return 0;
498}
499
9da06d7b
CLG		 500static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
501{
502 struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
503 struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select];
504 struct spi_mem_op *op = &desc->info.op_tmpl;
505 u32 ctl_val;
506 int ret = 0;
507
508 chip->clk_freq = desc->mem->spi->max_speed_hz;
509
510 /* Only for reads */
511 if (op->data.dir != SPI_MEM_DATA_IN)
512 return -EOPNOTSUPP;
513
bb084f94
CLG		 514 aspeed_spi_chip_adjust_window(chip, desc->info.offset, desc->info.length);
515
9da06d7b
CLG		 516 if (desc->info.length > chip->ahb_window_size)
517 dev_warn(aspi->dev, "CE%d window (%dMB) too small for mapping",
518 chip->cs, chip->ahb_window_size >> 20);
519
520 /* Define the default IO read settings */
521 ctl_val = readl(chip->ctl) & ~CTRL_IO_CMD_MASK;
522 ctl_val |= aspeed_spi_get_io_mode(op) |
523 op->cmd.opcode << CTRL_COMMAND_SHIFT |
524 CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth) |
525 CTRL_IO_MODE_READ;
526
527 /* Tune 4BYTE address mode */
528 if (op->addr.nbytes) {
529 u32 addr_mode = readl(aspi->regs + CE_CTRL_REG);
530
531 if (op->addr.nbytes == 4)
532 addr_mode |= (0x11 << chip->cs);
533 else
534 addr_mode &= ~(0x11 << chip->cs);
535 writel(addr_mode, aspi->regs + CE_CTRL_REG);
536 }
537
538 /* READ mode is the controller default setting */
539 chip->ctl_val[ASPEED_SPI_READ] = ctl_val;
540 writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
541
542 dev_info(aspi->dev, "CE%d read buswidth:%d [0x%08x]\n",
543 chip->cs, op->data.buswidth, chip->ctl_val[ASPEED_SPI_READ]);
544
545 return ret;
546}
547
548static ssize_t aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc,
549 u64 offset, size_t len, void *buf)
550{
551 struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
552 struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select];
553
554 /* Switch to USER command mode if mapping window is too small */
555 if (chip->ahb_window_size < offset + len) {
556 int ret;
557
558 ret = aspeed_spi_read_user(chip, &desc->info.op_tmpl, offset, len, buf);
559 if (ret < 0)
560 return ret;
561 } else {
562 memcpy_fromio(buf, chip->ahb_base + offset, len);
563 }
564
565 return len;
566}
567
e3228ed9
CLG		 568static const struct spi_controller_mem_ops aspeed_spi_mem_ops = {
569 .supports_op = aspeed_spi_supports_op,
570 .exec_op = aspeed_spi_exec_op,
571 .get_name = aspeed_spi_get_name,
9da06d7b
CLG		 572 .dirmap_create = aspeed_spi_dirmap_create,
573 .dirmap_read = aspeed_spi_dirmap_read,
e3228ed9
CLG		 574};
575
576static void aspeed_spi_chip_set_type(struct aspeed_spi *aspi, unsigned int cs, int type)
577{
578 u32 reg;
579
580 reg = readl(aspi->regs + CONFIG_REG);
581 reg &= ~(0x3 << (cs * 2));
582 reg |= type << (cs * 2);
583 writel(reg, aspi->regs + CONFIG_REG);
584}
585
586static void aspeed_spi_chip_enable(struct aspeed_spi *aspi, unsigned int cs, bool enable)
587{
588 u32 we_bit = BIT(aspi->data->we0 + cs);
589 u32 reg = readl(aspi->regs + CONFIG_REG);
590
591 if (enable)
592 reg |= we_bit;
593 else
594 reg &= ~we_bit;
595 writel(reg, aspi->regs + CONFIG_REG);
596}
597
598static int aspeed_spi_setup(struct spi_device *spi)
599{
600 struct aspeed_spi *aspi = spi_controller_get_devdata(spi->master);
601 const struct aspeed_spi_data *data = aspi->data;
602 unsigned int cs = spi->chip_select;
603 struct aspeed_spi_chip *chip = &aspi->chips[cs];
604
605 chip->aspi = aspi;
606 chip->cs = cs;
607 chip->ctl = aspi->regs + data->ctl0 + cs * 4;
608
609 /* The driver only supports SPI type flash */
610 if (data->hastype)
611 aspeed_spi_chip_set_type(aspi, cs, CONFIG_TYPE_SPI);
612
613 if (aspeed_spi_chip_set_default_window(chip) < 0) {
614 dev_warn(aspi->dev, "CE%d window invalid", cs);
615 return -EINVAL;
616 }
617
618 aspeed_spi_chip_enable(aspi, cs, true);
619
620 chip->ctl_val[ASPEED_SPI_BASE] = CTRL_CE_STOP_ACTIVE | CTRL_IO_MODE_USER;
621
622 dev_dbg(aspi->dev, "CE%d setup done\n", cs);
623 return 0;
624}
625
626static void aspeed_spi_cleanup(struct spi_device *spi)
627{
628 struct aspeed_spi *aspi = spi_controller_get_devdata(spi->master);
629 unsigned int cs = spi->chip_select;
630
631 aspeed_spi_chip_enable(aspi, cs, false);
632
633 dev_dbg(aspi->dev, "CE%d cleanup done\n", cs);
634}
635
636static void aspeed_spi_enable(struct aspeed_spi *aspi, bool enable)
637{
638 int cs;
639
640 for (cs = 0; cs < aspi->data->max_cs; cs++)
641 aspeed_spi_chip_enable(aspi, cs, enable);
642}
643
644static int aspeed_spi_probe(struct platform_device *pdev)
645{
646 struct device *dev = &pdev->dev;
647 const struct aspeed_spi_data *data;
648 struct spi_controller *ctlr;
649 struct aspeed_spi *aspi;
650 struct resource *res;
651 int ret;
652
653 data = of_device_get_match_data(&pdev->dev);
654 if (!data)
655 return -ENODEV;
656
657 ctlr = devm_spi_alloc_master(dev, sizeof(*aspi));
658 if (!ctlr)
659 return -ENOMEM;
660
661 aspi = spi_controller_get_devdata(ctlr);
662 platform_set_drvdata(pdev, aspi);
663 aspi->data = data;
664 aspi->dev = dev;
665
666 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
667 aspi->regs = devm_ioremap_resource(dev, res);
668 if (IS_ERR(aspi->regs)) {
669 dev_err(dev, "missing AHB register window\n");
670 return PTR_ERR(aspi->regs);
671 }
672
673 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
674 aspi->ahb_base = devm_ioremap_resource(dev, res);
675 if (IS_ERR(aspi->ahb_base)) {
676 dev_err(dev, "missing AHB mapping window\n");
677 return PTR_ERR(aspi->ahb_base);
678 }
679
680 aspi->ahb_window_size = resource_size(res);
681 aspi->ahb_base_phy = res->start;
682
683 aspi->clk = devm_clk_get(&pdev->dev, NULL);
684 if (IS_ERR(aspi->clk)) {
685 dev_err(dev, "missing clock\n");
686 return PTR_ERR(aspi->clk);
687 }
688
689 aspi->clk_freq = clk_get_rate(aspi->clk);
690 if (!aspi->clk_freq) {
691 dev_err(dev, "invalid clock\n");
692 return -EINVAL;
693 }
694
695 ret = clk_prepare_enable(aspi->clk);
696 if (ret) {
697 dev_err(dev, "can not enable the clock\n");
698 return ret;
699 }
700
701 /* IRQ is for DMA, which the driver doesn't support yet */
702
703 ctlr->mode_bits = SPI_RX_DUAL | SPI_TX_DUAL | data->mode_bits;
704 ctlr->bus_num = pdev->id;
705 ctlr->mem_ops = &aspeed_spi_mem_ops;
706 ctlr->setup = aspeed_spi_setup;
707 ctlr->cleanup = aspeed_spi_cleanup;
708 ctlr->num_chipselect = data->max_cs;
709 ctlr->dev.of_node = dev->of_node;
710
711 ret = devm_spi_register_controller(dev, ctlr);
712 if (ret) {
713 dev_err(&pdev->dev, "spi_register_controller failed\n");
714 goto disable_clk;
715 }
716 return 0;
717
718disable_clk:
719 clk_disable_unprepare(aspi->clk);
720 return ret;
721}
722
723static int aspeed_spi_remove(struct platform_device *pdev)
724{
725 struct aspeed_spi *aspi = platform_get_drvdata(pdev);
726
727 aspeed_spi_enable(aspi, false);
728 clk_disable_unprepare(aspi->clk);
729 return 0;
730}
731
732/*
733 * AHB mappings
734 */
735
736/*
737 * The Segment Registers of the AST2400 and AST2500 use a 8MB unit.
738 * The address range is encoded with absolute addresses in the overall
739 * mapping window.
740 */
741static u32 aspeed_spi_segment_start(struct aspeed_spi *aspi, u32 reg)
742{
743 return ((reg >> 16) & 0xFF) << 23;
744}
745
746static u32 aspeed_spi_segment_end(struct aspeed_spi *aspi, u32 reg)
747{
748 return ((reg >> 24) & 0xFF) << 23;
749}
750
751static u32 aspeed_spi_segment_reg(struct aspeed_spi *aspi, u32 start, u32 end)
752{
753 return (((start >> 23) & 0xFF) << 16) | (((end >> 23) & 0xFF) << 24);
754}
755
756/*
757 * The Segment Registers of the AST2600 use a 1MB unit. The address
758 * range is encoded with offsets in the overall mapping window.
759 */
760
761#define AST2600_SEG_ADDR_MASK 0x0ff00000
762
763static u32 aspeed_spi_segment_ast2600_start(struct aspeed_spi *aspi,
764 u32 reg)
765{
766 u32 start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK;
767
768 return aspi->ahb_base_phy + start_offset;
769}
770
771static u32 aspeed_spi_segment_ast2600_end(struct aspeed_spi *aspi,
772 u32 reg)
773{
774 u32 end_offset = reg & AST2600_SEG_ADDR_MASK;
775
776 /* segment is disabled */
777 if (!end_offset)
778 return aspi->ahb_base_phy;
779
780 return aspi->ahb_base_phy + end_offset + 0x100000;
781}
782
783static u32 aspeed_spi_segment_ast2600_reg(struct aspeed_spi *aspi,
784 u32 start, u32 end)
785{
786 /* disable zero size segments */
787 if (start == end)
788 return 0;
789
790 return ((start & AST2600_SEG_ADDR_MASK) >> 16) |
791 ((end - 1) & AST2600_SEG_ADDR_MASK);
792}
793
794/*
795 * Platform definitions
796 */
797static const struct aspeed_spi_data ast2400_fmc_data = {
798 .max_cs = 5,
799 .hastype = true,
800 .we0 = 16,
801 .ctl0 = CE0_CTRL_REG,
802 .segment_start = aspeed_spi_segment_start,
803 .segment_end = aspeed_spi_segment_end,
804 .segment_reg = aspeed_spi_segment_reg,
805};
806
807static const struct aspeed_spi_data ast2500_fmc_data = {
808 .max_cs = 3,
809 .hastype = true,
810 .we0 = 16,
811 .ctl0 = CE0_CTRL_REG,
812 .segment_start = aspeed_spi_segment_start,
813 .segment_end = aspeed_spi_segment_end,
814 .segment_reg = aspeed_spi_segment_reg,
815};
816
817static const struct aspeed_spi_data ast2500_spi_data = {
818 .max_cs = 2,
819 .hastype = false,
820 .we0 = 16,
821 .ctl0 = CE0_CTRL_REG,
822 .segment_start = aspeed_spi_segment_start,
823 .segment_end = aspeed_spi_segment_end,
824 .segment_reg = aspeed_spi_segment_reg,
825};
826
827static const struct aspeed_spi_data ast2600_fmc_data = {
828 .max_cs = 3,
829 .hastype = false,
830 .mode_bits = SPI_RX_QUAD | SPI_RX_QUAD,
831 .we0 = 16,
832 .ctl0 = CE0_CTRL_REG,
833 .segment_start = aspeed_spi_segment_ast2600_start,
834 .segment_end = aspeed_spi_segment_ast2600_end,
835 .segment_reg = aspeed_spi_segment_ast2600_reg,
836};
837
838static const struct aspeed_spi_data ast2600_spi_data = {
839 .max_cs = 2,
840 .hastype = false,
841 .mode_bits = SPI_RX_QUAD | SPI_RX_QUAD,
842 .we0 = 16,
843 .ctl0 = CE0_CTRL_REG,
844 .segment_start = aspeed_spi_segment_ast2600_start,
845 .segment_end = aspeed_spi_segment_ast2600_end,
846 .segment_reg = aspeed_spi_segment_ast2600_reg,
847};
848
849static const struct of_device_id aspeed_spi_matches[] = {
850 { .compatible = "aspeed,ast2400-fmc", .data = &ast2400_fmc_data },
851 { .compatible = "aspeed,ast2500-fmc", .data = &ast2500_fmc_data },
852 { .compatible = "aspeed,ast2500-spi", .data = &ast2500_spi_data },
853 { .compatible = "aspeed,ast2600-fmc", .data = &ast2600_fmc_data },
854 { .compatible = "aspeed,ast2600-spi", .data = &ast2600_spi_data },
855 { }
856};
857MODULE_DEVICE_TABLE(of, aspeed_spi_matches);
858
859static struct platform_driver aspeed_spi_driver = {
860 .probe = aspeed_spi_probe,
861 .remove = aspeed_spi_remove,
862 .driver = {
863 .name = DEVICE_NAME,
864 .of_match_table = aspeed_spi_matches,
865 }
866};
867
868module_platform_driver(aspeed_spi_driver);
869
870MODULE_DESCRIPTION("ASPEED Static Memory Controller Driver");
871MODULE_AUTHOR("Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>");
872MODULE_AUTHOR("Cedric Le Goater <clg@kaod.org>");
873MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)