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spi: mpc5xxx-psc: Remove goto to the unexisted label
[linux-2.6-block.git] / drivers / spi / spi-aspeed-smc.c
CommitLineData
e3228ed9
CLG		 1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * ASPEED FMC/SPI Memory Controller Driver
4 *
5 * Copyright (c) 2015-2022, IBM Corporation.
6 * Copyright (c) 2020, ASPEED Corporation.
7 */
8
9#include <linux/clk.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/of_platform.h>
13#include <linux/platform_device.h>
14#include <linux/spi/spi.h>
15#include <linux/spi/spi-mem.h>
16
17#define DEVICE_NAME "spi-aspeed-smc"
18
19/* Type setting Register */
20#define CONFIG_REG 0x0
21#define CONFIG_TYPE_SPI 0x2
22
23/* CE Control Register */
24#define CE_CTRL_REG 0x4
25
26/* CEx Control Register */
27#define CE0_CTRL_REG 0x10
28#define CTRL_IO_MODE_MASK GENMASK(30, 28)
29#define CTRL_IO_SINGLE_DATA 0x0
30#define CTRL_IO_DUAL_DATA BIT(29)
31#define CTRL_IO_QUAD_DATA BIT(30)
32#define CTRL_COMMAND_SHIFT 16
53526ab2 33#define CTRL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI only */
e3228ed9
CLG		 34#define CTRL_IO_DUMMY_SET(dummy) \
35 (((((dummy) >> 2) & 0x1) << 14) | (((dummy) & 0x3) << 6))
eeaec1ea
CLG		 36#define CTRL_FREQ_SEL_SHIFT 8
37#define CTRL_FREQ_SEL_MASK GENMASK(11, CTRL_FREQ_SEL_SHIFT)
e3228ed9
CLG		 38#define CTRL_CE_STOP_ACTIVE BIT(2)
39#define CTRL_IO_MODE_CMD_MASK GENMASK(1, 0)
40#define CTRL_IO_MODE_NORMAL 0x0
41#define CTRL_IO_MODE_READ 0x1
42#define CTRL_IO_MODE_WRITE 0x2
43#define CTRL_IO_MODE_USER 0x3
44
45#define CTRL_IO_CMD_MASK 0xf0ff40c3
46
47/* CEx Address Decoding Range Register */
48#define CE0_SEGMENT_ADDR_REG 0x30
49
eeaec1ea
CLG		 50/* CEx Read timing compensation register */
51#define CE0_TIMING_COMPENSATION_REG 0x94
52
e3228ed9
CLG		 53enum aspeed_spi_ctl_reg_value {
54 ASPEED_SPI_BASE,
55 ASPEED_SPI_READ,
56 ASPEED_SPI_WRITE,
57 ASPEED_SPI_MAX,
58};
59
60struct aspeed_spi;
61
62struct aspeed_spi_chip {
63 struct aspeed_spi *aspi;
64 u32 cs;
65 void __iomem *ctl;
66 void __iomem *ahb_base;
67 u32 ahb_window_size;
68 u32 ctl_val[ASPEED_SPI_MAX];
69 u32 clk_freq;
70};
71
72struct aspeed_spi_data {
73 u32 ctl0;
74 u32 max_cs;
75 bool hastype;
76 u32 mode_bits;
77 u32 we0;
eeaec1ea
CLG		 78 u32 timing;
79 u32 hclk_mask;
80 u32 hdiv_max;
e3228ed9
CLG		 81
82 u32 (*segment_start)(struct aspeed_spi *aspi, u32 reg);
83 u32 (*segment_end)(struct aspeed_spi *aspi, u32 reg);
84 u32 (*segment_reg)(struct aspeed_spi *aspi, u32 start, u32 end);
eeaec1ea
CLG		 85 int (*calibrate)(struct aspeed_spi_chip *chip, u32 hdiv,
86 const u8 *golden_buf, u8 *test_buf);
e3228ed9
CLG		 87};
88
89#define ASPEED_SPI_MAX_NUM_CS 5
90
91struct aspeed_spi {
92 const struct aspeed_spi_data *data;
93
94 void __iomem *regs;
95 void __iomem *ahb_base;
96 u32 ahb_base_phy;
97 u32 ahb_window_size;
98 struct device *dev;
99
100 struct clk *clk;
101 u32 clk_freq;
102
103 struct aspeed_spi_chip chips[ASPEED_SPI_MAX_NUM_CS];
104};
105
106static u32 aspeed_spi_get_io_mode(const struct spi_mem_op *op)
107{
108 switch (op->data.buswidth) {
109 case 1:
110 return CTRL_IO_SINGLE_DATA;
111 case 2:
112 return CTRL_IO_DUAL_DATA;
113 case 4:
114 return CTRL_IO_QUAD_DATA;
115 default:
116 return CTRL_IO_SINGLE_DATA;
117 }
118}
119
120static void aspeed_spi_set_io_mode(struct aspeed_spi_chip *chip, u32 io_mode)
121{
122 u32 ctl;
123
124 if (io_mode > 0) {
125 ctl = readl(chip->ctl) & ~CTRL_IO_MODE_MASK;
126 ctl |= io_mode;
127 writel(ctl, chip->ctl);
128 }
129}
130
131static void aspeed_spi_start_user(struct aspeed_spi_chip *chip)
132{
133 u32 ctl = chip->ctl_val[ASPEED_SPI_BASE];
134
135 ctl |= CTRL_IO_MODE_USER | CTRL_CE_STOP_ACTIVE;
136 writel(ctl, chip->ctl);
137
138 ctl &= ~CTRL_CE_STOP_ACTIVE;
139 writel(ctl, chip->ctl);
140}
141
142static void aspeed_spi_stop_user(struct aspeed_spi_chip *chip)
143{
144 u32 ctl = chip->ctl_val[ASPEED_SPI_READ] |
145 CTRL_IO_MODE_USER | CTRL_CE_STOP_ACTIVE;
146
147 writel(ctl, chip->ctl);
148
149 /* Restore defaults */
150 writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
151}
152
153static int aspeed_spi_read_from_ahb(void *buf, void __iomem *src, size_t len)
154{
155 size_t offset = 0;
156
157 if (IS_ALIGNED((uintptr_t)src, sizeof(uintptr_t)) &&
158 IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) {
159 ioread32_rep(src, buf, len >> 2);
160 offset = len & ~0x3;
161 len -= offset;
162 }
163 ioread8_rep(src, (u8 *)buf + offset, len);
164 return 0;
165}
166
167static int aspeed_spi_write_to_ahb(void __iomem *dst, const void *buf, size_t len)
168{
169 size_t offset = 0;
170
171 if (IS_ALIGNED((uintptr_t)dst, sizeof(uintptr_t)) &&
172 IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) {
173 iowrite32_rep(dst, buf, len >> 2);
174 offset = len & ~0x3;
175 len -= offset;
176 }
177 iowrite8_rep(dst, (const u8 *)buf + offset, len);
178 return 0;
179}
180
181static int aspeed_spi_send_cmd_addr(struct aspeed_spi_chip *chip, u8 addr_nbytes,
182 u64 offset, u32 opcode)
183{
184 __be32 temp;
185 u32 cmdaddr;
186
187 switch (addr_nbytes) {
188 case 3:
189 cmdaddr = offset & 0xFFFFFF;
190 cmdaddr |= opcode << 24;
191
192 temp = cpu_to_be32(cmdaddr);
193 aspeed_spi_write_to_ahb(chip->ahb_base, &temp, 4);
194 break;
195 case 4:
196 temp = cpu_to_be32(offset);
197 aspeed_spi_write_to_ahb(chip->ahb_base, &opcode, 1);
198 aspeed_spi_write_to_ahb(chip->ahb_base, &temp, 4);
199 break;
200 default:
201 WARN_ONCE(1, "Unexpected address width %u", addr_nbytes);
202 return -EOPNOTSUPP;
203 }
204 return 0;
205}
206
207static int aspeed_spi_read_reg(struct aspeed_spi_chip *chip,
208 const struct spi_mem_op *op)
209{
210 aspeed_spi_start_user(chip);
211 aspeed_spi_write_to_ahb(chip->ahb_base, &op->cmd.opcode, 1);
212 aspeed_spi_read_from_ahb(op->data.buf.in,
213 chip->ahb_base, op->data.nbytes);
214 aspeed_spi_stop_user(chip);
215 return 0;
216}
217
218static int aspeed_spi_write_reg(struct aspeed_spi_chip *chip,
219 const struct spi_mem_op *op)
220{
221 aspeed_spi_start_user(chip);
222 aspeed_spi_write_to_ahb(chip->ahb_base, &op->cmd.opcode, 1);
223 aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out,
224 op->data.nbytes);
225 aspeed_spi_stop_user(chip);
226 return 0;
227}
228
229static ssize_t aspeed_spi_read_user(struct aspeed_spi_chip *chip,
230 const struct spi_mem_op *op,
231 u64 offset, size_t len, void *buf)
232{
233 int io_mode = aspeed_spi_get_io_mode(op);
234 u8 dummy = 0xFF;
235 int i;
236 int ret;
237
238 aspeed_spi_start_user(chip);
239
240 ret = aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, offset, op->cmd.opcode);
241 if (ret < 0)
242 return ret;
243
244 if (op->dummy.buswidth && op->dummy.nbytes) {
245 for (i = 0; i < op->dummy.nbytes / op->dummy.buswidth; i++)
246 aspeed_spi_write_to_ahb(chip->ahb_base, &dummy, sizeof(dummy));
247 }
248
249 aspeed_spi_set_io_mode(chip, io_mode);
250
251 aspeed_spi_read_from_ahb(buf, chip->ahb_base, len);
252 aspeed_spi_stop_user(chip);
253 return 0;
254}
255
256static ssize_t aspeed_spi_write_user(struct aspeed_spi_chip *chip,
257 const struct spi_mem_op *op)
258{
259 int ret;
260
261 aspeed_spi_start_user(chip);
262 ret = aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, op->addr.val, op->cmd.opcode);
263 if (ret < 0)
264 return ret;
265 aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out, op->data.nbytes);
266 aspeed_spi_stop_user(chip);
267 return 0;
268}
269
270/* support for 1-1-1, 1-1-2 or 1-1-4 */
271static bool aspeed_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
272{
273 if (op->cmd.buswidth > 1)
274 return false;
275
276 if (op->addr.nbytes != 0) {
277 if (op->addr.buswidth > 1)
278 return false;
279 if (op->addr.nbytes < 3 || op->addr.nbytes > 4)
280 return false;
281 }
282
283 if (op->dummy.nbytes != 0) {
284 if (op->dummy.buswidth > 1 || op->dummy.nbytes > 7)
285 return false;
286 }
287
288 if (op->data.nbytes != 0 && op->data.buswidth > 4)
289 return false;
290
291 return spi_mem_default_supports_op(mem, op);
292}
293
53526ab2
CLG		 294static const struct aspeed_spi_data ast2400_spi_data;
295
e3228ed9
CLG		 296static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
297{
298 struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
299 struct aspeed_spi_chip *chip = &aspi->chips[mem->spi->chip_select];
300 u32 addr_mode, addr_mode_backup;
301 u32 ctl_val;
302 int ret = 0;
303
304 dev_dbg(aspi->dev,
305 "CE%d %s OP %#x mode:%d.%d.%d.%d naddr:%#x ndummies:%#x len:%#x",
306 chip->cs, op->data.dir == SPI_MEM_DATA_IN ? "read" : "write",
307 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
308 op->dummy.buswidth, op->data.buswidth,
309 op->addr.nbytes, op->dummy.nbytes, op->data.nbytes);
310
311 addr_mode = readl(aspi->regs + CE_CTRL_REG);
312 addr_mode_backup = addr_mode;
313
314 ctl_val = chip->ctl_val[ASPEED_SPI_BASE];
315 ctl_val &= ~CTRL_IO_CMD_MASK;
316
317 ctl_val |= op->cmd.opcode << CTRL_COMMAND_SHIFT;
318
319 /* 4BYTE address mode */
320 if (op->addr.nbytes) {
321 if (op->addr.nbytes == 4)
322 addr_mode |= (0x11 << chip->cs);
323 else
324 addr_mode &= ~(0x11 << chip->cs);
53526ab2
CLG		 325
326 if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data)
327 ctl_val |= CTRL_IO_ADDRESS_4B;
e3228ed9
CLG		 328 }
329
330 if (op->dummy.nbytes)
331 ctl_val |= CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth);
332
333 if (op->data.nbytes)
334 ctl_val |= aspeed_spi_get_io_mode(op);
335
336 if (op->data.dir == SPI_MEM_DATA_OUT)
337 ctl_val |= CTRL_IO_MODE_WRITE;
338 else
339 ctl_val |= CTRL_IO_MODE_READ;
340
341 if (addr_mode != addr_mode_backup)
342 writel(addr_mode, aspi->regs + CE_CTRL_REG);
343 writel(ctl_val, chip->ctl);
344
345 if (op->data.dir == SPI_MEM_DATA_IN) {
346 if (!op->addr.nbytes)
347 ret = aspeed_spi_read_reg(chip, op);
348 else
349 ret = aspeed_spi_read_user(chip, op, op->addr.val,
350 op->data.nbytes, op->data.buf.in);
351 } else {
352 if (!op->addr.nbytes)
353 ret = aspeed_spi_write_reg(chip, op);
354 else
355 ret = aspeed_spi_write_user(chip, op);
356 }
357
358 /* Restore defaults */
359 if (addr_mode != addr_mode_backup)
360 writel(addr_mode_backup, aspi->regs + CE_CTRL_REG);
361 writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
362 return ret;
363}
364
365static int aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
366{
367 int ret;
368
369 ret = do_aspeed_spi_exec_op(mem, op);
370 if (ret)
371 dev_err(&mem->spi->dev, "operation failed: %d\n", ret);
372 return ret;
373}
374
375static const char *aspeed_spi_get_name(struct spi_mem *mem)
376{
377 struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
378 struct device *dev = aspi->dev;
379
380 return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select);
381}
382
383struct aspeed_spi_window {
384 u32 cs;
385 u32 offset;
386 u32 size;
387};
388
389static void aspeed_spi_get_windows(struct aspeed_spi *aspi,
390 struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS])
391{
392 const struct aspeed_spi_data *data = aspi->data;
393 u32 reg_val;
394 u32 cs;
395
396 for (cs = 0; cs < aspi->data->max_cs; cs++) {
397 reg_val = readl(aspi->regs + CE0_SEGMENT_ADDR_REG + cs * 4);
398 windows[cs].cs = cs;
399 windows[cs].size = data->segment_end(aspi, reg_val) -
400 data->segment_start(aspi, reg_val);
f8aa6c89 401 windows[cs].offset = data->segment_start(aspi, reg_val) - aspi->ahb_base_phy;
e3228ed9
CLG		 402 dev_vdbg(aspi->dev, "CE%d offset=0x%.8x size=0x%x\n", cs,
403 windows[cs].offset, windows[cs].size);
404 }
405}
406
407/*
408 * On the AST2600, some CE windows are closed by default at reset but
409 * U-Boot should open all.
410 */
411static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip)
412{
413 struct aspeed_spi *aspi = chip->aspi;
414 struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 };
415 struct aspeed_spi_window *win = &windows[chip->cs];
416
53526ab2
CLG		 417 /* No segment registers for the AST2400 SPI controller */
418 if (aspi->data == &ast2400_spi_data) {
419 win->offset = 0;
420 win->size = aspi->ahb_window_size;
421 } else {
422 aspeed_spi_get_windows(aspi, windows);
423 }
e3228ed9
CLG		 424
425 chip->ahb_base = aspi->ahb_base + win->offset;
426 chip->ahb_window_size = win->size;
427
428 dev_dbg(aspi->dev, "CE%d default window [ 0x%.8x - 0x%.8x ] %dMB",
429 chip->cs, aspi->ahb_base_phy + win->offset,
430 aspi->ahb_base_phy + win->offset + win->size - 1,
431 win->size >> 20);
432
433 return chip->ahb_window_size ? 0 : -1;
434}
435
bb084f94
CLG		 436static int aspeed_spi_set_window(struct aspeed_spi *aspi,
437 const struct aspeed_spi_window *win)
438{
439 u32 start = aspi->ahb_base_phy + win->offset;
440 u32 end = start + win->size;
441 void __iomem *seg_reg = aspi->regs + CE0_SEGMENT_ADDR_REG + win->cs * 4;
442 u32 seg_val_backup = readl(seg_reg);
443 u32 seg_val = aspi->data->segment_reg(aspi, start, end);
444
445 if (seg_val == seg_val_backup)
446 return 0;
447
448 writel(seg_val, seg_reg);
449
450 /*
451 * Restore initial value if something goes wrong else we could
452 * loose access to the chip.
453 */
454 if (seg_val != readl(seg_reg)) {
455 dev_err(aspi->dev, "CE%d invalid window [ 0x%.8x - 0x%.8x ] %dMB",
456 win->cs, start, end - 1, win->size >> 20);
457 writel(seg_val_backup, seg_reg);
458 return -EIO;
459 }
460
461 if (win->size)
462 dev_dbg(aspi->dev, "CE%d new window [ 0x%.8x - 0x%.8x ] %dMB",
463 win->cs, start, end - 1, win->size >> 20);
464 else
465 dev_dbg(aspi->dev, "CE%d window closed", win->cs);
466
467 return 0;
468}
469
470/*
471 * Yet to be done when possible :
472 * - Align mappings on flash size (we don't have the info)
473 * - ioremap each window, not strictly necessary since the overall window
474 * is correct.
475 */
5785eede 476static const struct aspeed_spi_data ast2500_spi_data;
73ae97e3
PL		 477static const struct aspeed_spi_data ast2600_spi_data;
478static const struct aspeed_spi_data ast2600_fmc_data;
5785eede 479
bb084f94
CLG		 480static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
481 u32 local_offset, u32 size)
482{
483 struct aspeed_spi *aspi = chip->aspi;
484 struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 };
485 struct aspeed_spi_window *win = &windows[chip->cs];
486 int ret;
487
53526ab2
CLG		 488 /* No segment registers for the AST2400 SPI controller */
489 if (aspi->data == &ast2400_spi_data)
490 return 0;
491
5785eede
CLG		 492 /*
493 * Due to an HW issue on the AST2500 SPI controller, the CE0
494 * window size should be smaller than the maximum 128MB.
495 */
496 if (aspi->data == &ast2500_spi_data && chip->cs == 0 && size == SZ_128M) {
497 size = 120 << 20;
498 dev_info(aspi->dev, "CE%d window resized to %dMB (AST2500 HW quirk)",
499 chip->cs, size >> 20);
500 }
501
73ae97e3
PL		 502 /*
503 * The decoding size of AST2600 SPI controller should set at
504 * least 2MB.
505 */
506 if ((aspi->data == &ast2600_spi_data || aspi->data == &ast2600_fmc_data) &&
507 size < SZ_2M) {
508 size = SZ_2M;
509 dev_info(aspi->dev, "CE%d window resized to %dMB (AST2600 Decoding)",
510 chip->cs, size >> 20);
511 }
512
bb084f94
CLG		 513 aspeed_spi_get_windows(aspi, windows);
514
515 /* Adjust this chip window */
516 win->offset += local_offset;
517 win->size = size;
518
519 if (win->offset + win->size > aspi->ahb_window_size) {
520 win->size = aspi->ahb_window_size - win->offset;
521 dev_warn(aspi->dev, "CE%d window resized to %dMB", chip->cs, win->size >> 20);
522 }
523
524 ret = aspeed_spi_set_window(aspi, win);
525 if (ret)
526 return ret;
527
528 /* Update chip mapping info */
529 chip->ahb_base = aspi->ahb_base + win->offset;
530 chip->ahb_window_size = win->size;
531
532 /*
533 * Also adjust next chip window to make sure that it does not
534 * overlap with the current window.
535 */
536 if (chip->cs < aspi->data->max_cs - 1) {
537 struct aspeed_spi_window *next = &windows[chip->cs + 1];
538
539 /* Change offset and size to keep the same end address */
540 if ((next->offset + next->size) > (win->offset + win->size))
541 next->size = (next->offset + next->size) - (win->offset + win->size);
542 else
543 next->size = 0;
544 next->offset = win->offset + win->size;
545
546 aspeed_spi_set_window(aspi, next);
547 }
548 return 0;
549}
550
eeaec1ea
CLG		 551static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip);
552
9da06d7b
CLG		 553static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
554{
555 struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
556 struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select];
557 struct spi_mem_op *op = &desc->info.op_tmpl;
558 u32 ctl_val;
559 int ret = 0;
560
8988ba7d
CLG		 561 dev_dbg(aspi->dev,
562 "CE%d %s dirmap [ 0x%.8llx - 0x%.8llx ] OP %#x mode:%d.%d.%d.%d naddr:%#x ndummies:%#x\n",
563 chip->cs, op->data.dir == SPI_MEM_DATA_IN ? "read" : "write",
564 desc->info.offset, desc->info.offset + desc->info.length,
565 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
566 op->dummy.buswidth, op->data.buswidth,
567 op->addr.nbytes, op->dummy.nbytes);
568
9da06d7b
CLG		 569 chip->clk_freq = desc->mem->spi->max_speed_hz;
570
571 /* Only for reads */
572 if (op->data.dir != SPI_MEM_DATA_IN)
573 return -EOPNOTSUPP;
574
bb084f94
CLG		 575 aspeed_spi_chip_adjust_window(chip, desc->info.offset, desc->info.length);
576
9da06d7b
CLG		 577 if (desc->info.length > chip->ahb_window_size)
578 dev_warn(aspi->dev, "CE%d window (%dMB) too small for mapping",
579 chip->cs, chip->ahb_window_size >> 20);
580
581 /* Define the default IO read settings */
582 ctl_val = readl(chip->ctl) & ~CTRL_IO_CMD_MASK;
583 ctl_val |= aspeed_spi_get_io_mode(op) |
584 op->cmd.opcode << CTRL_COMMAND_SHIFT |
9da06d7b
CLG		 585 CTRL_IO_MODE_READ;
586
30554a1f
CLG		 587 if (op->dummy.nbytes)
588 ctl_val |= CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth);
589
9da06d7b
CLG		 590 /* Tune 4BYTE address mode */
591 if (op->addr.nbytes) {
592 u32 addr_mode = readl(aspi->regs + CE_CTRL_REG);
593
594 if (op->addr.nbytes == 4)
595 addr_mode |= (0x11 << chip->cs);
596 else
597 addr_mode &= ~(0x11 << chip->cs);
598 writel(addr_mode, aspi->regs + CE_CTRL_REG);
53526ab2
CLG		 599
600 /* AST2400 SPI controller sets 4BYTE address mode in
601 * CE0 Control Register
602 */
603 if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data)
604 ctl_val |= CTRL_IO_ADDRESS_4B;
9da06d7b
CLG		 605 }
606
607 /* READ mode is the controller default setting */
608 chip->ctl_val[ASPEED_SPI_READ] = ctl_val;
609 writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
610
eeaec1ea
CLG		 611 ret = aspeed_spi_do_calibration(chip);
612
9da06d7b
CLG		 613 dev_info(aspi->dev, "CE%d read buswidth:%d [0x%08x]\n",
614 chip->cs, op->data.buswidth, chip->ctl_val[ASPEED_SPI_READ]);
615
616 return ret;
617}
618
619static ssize_t aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc,
620 u64 offset, size_t len, void *buf)
621{
622 struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
623 struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select];
624
625 /* Switch to USER command mode if mapping window is too small */
626 if (chip->ahb_window_size < offset + len) {
627 int ret;
628
629 ret = aspeed_spi_read_user(chip, &desc->info.op_tmpl, offset, len, buf);
630 if (ret < 0)
631 return ret;
632 } else {
633 memcpy_fromio(buf, chip->ahb_base + offset, len);
634 }
635
636 return len;
637}
638
e3228ed9
CLG		 639static const struct spi_controller_mem_ops aspeed_spi_mem_ops = {
640 .supports_op = aspeed_spi_supports_op,
641 .exec_op = aspeed_spi_exec_op,
642 .get_name = aspeed_spi_get_name,
9da06d7b
CLG		 643 .dirmap_create = aspeed_spi_dirmap_create,
644 .dirmap_read = aspeed_spi_dirmap_read,
e3228ed9
CLG		 645};
646
647static void aspeed_spi_chip_set_type(struct aspeed_spi *aspi, unsigned int cs, int type)
648{
649 u32 reg;
650
651 reg = readl(aspi->regs + CONFIG_REG);
652 reg &= ~(0x3 << (cs * 2));
653 reg |= type << (cs * 2);
654 writel(reg, aspi->regs + CONFIG_REG);
655}
656
657static void aspeed_spi_chip_enable(struct aspeed_spi *aspi, unsigned int cs, bool enable)
658{
659 u32 we_bit = BIT(aspi->data->we0 + cs);
660 u32 reg = readl(aspi->regs + CONFIG_REG);
661
662 if (enable)
663 reg |= we_bit;
664 else
665 reg &= ~we_bit;
666 writel(reg, aspi->regs + CONFIG_REG);
667}
668
669static int aspeed_spi_setup(struct spi_device *spi)
670{
671 struct aspeed_spi *aspi = spi_controller_get_devdata(spi->master);
672 const struct aspeed_spi_data *data = aspi->data;
673 unsigned int cs = spi->chip_select;
674 struct aspeed_spi_chip *chip = &aspi->chips[cs];
675
676 chip->aspi = aspi;
677 chip->cs = cs;
678 chip->ctl = aspi->regs + data->ctl0 + cs * 4;
679
680 /* The driver only supports SPI type flash */
681 if (data->hastype)
682 aspeed_spi_chip_set_type(aspi, cs, CONFIG_TYPE_SPI);
683
684 if (aspeed_spi_chip_set_default_window(chip) < 0) {
685 dev_warn(aspi->dev, "CE%d window invalid", cs);
686 return -EINVAL;
687 }
688
689 aspeed_spi_chip_enable(aspi, cs, true);
690
691 chip->ctl_val[ASPEED_SPI_BASE] = CTRL_CE_STOP_ACTIVE | CTRL_IO_MODE_USER;
692
693 dev_dbg(aspi->dev, "CE%d setup done\n", cs);
694 return 0;
695}
696
697static void aspeed_spi_cleanup(struct spi_device *spi)
698{
699 struct aspeed_spi *aspi = spi_controller_get_devdata(spi->master);
700 unsigned int cs = spi->chip_select;
701
702 aspeed_spi_chip_enable(aspi, cs, false);
703
704 dev_dbg(aspi->dev, "CE%d cleanup done\n", cs);
705}
706
707static void aspeed_spi_enable(struct aspeed_spi *aspi, bool enable)
708{
709 int cs;
710
711 for (cs = 0; cs < aspi->data->max_cs; cs++)
712 aspeed_spi_chip_enable(aspi, cs, enable);
713}
714
715static int aspeed_spi_probe(struct platform_device *pdev)
716{
717 struct device *dev = &pdev->dev;
718 const struct aspeed_spi_data *data;
719 struct spi_controller *ctlr;
720 struct aspeed_spi *aspi;
721 struct resource *res;
722 int ret;
723
724 data = of_device_get_match_data(&pdev->dev);
725 if (!data)
726 return -ENODEV;
727
728 ctlr = devm_spi_alloc_master(dev, sizeof(*aspi));
729 if (!ctlr)
730 return -ENOMEM;
731
732 aspi = spi_controller_get_devdata(ctlr);
733 platform_set_drvdata(pdev, aspi);
734 aspi->data = data;
735 aspi->dev = dev;
736
6d0cebbd 737 aspi->regs = devm_platform_ioremap_resource(pdev, 0);
04e0456f 738 if (IS_ERR(aspi->regs))
e3228ed9 739 return PTR_ERR(aspi->regs);
e3228ed9 740
6d0cebbd 741 aspi->ahb_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
e3228ed9
CLG		 742 if (IS_ERR(aspi->ahb_base)) {
743 dev_err(dev, "missing AHB mapping window\n");
744 return PTR_ERR(aspi->ahb_base);
745 }
746
747 aspi->ahb_window_size = resource_size(res);
748 aspi->ahb_base_phy = res->start;
749
750 aspi->clk = devm_clk_get(&pdev->dev, NULL);
751 if (IS_ERR(aspi->clk)) {
752 dev_err(dev, "missing clock\n");
753 return PTR_ERR(aspi->clk);
754 }
755
756 aspi->clk_freq = clk_get_rate(aspi->clk);
757 if (!aspi->clk_freq) {
758 dev_err(dev, "invalid clock\n");
759 return -EINVAL;
760 }
761
762 ret = clk_prepare_enable(aspi->clk);
763 if (ret) {
764 dev_err(dev, "can not enable the clock\n");
765 return ret;
766 }
767
768 /* IRQ is for DMA, which the driver doesn't support yet */
769
770 ctlr->mode_bits = SPI_RX_DUAL | SPI_TX_DUAL | data->mode_bits;
771 ctlr->bus_num = pdev->id;
772 ctlr->mem_ops = &aspeed_spi_mem_ops;
773 ctlr->setup = aspeed_spi_setup;
774 ctlr->cleanup = aspeed_spi_cleanup;
775 ctlr->num_chipselect = data->max_cs;
776 ctlr->dev.of_node = dev->of_node;
777
778 ret = devm_spi_register_controller(dev, ctlr);
779 if (ret) {
780 dev_err(&pdev->dev, "spi_register_controller failed\n");
781 goto disable_clk;
782 }
783 return 0;
784
785disable_clk:
786 clk_disable_unprepare(aspi->clk);
787 return ret;
788}
789
ebf9a50d 790static void aspeed_spi_remove(struct platform_device *pdev)
e3228ed9
CLG		 791{
792 struct aspeed_spi *aspi = platform_get_drvdata(pdev);
793
794 aspeed_spi_enable(aspi, false);
795 clk_disable_unprepare(aspi->clk);
e3228ed9
CLG		 796}
797
798/*
799 * AHB mappings
800 */
801
802/*
803 * The Segment Registers of the AST2400 and AST2500 use a 8MB unit.
804 * The address range is encoded with absolute addresses in the overall
805 * mapping window.
806 */
807static u32 aspeed_spi_segment_start(struct aspeed_spi *aspi, u32 reg)
808{
809 return ((reg >> 16) & 0xFF) << 23;
810}
811
812static u32 aspeed_spi_segment_end(struct aspeed_spi *aspi, u32 reg)
813{
814 return ((reg >> 24) & 0xFF) << 23;
815}
816
817static u32 aspeed_spi_segment_reg(struct aspeed_spi *aspi, u32 start, u32 end)
818{
819 return (((start >> 23) & 0xFF) << 16) | (((end >> 23) & 0xFF) << 24);
820}
821
822/*
823 * The Segment Registers of the AST2600 use a 1MB unit. The address
824 * range is encoded with offsets in the overall mapping window.
825 */
826
827#define AST2600_SEG_ADDR_MASK 0x0ff00000
828
829static u32 aspeed_spi_segment_ast2600_start(struct aspeed_spi *aspi,
830 u32 reg)
831{
832 u32 start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK;
833
834 return aspi->ahb_base_phy + start_offset;
835}
836
837static u32 aspeed_spi_segment_ast2600_end(struct aspeed_spi *aspi,
838 u32 reg)
839{
840 u32 end_offset = reg & AST2600_SEG_ADDR_MASK;
841
842 /* segment is disabled */
843 if (!end_offset)
844 return aspi->ahb_base_phy;
845
846 return aspi->ahb_base_phy + end_offset + 0x100000;
847}
848
849static u32 aspeed_spi_segment_ast2600_reg(struct aspeed_spi *aspi,
850 u32 start, u32 end)
851{
852 /* disable zero size segments */
853 if (start == end)
854 return 0;
855
856 return ((start & AST2600_SEG_ADDR_MASK) >> 16) |
857 ((end - 1) & AST2600_SEG_ADDR_MASK);
858}
859
eeaec1ea
CLG		 860/*
861 * Read timing compensation sequences
862 */
863
864#define CALIBRATE_BUF_SIZE SZ_16K
865
866static bool aspeed_spi_check_reads(struct aspeed_spi_chip *chip,
867 const u8 *golden_buf, u8 *test_buf)
868{
869 int i;
870
871 for (i = 0; i < 10; i++) {
872 memcpy_fromio(test_buf, chip->ahb_base, CALIBRATE_BUF_SIZE);
873 if (memcmp(test_buf, golden_buf, CALIBRATE_BUF_SIZE) != 0) {
874#if defined(VERBOSE_DEBUG)
875 print_hex_dump_bytes(DEVICE_NAME " fail: ", DUMP_PREFIX_NONE,
876 test_buf, 0x100);
877#endif
878 return false;
879 }
880 }
881 return true;
882}
883
884#define FREAD_TPASS(i) (((i) / 2) | (((i) & 1) ? 0 : 8))
885
886/*
887 * The timing register is shared by all devices. Only update for CE0.
888 */
889static int aspeed_spi_calibrate(struct aspeed_spi_chip *chip, u32 hdiv,
890 const u8 *golden_buf, u8 *test_buf)
891{
892 struct aspeed_spi *aspi = chip->aspi;
893 const struct aspeed_spi_data *data = aspi->data;
894 int i;
895 int good_pass = -1, pass_count = 0;
896 u32 shift = (hdiv - 1) << 2;
897 u32 mask = ~(0xfu << shift);
898 u32 fread_timing_val = 0;
899
900 /* Try HCLK delay 0..5, each one with/without delay and look for a
901 * good pair.
902 */
903 for (i = 0; i < 12; i++) {
904 bool pass;
905
906 if (chip->cs == 0) {
907 fread_timing_val &= mask;
908 fread_timing_val |= FREAD_TPASS(i) << shift;
909 writel(fread_timing_val, aspi->regs + data->timing);
910 }
911 pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
912 dev_dbg(aspi->dev,
913 " * [%08x] %d HCLK delay, %dns DI delay : %s",
914 fread_timing_val, i / 2, (i & 1) ? 0 : 4,
915 pass ? "PASS" : "FAIL");
916 if (pass) {
917 pass_count++;
918 if (pass_count == 3) {
919 good_pass = i - 1;
920 break;
921 }
922 } else {
923 pass_count = 0;
924 }
925 }
926
927 /* No good setting for this frequency */
928 if (good_pass < 0)
929 return -1;
930
931 /* We have at least one pass of margin, let's use first pass */
932 if (chip->cs == 0) {
933 fread_timing_val &= mask;
934 fread_timing_val |= FREAD_TPASS(good_pass) << shift;
935 writel(fread_timing_val, aspi->regs + data->timing);
936 }
937 dev_dbg(aspi->dev, " * -> good is pass %d [0x%08x]",
938 good_pass, fread_timing_val);
939 return 0;
940}
941
942static bool aspeed_spi_check_calib_data(const u8 *test_buf, u32 size)
943{
944 const u32 *tb32 = (const u32 *)test_buf;
945 u32 i, cnt = 0;
946
947 /* We check if we have enough words that are neither all 0
948 * nor all 1's so the calibration can be considered valid.
949 *
950 * I use an arbitrary threshold for now of 64
951 */
952 size >>= 2;
953 for (i = 0; i < size; i++) {
954 if (tb32[i] != 0 && tb32[i] != 0xffffffff)
955 cnt++;
956 }
957 return cnt >= 64;
958}
959
960static const u32 aspeed_spi_hclk_divs[] = {
961 0xf, /* HCLK */
962 0x7, /* HCLK/2 */
963 0xe, /* HCLK/3 */
964 0x6, /* HCLK/4 */
965 0xd, /* HCLK/5 */
966};
967
968#define ASPEED_SPI_HCLK_DIV(i) \
969 (aspeed_spi_hclk_divs[(i) - 1] << CTRL_FREQ_SEL_SHIFT)
970
971static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip)
972{
973 struct aspeed_spi *aspi = chip->aspi;
974 const struct aspeed_spi_data *data = aspi->data;
975 u32 ahb_freq = aspi->clk_freq;
976 u32 max_freq = chip->clk_freq;
977 u32 ctl_val;
978 u8 *golden_buf = NULL;
979 u8 *test_buf = NULL;
980 int i, rc, best_div = -1;
981
982 dev_dbg(aspi->dev, "calculate timing compensation - AHB freq: %d MHz",
983 ahb_freq / 1000000);
984
985 /*
986 * use the related low frequency to get check calibration data
987 * and get golden data.
988 */
989 ctl_val = chip->ctl_val[ASPEED_SPI_READ] & data->hclk_mask;
990 writel(ctl_val, chip->ctl);
991
992 test_buf = kzalloc(CALIBRATE_BUF_SIZE * 2, GFP_KERNEL);
993 if (!test_buf)
994 return -ENOMEM;
995
996 golden_buf = test_buf + CALIBRATE_BUF_SIZE;
997
998 memcpy_fromio(golden_buf, chip->ahb_base, CALIBRATE_BUF_SIZE);
999 if (!aspeed_spi_check_calib_data(golden_buf, CALIBRATE_BUF_SIZE)) {
1000 dev_info(aspi->dev, "Calibration area too uniform, using low speed");
1001 goto no_calib;
1002 }
1003
1004#if defined(VERBOSE_DEBUG)
1005 print_hex_dump_bytes(DEVICE_NAME " good: ", DUMP_PREFIX_NONE,
1006 golden_buf, 0x100);
1007#endif
1008
1009 /* Now we iterate the HCLK dividers until we find our breaking point */
1010 for (i = ARRAY_SIZE(aspeed_spi_hclk_divs); i > data->hdiv_max - 1; i--) {
1011 u32 tv, freq;
1012
1013 freq = ahb_freq / i;
1014 if (freq > max_freq)
1015 continue;
1016
1017 /* Set the timing */
1018 tv = chip->ctl_val[ASPEED_SPI_READ] | ASPEED_SPI_HCLK_DIV(i);
1019 writel(tv, chip->ctl);
1020 dev_dbg(aspi->dev, "Trying HCLK/%d [%08x] ...", i, tv);
1021 rc = data->calibrate(chip, i, golden_buf, test_buf);
1022 if (rc == 0)
1023 best_div = i;
1024 }
1025
1026 /* Nothing found ? */
1027 if (best_div < 0) {
1028 dev_warn(aspi->dev, "No good frequency, using dumb slow");
1029 } else {
1030 dev_dbg(aspi->dev, "Found good read timings at HCLK/%d", best_div);
1031
1032 /* Record the freq */
1033 for (i = 0; i < ASPEED_SPI_MAX; i++)
1034 chip->ctl_val[i] = (chip->ctl_val[i] & data->hclk_mask) |
1035 ASPEED_SPI_HCLK_DIV(best_div);
1036 }
1037
1038no_calib:
1039 writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
1040 kfree(test_buf);
1041 return 0;
1042}
1043
1044#define TIMING_DELAY_DI BIT(3)
1045#define TIMING_DELAY_HCYCLE_MAX 5
1046#define TIMING_REG_AST2600(chip) \
1047 ((chip)->aspi->regs + (chip)->aspi->data->timing + \
1048 (chip)->cs * 4)
1049
1050static int aspeed_spi_ast2600_calibrate(struct aspeed_spi_chip *chip, u32 hdiv,
1051 const u8 *golden_buf, u8 *test_buf)
1052{
1053 struct aspeed_spi *aspi = chip->aspi;
1054 int hcycle;
1055 u32 shift = (hdiv - 2) << 3;
1056 u32 mask = ~(0xfu << shift);
1057 u32 fread_timing_val = 0;
1058
1059 for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) {
1060 int delay_ns;
1061 bool pass = false;
1062
1063 fread_timing_val &= mask;
1064 fread_timing_val |= hcycle << shift;
1065
1066 /* no DI input delay first */
1067 writel(fread_timing_val, TIMING_REG_AST2600(chip));
1068 pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
1069 dev_dbg(aspi->dev,
1070 " * [%08x] %d HCLK delay, DI delay none : %s",
1071 fread_timing_val, hcycle, pass ? "PASS" : "FAIL");
1072 if (pass)
1073 return 0;
1074
1075 /* Add DI input delays */
1076 fread_timing_val &= mask;
1077 fread_timing_val |= (TIMING_DELAY_DI | hcycle) << shift;
1078
1079 for (delay_ns = 0; delay_ns < 0x10; delay_ns++) {
1080 fread_timing_val &= ~(0xf << (4 + shift));
1081 fread_timing_val |= delay_ns << (4 + shift);
1082
1083 writel(fread_timing_val, TIMING_REG_AST2600(chip));
1084 pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
1085 dev_dbg(aspi->dev,
1086 " * [%08x] %d HCLK delay, DI delay %d.%dns : %s",
1087 fread_timing_val, hcycle, (delay_ns + 1) / 2,
1088 (delay_ns + 1) & 1 ? 5 : 5, pass ? "PASS" : "FAIL");
1089 /*
1090 * TODO: This is optimistic. We should look
1091 * for a working interval and save the middle
1092 * value in the read timing register.
1093 */
1094 if (pass)
1095 return 0;
1096 }
1097 }
1098
1099 /* No good setting for this frequency */
1100 return -1;
1101}
1102
e3228ed9
CLG		 1103/*
1104 * Platform definitions
1105 */
1106static const struct aspeed_spi_data ast2400_fmc_data = {
1107 .max_cs = 5,
1108 .hastype = true,
1109 .we0 = 16,
1110 .ctl0 = CE0_CTRL_REG,
eeaec1ea
CLG		 1111 .timing = CE0_TIMING_COMPENSATION_REG,
1112 .hclk_mask = 0xfffff0ff,
1113 .hdiv_max = 1,
1114 .calibrate = aspeed_spi_calibrate,
e3228ed9
CLG		 1115 .segment_start = aspeed_spi_segment_start,
1116 .segment_end = aspeed_spi_segment_end,
1117 .segment_reg = aspeed_spi_segment_reg,
1118};
1119
53526ab2
CLG		 1120static const struct aspeed_spi_data ast2400_spi_data = {
1121 .max_cs = 1,
1122 .hastype = false,
1123 .we0 = 0,
1124 .ctl0 = 0x04,
eeaec1ea
CLG		 1125 .timing = 0x14,
1126 .hclk_mask = 0xfffff0ff,
1127 .hdiv_max = 1,
1128 .calibrate = aspeed_spi_calibrate,
53526ab2
CLG		 1129 /* No segment registers */
1130};
1131
e3228ed9
CLG		 1132static const struct aspeed_spi_data ast2500_fmc_data = {
1133 .max_cs = 3,
1134 .hastype = true,
1135 .we0 = 16,
1136 .ctl0 = CE0_CTRL_REG,
eeaec1ea
CLG		 1137 .timing = CE0_TIMING_COMPENSATION_REG,
1138 .hclk_mask = 0xffffd0ff,
1139 .hdiv_max = 1,
1140 .calibrate = aspeed_spi_calibrate,
e3228ed9
CLG		 1141 .segment_start = aspeed_spi_segment_start,
1142 .segment_end = aspeed_spi_segment_end,
1143 .segment_reg = aspeed_spi_segment_reg,
1144};
1145
1146static const struct aspeed_spi_data ast2500_spi_data = {
1147 .max_cs = 2,
1148 .hastype = false,
1149 .we0 = 16,
1150 .ctl0 = CE0_CTRL_REG,
eeaec1ea
CLG		 1151 .timing = CE0_TIMING_COMPENSATION_REG,
1152 .hclk_mask = 0xffffd0ff,
1153 .hdiv_max = 1,
1154 .calibrate = aspeed_spi_calibrate,
e3228ed9
CLG		 1155 .segment_start = aspeed_spi_segment_start,
1156 .segment_end = aspeed_spi_segment_end,
1157 .segment_reg = aspeed_spi_segment_reg,
1158};
1159
1160static const struct aspeed_spi_data ast2600_fmc_data = {
1161 .max_cs = 3,
1162 .hastype = false,
5302e1ff 1163 .mode_bits = SPI_RX_QUAD | SPI_TX_QUAD,
e3228ed9
CLG		 1164 .we0 = 16,
1165 .ctl0 = CE0_CTRL_REG,
eeaec1ea
CLG		 1166 .timing = CE0_TIMING_COMPENSATION_REG,
1167 .hclk_mask = 0xf0fff0ff,
1168 .hdiv_max = 2,
1169 .calibrate = aspeed_spi_ast2600_calibrate,
e3228ed9
CLG		 1170 .segment_start = aspeed_spi_segment_ast2600_start,
1171 .segment_end = aspeed_spi_segment_ast2600_end,
1172 .segment_reg = aspeed_spi_segment_ast2600_reg,
1173};
1174
1175static const struct aspeed_spi_data ast2600_spi_data = {
1176 .max_cs = 2,
1177 .hastype = false,
5302e1ff 1178 .mode_bits = SPI_RX_QUAD | SPI_TX_QUAD,
e3228ed9
CLG		 1179 .we0 = 16,
1180 .ctl0 = CE0_CTRL_REG,
eeaec1ea
CLG		 1181 .timing = CE0_TIMING_COMPENSATION_REG,
1182 .hclk_mask = 0xf0fff0ff,
1183 .hdiv_max = 2,
1184 .calibrate = aspeed_spi_ast2600_calibrate,
e3228ed9
CLG		 1185 .segment_start = aspeed_spi_segment_ast2600_start,
1186 .segment_end = aspeed_spi_segment_ast2600_end,
1187 .segment_reg = aspeed_spi_segment_ast2600_reg,
1188};
1189
1190static const struct of_device_id aspeed_spi_matches[] = {
1191 { .compatible = "aspeed,ast2400-fmc", .data = &ast2400_fmc_data },
53526ab2 1192 { .compatible = "aspeed,ast2400-spi", .data = &ast2400_spi_data },
e3228ed9
CLG		 1193 { .compatible = "aspeed,ast2500-fmc", .data = &ast2500_fmc_data },
1194 { .compatible = "aspeed,ast2500-spi", .data = &ast2500_spi_data },
1195 { .compatible = "aspeed,ast2600-fmc", .data = &ast2600_fmc_data },
1196 { .compatible = "aspeed,ast2600-spi", .data = &ast2600_spi_data },
1197 { }
1198};
1199MODULE_DEVICE_TABLE(of, aspeed_spi_matches);
1200
1201static struct platform_driver aspeed_spi_driver = {
1202 .probe = aspeed_spi_probe,
ebf9a50d 1203 .remove_new = aspeed_spi_remove,
e3228ed9
CLG		 1204 .driver = {
1205 .name = DEVICE_NAME,
1206 .of_match_table = aspeed_spi_matches,
1207 }
1208};
1209
1210module_platform_driver(aspeed_spi_driver);
1211
1212MODULE_DESCRIPTION("ASPEED Static Memory Controller Driver");
1213MODULE_AUTHOR("Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>");
1214MODULE_AUTHOR("Cedric Le Goater <clg@kaod.org>");
1215MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)