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5762ab71 RP |
1 | /* |
2 | * Marvell Armada-3700 SPI controller driver | |
3 | * | |
4 | * Copyright (C) 2016 Marvell Ltd. | |
5 | * | |
6 | * Author: Wilson Ding <dingwei@marvell.com> | |
7 | * Author: Romain Perier <romain.perier@free-electrons.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/completion.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/of.h> | |
23 | #include <linux/of_irq.h> | |
24 | #include <linux/of_device.h> | |
25 | #include <linux/pinctrl/consumer.h> | |
26 | #include <linux/spi/spi.h> | |
27 | ||
28 | #define DRIVER_NAME "armada_3700_spi" | |
29 | ||
abf3a49e MC |
30 | #define A3700_SPI_MAX_SPEED_HZ 100000000 |
31 | #define A3700_SPI_MAX_PRESCALE 30 | |
5762ab71 RP |
32 | #define A3700_SPI_TIMEOUT 10 |
33 | ||
34 | /* SPI Register Offest */ | |
35 | #define A3700_SPI_IF_CTRL_REG 0x00 | |
36 | #define A3700_SPI_IF_CFG_REG 0x04 | |
37 | #define A3700_SPI_DATA_OUT_REG 0x08 | |
38 | #define A3700_SPI_DATA_IN_REG 0x0C | |
39 | #define A3700_SPI_IF_INST_REG 0x10 | |
40 | #define A3700_SPI_IF_ADDR_REG 0x14 | |
41 | #define A3700_SPI_IF_RMODE_REG 0x18 | |
42 | #define A3700_SPI_IF_HDR_CNT_REG 0x1C | |
43 | #define A3700_SPI_IF_DIN_CNT_REG 0x20 | |
44 | #define A3700_SPI_IF_TIME_REG 0x24 | |
45 | #define A3700_SPI_INT_STAT_REG 0x28 | |
46 | #define A3700_SPI_INT_MASK_REG 0x2C | |
47 | ||
48 | /* A3700_SPI_IF_CTRL_REG */ | |
49 | #define A3700_SPI_EN BIT(16) | |
50 | #define A3700_SPI_ADDR_NOT_CONFIG BIT(12) | |
51 | #define A3700_SPI_WFIFO_OVERFLOW BIT(11) | |
52 | #define A3700_SPI_WFIFO_UNDERFLOW BIT(10) | |
53 | #define A3700_SPI_RFIFO_OVERFLOW BIT(9) | |
54 | #define A3700_SPI_RFIFO_UNDERFLOW BIT(8) | |
55 | #define A3700_SPI_WFIFO_FULL BIT(7) | |
56 | #define A3700_SPI_WFIFO_EMPTY BIT(6) | |
57 | #define A3700_SPI_RFIFO_FULL BIT(5) | |
58 | #define A3700_SPI_RFIFO_EMPTY BIT(4) | |
59 | #define A3700_SPI_WFIFO_RDY BIT(3) | |
60 | #define A3700_SPI_RFIFO_RDY BIT(2) | |
61 | #define A3700_SPI_XFER_RDY BIT(1) | |
62 | #define A3700_SPI_XFER_DONE BIT(0) | |
63 | ||
64 | /* A3700_SPI_IF_CFG_REG */ | |
65 | #define A3700_SPI_WFIFO_THRS BIT(28) | |
66 | #define A3700_SPI_RFIFO_THRS BIT(24) | |
67 | #define A3700_SPI_AUTO_CS BIT(20) | |
68 | #define A3700_SPI_DMA_RD_EN BIT(18) | |
69 | #define A3700_SPI_FIFO_MODE BIT(17) | |
70 | #define A3700_SPI_SRST BIT(16) | |
71 | #define A3700_SPI_XFER_START BIT(15) | |
72 | #define A3700_SPI_XFER_STOP BIT(14) | |
73 | #define A3700_SPI_INST_PIN BIT(13) | |
74 | #define A3700_SPI_ADDR_PIN BIT(12) | |
75 | #define A3700_SPI_DATA_PIN1 BIT(11) | |
76 | #define A3700_SPI_DATA_PIN0 BIT(10) | |
77 | #define A3700_SPI_FIFO_FLUSH BIT(9) | |
78 | #define A3700_SPI_RW_EN BIT(8) | |
79 | #define A3700_SPI_CLK_POL BIT(7) | |
80 | #define A3700_SPI_CLK_PHA BIT(6) | |
81 | #define A3700_SPI_BYTE_LEN BIT(5) | |
82 | #define A3700_SPI_CLK_PRESCALE BIT(0) | |
83 | #define A3700_SPI_CLK_PRESCALE_MASK (0x1f) | |
84 | ||
85 | #define A3700_SPI_WFIFO_THRS_BIT 28 | |
86 | #define A3700_SPI_RFIFO_THRS_BIT 24 | |
87 | #define A3700_SPI_FIFO_THRS_MASK 0x7 | |
88 | ||
89 | #define A3700_SPI_DATA_PIN_MASK 0x3 | |
90 | ||
91 | /* A3700_SPI_IF_HDR_CNT_REG */ | |
92 | #define A3700_SPI_DUMMY_CNT_BIT 12 | |
93 | #define A3700_SPI_DUMMY_CNT_MASK 0x7 | |
94 | #define A3700_SPI_RMODE_CNT_BIT 8 | |
95 | #define A3700_SPI_RMODE_CNT_MASK 0x3 | |
96 | #define A3700_SPI_ADDR_CNT_BIT 4 | |
97 | #define A3700_SPI_ADDR_CNT_MASK 0x7 | |
98 | #define A3700_SPI_INSTR_CNT_BIT 0 | |
99 | #define A3700_SPI_INSTR_CNT_MASK 0x3 | |
100 | ||
101 | /* A3700_SPI_IF_TIME_REG */ | |
102 | #define A3700_SPI_CLK_CAPT_EDGE BIT(7) | |
103 | ||
5762ab71 RP |
104 | struct a3700_spi { |
105 | struct spi_master *master; | |
106 | void __iomem *base; | |
107 | struct clk *clk; | |
108 | unsigned int irq; | |
109 | unsigned int flags; | |
110 | bool xmit_data; | |
111 | const u8 *tx_buf; | |
112 | u8 *rx_buf; | |
113 | size_t buf_len; | |
114 | u8 byte_len; | |
115 | u32 wait_mask; | |
116 | struct completion done; | |
5762ab71 RP |
117 | }; |
118 | ||
119 | static u32 spireg_read(struct a3700_spi *a3700_spi, u32 offset) | |
120 | { | |
121 | return readl(a3700_spi->base + offset); | |
122 | } | |
123 | ||
124 | static void spireg_write(struct a3700_spi *a3700_spi, u32 offset, u32 data) | |
125 | { | |
126 | writel(data, a3700_spi->base + offset); | |
127 | } | |
128 | ||
129 | static void a3700_spi_auto_cs_unset(struct a3700_spi *a3700_spi) | |
130 | { | |
131 | u32 val; | |
132 | ||
133 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
134 | val &= ~A3700_SPI_AUTO_CS; | |
135 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
136 | } | |
137 | ||
138 | static void a3700_spi_activate_cs(struct a3700_spi *a3700_spi, unsigned int cs) | |
139 | { | |
140 | u32 val; | |
141 | ||
142 | val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); | |
143 | val |= (A3700_SPI_EN << cs); | |
144 | spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val); | |
145 | } | |
146 | ||
147 | static void a3700_spi_deactivate_cs(struct a3700_spi *a3700_spi, | |
148 | unsigned int cs) | |
149 | { | |
150 | u32 val; | |
151 | ||
152 | val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); | |
153 | val &= ~(A3700_SPI_EN << cs); | |
154 | spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val); | |
155 | } | |
156 | ||
157 | static int a3700_spi_pin_mode_set(struct a3700_spi *a3700_spi, | |
747e1f60 | 158 | unsigned int pin_mode, bool receiving) |
5762ab71 RP |
159 | { |
160 | u32 val; | |
161 | ||
162 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
163 | val &= ~(A3700_SPI_INST_PIN | A3700_SPI_ADDR_PIN); | |
164 | val &= ~(A3700_SPI_DATA_PIN0 | A3700_SPI_DATA_PIN1); | |
165 | ||
166 | switch (pin_mode) { | |
cfd6693c | 167 | case SPI_NBITS_SINGLE: |
5762ab71 | 168 | break; |
cfd6693c | 169 | case SPI_NBITS_DUAL: |
5762ab71 RP |
170 | val |= A3700_SPI_DATA_PIN0; |
171 | break; | |
cfd6693c | 172 | case SPI_NBITS_QUAD: |
5762ab71 | 173 | val |= A3700_SPI_DATA_PIN1; |
747e1f60 MR |
174 | /* RX during address reception uses 4-pin */ |
175 | if (receiving) | |
176 | val |= A3700_SPI_ADDR_PIN; | |
5762ab71 RP |
177 | break; |
178 | default: | |
179 | dev_err(&a3700_spi->master->dev, "wrong pin mode %u", pin_mode); | |
180 | return -EINVAL; | |
181 | } | |
182 | ||
183 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
184 | ||
185 | return 0; | |
186 | } | |
187 | ||
188 | static void a3700_spi_fifo_mode_set(struct a3700_spi *a3700_spi) | |
189 | { | |
190 | u32 val; | |
191 | ||
192 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
193 | val |= A3700_SPI_FIFO_MODE; | |
194 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
195 | } | |
196 | ||
197 | static void a3700_spi_mode_set(struct a3700_spi *a3700_spi, | |
198 | unsigned int mode_bits) | |
199 | { | |
200 | u32 val; | |
201 | ||
202 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
203 | ||
204 | if (mode_bits & SPI_CPOL) | |
205 | val |= A3700_SPI_CLK_POL; | |
206 | else | |
207 | val &= ~A3700_SPI_CLK_POL; | |
208 | ||
209 | if (mode_bits & SPI_CPHA) | |
210 | val |= A3700_SPI_CLK_PHA; | |
211 | else | |
212 | val &= ~A3700_SPI_CLK_PHA; | |
213 | ||
214 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
215 | } | |
216 | ||
217 | static void a3700_spi_clock_set(struct a3700_spi *a3700_spi, | |
dd7aa8d4 | 218 | unsigned int speed_hz) |
5762ab71 RP |
219 | { |
220 | u32 val; | |
221 | u32 prescale; | |
222 | ||
223 | prescale = DIV_ROUND_UP(clk_get_rate(a3700_spi->clk), speed_hz); | |
224 | ||
225 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
226 | val = val & ~A3700_SPI_CLK_PRESCALE_MASK; | |
227 | ||
228 | val = val | (prescale & A3700_SPI_CLK_PRESCALE_MASK); | |
229 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
230 | ||
231 | if (prescale <= 2) { | |
232 | val = spireg_read(a3700_spi, A3700_SPI_IF_TIME_REG); | |
233 | val |= A3700_SPI_CLK_CAPT_EDGE; | |
234 | spireg_write(a3700_spi, A3700_SPI_IF_TIME_REG, val); | |
235 | } | |
5762ab71 RP |
236 | } |
237 | ||
238 | static void a3700_spi_bytelen_set(struct a3700_spi *a3700_spi, unsigned int len) | |
239 | { | |
240 | u32 val; | |
241 | ||
242 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
243 | if (len == 4) | |
244 | val |= A3700_SPI_BYTE_LEN; | |
245 | else | |
246 | val &= ~A3700_SPI_BYTE_LEN; | |
247 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
248 | ||
249 | a3700_spi->byte_len = len; | |
250 | } | |
251 | ||
252 | static int a3700_spi_fifo_flush(struct a3700_spi *a3700_spi) | |
253 | { | |
254 | int timeout = A3700_SPI_TIMEOUT; | |
255 | u32 val; | |
256 | ||
257 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
258 | val |= A3700_SPI_FIFO_FLUSH; | |
259 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
260 | ||
261 | while (--timeout) { | |
262 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
263 | if (!(val & A3700_SPI_FIFO_FLUSH)) | |
264 | return 0; | |
265 | udelay(1); | |
266 | } | |
267 | ||
268 | return -ETIMEDOUT; | |
269 | } | |
270 | ||
271 | static int a3700_spi_init(struct a3700_spi *a3700_spi) | |
272 | { | |
273 | struct spi_master *master = a3700_spi->master; | |
274 | u32 val; | |
275 | int i, ret = 0; | |
276 | ||
277 | /* Reset SPI unit */ | |
278 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
279 | val |= A3700_SPI_SRST; | |
280 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
281 | ||
282 | udelay(A3700_SPI_TIMEOUT); | |
283 | ||
284 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
285 | val &= ~A3700_SPI_SRST; | |
286 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
287 | ||
288 | /* Disable AUTO_CS and deactivate all chip-selects */ | |
289 | a3700_spi_auto_cs_unset(a3700_spi); | |
290 | for (i = 0; i < master->num_chipselect; i++) | |
291 | a3700_spi_deactivate_cs(a3700_spi, i); | |
292 | ||
293 | /* Enable FIFO mode */ | |
294 | a3700_spi_fifo_mode_set(a3700_spi); | |
295 | ||
296 | /* Set SPI mode */ | |
297 | a3700_spi_mode_set(a3700_spi, master->mode_bits); | |
298 | ||
299 | /* Reset counters */ | |
300 | spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0); | |
301 | spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 0); | |
302 | ||
303 | /* Mask the interrupts and clear cause bits */ | |
304 | spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); | |
305 | spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, ~0U); | |
306 | ||
307 | return ret; | |
308 | } | |
309 | ||
310 | static irqreturn_t a3700_spi_interrupt(int irq, void *dev_id) | |
311 | { | |
312 | struct spi_master *master = dev_id; | |
313 | struct a3700_spi *a3700_spi; | |
314 | u32 cause; | |
315 | ||
316 | a3700_spi = spi_master_get_devdata(master); | |
317 | ||
318 | /* Get interrupt causes */ | |
319 | cause = spireg_read(a3700_spi, A3700_SPI_INT_STAT_REG); | |
320 | ||
321 | if (!cause || !(a3700_spi->wait_mask & cause)) | |
322 | return IRQ_NONE; | |
323 | ||
324 | /* mask and acknowledge the SPI interrupts */ | |
325 | spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); | |
326 | spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, cause); | |
327 | ||
328 | /* Wake up the transfer */ | |
0cc059ab | 329 | complete(&a3700_spi->done); |
5762ab71 RP |
330 | |
331 | return IRQ_HANDLED; | |
332 | } | |
333 | ||
334 | static bool a3700_spi_wait_completion(struct spi_device *spi) | |
335 | { | |
336 | struct a3700_spi *a3700_spi; | |
337 | unsigned int timeout; | |
338 | unsigned int ctrl_reg; | |
339 | unsigned long timeout_jiffies; | |
340 | ||
341 | a3700_spi = spi_master_get_devdata(spi->master); | |
342 | ||
343 | /* SPI interrupt is edge-triggered, which means an interrupt will | |
344 | * be generated only when detecting a specific status bit changed | |
345 | * from '0' to '1'. So when we start waiting for a interrupt, we | |
346 | * need to check status bit in control reg first, if it is already 1, | |
347 | * then we do not need to wait for interrupt | |
348 | */ | |
349 | ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); | |
350 | if (a3700_spi->wait_mask & ctrl_reg) | |
351 | return true; | |
352 | ||
353 | reinit_completion(&a3700_spi->done); | |
354 | ||
355 | spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, | |
356 | a3700_spi->wait_mask); | |
357 | ||
358 | timeout_jiffies = msecs_to_jiffies(A3700_SPI_TIMEOUT); | |
359 | timeout = wait_for_completion_timeout(&a3700_spi->done, | |
360 | timeout_jiffies); | |
361 | ||
362 | a3700_spi->wait_mask = 0; | |
363 | ||
364 | if (timeout) | |
365 | return true; | |
366 | ||
367 | /* there might be the case that right after we checked the | |
368 | * status bits in this routine and before start to wait for | |
369 | * interrupt by wait_for_completion_timeout, the interrupt | |
370 | * happens, to avoid missing it we need to double check | |
371 | * status bits in control reg, if it is already 1, then | |
372 | * consider that we have the interrupt successfully and | |
373 | * return true. | |
374 | */ | |
375 | ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); | |
376 | if (a3700_spi->wait_mask & ctrl_reg) | |
377 | return true; | |
378 | ||
379 | spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); | |
380 | ||
5a866ec0 MC |
381 | /* Timeout was reached */ |
382 | return false; | |
5762ab71 RP |
383 | } |
384 | ||
385 | static bool a3700_spi_transfer_wait(struct spi_device *spi, | |
386 | unsigned int bit_mask) | |
387 | { | |
388 | struct a3700_spi *a3700_spi; | |
389 | ||
390 | a3700_spi = spi_master_get_devdata(spi->master); | |
391 | a3700_spi->wait_mask = bit_mask; | |
392 | ||
393 | return a3700_spi_wait_completion(spi); | |
394 | } | |
395 | ||
396 | static void a3700_spi_fifo_thres_set(struct a3700_spi *a3700_spi, | |
397 | unsigned int bytes) | |
398 | { | |
399 | u32 val; | |
400 | ||
401 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
402 | val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_RFIFO_THRS_BIT); | |
403 | val |= (bytes - 1) << A3700_SPI_RFIFO_THRS_BIT; | |
404 | val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_WFIFO_THRS_BIT); | |
405 | val |= (7 - bytes) << A3700_SPI_WFIFO_THRS_BIT; | |
406 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
407 | } | |
408 | ||
409 | static void a3700_spi_transfer_setup(struct spi_device *spi, | |
85798e15 | 410 | struct spi_transfer *xfer) |
5762ab71 RP |
411 | { |
412 | struct a3700_spi *a3700_spi; | |
413 | unsigned int byte_len; | |
414 | ||
415 | a3700_spi = spi_master_get_devdata(spi->master); | |
416 | ||
dd7aa8d4 | 417 | a3700_spi_clock_set(a3700_spi, xfer->speed_hz); |
5762ab71 RP |
418 | |
419 | byte_len = xfer->bits_per_word >> 3; | |
420 | ||
421 | a3700_spi_fifo_thres_set(a3700_spi, byte_len); | |
422 | } | |
423 | ||
424 | static void a3700_spi_set_cs(struct spi_device *spi, bool enable) | |
425 | { | |
426 | struct a3700_spi *a3700_spi = spi_master_get_devdata(spi->master); | |
427 | ||
428 | if (!enable) | |
429 | a3700_spi_activate_cs(a3700_spi, spi->chip_select); | |
430 | else | |
431 | a3700_spi_deactivate_cs(a3700_spi, spi->chip_select); | |
432 | } | |
433 | ||
434 | static void a3700_spi_header_set(struct a3700_spi *a3700_spi) | |
435 | { | |
6fd6fd68 | 436 | unsigned int addr_cnt; |
5762ab71 RP |
437 | u32 val = 0; |
438 | ||
439 | /* Clear the header registers */ | |
440 | spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, 0); | |
441 | spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, 0); | |
442 | spireg_write(a3700_spi, A3700_SPI_IF_RMODE_REG, 0); | |
6fd6fd68 | 443 | spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0); |
5762ab71 RP |
444 | |
445 | /* Set header counters */ | |
446 | if (a3700_spi->tx_buf) { | |
6fd6fd68 ZZ |
447 | /* |
448 | * when tx data is not 4 bytes aligned, there will be unexpected | |
449 | * bytes out of SPI output register, since it always shifts out | |
450 | * as whole 4 bytes. This might cause incorrect transaction with | |
451 | * some devices. To avoid that, use SPI header count feature to | |
452 | * transfer up to 3 bytes of data first, and then make the rest | |
453 | * of data 4-byte aligned. | |
454 | */ | |
455 | addr_cnt = a3700_spi->buf_len % 4; | |
456 | if (addr_cnt) { | |
457 | val = (addr_cnt & A3700_SPI_ADDR_CNT_MASK) | |
458 | << A3700_SPI_ADDR_CNT_BIT; | |
459 | spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, val); | |
460 | ||
461 | /* Update the buffer length to be transferred */ | |
462 | a3700_spi->buf_len -= addr_cnt; | |
463 | ||
464 | /* transfer 1~3 bytes through address count */ | |
465 | val = 0; | |
466 | while (addr_cnt--) { | |
467 | val = (val << 8) | a3700_spi->tx_buf[0]; | |
468 | a3700_spi->tx_buf++; | |
469 | } | |
470 | spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, val); | |
5762ab71 | 471 | } |
5762ab71 | 472 | } |
5762ab71 RP |
473 | } |
474 | ||
475 | static int a3700_is_wfifo_full(struct a3700_spi *a3700_spi) | |
476 | { | |
477 | u32 val; | |
478 | ||
479 | val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); | |
480 | return (val & A3700_SPI_WFIFO_FULL); | |
481 | } | |
482 | ||
483 | static int a3700_spi_fifo_write(struct a3700_spi *a3700_spi) | |
484 | { | |
485 | u32 val; | |
5762ab71 RP |
486 | |
487 | while (!a3700_is_wfifo_full(a3700_spi) && a3700_spi->buf_len) { | |
6fd6fd68 ZZ |
488 | val = cpu_to_le32(*(u32 *)a3700_spi->tx_buf); |
489 | spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val); | |
490 | a3700_spi->buf_len -= 4; | |
491 | a3700_spi->tx_buf += 4; | |
5762ab71 RP |
492 | } |
493 | ||
494 | return 0; | |
495 | } | |
496 | ||
497 | static int a3700_is_rfifo_empty(struct a3700_spi *a3700_spi) | |
498 | { | |
499 | u32 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); | |
500 | ||
501 | return (val & A3700_SPI_RFIFO_EMPTY); | |
502 | } | |
503 | ||
504 | static int a3700_spi_fifo_read(struct a3700_spi *a3700_spi) | |
505 | { | |
506 | u32 val; | |
507 | ||
508 | while (!a3700_is_rfifo_empty(a3700_spi) && a3700_spi->buf_len) { | |
509 | val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG); | |
510 | if (a3700_spi->buf_len >= 4) { | |
511 | u32 data = le32_to_cpu(val); | |
85798e15 | 512 | |
5762ab71 RP |
513 | memcpy(a3700_spi->rx_buf, &data, 4); |
514 | ||
515 | a3700_spi->buf_len -= 4; | |
516 | a3700_spi->rx_buf += 4; | |
517 | } else { | |
518 | /* | |
519 | * When remain bytes is not larger than 4, we should | |
520 | * avoid memory overwriting and just write the left rx | |
521 | * buffer bytes. | |
522 | */ | |
523 | while (a3700_spi->buf_len) { | |
524 | *a3700_spi->rx_buf = val & 0xff; | |
525 | val >>= 8; | |
526 | ||
527 | a3700_spi->buf_len--; | |
528 | a3700_spi->rx_buf++; | |
529 | } | |
530 | } | |
531 | } | |
532 | ||
533 | return 0; | |
534 | } | |
535 | ||
536 | static void a3700_spi_transfer_abort_fifo(struct a3700_spi *a3700_spi) | |
537 | { | |
538 | int timeout = A3700_SPI_TIMEOUT; | |
539 | u32 val; | |
540 | ||
541 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
542 | val |= A3700_SPI_XFER_STOP; | |
543 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
544 | ||
545 | while (--timeout) { | |
546 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
547 | if (!(val & A3700_SPI_XFER_START)) | |
548 | break; | |
549 | udelay(1); | |
550 | } | |
551 | ||
552 | a3700_spi_fifo_flush(a3700_spi); | |
553 | ||
554 | val &= ~A3700_SPI_XFER_STOP; | |
555 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
556 | } | |
557 | ||
558 | static int a3700_spi_prepare_message(struct spi_master *master, | |
559 | struct spi_message *message) | |
560 | { | |
561 | struct a3700_spi *a3700_spi = spi_master_get_devdata(master); | |
562 | struct spi_device *spi = message->spi; | |
563 | int ret; | |
564 | ||
565 | ret = clk_enable(a3700_spi->clk); | |
566 | if (ret) { | |
567 | dev_err(&spi->dev, "failed to enable clk with error %d\n", ret); | |
568 | return ret; | |
569 | } | |
570 | ||
571 | /* Flush the FIFOs */ | |
572 | ret = a3700_spi_fifo_flush(a3700_spi); | |
573 | if (ret) | |
574 | return ret; | |
575 | ||
576 | a3700_spi_bytelen_set(a3700_spi, 4); | |
577 | ||
dd7aa8d4 MC |
578 | a3700_spi_mode_set(a3700_spi, spi->mode); |
579 | ||
5762ab71 RP |
580 | return 0; |
581 | } | |
582 | ||
583 | static int a3700_spi_transfer_one(struct spi_master *master, | |
584 | struct spi_device *spi, | |
585 | struct spi_transfer *xfer) | |
586 | { | |
587 | struct a3700_spi *a3700_spi = spi_master_get_devdata(master); | |
588 | int ret = 0, timeout = A3700_SPI_TIMEOUT; | |
589 | unsigned int nbits = 0; | |
590 | u32 val; | |
591 | ||
592 | a3700_spi_transfer_setup(spi, xfer); | |
593 | ||
594 | a3700_spi->tx_buf = xfer->tx_buf; | |
595 | a3700_spi->rx_buf = xfer->rx_buf; | |
596 | a3700_spi->buf_len = xfer->len; | |
597 | ||
5762ab71 RP |
598 | if (xfer->tx_buf) |
599 | nbits = xfer->tx_nbits; | |
600 | else if (xfer->rx_buf) | |
601 | nbits = xfer->rx_nbits; | |
602 | ||
747e1f60 | 603 | a3700_spi_pin_mode_set(a3700_spi, nbits, xfer->rx_buf ? true : false); |
5762ab71 | 604 | |
6fd6fd68 ZZ |
605 | /* Flush the FIFOs */ |
606 | a3700_spi_fifo_flush(a3700_spi); | |
607 | ||
608 | /* Transfer first bytes of data when buffer is not 4-byte aligned */ | |
609 | a3700_spi_header_set(a3700_spi); | |
610 | ||
5762ab71 | 611 | if (xfer->rx_buf) { |
44a5f423 MC |
612 | /* Clear WFIFO, since it's last 2 bytes are shifted out during |
613 | * a read operation | |
614 | */ | |
615 | spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, 0); | |
616 | ||
5762ab71 RP |
617 | /* Set read data length */ |
618 | spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, | |
619 | a3700_spi->buf_len); | |
620 | /* Start READ transfer */ | |
621 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
622 | val &= ~A3700_SPI_RW_EN; | |
623 | val |= A3700_SPI_XFER_START; | |
624 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
625 | } else if (xfer->tx_buf) { | |
626 | /* Start Write transfer */ | |
627 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
628 | val |= (A3700_SPI_XFER_START | A3700_SPI_RW_EN); | |
629 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
630 | ||
631 | /* | |
632 | * If there are data to be written to the SPI device, xmit_data | |
633 | * flag is set true; otherwise the instruction in SPI_INSTR does | |
634 | * not require data to be written to the SPI device, then | |
635 | * xmit_data flag is set false. | |
636 | */ | |
637 | a3700_spi->xmit_data = (a3700_spi->buf_len != 0); | |
638 | } | |
639 | ||
640 | while (a3700_spi->buf_len) { | |
641 | if (a3700_spi->tx_buf) { | |
642 | /* Wait wfifo ready */ | |
643 | if (!a3700_spi_transfer_wait(spi, | |
644 | A3700_SPI_WFIFO_RDY)) { | |
645 | dev_err(&spi->dev, | |
646 | "wait wfifo ready timed out\n"); | |
647 | ret = -ETIMEDOUT; | |
648 | goto error; | |
649 | } | |
650 | /* Fill up the wfifo */ | |
651 | ret = a3700_spi_fifo_write(a3700_spi); | |
652 | if (ret) | |
653 | goto error; | |
654 | } else if (a3700_spi->rx_buf) { | |
655 | /* Wait rfifo ready */ | |
656 | if (!a3700_spi_transfer_wait(spi, | |
657 | A3700_SPI_RFIFO_RDY)) { | |
658 | dev_err(&spi->dev, | |
659 | "wait rfifo ready timed out\n"); | |
660 | ret = -ETIMEDOUT; | |
661 | goto error; | |
662 | } | |
663 | /* Drain out the rfifo */ | |
664 | ret = a3700_spi_fifo_read(a3700_spi); | |
665 | if (ret) | |
666 | goto error; | |
667 | } | |
668 | } | |
669 | ||
670 | /* | |
671 | * Stop a write transfer in fifo mode: | |
672 | * - wait all the bytes in wfifo to be shifted out | |
673 | * - set XFER_STOP bit | |
674 | * - wait XFER_START bit clear | |
675 | * - clear XFER_STOP bit | |
676 | * Stop a read transfer in fifo mode: | |
677 | * - the hardware is to reset the XFER_START bit | |
678 | * after the number of bytes indicated in DIN_CNT | |
679 | * register | |
680 | * - just wait XFER_START bit clear | |
681 | */ | |
682 | if (a3700_spi->tx_buf) { | |
683 | if (a3700_spi->xmit_data) { | |
684 | /* | |
685 | * If there are data written to the SPI device, wait | |
686 | * until SPI_WFIFO_EMPTY is 1 to wait for all data to | |
687 | * transfer out of write FIFO. | |
688 | */ | |
689 | if (!a3700_spi_transfer_wait(spi, | |
690 | A3700_SPI_WFIFO_EMPTY)) { | |
691 | dev_err(&spi->dev, "wait wfifo empty timed out\n"); | |
692 | return -ETIMEDOUT; | |
693 | } | |
6fd6fd68 ZZ |
694 | } |
695 | ||
696 | if (!a3700_spi_transfer_wait(spi, A3700_SPI_XFER_RDY)) { | |
697 | dev_err(&spi->dev, "wait xfer ready timed out\n"); | |
698 | return -ETIMEDOUT; | |
5762ab71 RP |
699 | } |
700 | ||
701 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
702 | val |= A3700_SPI_XFER_STOP; | |
703 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
704 | } | |
705 | ||
706 | while (--timeout) { | |
707 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
708 | if (!(val & A3700_SPI_XFER_START)) | |
709 | break; | |
710 | udelay(1); | |
711 | } | |
712 | ||
713 | if (timeout == 0) { | |
714 | dev_err(&spi->dev, "wait transfer start clear timed out\n"); | |
715 | ret = -ETIMEDOUT; | |
716 | goto error; | |
717 | } | |
718 | ||
719 | val &= ~A3700_SPI_XFER_STOP; | |
720 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
721 | goto out; | |
722 | ||
723 | error: | |
724 | a3700_spi_transfer_abort_fifo(a3700_spi); | |
725 | out: | |
726 | spi_finalize_current_transfer(master); | |
727 | ||
728 | return ret; | |
729 | } | |
730 | ||
731 | static int a3700_spi_unprepare_message(struct spi_master *master, | |
732 | struct spi_message *message) | |
733 | { | |
734 | struct a3700_spi *a3700_spi = spi_master_get_devdata(master); | |
735 | ||
736 | clk_disable(a3700_spi->clk); | |
737 | ||
738 | return 0; | |
739 | } | |
740 | ||
741 | static const struct of_device_id a3700_spi_dt_ids[] = { | |
742 | { .compatible = "marvell,armada-3700-spi", .data = NULL }, | |
743 | {}, | |
744 | }; | |
745 | ||
746 | MODULE_DEVICE_TABLE(of, a3700_spi_dt_ids); | |
747 | ||
748 | static int a3700_spi_probe(struct platform_device *pdev) | |
749 | { | |
750 | struct device *dev = &pdev->dev; | |
751 | struct device_node *of_node = dev->of_node; | |
752 | struct resource *res; | |
753 | struct spi_master *master; | |
754 | struct a3700_spi *spi; | |
755 | u32 num_cs = 0; | |
f6f0083c | 756 | int irq, ret = 0; |
5762ab71 RP |
757 | |
758 | master = spi_alloc_master(dev, sizeof(*spi)); | |
759 | if (!master) { | |
760 | dev_err(dev, "master allocation failed\n"); | |
761 | ret = -ENOMEM; | |
762 | goto out; | |
763 | } | |
764 | ||
765 | if (of_property_read_u32(of_node, "num-cs", &num_cs)) { | |
766 | dev_err(dev, "could not find num-cs\n"); | |
767 | ret = -ENXIO; | |
768 | goto error; | |
769 | } | |
770 | ||
771 | master->bus_num = pdev->id; | |
772 | master->dev.of_node = of_node; | |
773 | master->mode_bits = SPI_MODE_3; | |
774 | master->num_chipselect = num_cs; | |
775 | master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(32); | |
776 | master->prepare_message = a3700_spi_prepare_message; | |
777 | master->transfer_one = a3700_spi_transfer_one; | |
778 | master->unprepare_message = a3700_spi_unprepare_message; | |
779 | master->set_cs = a3700_spi_set_cs; | |
780 | master->flags = SPI_MASTER_HALF_DUPLEX; | |
42cd4ed8 | 781 | master->mode_bits |= (SPI_RX_DUAL | SPI_TX_DUAL | |
5762ab71 RP |
782 | SPI_RX_QUAD | SPI_TX_QUAD); |
783 | ||
784 | platform_set_drvdata(pdev, master); | |
785 | ||
786 | spi = spi_master_get_devdata(master); | |
787 | memset(spi, 0, sizeof(struct a3700_spi)); | |
788 | ||
789 | spi->master = master; | |
5762ab71 RP |
790 | |
791 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
792 | spi->base = devm_ioremap_resource(dev, res); | |
793 | if (IS_ERR(spi->base)) { | |
794 | ret = PTR_ERR(spi->base); | |
795 | goto error; | |
796 | } | |
797 | ||
f6f0083c CIK |
798 | irq = platform_get_irq(pdev, 0); |
799 | if (irq < 0) { | |
800 | dev_err(dev, "could not get irq: %d\n", irq); | |
5762ab71 RP |
801 | ret = -ENXIO; |
802 | goto error; | |
803 | } | |
f6f0083c | 804 | spi->irq = irq; |
5762ab71 RP |
805 | |
806 | init_completion(&spi->done); | |
807 | ||
808 | spi->clk = devm_clk_get(dev, NULL); | |
809 | if (IS_ERR(spi->clk)) { | |
810 | dev_err(dev, "could not find clk: %ld\n", PTR_ERR(spi->clk)); | |
811 | goto error; | |
812 | } | |
813 | ||
814 | ret = clk_prepare(spi->clk); | |
815 | if (ret) { | |
816 | dev_err(dev, "could not prepare clk: %d\n", ret); | |
817 | goto error; | |
818 | } | |
819 | ||
abf3a49e MC |
820 | master->max_speed_hz = min_t(unsigned long, A3700_SPI_MAX_SPEED_HZ, |
821 | clk_get_rate(spi->clk)); | |
822 | master->min_speed_hz = DIV_ROUND_UP(clk_get_rate(spi->clk), | |
823 | A3700_SPI_MAX_PRESCALE); | |
824 | ||
5762ab71 RP |
825 | ret = a3700_spi_init(spi); |
826 | if (ret) | |
827 | goto error_clk; | |
828 | ||
829 | ret = devm_request_irq(dev, spi->irq, a3700_spi_interrupt, 0, | |
830 | dev_name(dev), master); | |
831 | if (ret) { | |
832 | dev_err(dev, "could not request IRQ: %d\n", ret); | |
833 | goto error_clk; | |
834 | } | |
835 | ||
836 | ret = devm_spi_register_master(dev, master); | |
837 | if (ret) { | |
838 | dev_err(dev, "Failed to register master\n"); | |
839 | goto error_clk; | |
840 | } | |
841 | ||
842 | return 0; | |
843 | ||
844 | error_clk: | |
845 | clk_disable_unprepare(spi->clk); | |
846 | error: | |
847 | spi_master_put(master); | |
848 | out: | |
849 | return ret; | |
850 | } | |
851 | ||
852 | static int a3700_spi_remove(struct platform_device *pdev) | |
853 | { | |
854 | struct spi_master *master = platform_get_drvdata(pdev); | |
855 | struct a3700_spi *spi = spi_master_get_devdata(master); | |
856 | ||
857 | clk_unprepare(spi->clk); | |
5762ab71 RP |
858 | |
859 | return 0; | |
860 | } | |
861 | ||
862 | static struct platform_driver a3700_spi_driver = { | |
863 | .driver = { | |
864 | .name = DRIVER_NAME, | |
5762ab71 RP |
865 | .of_match_table = of_match_ptr(a3700_spi_dt_ids), |
866 | }, | |
867 | .probe = a3700_spi_probe, | |
868 | .remove = a3700_spi_remove, | |
869 | }; | |
870 | ||
871 | module_platform_driver(a3700_spi_driver); | |
872 | ||
873 | MODULE_DESCRIPTION("Armada-3700 SPI driver"); | |
874 | MODULE_AUTHOR("Wilson Ding <dingwei@marvell.com>"); | |
875 | MODULE_LICENSE("GPL"); | |
876 | MODULE_ALIAS("platform:" DRIVER_NAME); |