[linux-block.git] / drivers / spi / spi-ar934x.c

// SPDX-License-Identifier: GPL-2.0
//
// SPI controller driver for Qualcomm Atheros AR934x/QCA95xx SoCs
//
// Copyright (C) 2020 Chuanhong Guo <gch981213@gmail.com>
//
// Based on spi-mt7621.c:
// Copyright (C) 2011 Sergiy <piratfm@gmail.com>
// Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
// Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>

#include <linux/clk.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/spi/spi.h>

#define DRIVER_NAME "spi-ar934x"

#define AR934X_SPI_REG_FS		0x00
#define AR934X_SPI_ENABLE		BIT(0)

#define AR934X_SPI_REG_IOC		0x08
#define AR934X_SPI_IOC_INITVAL		0x70000

#define AR934X_SPI_REG_CTRL		0x04
#define AR934X_SPI_CLK_MASK		GENMASK(5, 0)

#define AR934X_SPI_DATAOUT		0x10

#define AR934X_SPI_REG_SHIFT_CTRL	0x14
#define AR934X_SPI_SHIFT_EN		BIT(31)
#define AR934X_SPI_SHIFT_CS(n)		BIT(28 + (n))
#define AR934X_SPI_SHIFT_TERM		26
#define AR934X_SPI_SHIFT_VAL(cs, term, count)			\
	(AR934X_SPI_SHIFT_EN | AR934X_SPI_SHIFT_CS(cs) |	\
	(term) << AR934X_SPI_SHIFT_TERM | (count))

#define AR934X_SPI_DATAIN 0x18

struct ar934x_spi {
	struct spi_controller *ctlr;
	void __iomem *base;
	struct clk *clk;
	unsigned int clk_freq;
};

static inline int ar934x_spi_clk_div(struct ar934x_spi *sp, unsigned int freq)
{
	int div = DIV_ROUND_UP(sp->clk_freq, freq * 2) - 1;

	if (div < 0)
		return 0;
	else if (div > AR934X_SPI_CLK_MASK)
		return -EINVAL;
	else
		return div;
}

static int ar934x_spi_setup(struct spi_device *spi)
{
	struct ar934x_spi *sp = spi_controller_get_devdata(spi->master);

	if ((spi->max_speed_hz == 0) ||
	    (spi->max_speed_hz > (sp->clk_freq / 2))) {
		spi->max_speed_hz = sp->clk_freq / 2;
	} else if (spi->max_speed_hz < (sp->clk_freq / 128)) {
		dev_err(&spi->dev, "spi clock is too low\n");
		return -EINVAL;
	}

	return 0;
}

static int ar934x_spi_transfer_one_message(struct spi_controller *master,
					   struct spi_message *m)
{
	struct ar934x_spi *sp = spi_controller_get_devdata(master);
	struct spi_transfer *t = NULL;
	struct spi_device *spi = m->spi;
	unsigned long trx_done, trx_cur;
	int stat = 0;
	u8 bpw, term = 0;
	int div, i;
	u32 reg;
	const u8 *tx_buf;
	u8 *buf;

	m->actual_length = 0;
	list_for_each_entry(t, &m->transfers, transfer_list) {
		if (t->bits_per_word >= 8 && t->bits_per_word < 32)
			bpw = t->bits_per_word >> 3;
		else
			bpw = 4;

		if (t->speed_hz)
			div = ar934x_spi_clk_div(sp, t->speed_hz);
		else
			div = ar934x_spi_clk_div(sp, spi->max_speed_hz);
		if (div < 0) {
			stat = -EIO;
			goto msg_done;
		}

		reg = ioread32(sp->base + AR934X_SPI_REG_CTRL);
		reg &= ~AR934X_SPI_CLK_MASK;
		reg |= div;
		iowrite32(reg, sp->base + AR934X_SPI_REG_CTRL);
		iowrite32(0, sp->base + AR934X_SPI_DATAOUT);

		for (trx_done = 0; trx_done < t->len; trx_done += bpw) {
			trx_cur = t->len - trx_done;
			if (trx_cur > bpw)
				trx_cur = bpw;
			else if (list_is_last(&t->transfer_list, &m->transfers))
				term = 1;

			if (t->tx_buf) {
				tx_buf = t->tx_buf + trx_done;
				reg = tx_buf[0];
				for (i = 1; i < trx_cur; i++)
					reg = reg << 8 | tx_buf[i];
				iowrite32(reg, sp->base + AR934X_SPI_DATAOUT);
			}

			reg = AR934X_SPI_SHIFT_VAL(spi->chip_select, term,
						   trx_cur * 8);
			iowrite32(reg, sp->base + AR934X_SPI_REG_SHIFT_CTRL);
			stat = readl_poll_timeout(
				sp->base + AR934X_SPI_REG_SHIFT_CTRL, reg,
				!(reg & AR934X_SPI_SHIFT_EN), 0, 5);
			if (stat < 0)
				goto msg_done;

			if (t->rx_buf) {
				reg = ioread32(sp->base + AR934X_SPI_DATAIN);
				buf = t->rx_buf + trx_done;
				for (i = 0; i < trx_cur; i++) {
					buf[trx_cur - i - 1] = reg & 0xff;
					reg >>= 8;
				}
			}
			spi_delay_exec(&t->word_delay, t);
		}
		m->actual_length += t->len;
		spi_transfer_delay_exec(t);
	}

msg_done:
	m->status = stat;
	spi_finalize_current_message(master);

	return 0;
}

static const struct of_device_id ar934x_spi_match[] = {
	{ .compatible = "qca,ar934x-spi" },
	{},
};
MODULE_DEVICE_TABLE(of, ar934x_spi_match);

static int ar934x_spi_probe(struct platform_device *pdev)
{
	struct spi_controller *ctlr;
	struct ar934x_spi *sp;
	void __iomem *base;
	struct clk *clk;
	int ret;

	base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(base))
		return PTR_ERR(base);

	clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(clk)) {
		dev_err(&pdev->dev, "failed to get clock\n");
		return PTR_ERR(clk);
	}

	ret = clk_prepare_enable(clk);
	if (ret)
		return ret;

	ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*sp));
	if (!ctlr) {
		dev_info(&pdev->dev, "failed to allocate spi controller\n");
		ret = -ENOMEM;
		goto err_clk_disable;
	}

	/* disable flash mapping and expose spi controller registers */
	iowrite32(AR934X_SPI_ENABLE, base + AR934X_SPI_REG_FS);
	/* restore pins to default state: CSn=1 DO=CLK=0 */
	iowrite32(AR934X_SPI_IOC_INITVAL, base + AR934X_SPI_REG_IOC);

	ctlr->mode_bits = SPI_LSB_FIRST;
	ctlr->setup = ar934x_spi_setup;
	ctlr->transfer_one_message = ar934x_spi_transfer_one_message;
	ctlr->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(24) |
				   SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
	ctlr->dev.of_node = pdev->dev.of_node;
	ctlr->num_chipselect = 3;

	dev_set_drvdata(&pdev->dev, ctlr);

	sp = spi_controller_get_devdata(ctlr);
	sp->base = base;
	sp->clk = clk;
	sp->clk_freq = clk_get_rate(clk);
	sp->ctlr = ctlr;

	ret = spi_register_controller(ctlr);
	if (!ret)
		return 0;

err_clk_disable:
	clk_disable_unprepare(clk);
	return ret;
}

static int ar934x_spi_remove(struct platform_device *pdev)
{
	struct spi_controller *ctlr;
	struct ar934x_spi *sp;

	ctlr = dev_get_drvdata(&pdev->dev);
	sp = spi_controller_get_devdata(ctlr);

	spi_unregister_controller(ctlr);
	clk_disable_unprepare(sp->clk);

	return 0;
}

static struct platform_driver ar934x_spi_driver = {
	.driver = {
		.name = DRIVER_NAME,
		.of_match_table = ar934x_spi_match,
	},
	.probe = ar934x_spi_probe,
	.remove = ar934x_spi_remove,
};

module_platform_driver(ar934x_spi_driver);

MODULE_DESCRIPTION("SPI controller driver for Qualcomm Atheros AR934x/QCA95xx");
MODULE_AUTHOR("Chuanhong Guo <gch981213@gmail.com>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRIVER_NAME);
Commit	Line	Data
047980c5 CG	1	// SPDX-License-Identifier: GPL-2.0
	2	//
	3	// SPI controller driver for Qualcomm Atheros AR934x/QCA95xx SoCs
	4	//
	5	// Copyright (C) 2020 Chuanhong Guo <gch981213@gmail.com>
	6	//
	7	// Based on spi-mt7621.c:
	8	// Copyright (C) 2011 Sergiy <piratfm@gmail.com>
	9	// Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
	10	// Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
	11
	12	#include <linux/clk.h>
	13	#include <linux/io.h>
	14	#include <linux/iopoll.h>
	15	#include <linux/kernel.h>
	16	#include <linux/module.h>
	17	#include <linux/of_device.h>
	18	#include <linux/spi/spi.h>
	19
	20	#define DRIVER_NAME "spi-ar934x"
	21
	22	#define AR934X_SPI_REG_FS 0x00
	23	#define AR934X_SPI_ENABLE BIT(0)
	24
	25	#define AR934X_SPI_REG_IOC 0x08
	26	#define AR934X_SPI_IOC_INITVAL 0x70000
	27
	28	#define AR934X_SPI_REG_CTRL 0x04
	29	#define AR934X_SPI_CLK_MASK GENMASK(5, 0)
	30
	31	#define AR934X_SPI_DATAOUT 0x10
	32
	33	#define AR934X_SPI_REG_SHIFT_CTRL 0x14
	34	#define AR934X_SPI_SHIFT_EN BIT(31)
	35	#define AR934X_SPI_SHIFT_CS(n) BIT(28 + (n))
	36	#define AR934X_SPI_SHIFT_TERM 26
	37	#define AR934X_SPI_SHIFT_VAL(cs, term, count) \
	38	(AR934X_SPI_SHIFT_EN \| AR934X_SPI_SHIFT_CS(cs) \| \
	39	(term) << AR934X_SPI_SHIFT_TERM \| (count))
	40
	41	#define AR934X_SPI_DATAIN 0x18
	42
	43	struct ar934x_spi {
	44	struct spi_controller *ctlr;
	45	void __iomem *base;
	46	struct clk *clk;
	47	unsigned int clk_freq;
	48	};
	49
	50	static inline int ar934x_spi_clk_div(struct ar934x_spi *sp, unsigned int freq)
	51	{
	52	int div = DIV_ROUND_UP(sp->clk_freq, freq * 2) - 1;
	53
	54	if (div < 0)
	55	return 0;
	56	else if (div > AR934X_SPI_CLK_MASK)
	57	return -EINVAL;
	58	else
	59	return div;
	60	}
	61
	62	static int ar934x_spi_setup(struct spi_device *spi)
	63	{
	64	struct ar934x_spi *sp = spi_controller_get_devdata(spi->master);
65
66	if ((spi->max_speed_hz == 0) \|\|
67	(spi->max_speed_hz > (sp->clk_freq / 2))) {
68	spi->max_speed_hz = sp->clk_freq / 2;
69	} else if (spi->max_speed_hz < (sp->clk_freq / 128)) {
70	dev_err(&spi->dev, "spi clock is too low\n");
71	return -EINVAL;
72	}
73
74	return 0;
75	}
76
77	static int ar934x_spi_transfer_one_message(struct spi_controller *master,
78	struct spi_message *m)
79	{
80	struct ar934x_spi *sp = spi_controller_get_devdata(master);
81	struct spi_transfer *t = NULL;
82	struct spi_device *spi = m->spi;
83	unsigned long trx_done, trx_cur;
84	int stat = 0;
ebe33e5a	85	u8 bpw, term = 0;
047980c5 CG	86	int div, i;
	87	u32 reg;
	88	const u8 *tx_buf;
	89	u8 *buf;
	90
	91	m->actual_length = 0;
	92	list_for_each_entry(t, &m->transfers, transfer_list) {
ebe33e5a OL	93	if (t->bits_per_word >= 8 && t->bits_per_word < 32)
	94	bpw = t->bits_per_word >> 3;
	95	else
	96	bpw = 4;
	97
047980c5 CG	98	if (t->speed_hz)
	99	div = ar934x_spi_clk_div(sp, t->speed_hz);
	100	else
	101	div = ar934x_spi_clk_div(sp, spi->max_speed_hz);
	102	if (div < 0) {
	103	stat = -EIO;
	104	goto msg_done;
	105	}
	106
	107	reg = ioread32(sp->base + AR934X_SPI_REG_CTRL);
	108	reg &= ~AR934X_SPI_CLK_MASK;
	109	reg \|= div;
	110	iowrite32(reg, sp->base + AR934X_SPI_REG_CTRL);
	111	iowrite32(0, sp->base + AR934X_SPI_DATAOUT);
	112
ebe33e5a	113	for (trx_done = 0; trx_done < t->len; trx_done += bpw) {
047980c5	114	trx_cur = t->len - trx_done;
ebe33e5a OL	115	if (trx_cur > bpw)
ebe33e5a OL	116	trx_cur = bpw;
047980c5 CG	117	else if (list_is_last(&t->transfer_list, &m->transfers))
	118	term = 1;
	119
	120	if (t->tx_buf) {
	121	tx_buf = t->tx_buf + trx_done;
	122	reg = tx_buf[0];
	123	for (i = 1; i < trx_cur; i++)
	124	reg = reg << 8 \| tx_buf[i];
	125	iowrite32(reg, sp->base + AR934X_SPI_DATAOUT);
	126	}
	127
	128	reg = AR934X_SPI_SHIFT_VAL(spi->chip_select, term,
	129	trx_cur * 8);
	130	iowrite32(reg, sp->base + AR934X_SPI_REG_SHIFT_CTRL);
	131	stat = readl_poll_timeout(
	132	sp->base + AR934X_SPI_REG_SHIFT_CTRL, reg,
	133	!(reg & AR934X_SPI_SHIFT_EN), 0, 5);
	134	if (stat < 0)
	135	goto msg_done;
	136
	137	if (t->rx_buf) {
	138	reg = ioread32(sp->base + AR934X_SPI_DATAIN);
	139	buf = t->rx_buf + trx_done;
	140	for (i = 0; i < trx_cur; i++) {
	141	buf[trx_cur - i - 1] = reg & 0xff;
	142	reg >>= 8;
	143	}
	144	}
c7028245	145	spi_delay_exec(&t->word_delay, t);
047980c5 CG	146	}
047980c5 CG	147	m->actual_length += t->len;
c7028245	148	spi_transfer_delay_exec(t);
047980c5 CG	149	}
	150
	151	msg_done:
	152	m->status = stat;
	153	spi_finalize_current_message(master);
	154
	155	return 0;
	156	}
	157
	158	static const struct of_device_id ar934x_spi_match[] = {
	159	{ .compatible = "qca,ar934x-spi" },
	160	{},
	161	};
	162	MODULE_DEVICE_TABLE(of, ar934x_spi_match);
	163
	164	static int ar934x_spi_probe(struct platform_device *pdev)
	165	{
	166	struct spi_controller *ctlr;
	167	struct ar934x_spi *sp;
	168	void __iomem *base;
	169	struct clk *clk;
	170	int ret;
	171
	172	base = devm_platform_ioremap_resource(pdev, 0);
	173	if (IS_ERR(base))
	174	return PTR_ERR(base);
	175
	176	clk = devm_clk_get(&pdev->dev, NULL);
	177	if (IS_ERR(clk)) {
	178	dev_err(&pdev->dev, "failed to get clock\n");
	179	return PTR_ERR(clk);
	180	}
	181
	182	ret = clk_prepare_enable(clk);
	183	if (ret)
	184	return ret;
	185
236924ee	186	ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*sp));
047980c5 CG	187	if (!ctlr) {
047980c5 CG	188	dev_info(&pdev->dev, "failed to allocate spi controller\n");
236924ee LW	189	ret = -ENOMEM;
236924ee LW	190	goto err_clk_disable;
047980c5 CG	191	}
	192
	193	/* disable flash mapping and expose spi controller registers */
	194	iowrite32(AR934X_SPI_ENABLE, base + AR934X_SPI_REG_FS);
	195	/* restore pins to default state: CSn=1 DO=CLK=0 */
	196	iowrite32(AR934X_SPI_IOC_INITVAL, base + AR934X_SPI_REG_IOC);
	197
	198	ctlr->mode_bits = SPI_LSB_FIRST;
	199	ctlr->setup = ar934x_spi_setup;
	200	ctlr->transfer_one_message = ar934x_spi_transfer_one_message;
ebe33e5a OL	201	ctlr->bits_per_word_mask = SPI_BPW_MASK(32) \| SPI_BPW_MASK(24) \|
ebe33e5a OL	202	SPI_BPW_MASK(16) \| SPI_BPW_MASK(8);
047980c5 CG	203	ctlr->dev.of_node = pdev->dev.of_node;
	204	ctlr->num_chipselect = 3;
	205
	206	dev_set_drvdata(&pdev->dev, ctlr);
	207
	208	sp = spi_controller_get_devdata(ctlr);
	209	sp->base = base;
	210	sp->clk = clk;
	211	sp->clk_freq = clk_get_rate(clk);
	212	sp->ctlr = ctlr;
	213
236924ee LW	214	ret = spi_register_controller(ctlr);
	215	if (!ret)
	216	return 0;
	217
	218	err_clk_disable:
	219	clk_disable_unprepare(clk);
	220	return ret;
047980c5 CG	221	}
	222
	223	static int ar934x_spi_remove(struct platform_device *pdev)
	224	{
	225	struct spi_controller *ctlr;
	226	struct ar934x_spi *sp;
	227
	228	ctlr = dev_get_drvdata(&pdev->dev);
	229	sp = spi_controller_get_devdata(ctlr);
	230
236924ee	231	spi_unregister_controller(ctlr);
047980c5 CG	232	clk_disable_unprepare(sp->clk);
	233
	234	return 0;
	235	}
	236
	237	static struct platform_driver ar934x_spi_driver = {
	238	.driver = {
	239	.name = DRIVER_NAME,
	240	.of_match_table = ar934x_spi_match,
	241	},
	242	.probe = ar934x_spi_probe,
	243	.remove = ar934x_spi_remove,
	244	};
	245
	246	module_platform_driver(ar934x_spi_driver);
	247
	248	MODULE_DESCRIPTION("SPI controller driver for Qualcomm Atheros AR934x/QCA95xx");
	249	MODULE_AUTHOR("Chuanhong Guo <gch981213@gmail.com>");
	250	MODULE_LICENSE("GPL v2");
	251	MODULE_ALIAS("platform:" DRIVER_NAME);