[linux-block.git] / drivers / spi / spi-amd.c

// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
//
// AMD SPI controller driver
//
// Copyright (c) 2020, Advanced Micro Devices, Inc.
//
// Author: Sanjay R Mehta <sanju.mehta@amd.com>

#include <linux/acpi.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/spi/spi.h>
#include <linux/iopoll.h>

#define AMD_SPI_CTRL0_REG	0x00
#define AMD_SPI_EXEC_CMD	BIT(16)
#define AMD_SPI_FIFO_CLEAR	BIT(20)
#define AMD_SPI_BUSY		BIT(31)

#define AMD_SPI_OPCODE_REG	0x45
#define AMD_SPI_CMD_TRIGGER_REG	0x47
#define AMD_SPI_TRIGGER_CMD	BIT(7)

#define AMD_SPI_OPCODE_MASK	0xFF

#define AMD_SPI_ALT_CS_REG	0x1D
#define AMD_SPI_ALT_CS_MASK	0x3

#define AMD_SPI_FIFO_BASE	0x80
#define AMD_SPI_TX_COUNT_REG	0x48
#define AMD_SPI_RX_COUNT_REG	0x4B
#define AMD_SPI_STATUS_REG	0x4C

#define AMD_SPI_FIFO_SIZE	70
#define AMD_SPI_MEM_SIZE	200

#define AMD_SPI_ENA_REG		0x20
#define AMD_SPI_ALT_SPD_SHIFT	20
#define AMD_SPI_ALT_SPD_MASK	GENMASK(23, AMD_SPI_ALT_SPD_SHIFT)
#define AMD_SPI_SPI100_SHIFT	0
#define AMD_SPI_SPI100_MASK	GENMASK(AMD_SPI_SPI100_SHIFT, AMD_SPI_SPI100_SHIFT)
#define AMD_SPI_SPEED_REG	0x6C
#define AMD_SPI_SPD7_SHIFT	8
#define AMD_SPI_SPD7_MASK	GENMASK(13, AMD_SPI_SPD7_SHIFT)

#define AMD_SPI_MAX_HZ		100000000
#define AMD_SPI_MIN_HZ		800000

/**
 * enum amd_spi_versions - SPI controller versions
 * @AMD_SPI_V1:		AMDI0061 hardware version
 * @AMD_SPI_V2:		AMDI0062 hardware version
 */
enum amd_spi_versions {
	AMD_SPI_V1 = 1,
	AMD_SPI_V2,
};

enum amd_spi_speed {
	F_66_66MHz,
	F_33_33MHz,
	F_22_22MHz,
	F_16_66MHz,
	F_100MHz,
	F_800KHz,
	SPI_SPD7 = 0x7,
	F_50MHz = 0x4,
	F_4MHz = 0x32,
	F_3_17MHz = 0x3F
};

/**
 * struct amd_spi_freq - Matches device speed with values to write in regs
 * @speed_hz: Device frequency
 * @enable_val: Value to be written to "enable register"
 * @spd7_val: Some frequencies requires to have a value written at SPISPEED register
 */
struct amd_spi_freq {
	u32 speed_hz;
	u32 enable_val;
	u32 spd7_val;
};

/**
 * struct amd_spi - SPI driver instance
 * @io_remap_addr:	Start address of the SPI controller registers
 * @version:		SPI controller hardware version
 * @speed_hz:		Device frequency
 */
struct amd_spi {
	void __iomem *io_remap_addr;
	enum amd_spi_versions version;
	unsigned int speed_hz;
};

static inline u8 amd_spi_readreg8(struct amd_spi *amd_spi, int idx)
{
	return ioread8((u8 __iomem *)amd_spi->io_remap_addr + idx);
}

static inline void amd_spi_writereg8(struct amd_spi *amd_spi, int idx, u8 val)
{
	iowrite8(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
}

static void amd_spi_setclear_reg8(struct amd_spi *amd_spi, int idx, u8 set, u8 clear)
{
	u8 tmp = amd_spi_readreg8(amd_spi, idx);

	tmp = (tmp & ~clear) | set;
	amd_spi_writereg8(amd_spi, idx, tmp);
}

static inline u32 amd_spi_readreg32(struct amd_spi *amd_spi, int idx)
{
	return ioread32((u8 __iomem *)amd_spi->io_remap_addr + idx);
}

static inline void amd_spi_writereg32(struct amd_spi *amd_spi, int idx, u32 val)
{
	iowrite32(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
}

static inline void amd_spi_setclear_reg32(struct amd_spi *amd_spi, int idx, u32 set, u32 clear)
{
	u32 tmp = amd_spi_readreg32(amd_spi, idx);

	tmp = (tmp & ~clear) | set;
	amd_spi_writereg32(amd_spi, idx, tmp);
}

static void amd_spi_select_chip(struct amd_spi *amd_spi, u8 cs)
{
	amd_spi_setclear_reg8(amd_spi, AMD_SPI_ALT_CS_REG, cs, AMD_SPI_ALT_CS_MASK);
}

static inline void amd_spi_clear_chip(struct amd_spi *amd_spi, u8 chip_select)
{
	amd_spi_writereg8(amd_spi, AMD_SPI_ALT_CS_REG, chip_select & ~AMD_SPI_ALT_CS_MASK);
}

static void amd_spi_clear_fifo_ptr(struct amd_spi *amd_spi)
{
	amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_FIFO_CLEAR, AMD_SPI_FIFO_CLEAR);
}

static int amd_spi_set_opcode(struct amd_spi *amd_spi, u8 cmd_opcode)
{
	switch (amd_spi->version) {
	case AMD_SPI_V1:
		amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, cmd_opcode,
				       AMD_SPI_OPCODE_MASK);
		return 0;
	case AMD_SPI_V2:
		amd_spi_writereg8(amd_spi, AMD_SPI_OPCODE_REG, cmd_opcode);
		return 0;
	default:
		return -ENODEV;
	}
}

static inline void amd_spi_set_rx_count(struct amd_spi *amd_spi, u8 rx_count)
{
	amd_spi_setclear_reg8(amd_spi, AMD_SPI_RX_COUNT_REG, rx_count, 0xff);
}

static inline void amd_spi_set_tx_count(struct amd_spi *amd_spi, u8 tx_count)
{
	amd_spi_setclear_reg8(amd_spi, AMD_SPI_TX_COUNT_REG, tx_count, 0xff);
}

static int amd_spi_busy_wait(struct amd_spi *amd_spi)
{
	u32 val;
	int reg;

	switch (amd_spi->version) {
	case AMD_SPI_V1:
		reg = AMD_SPI_CTRL0_REG;
		break;
	case AMD_SPI_V2:
		reg = AMD_SPI_STATUS_REG;
		break;
	default:
		return -ENODEV;
	}

	return readl_poll_timeout(amd_spi->io_remap_addr + reg, val,
				  !(val & AMD_SPI_BUSY), 20, 2000000);
}

static int amd_spi_execute_opcode(struct amd_spi *amd_spi)
{
	int ret;

	ret = amd_spi_busy_wait(amd_spi);
	if (ret)
		return ret;

	switch (amd_spi->version) {
	case AMD_SPI_V1:
		/* Set ExecuteOpCode bit in the CTRL0 register */
		amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD,
				       AMD_SPI_EXEC_CMD);
		return 0;
	case AMD_SPI_V2:
		/* Trigger the command execution */
		amd_spi_setclear_reg8(amd_spi, AMD_SPI_CMD_TRIGGER_REG,
				      AMD_SPI_TRIGGER_CMD, AMD_SPI_TRIGGER_CMD);
		return 0;
	default:
		return -ENODEV;
	}
}

static int amd_spi_master_setup(struct spi_device *spi)
{
	struct amd_spi *amd_spi = spi_master_get_devdata(spi->master);

	amd_spi_clear_fifo_ptr(amd_spi);

	return 0;
}

static const struct amd_spi_freq amd_spi_freq[] = {
	{ AMD_SPI_MAX_HZ,   F_100MHz,         0},
	{       66660000, F_66_66MHz,         0},
	{       50000000,   SPI_SPD7,   F_50MHz},
	{       33330000, F_33_33MHz,         0},
	{       22220000, F_22_22MHz,         0},
	{       16660000, F_16_66MHz,         0},
	{        4000000,   SPI_SPD7,    F_4MHz},
	{        3170000,   SPI_SPD7, F_3_17MHz},
	{ AMD_SPI_MIN_HZ,   F_800KHz,         0},
};

static int amd_set_spi_freq(struct amd_spi *amd_spi, u32 speed_hz)
{
	unsigned int i, spd7_val, alt_spd;

	if (speed_hz < AMD_SPI_MIN_HZ)
		return -EINVAL;

	for (i = 0; i < ARRAY_SIZE(amd_spi_freq); i++)
		if (speed_hz >= amd_spi_freq[i].speed_hz)
			break;

	if (amd_spi->speed_hz == amd_spi_freq[i].speed_hz)
		return 0;

	amd_spi->speed_hz = amd_spi_freq[i].speed_hz;

	alt_spd = (amd_spi_freq[i].enable_val << AMD_SPI_ALT_SPD_SHIFT)
		   & AMD_SPI_ALT_SPD_MASK;
	amd_spi_setclear_reg32(amd_spi, AMD_SPI_ENA_REG, alt_spd,
			       AMD_SPI_ALT_SPD_MASK);

	if (amd_spi->speed_hz == AMD_SPI_MAX_HZ)
		amd_spi_setclear_reg32(amd_spi, AMD_SPI_ENA_REG, 1,
				       AMD_SPI_SPI100_MASK);

	if (amd_spi_freq[i].spd7_val) {
		spd7_val = (amd_spi_freq[i].spd7_val << AMD_SPI_SPD7_SHIFT)
			    & AMD_SPI_SPD7_MASK;
		amd_spi_setclear_reg32(amd_spi, AMD_SPI_SPEED_REG, spd7_val,
				       AMD_SPI_SPD7_MASK);
	}

	return 0;
}

static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi,
				    struct spi_master *master,
				    struct spi_message *message)
{
	struct spi_transfer *xfer = NULL;
	struct spi_device *spi = message->spi;
	u8 cmd_opcode = 0, fifo_pos = AMD_SPI_FIFO_BASE;
	u8 *buf = NULL;
	u32 i = 0;
	u32 tx_len = 0, rx_len = 0;

	list_for_each_entry(xfer, &message->transfers,
			    transfer_list) {
		if (xfer->speed_hz)
			amd_set_spi_freq(amd_spi, xfer->speed_hz);
		else
			amd_set_spi_freq(amd_spi, spi->max_speed_hz);

		if (xfer->tx_buf) {
			buf = (u8 *)xfer->tx_buf;
			if (!tx_len) {
				cmd_opcode = *(u8 *)xfer->tx_buf;
				buf++;
				xfer->len--;
			}
			tx_len += xfer->len;

			/* Write data into the FIFO. */
			for (i = 0; i < xfer->len; i++)
				amd_spi_writereg8(amd_spi, fifo_pos + i, buf[i]);

			fifo_pos += xfer->len;
		}

		/* Store no. of bytes to be received from FIFO */
		if (xfer->rx_buf)
			rx_len += xfer->len;
	}

	if (!buf) {
		message->status = -EINVAL;
		goto fin_msg;
	}

	amd_spi_set_opcode(amd_spi, cmd_opcode);
	amd_spi_set_tx_count(amd_spi, tx_len);
	amd_spi_set_rx_count(amd_spi, rx_len);

	/* Execute command */
	message->status = amd_spi_execute_opcode(amd_spi);
	if (message->status)
		goto fin_msg;

	if (rx_len) {
		message->status = amd_spi_busy_wait(amd_spi);
		if (message->status)
			goto fin_msg;

		list_for_each_entry(xfer, &message->transfers, transfer_list)
			if (xfer->rx_buf) {
				buf = (u8 *)xfer->rx_buf;
				/* Read data from FIFO to receive buffer */
				for (i = 0; i < xfer->len; i++)
					buf[i] = amd_spi_readreg8(amd_spi, fifo_pos + i);
				fifo_pos += xfer->len;
			}
	}

	/* Update statistics */
	message->actual_length = tx_len + rx_len + 1;

fin_msg:
	switch (amd_spi->version) {
	case AMD_SPI_V1:
		break;
	case AMD_SPI_V2:
		amd_spi_clear_chip(amd_spi, spi_get_chipselect(message->spi, 0));
		break;
	default:
		return -ENODEV;
	}

	spi_finalize_current_message(master);

	return message->status;
}

static int amd_spi_master_transfer(struct spi_master *master,
				   struct spi_message *msg)
{
	struct amd_spi *amd_spi = spi_master_get_devdata(master);
	struct spi_device *spi = msg->spi;

	amd_spi_select_chip(amd_spi, spi_get_chipselect(spi, 0));

	/*
	 * Extract spi_transfers from the spi message and
	 * program the controller.
	 */
	return amd_spi_fifo_xfer(amd_spi, master, msg);
}

static size_t amd_spi_max_transfer_size(struct spi_device *spi)
{
	return AMD_SPI_FIFO_SIZE;
}

static int amd_spi_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct spi_master *master;
	struct amd_spi *amd_spi;
	int err;

	/* Allocate storage for spi_master and driver private data */
	master = devm_spi_alloc_master(dev, sizeof(struct amd_spi));
	if (!master)
		return dev_err_probe(dev, -ENOMEM, "Error allocating SPI master\n");

	amd_spi = spi_master_get_devdata(master);
	amd_spi->io_remap_addr = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(amd_spi->io_remap_addr))
		return dev_err_probe(dev, PTR_ERR(amd_spi->io_remap_addr),
				     "ioremap of SPI registers failed\n");

	dev_dbg(dev, "io_remap_address: %p\n", amd_spi->io_remap_addr);

	amd_spi->version = (enum amd_spi_versions) device_get_match_data(dev);

	/* Initialize the spi_master fields */
	master->bus_num = 0;
	master->num_chipselect = 4;
	master->mode_bits = 0;
	master->flags = SPI_MASTER_HALF_DUPLEX;
	master->max_speed_hz = AMD_SPI_MAX_HZ;
	master->min_speed_hz = AMD_SPI_MIN_HZ;
	master->setup = amd_spi_master_setup;
	master->transfer_one_message = amd_spi_master_transfer;
	master->max_transfer_size = amd_spi_max_transfer_size;
	master->max_message_size = amd_spi_max_transfer_size;

	/* Register the controller with SPI framework */
	err = devm_spi_register_master(dev, master);
	if (err)
		return dev_err_probe(dev, err, "error registering SPI controller\n");

	return 0;
}

#ifdef CONFIG_ACPI
static const struct acpi_device_id spi_acpi_match[] = {
	{ "AMDI0061", AMD_SPI_V1 },
	{ "AMDI0062", AMD_SPI_V2 },
	{},
};
MODULE_DEVICE_TABLE(acpi, spi_acpi_match);
#endif

static struct platform_driver amd_spi_driver = {
	.driver = {
		.name = "amd_spi",
		.acpi_match_table = ACPI_PTR(spi_acpi_match),
	},
	.probe = amd_spi_probe,
};

module_platform_driver(amd_spi_driver);

MODULE_LICENSE("Dual BSD/GPL");
MODULE_AUTHOR("Sanjay Mehta <sanju.mehta@amd.com>");
MODULE_DESCRIPTION("AMD SPI Master Controller Driver");
Commit	Line	Data
bbb336f3 SM	1	// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
	2	//
	3	// AMD SPI controller driver
	4	//
	5	// Copyright (c) 2020, Advanced Micro Devices, Inc.
	6	//
	7	// Author: Sanjay R Mehta <sanju.mehta@amd.com>
	8
	9	#include <linux/acpi.h>
	10	#include <linux/init.h>
	11	#include <linux/module.h>
	12	#include <linux/platform_device.h>
	13	#include <linux/delay.h>
	14	#include <linux/spi/spi.h>
715bea35	15	#include <linux/iopoll.h>
bbb336f3 SM	16
	17	#define AMD_SPI_CTRL0_REG 0x00
	18	#define AMD_SPI_EXEC_CMD BIT(16)
	19	#define AMD_SPI_FIFO_CLEAR BIT(20)
	20	#define AMD_SPI_BUSY BIT(31)
	21
20904355 AA	22	#define AMD_SPI_OPCODE_REG 0x45
	23	#define AMD_SPI_CMD_TRIGGER_REG 0x47
	24	#define AMD_SPI_TRIGGER_CMD BIT(7)
	25
bbb336f3 SM	26	#define AMD_SPI_OPCODE_MASK 0xFF
	27
	28	#define AMD_SPI_ALT_CS_REG 0x1D
	29	#define AMD_SPI_ALT_CS_MASK 0x3
	30
	31	#define AMD_SPI_FIFO_BASE 0x80
	32	#define AMD_SPI_TX_COUNT_REG 0x48
	33	#define AMD_SPI_RX_COUNT_REG 0x4B
	34	#define AMD_SPI_STATUS_REG 0x4C
	35
6ece49c5	36	#define AMD_SPI_FIFO_SIZE 70
bbb336f3 SM	37	#define AMD_SPI_MEM_SIZE 200
bbb336f3 SM	38
3fe26121 LT	39	#define AMD_SPI_ENA_REG 0x20
	40	#define AMD_SPI_ALT_SPD_SHIFT 20
	41	#define AMD_SPI_ALT_SPD_MASK GENMASK(23, AMD_SPI_ALT_SPD_SHIFT)
	42	#define AMD_SPI_SPI100_SHIFT 0
	43	#define AMD_SPI_SPI100_MASK GENMASK(AMD_SPI_SPI100_SHIFT, AMD_SPI_SPI100_SHIFT)
	44	#define AMD_SPI_SPEED_REG 0x6C
	45	#define AMD_SPI_SPD7_SHIFT 8
	46	#define AMD_SPI_SPD7_MASK GENMASK(13, AMD_SPI_SPD7_SHIFT)
	47
	48	#define AMD_SPI_MAX_HZ 100000000
	49	#define AMD_SPI_MIN_HZ 800000
	50
55861e36 CC	51	/**
	52	* enum amd_spi_versions - SPI controller versions
	53	* @AMD_SPI_V1: AMDI0061 hardware version
	54	* @AMD_SPI_V2: AMDI0062 hardware version
	55	*/
20904355	56	enum amd_spi_versions {
55861e36 CC	57	AMD_SPI_V1 = 1,
55861e36 CC	58	AMD_SPI_V2,
20904355 AA	59	};
20904355 AA	60
3fe26121 LT	61	enum amd_spi_speed {
	62	F_66_66MHz,
	63	F_33_33MHz,
	64	F_22_22MHz,
	65	F_16_66MHz,
	66	F_100MHz,
	67	F_800KHz,
bff6bef7	68	SPI_SPD7 = 0x7,
3fe26121 LT	69	F_50MHz = 0x4,
	70	F_4MHz = 0x32,
	71	F_3_17MHz = 0x3F
	72	};
	73
	74	/**
	75	* struct amd_spi_freq - Matches device speed with values to write in regs
	76	* @speed_hz: Device frequency
	77	* @enable_val: Value to be written to "enable register"
	78	* @spd7_val: Some frequencies requires to have a value written at SPISPEED register
	79	*/
	80	struct amd_spi_freq {
	81	u32 speed_hz;
	82	u32 enable_val;
	83	u32 spd7_val;
	84	};
	85
55861e36 CC	86	/**
	87	* struct amd_spi - SPI driver instance
	88	* @io_remap_addr: Start address of the SPI controller registers
	89	* @version: SPI controller hardware version
3fe26121	90	* @speed_hz: Device frequency
55861e36	91	*/
bbb336f3 SM	92	struct amd_spi {
bbb336f3 SM	93	void __iomem *io_remap_addr;
20904355	94	enum amd_spi_versions version;
3fe26121	95	unsigned int speed_hz;
bbb336f3 SM	96	};
bbb336f3 SM	97
ca8e8a18	98	static inline u8 amd_spi_readreg8(struct amd_spi *amd_spi, int idx)
bbb336f3	99	{
bbb336f3 SM	100	return ioread8((u8 __iomem *)amd_spi->io_remap_addr + idx);
	101	}
	102
ca8e8a18	103	static inline void amd_spi_writereg8(struct amd_spi *amd_spi, int idx, u8 val)
bbb336f3	104	{
bbb336f3 SM	105	iowrite8(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
	106	}
	107
ca8e8a18	108	static void amd_spi_setclear_reg8(struct amd_spi *amd_spi, int idx, u8 set, u8 clear)
bbb336f3	109	{
ca8e8a18	110	u8 tmp = amd_spi_readreg8(amd_spi, idx);
bbb336f3 SM	111
bbb336f3 SM	112	tmp = (tmp & ~clear) \| set;
ca8e8a18	113	amd_spi_writereg8(amd_spi, idx, tmp);
bbb336f3 SM	114	}
bbb336f3 SM	115
ca8e8a18	116	static inline u32 amd_spi_readreg32(struct amd_spi *amd_spi, int idx)
bbb336f3	117	{
bbb336f3 SM	118	return ioread32((u8 __iomem *)amd_spi->io_remap_addr + idx);
	119	}
	120
ca8e8a18	121	static inline void amd_spi_writereg32(struct amd_spi *amd_spi, int idx, u32 val)
bbb336f3	122	{
bbb336f3 SM	123	iowrite32(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
	124	}
	125
ca8e8a18	126	static inline void amd_spi_setclear_reg32(struct amd_spi *amd_spi, int idx, u32 set, u32 clear)
bbb336f3	127	{
ca8e8a18	128	u32 tmp = amd_spi_readreg32(amd_spi, idx);
bbb336f3 SM	129
bbb336f3 SM	130	tmp = (tmp & ~clear) \| set;
ca8e8a18	131	amd_spi_writereg32(amd_spi, idx, tmp);
bbb336f3 SM	132	}
bbb336f3 SM	133
3b02d289	134	static void amd_spi_select_chip(struct amd_spi *amd_spi, u8 cs)
bbb336f3	135	{
3b02d289	136	amd_spi_setclear_reg8(amd_spi, AMD_SPI_ALT_CS_REG, cs, AMD_SPI_ALT_CS_MASK);
bbb336f3 SM	137	}
bbb336f3 SM	138
20904355 AA	139	static inline void amd_spi_clear_chip(struct amd_spi *amd_spi, u8 chip_select)
	140	{
	141	amd_spi_writereg8(amd_spi, AMD_SPI_ALT_CS_REG, chip_select & ~AMD_SPI_ALT_CS_MASK);
	142	}
	143
ca8e8a18	144	static void amd_spi_clear_fifo_ptr(struct amd_spi *amd_spi)
bbb336f3	145	{
ca8e8a18	146	amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_FIFO_CLEAR, AMD_SPI_FIFO_CLEAR);
bbb336f3 SM	147	}
bbb336f3 SM	148
20904355	149	static int amd_spi_set_opcode(struct amd_spi *amd_spi, u8 cmd_opcode)
bbb336f3	150	{
20904355 AA	151	switch (amd_spi->version) {
	152	case AMD_SPI_V1:
	153	amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, cmd_opcode,
	154	AMD_SPI_OPCODE_MASK);
	155	return 0;
	156	case AMD_SPI_V2:
	157	amd_spi_writereg8(amd_spi, AMD_SPI_OPCODE_REG, cmd_opcode);
	158	return 0;
	159	default:
	160	return -ENODEV;
	161	}
bbb336f3 SM	162	}
bbb336f3 SM	163
ca8e8a18	164	static inline void amd_spi_set_rx_count(struct amd_spi *amd_spi, u8 rx_count)
bbb336f3	165	{
ca8e8a18	166	amd_spi_setclear_reg8(amd_spi, AMD_SPI_RX_COUNT_REG, rx_count, 0xff);
bbb336f3 SM	167	}
bbb336f3 SM	168
ca8e8a18	169	static inline void amd_spi_set_tx_count(struct amd_spi *amd_spi, u8 tx_count)
bbb336f3	170	{
ca8e8a18	171	amd_spi_setclear_reg8(amd_spi, AMD_SPI_TX_COUNT_REG, tx_count, 0xff);
bbb336f3 SM	172	}
bbb336f3 SM	173
356b02f9	174	static int amd_spi_busy_wait(struct amd_spi *amd_spi)
bbb336f3	175	{
715bea35	176	u32 val;
20904355 AA	177	int reg;
	178
	179	switch (amd_spi->version) {
	180	case AMD_SPI_V1:
	181	reg = AMD_SPI_CTRL0_REG;
	182	break;
	183	case AMD_SPI_V2:
	184	reg = AMD_SPI_STATUS_REG;
	185	break;
	186	default:
	187	return -ENODEV;
	188	}
bbb336f3	189
20904355 AA	190	return readl_poll_timeout(amd_spi->io_remap_addr + reg, val,
20904355 AA	191	!(val & AMD_SPI_BUSY), 20, 2000000);
bbb336f3 SM	192	}
bbb336f3 SM	193
777a2cbb	194	static int amd_spi_execute_opcode(struct amd_spi *amd_spi)
bbb336f3	195	{
777a2cbb LT	196	int ret;
	197
	198	ret = amd_spi_busy_wait(amd_spi);
	199	if (ret)
	200	return ret;
	201
20904355 AA	202	switch (amd_spi->version) {
	203	case AMD_SPI_V1:
	204	/* Set ExecuteOpCode bit in the CTRL0 register */
	205	amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD,
	206	AMD_SPI_EXEC_CMD);
	207	return 0;
	208	case AMD_SPI_V2:
	209	/* Trigger the command execution */
	210	amd_spi_setclear_reg8(amd_spi, AMD_SPI_CMD_TRIGGER_REG,
	211	AMD_SPI_TRIGGER_CMD, AMD_SPI_TRIGGER_CMD);
	212	return 0;
	213	default:
	214	return -ENODEV;
	215	}
bbb336f3 SM	216	}
	217
	218	static int amd_spi_master_setup(struct spi_device *spi)
	219	{
ca8e8a18	220	struct amd_spi *amd_spi = spi_master_get_devdata(spi->master);
bbb336f3	221
ca8e8a18	222	amd_spi_clear_fifo_ptr(amd_spi);
bbb336f3 SM	223
	224	return 0;
	225	}
	226
3fe26121 LT	227	static const struct amd_spi_freq amd_spi_freq[] = {
	228	{ AMD_SPI_MAX_HZ, F_100MHz, 0},
	229	{ 66660000, F_66_66MHz, 0},
	230	{ 50000000, SPI_SPD7, F_50MHz},
	231	{ 33330000, F_33_33MHz, 0},
	232	{ 22220000, F_22_22MHz, 0},
	233	{ 16660000, F_16_66MHz, 0},
	234	{ 4000000, SPI_SPD7, F_4MHz},
	235	{ 3170000, SPI_SPD7, F_3_17MHz},
	236	{ AMD_SPI_MIN_HZ, F_800KHz, 0},
	237	};
	238
	239	static int amd_set_spi_freq(struct amd_spi *amd_spi, u32 speed_hz)
	240	{
	241	unsigned int i, spd7_val, alt_spd;
	242
3fe26121 LT	243	if (speed_hz < AMD_SPI_MIN_HZ)
	244	return -EINVAL;
	245
	246	for (i = 0; i < ARRAY_SIZE(amd_spi_freq); i++)
	247	if (speed_hz >= amd_spi_freq[i].speed_hz)
	248	break;
	249
9477420e	250	if (amd_spi->speed_hz == amd_spi_freq[i].speed_hz)
3fe26121 LT	251	return 0;
	252
	253	amd_spi->speed_hz = amd_spi_freq[i].speed_hz;
	254
	255	alt_spd = (amd_spi_freq[i].enable_val << AMD_SPI_ALT_SPD_SHIFT)
	256	& AMD_SPI_ALT_SPD_MASK;
	257	amd_spi_setclear_reg32(amd_spi, AMD_SPI_ENA_REG, alt_spd,
	258	AMD_SPI_ALT_SPD_MASK);
	259
	260	if (amd_spi->speed_hz == AMD_SPI_MAX_HZ)
	261	amd_spi_setclear_reg32(amd_spi, AMD_SPI_ENA_REG, 1,
	262	AMD_SPI_SPI100_MASK);
	263
	264	if (amd_spi_freq[i].spd7_val) {
	265	spd7_val = (amd_spi_freq[i].spd7_val << AMD_SPI_SPD7_SHIFT)
	266	& AMD_SPI_SPD7_MASK;
	267	amd_spi_setclear_reg32(amd_spi, AMD_SPI_SPEED_REG, spd7_val,
	268	AMD_SPI_SPD7_MASK);
	269	}
	270
	271	return 0;
	272	}
	273
bbb336f3	274	static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi,
36c72a58	275	struct spi_master *master,
bbb336f3 SM	276	struct spi_message *message)
bbb336f3 SM	277	{
bbb336f3	278	struct spi_transfer *xfer = NULL;
3fe26121	279	struct spi_device *spi = message->spi;
9d08f700	280	u8 cmd_opcode = 0, fifo_pos = AMD_SPI_FIFO_BASE;
bbb336f3	281	u8 *buf = NULL;
bbb336f3 SM	282	u32 i = 0;
	283	u32 tx_len = 0, rx_len = 0;
	284
	285	list_for_each_entry(xfer, &message->transfers,
	286	transfer_list) {
3fe26121 LT	287	if (xfer->speed_hz)
	288	amd_set_spi_freq(amd_spi, xfer->speed_hz);
	289	else
	290	amd_set_spi_freq(amd_spi, spi->max_speed_hz);
	291
9d08f700	292	if (xfer->tx_buf) {
bbb336f3	293	buf = (u8 *)xfer->tx_buf;
9d08f700 CC	294	if (!tx_len) {
	295	cmd_opcode = (u8 )xfer->tx_buf;
	296	buf++;
	297	xfer->len--;
	298	}
	299	tx_len += xfer->len;
bbb336f3 SM	300
bbb336f3 SM	301	/* Write data into the FIFO. */
9d08f700 CC	302	for (i = 0; i < xfer->len; i++)
9d08f700 CC	303	amd_spi_writereg8(amd_spi, fifo_pos + i, buf[i]);
bbb336f3	304
9d08f700	305	fifo_pos += xfer->len;
bbb336f3	306	}
9d08f700 CC	307
	308	/* Store no. of bytes to be received from FIFO */
	309	if (xfer->rx_buf)
	310	rx_len += xfer->len;
	311	}
	312
	313	if (!buf) {
	314	message->status = -EINVAL;
	315	goto fin_msg;
	316	}
	317
	318	amd_spi_set_opcode(amd_spi, cmd_opcode);
	319	amd_spi_set_tx_count(amd_spi, tx_len);
	320	amd_spi_set_rx_count(amd_spi, rx_len);
	321
	322	/* Execute command */
	323	message->status = amd_spi_execute_opcode(amd_spi);
	324	if (message->status)
	325	goto fin_msg;
	326
	327	if (rx_len) {
	328	message->status = amd_spi_busy_wait(amd_spi);
	329	if (message->status)
	330	goto fin_msg;
	331
	332	list_for_each_entry(xfer, &message->transfers, transfer_list)
	333	if (xfer->rx_buf) {
	334	buf = (u8 *)xfer->rx_buf;
	335	/* Read data from FIFO to receive buffer */
	336	for (i = 0; i < xfer->len; i++)
	337	buf[i] = amd_spi_readreg8(amd_spi, fifo_pos + i);
	338	fifo_pos += xfer->len;
	339	}
bbb336f3 SM	340	}
	341
	342	/* Update statistics */
	343	message->actual_length = tx_len + rx_len + 1;
20904355	344
9d08f700	345	fin_msg:
20904355 AA	346	switch (amd_spi->version) {
	347	case AMD_SPI_V1:
	348	break;
	349	case AMD_SPI_V2:
9e264f3f	350	amd_spi_clear_chip(amd_spi, spi_get_chipselect(message->spi, 0));
20904355 AA	351	break;
	352	default:
	353	return -ENODEV;
	354	}
	355
bbb336f3 SM	356	spi_finalize_current_message(master);
bbb336f3 SM	357
9d08f700	358	return message->status;
bbb336f3 SM	359	}
	360
	361	static int amd_spi_master_transfer(struct spi_master *master,
	362	struct spi_message *msg)
	363	{
	364	struct amd_spi *amd_spi = spi_master_get_devdata(master);
	365	struct spi_device *spi = msg->spi;
	366
9e264f3f	367	amd_spi_select_chip(amd_spi, spi_get_chipselect(spi, 0));
bbb336f3 SM	368
	369	/*
	370	* Extract spi_transfers from the spi message and
	371	* program the controller.
	372	*/
9d08f700	373	return amd_spi_fifo_xfer(amd_spi, master, msg);
bbb336f3 SM	374	}
bbb336f3 SM	375
6ece49c5 CC	376	static size_t amd_spi_max_transfer_size(struct spi_device *spi)
	377	{
	378	return AMD_SPI_FIFO_SIZE;
	379	}
	380
bbb336f3 SM	381	static int amd_spi_probe(struct platform_device *pdev)
	382	{
	383	struct device *dev = &pdev->dev;
	384	struct spi_master *master;
	385	struct amd_spi *amd_spi;
2e063bb1	386	int err;
bbb336f3 SM	387
bbb336f3 SM	388	/* Allocate storage for spi_master and driver private data */
2e063bb1	389	master = devm_spi_alloc_master(dev, sizeof(struct amd_spi));
deef4da8 CC	390	if (!master)
deef4da8 CC	391	return dev_err_probe(dev, -ENOMEM, "Error allocating SPI master\n");
bbb336f3 SM	392
bbb336f3 SM	393	amd_spi = spi_master_get_devdata(master);
2ed6e3ba	394	amd_spi->io_remap_addr = devm_platform_ioremap_resource(pdev, 0);
deef4da8 CC	395	if (IS_ERR(amd_spi->io_remap_addr))
	396	return dev_err_probe(dev, PTR_ERR(amd_spi->io_remap_addr),
	397	"ioremap of SPI registers failed\n");
	398
bbb336f3 SM	399	dev_dbg(dev, "io_remap_address: %p\n", amd_spi->io_remap_addr);
bbb336f3 SM	400
20904355 AA	401	amd_spi->version = (enum amd_spi_versions) device_get_match_data(dev);
20904355 AA	402
bbb336f3 SM	403	/* Initialize the spi_master fields */
	404	master->bus_num = 0;
	405	master->num_chipselect = 4;
	406	master->mode_bits = 0;
	407	master->flags = SPI_MASTER_HALF_DUPLEX;
3fe26121 LT	408	master->max_speed_hz = AMD_SPI_MAX_HZ;
3fe26121 LT	409	master->min_speed_hz = AMD_SPI_MIN_HZ;
bbb336f3 SM	410	master->setup = amd_spi_master_setup;
bbb336f3 SM	411	master->transfer_one_message = amd_spi_master_transfer;
6ece49c5 CC	412	master->max_transfer_size = amd_spi_max_transfer_size;
6ece49c5 CC	413	master->max_message_size = amd_spi_max_transfer_size;
bbb336f3 SM	414
bbb336f3 SM	415	/* Register the controller with SPI framework */
7b9c94bd	416	err = devm_spi_register_master(dev, master);
2e063bb1	417	if (err)
deef4da8	418	return dev_err_probe(dev, err, "error registering SPI controller\n");
bbb336f3	419
deef4da8	420	return 0;
bbb336f3 SM	421	}
bbb336f3 SM	422
85ed0f63	423	#ifdef CONFIG_ACPI
bbb336f3	424	static const struct acpi_device_id spi_acpi_match[] = {
20904355 AA	425	{ "AMDI0061", AMD_SPI_V1 },
20904355 AA	426	{ "AMDI0062", AMD_SPI_V2 },
bbb336f3 SM	427	{},
	428	};
	429	MODULE_DEVICE_TABLE(acpi, spi_acpi_match);
85ed0f63	430	#endif
bbb336f3 SM	431
	432	static struct platform_driver amd_spi_driver = {
	433	.driver = {
	434	.name = "amd_spi",
2b993ab7	435	.acpi_match_table = ACPI_PTR(spi_acpi_match),
bbb336f3 SM	436	},
bbb336f3 SM	437	.probe = amd_spi_probe,
bbb336f3 SM	438	};
	439
	440	module_platform_driver(amd_spi_driver);
	441
	442	MODULE_LICENSE("Dual BSD/GPL");
	443	MODULE_AUTHOR("Sanjay Mehta <sanju.mehta@amd.com>");
	444	MODULE_DESCRIPTION("AMD SPI Master Controller Driver");