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e0c9905e SS |
1 | /* |
2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
19 | #include <linux/init.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/device.h> | |
22 | #include <linux/ioport.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/dma-mapping.h> | |
27 | #include <linux/spi/spi.h> | |
28 | #include <linux/workqueue.h> | |
e0c9905e | 29 | #include <linux/delay.h> |
2f1a74e5 | 30 | #include <linux/clk.h> |
e0c9905e SS |
31 | |
32 | #include <asm/io.h> | |
33 | #include <asm/irq.h> | |
e0c9905e SS |
34 | #include <asm/delay.h> |
35 | #include <asm/dma.h> | |
36 | ||
a09e64fb RK |
37 | #include <mach/hardware.h> |
38 | #include <mach/pxa-regs.h> | |
39 | #include <mach/regs-ssp.h> | |
40 | #include <mach/ssp.h> | |
41 | #include <mach/pxa2xx_spi.h> | |
e0c9905e SS |
42 | |
43 | MODULE_AUTHOR("Stephen Street"); | |
037cdafe | 44 | MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); |
e0c9905e | 45 | MODULE_LICENSE("GPL"); |
7e38c3c4 | 46 | MODULE_ALIAS("platform:pxa2xx-spi"); |
e0c9905e SS |
47 | |
48 | #define MAX_BUSES 3 | |
49 | ||
7e964455 NF |
50 | #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR) |
51 | #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK) | |
20b918dc | 52 | #define IS_DMA_ALIGNED(x) ((((u32)(x)) & 0x07) == 0) |
7e964455 | 53 | #define MAX_DMA_LEN 8191 |
e0c9905e | 54 | |
b97c74bd NF |
55 | /* |
56 | * for testing SSCR1 changes that require SSP restart, basically | |
57 | * everything except the service and interrupt enables, the pxa270 developer | |
58 | * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this | |
59 | * list, but the PXA255 dev man says all bits without really meaning the | |
60 | * service and interrupt enables | |
61 | */ | |
62 | #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ | |
8d94cc50 | 63 | | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ |
b97c74bd NF |
64 | | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ |
65 | | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ | |
66 | | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ | |
67 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
8d94cc50 | 68 | |
e0c9905e | 69 | #define DEFINE_SSP_REG(reg, off) \ |
cf43369d DB |
70 | static inline u32 read_##reg(void const __iomem *p) \ |
71 | { return __raw_readl(p + (off)); } \ | |
72 | \ | |
73 | static inline void write_##reg(u32 v, void __iomem *p) \ | |
74 | { __raw_writel(v, p + (off)); } | |
e0c9905e SS |
75 | |
76 | DEFINE_SSP_REG(SSCR0, 0x00) | |
77 | DEFINE_SSP_REG(SSCR1, 0x04) | |
78 | DEFINE_SSP_REG(SSSR, 0x08) | |
79 | DEFINE_SSP_REG(SSITR, 0x0c) | |
80 | DEFINE_SSP_REG(SSDR, 0x10) | |
81 | DEFINE_SSP_REG(SSTO, 0x28) | |
82 | DEFINE_SSP_REG(SSPSP, 0x2c) | |
83 | ||
84 | #define START_STATE ((void*)0) | |
85 | #define RUNNING_STATE ((void*)1) | |
86 | #define DONE_STATE ((void*)2) | |
87 | #define ERROR_STATE ((void*)-1) | |
88 | ||
89 | #define QUEUE_RUNNING 0 | |
90 | #define QUEUE_STOPPED 1 | |
91 | ||
92 | struct driver_data { | |
93 | /* Driver model hookup */ | |
94 | struct platform_device *pdev; | |
95 | ||
2f1a74e5 | 96 | /* SSP Info */ |
97 | struct ssp_device *ssp; | |
98 | ||
e0c9905e SS |
99 | /* SPI framework hookup */ |
100 | enum pxa_ssp_type ssp_type; | |
101 | struct spi_master *master; | |
102 | ||
103 | /* PXA hookup */ | |
104 | struct pxa2xx_spi_master *master_info; | |
105 | ||
106 | /* DMA setup stuff */ | |
107 | int rx_channel; | |
108 | int tx_channel; | |
109 | u32 *null_dma_buf; | |
110 | ||
111 | /* SSP register addresses */ | |
cf43369d | 112 | void __iomem *ioaddr; |
e0c9905e SS |
113 | u32 ssdr_physical; |
114 | ||
115 | /* SSP masks*/ | |
116 | u32 dma_cr1; | |
117 | u32 int_cr1; | |
118 | u32 clear_sr; | |
119 | u32 mask_sr; | |
120 | ||
121 | /* Driver message queue */ | |
122 | struct workqueue_struct *workqueue; | |
123 | struct work_struct pump_messages; | |
124 | spinlock_t lock; | |
125 | struct list_head queue; | |
126 | int busy; | |
127 | int run; | |
128 | ||
129 | /* Message Transfer pump */ | |
130 | struct tasklet_struct pump_transfers; | |
131 | ||
132 | /* Current message transfer state info */ | |
133 | struct spi_message* cur_msg; | |
134 | struct spi_transfer* cur_transfer; | |
135 | struct chip_data *cur_chip; | |
136 | size_t len; | |
137 | void *tx; | |
138 | void *tx_end; | |
139 | void *rx; | |
140 | void *rx_end; | |
141 | int dma_mapped; | |
142 | dma_addr_t rx_dma; | |
143 | dma_addr_t tx_dma; | |
144 | size_t rx_map_len; | |
145 | size_t tx_map_len; | |
9708c121 SS |
146 | u8 n_bytes; |
147 | u32 dma_width; | |
8d94cc50 SS |
148 | int (*write)(struct driver_data *drv_data); |
149 | int (*read)(struct driver_data *drv_data); | |
e0c9905e SS |
150 | irqreturn_t (*transfer_handler)(struct driver_data *drv_data); |
151 | void (*cs_control)(u32 command); | |
152 | }; | |
153 | ||
154 | struct chip_data { | |
155 | u32 cr0; | |
156 | u32 cr1; | |
e0c9905e SS |
157 | u32 psp; |
158 | u32 timeout; | |
159 | u8 n_bytes; | |
160 | u32 dma_width; | |
161 | u32 dma_burst_size; | |
162 | u32 threshold; | |
163 | u32 dma_threshold; | |
164 | u8 enable_dma; | |
9708c121 SS |
165 | u8 bits_per_word; |
166 | u32 speed_hz; | |
8d94cc50 SS |
167 | int (*write)(struct driver_data *drv_data); |
168 | int (*read)(struct driver_data *drv_data); | |
e0c9905e SS |
169 | void (*cs_control)(u32 command); |
170 | }; | |
171 | ||
6d5aefb8 | 172 | static void pump_messages(struct work_struct *work); |
e0c9905e SS |
173 | |
174 | static int flush(struct driver_data *drv_data) | |
175 | { | |
176 | unsigned long limit = loops_per_jiffy << 1; | |
177 | ||
cf43369d | 178 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
179 | |
180 | do { | |
181 | while (read_SSSR(reg) & SSSR_RNE) { | |
182 | read_SSDR(reg); | |
183 | } | |
184 | } while ((read_SSSR(reg) & SSSR_BSY) && limit--); | |
185 | write_SSSR(SSSR_ROR, reg); | |
186 | ||
187 | return limit; | |
188 | } | |
189 | ||
e0c9905e SS |
190 | static void null_cs_control(u32 command) |
191 | { | |
192 | } | |
193 | ||
8d94cc50 | 194 | static int null_writer(struct driver_data *drv_data) |
e0c9905e | 195 | { |
cf43369d | 196 | void __iomem *reg = drv_data->ioaddr; |
9708c121 | 197 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 198 | |
8d94cc50 SS |
199 | if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00) |
200 | || (drv_data->tx == drv_data->tx_end)) | |
201 | return 0; | |
202 | ||
203 | write_SSDR(0, reg); | |
204 | drv_data->tx += n_bytes; | |
205 | ||
206 | return 1; | |
e0c9905e SS |
207 | } |
208 | ||
8d94cc50 | 209 | static int null_reader(struct driver_data *drv_data) |
e0c9905e | 210 | { |
cf43369d | 211 | void __iomem *reg = drv_data->ioaddr; |
9708c121 | 212 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e SS |
213 | |
214 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 215 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
216 | read_SSDR(reg); |
217 | drv_data->rx += n_bytes; | |
218 | } | |
8d94cc50 SS |
219 | |
220 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
221 | } |
222 | ||
8d94cc50 | 223 | static int u8_writer(struct driver_data *drv_data) |
e0c9905e | 224 | { |
cf43369d | 225 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 226 | |
8d94cc50 SS |
227 | if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00) |
228 | || (drv_data->tx == drv_data->tx_end)) | |
229 | return 0; | |
230 | ||
231 | write_SSDR(*(u8 *)(drv_data->tx), reg); | |
232 | ++drv_data->tx; | |
233 | ||
234 | return 1; | |
e0c9905e SS |
235 | } |
236 | ||
8d94cc50 | 237 | static int u8_reader(struct driver_data *drv_data) |
e0c9905e | 238 | { |
cf43369d | 239 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
240 | |
241 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 242 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
243 | *(u8 *)(drv_data->rx) = read_SSDR(reg); |
244 | ++drv_data->rx; | |
245 | } | |
8d94cc50 SS |
246 | |
247 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
248 | } |
249 | ||
8d94cc50 | 250 | static int u16_writer(struct driver_data *drv_data) |
e0c9905e | 251 | { |
cf43369d | 252 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 253 | |
8d94cc50 SS |
254 | if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00) |
255 | || (drv_data->tx == drv_data->tx_end)) | |
256 | return 0; | |
257 | ||
258 | write_SSDR(*(u16 *)(drv_data->tx), reg); | |
259 | drv_data->tx += 2; | |
260 | ||
261 | return 1; | |
e0c9905e SS |
262 | } |
263 | ||
8d94cc50 | 264 | static int u16_reader(struct driver_data *drv_data) |
e0c9905e | 265 | { |
cf43369d | 266 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
267 | |
268 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 269 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
270 | *(u16 *)(drv_data->rx) = read_SSDR(reg); |
271 | drv_data->rx += 2; | |
272 | } | |
8d94cc50 SS |
273 | |
274 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e | 275 | } |
8d94cc50 SS |
276 | |
277 | static int u32_writer(struct driver_data *drv_data) | |
e0c9905e | 278 | { |
cf43369d | 279 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 280 | |
8d94cc50 SS |
281 | if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00) |
282 | || (drv_data->tx == drv_data->tx_end)) | |
283 | return 0; | |
284 | ||
285 | write_SSDR(*(u32 *)(drv_data->tx), reg); | |
286 | drv_data->tx += 4; | |
287 | ||
288 | return 1; | |
e0c9905e SS |
289 | } |
290 | ||
8d94cc50 | 291 | static int u32_reader(struct driver_data *drv_data) |
e0c9905e | 292 | { |
cf43369d | 293 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
294 | |
295 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 296 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
297 | *(u32 *)(drv_data->rx) = read_SSDR(reg); |
298 | drv_data->rx += 4; | |
299 | } | |
8d94cc50 SS |
300 | |
301 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
302 | } |
303 | ||
304 | static void *next_transfer(struct driver_data *drv_data) | |
305 | { | |
306 | struct spi_message *msg = drv_data->cur_msg; | |
307 | struct spi_transfer *trans = drv_data->cur_transfer; | |
308 | ||
309 | /* Move to next transfer */ | |
310 | if (trans->transfer_list.next != &msg->transfers) { | |
311 | drv_data->cur_transfer = | |
312 | list_entry(trans->transfer_list.next, | |
313 | struct spi_transfer, | |
314 | transfer_list); | |
315 | return RUNNING_STATE; | |
316 | } else | |
317 | return DONE_STATE; | |
318 | } | |
319 | ||
320 | static int map_dma_buffers(struct driver_data *drv_data) | |
321 | { | |
322 | struct spi_message *msg = drv_data->cur_msg; | |
323 | struct device *dev = &msg->spi->dev; | |
324 | ||
325 | if (!drv_data->cur_chip->enable_dma) | |
326 | return 0; | |
327 | ||
328 | if (msg->is_dma_mapped) | |
329 | return drv_data->rx_dma && drv_data->tx_dma; | |
330 | ||
331 | if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx)) | |
332 | return 0; | |
333 | ||
334 | /* Modify setup if rx buffer is null */ | |
335 | if (drv_data->rx == NULL) { | |
336 | *drv_data->null_dma_buf = 0; | |
337 | drv_data->rx = drv_data->null_dma_buf; | |
338 | drv_data->rx_map_len = 4; | |
339 | } else | |
340 | drv_data->rx_map_len = drv_data->len; | |
341 | ||
342 | ||
343 | /* Modify setup if tx buffer is null */ | |
344 | if (drv_data->tx == NULL) { | |
345 | *drv_data->null_dma_buf = 0; | |
346 | drv_data->tx = drv_data->null_dma_buf; | |
347 | drv_data->tx_map_len = 4; | |
348 | } else | |
349 | drv_data->tx_map_len = drv_data->len; | |
350 | ||
351 | /* Stream map the rx buffer */ | |
352 | drv_data->rx_dma = dma_map_single(dev, drv_data->rx, | |
353 | drv_data->rx_map_len, | |
354 | DMA_FROM_DEVICE); | |
8d8bb39b | 355 | if (dma_mapping_error(dev, drv_data->rx_dma)) |
e0c9905e SS |
356 | return 0; |
357 | ||
358 | /* Stream map the tx buffer */ | |
359 | drv_data->tx_dma = dma_map_single(dev, drv_data->tx, | |
360 | drv_data->tx_map_len, | |
361 | DMA_TO_DEVICE); | |
362 | ||
8d8bb39b | 363 | if (dma_mapping_error(dev, drv_data->tx_dma)) { |
e0c9905e SS |
364 | dma_unmap_single(dev, drv_data->rx_dma, |
365 | drv_data->rx_map_len, DMA_FROM_DEVICE); | |
366 | return 0; | |
367 | } | |
368 | ||
369 | return 1; | |
370 | } | |
371 | ||
372 | static void unmap_dma_buffers(struct driver_data *drv_data) | |
373 | { | |
374 | struct device *dev; | |
375 | ||
376 | if (!drv_data->dma_mapped) | |
377 | return; | |
378 | ||
379 | if (!drv_data->cur_msg->is_dma_mapped) { | |
380 | dev = &drv_data->cur_msg->spi->dev; | |
381 | dma_unmap_single(dev, drv_data->rx_dma, | |
382 | drv_data->rx_map_len, DMA_FROM_DEVICE); | |
383 | dma_unmap_single(dev, drv_data->tx_dma, | |
384 | drv_data->tx_map_len, DMA_TO_DEVICE); | |
385 | } | |
386 | ||
387 | drv_data->dma_mapped = 0; | |
388 | } | |
389 | ||
390 | /* caller already set message->status; dma and pio irqs are blocked */ | |
5daa3ba0 | 391 | static void giveback(struct driver_data *drv_data) |
e0c9905e SS |
392 | { |
393 | struct spi_transfer* last_transfer; | |
5daa3ba0 SS |
394 | unsigned long flags; |
395 | struct spi_message *msg; | |
e0c9905e | 396 | |
5daa3ba0 SS |
397 | spin_lock_irqsave(&drv_data->lock, flags); |
398 | msg = drv_data->cur_msg; | |
399 | drv_data->cur_msg = NULL; | |
400 | drv_data->cur_transfer = NULL; | |
401 | drv_data->cur_chip = NULL; | |
402 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
403 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
404 | ||
405 | last_transfer = list_entry(msg->transfers.prev, | |
e0c9905e SS |
406 | struct spi_transfer, |
407 | transfer_list); | |
408 | ||
8423597d NF |
409 | /* Delay if requested before any change in chip select */ |
410 | if (last_transfer->delay_usecs) | |
411 | udelay(last_transfer->delay_usecs); | |
412 | ||
413 | /* Drop chip select UNLESS cs_change is true or we are returning | |
414 | * a message with an error, or next message is for another chip | |
415 | */ | |
e0c9905e SS |
416 | if (!last_transfer->cs_change) |
417 | drv_data->cs_control(PXA2XX_CS_DEASSERT); | |
8423597d NF |
418 | else { |
419 | struct spi_message *next_msg; | |
420 | ||
421 | /* Holding of cs was hinted, but we need to make sure | |
422 | * the next message is for the same chip. Don't waste | |
423 | * time with the following tests unless this was hinted. | |
424 | * | |
425 | * We cannot postpone this until pump_messages, because | |
426 | * after calling msg->complete (below) the driver that | |
427 | * sent the current message could be unloaded, which | |
428 | * could invalidate the cs_control() callback... | |
429 | */ | |
430 | ||
431 | /* get a pointer to the next message, if any */ | |
432 | spin_lock_irqsave(&drv_data->lock, flags); | |
433 | if (list_empty(&drv_data->queue)) | |
434 | next_msg = NULL; | |
435 | else | |
436 | next_msg = list_entry(drv_data->queue.next, | |
437 | struct spi_message, queue); | |
438 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
439 | ||
440 | /* see if the next and current messages point | |
441 | * to the same chip | |
442 | */ | |
443 | if (next_msg && next_msg->spi != msg->spi) | |
444 | next_msg = NULL; | |
445 | if (!next_msg || msg->state == ERROR_STATE) | |
446 | drv_data->cs_control(PXA2XX_CS_DEASSERT); | |
447 | } | |
e0c9905e | 448 | |
5daa3ba0 SS |
449 | msg->state = NULL; |
450 | if (msg->complete) | |
451 | msg->complete(msg->context); | |
e0c9905e SS |
452 | } |
453 | ||
cf43369d | 454 | static int wait_ssp_rx_stall(void const __iomem *ioaddr) |
e0c9905e SS |
455 | { |
456 | unsigned long limit = loops_per_jiffy << 1; | |
457 | ||
458 | while ((read_SSSR(ioaddr) & SSSR_BSY) && limit--) | |
459 | cpu_relax(); | |
460 | ||
461 | return limit; | |
462 | } | |
463 | ||
464 | static int wait_dma_channel_stop(int channel) | |
465 | { | |
466 | unsigned long limit = loops_per_jiffy << 1; | |
467 | ||
468 | while (!(DCSR(channel) & DCSR_STOPSTATE) && limit--) | |
469 | cpu_relax(); | |
470 | ||
471 | return limit; | |
472 | } | |
473 | ||
cf43369d | 474 | static void dma_error_stop(struct driver_data *drv_data, const char *msg) |
e0c9905e | 475 | { |
cf43369d | 476 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 477 | |
8d94cc50 SS |
478 | /* Stop and reset */ |
479 | DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; | |
480 | DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; | |
481 | write_SSSR(drv_data->clear_sr, reg); | |
482 | write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); | |
483 | if (drv_data->ssp_type != PXA25x_SSP) | |
484 | write_SSTO(0, reg); | |
485 | flush(drv_data); | |
486 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | |
e0c9905e | 487 | |
8d94cc50 | 488 | unmap_dma_buffers(drv_data); |
e0c9905e | 489 | |
8d94cc50 | 490 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 491 | |
8d94cc50 SS |
492 | drv_data->cur_msg->state = ERROR_STATE; |
493 | tasklet_schedule(&drv_data->pump_transfers); | |
494 | } | |
495 | ||
496 | static void dma_transfer_complete(struct driver_data *drv_data) | |
497 | { | |
cf43369d | 498 | void __iomem *reg = drv_data->ioaddr; |
8d94cc50 SS |
499 | struct spi_message *msg = drv_data->cur_msg; |
500 | ||
501 | /* Clear and disable interrupts on SSP and DMA channels*/ | |
502 | write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); | |
503 | write_SSSR(drv_data->clear_sr, reg); | |
504 | DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; | |
505 | DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; | |
506 | ||
507 | if (wait_dma_channel_stop(drv_data->rx_channel) == 0) | |
508 | dev_err(&drv_data->pdev->dev, | |
509 | "dma_handler: dma rx channel stop failed\n"); | |
510 | ||
511 | if (wait_ssp_rx_stall(drv_data->ioaddr) == 0) | |
512 | dev_err(&drv_data->pdev->dev, | |
513 | "dma_transfer: ssp rx stall failed\n"); | |
514 | ||
515 | unmap_dma_buffers(drv_data); | |
516 | ||
517 | /* update the buffer pointer for the amount completed in dma */ | |
518 | drv_data->rx += drv_data->len - | |
519 | (DCMD(drv_data->rx_channel) & DCMD_LENGTH); | |
520 | ||
521 | /* read trailing data from fifo, it does not matter how many | |
522 | * bytes are in the fifo just read until buffer is full | |
523 | * or fifo is empty, which ever occurs first */ | |
524 | drv_data->read(drv_data); | |
525 | ||
526 | /* return count of what was actually read */ | |
527 | msg->actual_length += drv_data->len - | |
528 | (drv_data->rx_end - drv_data->rx); | |
529 | ||
8423597d NF |
530 | /* Transfer delays and chip select release are |
531 | * handled in pump_transfers or giveback | |
532 | */ | |
8d94cc50 SS |
533 | |
534 | /* Move to next transfer */ | |
535 | msg->state = next_transfer(drv_data); | |
536 | ||
537 | /* Schedule transfer tasklet */ | |
538 | tasklet_schedule(&drv_data->pump_transfers); | |
539 | } | |
540 | ||
541 | static void dma_handler(int channel, void *data) | |
542 | { | |
543 | struct driver_data *drv_data = data; | |
544 | u32 irq_status = DCSR(channel) & DMA_INT_MASK; | |
545 | ||
546 | if (irq_status & DCSR_BUSERR) { | |
e0c9905e SS |
547 | |
548 | if (channel == drv_data->tx_channel) | |
8d94cc50 SS |
549 | dma_error_stop(drv_data, |
550 | "dma_handler: " | |
551 | "bad bus address on tx channel"); | |
e0c9905e | 552 | else |
8d94cc50 SS |
553 | dma_error_stop(drv_data, |
554 | "dma_handler: " | |
555 | "bad bus address on rx channel"); | |
556 | return; | |
e0c9905e SS |
557 | } |
558 | ||
559 | /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */ | |
8d94cc50 SS |
560 | if ((channel == drv_data->tx_channel) |
561 | && (irq_status & DCSR_ENDINTR) | |
562 | && (drv_data->ssp_type == PXA25x_SSP)) { | |
e0c9905e SS |
563 | |
564 | /* Wait for rx to stall */ | |
565 | if (wait_ssp_rx_stall(drv_data->ioaddr) == 0) | |
566 | dev_err(&drv_data->pdev->dev, | |
567 | "dma_handler: ssp rx stall failed\n"); | |
568 | ||
8d94cc50 SS |
569 | /* finish this transfer, start the next */ |
570 | dma_transfer_complete(drv_data); | |
e0c9905e SS |
571 | } |
572 | } | |
573 | ||
574 | static irqreturn_t dma_transfer(struct driver_data *drv_data) | |
575 | { | |
576 | u32 irq_status; | |
cf43369d | 577 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
578 | |
579 | irq_status = read_SSSR(reg) & drv_data->mask_sr; | |
580 | if (irq_status & SSSR_ROR) { | |
8d94cc50 | 581 | dma_error_stop(drv_data, "dma_transfer: fifo overrun"); |
e0c9905e SS |
582 | return IRQ_HANDLED; |
583 | } | |
584 | ||
585 | /* Check for false positive timeout */ | |
8d94cc50 SS |
586 | if ((irq_status & SSSR_TINT) |
587 | && (DCSR(drv_data->tx_channel) & DCSR_RUN)) { | |
e0c9905e SS |
588 | write_SSSR(SSSR_TINT, reg); |
589 | return IRQ_HANDLED; | |
590 | } | |
591 | ||
592 | if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) { | |
593 | ||
8d94cc50 SS |
594 | /* Clear and disable timeout interrupt, do the rest in |
595 | * dma_transfer_complete */ | |
e0c9905e SS |
596 | if (drv_data->ssp_type != PXA25x_SSP) |
597 | write_SSTO(0, reg); | |
e0c9905e | 598 | |
8d94cc50 SS |
599 | /* finish this transfer, start the next */ |
600 | dma_transfer_complete(drv_data); | |
e0c9905e SS |
601 | |
602 | return IRQ_HANDLED; | |
603 | } | |
604 | ||
605 | /* Opps problem detected */ | |
606 | return IRQ_NONE; | |
607 | } | |
608 | ||
8d94cc50 | 609 | static void int_error_stop(struct driver_data *drv_data, const char* msg) |
e0c9905e | 610 | { |
cf43369d | 611 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 612 | |
8d94cc50 SS |
613 | /* Stop and reset SSP */ |
614 | write_SSSR(drv_data->clear_sr, reg); | |
615 | write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); | |
616 | if (drv_data->ssp_type != PXA25x_SSP) | |
617 | write_SSTO(0, reg); | |
618 | flush(drv_data); | |
619 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | |
e0c9905e | 620 | |
8d94cc50 | 621 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 622 | |
8d94cc50 SS |
623 | drv_data->cur_msg->state = ERROR_STATE; |
624 | tasklet_schedule(&drv_data->pump_transfers); | |
625 | } | |
5daa3ba0 | 626 | |
8d94cc50 SS |
627 | static void int_transfer_complete(struct driver_data *drv_data) |
628 | { | |
cf43369d | 629 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 630 | |
8d94cc50 SS |
631 | /* Stop SSP */ |
632 | write_SSSR(drv_data->clear_sr, reg); | |
633 | write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); | |
634 | if (drv_data->ssp_type != PXA25x_SSP) | |
635 | write_SSTO(0, reg); | |
e0c9905e | 636 | |
8d94cc50 SS |
637 | /* Update total byte transfered return count actual bytes read */ |
638 | drv_data->cur_msg->actual_length += drv_data->len - | |
639 | (drv_data->rx_end - drv_data->rx); | |
e0c9905e | 640 | |
8423597d NF |
641 | /* Transfer delays and chip select release are |
642 | * handled in pump_transfers or giveback | |
643 | */ | |
e0c9905e | 644 | |
8d94cc50 SS |
645 | /* Move to next transfer */ |
646 | drv_data->cur_msg->state = next_transfer(drv_data); | |
e0c9905e | 647 | |
8d94cc50 SS |
648 | /* Schedule transfer tasklet */ |
649 | tasklet_schedule(&drv_data->pump_transfers); | |
650 | } | |
e0c9905e | 651 | |
8d94cc50 SS |
652 | static irqreturn_t interrupt_transfer(struct driver_data *drv_data) |
653 | { | |
cf43369d | 654 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 655 | |
8d94cc50 SS |
656 | u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ? |
657 | drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; | |
e0c9905e | 658 | |
8d94cc50 | 659 | u32 irq_status = read_SSSR(reg) & irq_mask; |
e0c9905e | 660 | |
8d94cc50 SS |
661 | if (irq_status & SSSR_ROR) { |
662 | int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); | |
663 | return IRQ_HANDLED; | |
664 | } | |
e0c9905e | 665 | |
8d94cc50 SS |
666 | if (irq_status & SSSR_TINT) { |
667 | write_SSSR(SSSR_TINT, reg); | |
668 | if (drv_data->read(drv_data)) { | |
669 | int_transfer_complete(drv_data); | |
670 | return IRQ_HANDLED; | |
671 | } | |
672 | } | |
e0c9905e | 673 | |
8d94cc50 SS |
674 | /* Drain rx fifo, Fill tx fifo and prevent overruns */ |
675 | do { | |
676 | if (drv_data->read(drv_data)) { | |
677 | int_transfer_complete(drv_data); | |
678 | return IRQ_HANDLED; | |
679 | } | |
680 | } while (drv_data->write(drv_data)); | |
e0c9905e | 681 | |
8d94cc50 SS |
682 | if (drv_data->read(drv_data)) { |
683 | int_transfer_complete(drv_data); | |
684 | return IRQ_HANDLED; | |
685 | } | |
e0c9905e | 686 | |
8d94cc50 SS |
687 | if (drv_data->tx == drv_data->tx_end) { |
688 | write_SSCR1(read_SSCR1(reg) & ~SSCR1_TIE, reg); | |
689 | /* PXA25x_SSP has no timeout, read trailing bytes */ | |
690 | if (drv_data->ssp_type == PXA25x_SSP) { | |
691 | if (!wait_ssp_rx_stall(reg)) | |
692 | { | |
693 | int_error_stop(drv_data, "interrupt_transfer: " | |
694 | "rx stall failed"); | |
695 | return IRQ_HANDLED; | |
696 | } | |
697 | if (!drv_data->read(drv_data)) | |
698 | { | |
699 | int_error_stop(drv_data, | |
700 | "interrupt_transfer: " | |
701 | "trailing byte read failed"); | |
702 | return IRQ_HANDLED; | |
703 | } | |
704 | int_transfer_complete(drv_data); | |
e0c9905e | 705 | } |
e0c9905e SS |
706 | } |
707 | ||
5daa3ba0 SS |
708 | /* We did something */ |
709 | return IRQ_HANDLED; | |
e0c9905e SS |
710 | } |
711 | ||
7d12e780 | 712 | static irqreturn_t ssp_int(int irq, void *dev_id) |
e0c9905e | 713 | { |
c7bec5ab | 714 | struct driver_data *drv_data = dev_id; |
cf43369d | 715 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
716 | |
717 | if (!drv_data->cur_msg) { | |
5daa3ba0 SS |
718 | |
719 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | |
720 | write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); | |
721 | if (drv_data->ssp_type != PXA25x_SSP) | |
722 | write_SSTO(0, reg); | |
723 | write_SSSR(drv_data->clear_sr, reg); | |
724 | ||
e0c9905e | 725 | dev_err(&drv_data->pdev->dev, "bad message state " |
8d94cc50 | 726 | "in interrupt handler\n"); |
5daa3ba0 | 727 | |
e0c9905e SS |
728 | /* Never fail */ |
729 | return IRQ_HANDLED; | |
730 | } | |
731 | ||
732 | return drv_data->transfer_handler(drv_data); | |
733 | } | |
734 | ||
cf43369d DB |
735 | static int set_dma_burst_and_threshold(struct chip_data *chip, |
736 | struct spi_device *spi, | |
8d94cc50 SS |
737 | u8 bits_per_word, u32 *burst_code, |
738 | u32 *threshold) | |
739 | { | |
740 | struct pxa2xx_spi_chip *chip_info = | |
741 | (struct pxa2xx_spi_chip *)spi->controller_data; | |
742 | int bytes_per_word; | |
743 | int burst_bytes; | |
744 | int thresh_words; | |
745 | int req_burst_size; | |
746 | int retval = 0; | |
747 | ||
748 | /* Set the threshold (in registers) to equal the same amount of data | |
749 | * as represented by burst size (in bytes). The computation below | |
750 | * is (burst_size rounded up to nearest 8 byte, word or long word) | |
751 | * divided by (bytes/register); the tx threshold is the inverse of | |
752 | * the rx, so that there will always be enough data in the rx fifo | |
753 | * to satisfy a burst, and there will always be enough space in the | |
754 | * tx fifo to accept a burst (a tx burst will overwrite the fifo if | |
755 | * there is not enough space), there must always remain enough empty | |
756 | * space in the rx fifo for any data loaded to the tx fifo. | |
757 | * Whenever burst_size (in bytes) equals bits/word, the fifo threshold | |
758 | * will be 8, or half the fifo; | |
759 | * The threshold can only be set to 2, 4 or 8, but not 16, because | |
760 | * to burst 16 to the tx fifo, the fifo would have to be empty; | |
761 | * however, the minimum fifo trigger level is 1, and the tx will | |
762 | * request service when the fifo is at this level, with only 15 spaces. | |
763 | */ | |
764 | ||
765 | /* find bytes/word */ | |
766 | if (bits_per_word <= 8) | |
767 | bytes_per_word = 1; | |
768 | else if (bits_per_word <= 16) | |
769 | bytes_per_word = 2; | |
770 | else | |
771 | bytes_per_word = 4; | |
772 | ||
773 | /* use struct pxa2xx_spi_chip->dma_burst_size if available */ | |
774 | if (chip_info) | |
775 | req_burst_size = chip_info->dma_burst_size; | |
776 | else { | |
777 | switch (chip->dma_burst_size) { | |
778 | default: | |
779 | /* if the default burst size is not set, | |
780 | * do it now */ | |
781 | chip->dma_burst_size = DCMD_BURST8; | |
782 | case DCMD_BURST8: | |
783 | req_burst_size = 8; | |
784 | break; | |
785 | case DCMD_BURST16: | |
786 | req_burst_size = 16; | |
787 | break; | |
788 | case DCMD_BURST32: | |
789 | req_burst_size = 32; | |
790 | break; | |
791 | } | |
792 | } | |
793 | if (req_burst_size <= 8) { | |
794 | *burst_code = DCMD_BURST8; | |
795 | burst_bytes = 8; | |
796 | } else if (req_burst_size <= 16) { | |
797 | if (bytes_per_word == 1) { | |
798 | /* don't burst more than 1/2 the fifo */ | |
799 | *burst_code = DCMD_BURST8; | |
800 | burst_bytes = 8; | |
801 | retval = 1; | |
802 | } else { | |
803 | *burst_code = DCMD_BURST16; | |
804 | burst_bytes = 16; | |
805 | } | |
806 | } else { | |
807 | if (bytes_per_word == 1) { | |
808 | /* don't burst more than 1/2 the fifo */ | |
809 | *burst_code = DCMD_BURST8; | |
810 | burst_bytes = 8; | |
811 | retval = 1; | |
812 | } else if (bytes_per_word == 2) { | |
813 | /* don't burst more than 1/2 the fifo */ | |
814 | *burst_code = DCMD_BURST16; | |
815 | burst_bytes = 16; | |
816 | retval = 1; | |
817 | } else { | |
818 | *burst_code = DCMD_BURST32; | |
819 | burst_bytes = 32; | |
820 | } | |
821 | } | |
822 | ||
823 | thresh_words = burst_bytes / bytes_per_word; | |
824 | ||
825 | /* thresh_words will be between 2 and 8 */ | |
826 | *threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT) | |
827 | | (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT); | |
828 | ||
829 | return retval; | |
830 | } | |
831 | ||
2f1a74e5 | 832 | static unsigned int ssp_get_clk_div(struct ssp_device *ssp, int rate) |
833 | { | |
834 | unsigned long ssp_clk = clk_get_rate(ssp->clk); | |
835 | ||
836 | if (ssp->type == PXA25x_SSP) | |
837 | return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8; | |
838 | else | |
839 | return ((ssp_clk / rate - 1) & 0xfff) << 8; | |
840 | } | |
841 | ||
e0c9905e SS |
842 | static void pump_transfers(unsigned long data) |
843 | { | |
844 | struct driver_data *drv_data = (struct driver_data *)data; | |
845 | struct spi_message *message = NULL; | |
846 | struct spi_transfer *transfer = NULL; | |
847 | struct spi_transfer *previous = NULL; | |
848 | struct chip_data *chip = NULL; | |
2f1a74e5 | 849 | struct ssp_device *ssp = drv_data->ssp; |
cf43369d | 850 | void __iomem *reg = drv_data->ioaddr; |
9708c121 SS |
851 | u32 clk_div = 0; |
852 | u8 bits = 0; | |
853 | u32 speed = 0; | |
854 | u32 cr0; | |
8d94cc50 SS |
855 | u32 cr1; |
856 | u32 dma_thresh = drv_data->cur_chip->dma_threshold; | |
857 | u32 dma_burst = drv_data->cur_chip->dma_burst_size; | |
e0c9905e SS |
858 | |
859 | /* Get current state information */ | |
860 | message = drv_data->cur_msg; | |
861 | transfer = drv_data->cur_transfer; | |
862 | chip = drv_data->cur_chip; | |
863 | ||
864 | /* Handle for abort */ | |
865 | if (message->state == ERROR_STATE) { | |
866 | message->status = -EIO; | |
5daa3ba0 | 867 | giveback(drv_data); |
e0c9905e SS |
868 | return; |
869 | } | |
870 | ||
871 | /* Handle end of message */ | |
872 | if (message->state == DONE_STATE) { | |
873 | message->status = 0; | |
5daa3ba0 | 874 | giveback(drv_data); |
e0c9905e SS |
875 | return; |
876 | } | |
877 | ||
8423597d | 878 | /* Delay if requested at end of transfer before CS change */ |
e0c9905e SS |
879 | if (message->state == RUNNING_STATE) { |
880 | previous = list_entry(transfer->transfer_list.prev, | |
881 | struct spi_transfer, | |
882 | transfer_list); | |
883 | if (previous->delay_usecs) | |
884 | udelay(previous->delay_usecs); | |
8423597d NF |
885 | |
886 | /* Drop chip select only if cs_change is requested */ | |
887 | if (previous->cs_change) | |
888 | drv_data->cs_control(PXA2XX_CS_DEASSERT); | |
e0c9905e SS |
889 | } |
890 | ||
7e964455 NF |
891 | /* Check for transfers that need multiple DMA segments */ |
892 | if (transfer->len > MAX_DMA_LEN && chip->enable_dma) { | |
893 | ||
894 | /* reject already-mapped transfers; PIO won't always work */ | |
895 | if (message->is_dma_mapped | |
896 | || transfer->rx_dma || transfer->tx_dma) { | |
897 | dev_err(&drv_data->pdev->dev, | |
898 | "pump_transfers: mapped transfer length " | |
20b918dc | 899 | "of %u is greater than %d\n", |
7e964455 NF |
900 | transfer->len, MAX_DMA_LEN); |
901 | message->status = -EINVAL; | |
902 | giveback(drv_data); | |
903 | return; | |
904 | } | |
905 | ||
906 | /* warn ... we force this to PIO mode */ | |
907 | if (printk_ratelimit()) | |
908 | dev_warn(&message->spi->dev, "pump_transfers: " | |
909 | "DMA disabled for transfer length %ld " | |
910 | "greater than %d\n", | |
911 | (long)drv_data->len, MAX_DMA_LEN); | |
8d94cc50 SS |
912 | } |
913 | ||
e0c9905e SS |
914 | /* Setup the transfer state based on the type of transfer */ |
915 | if (flush(drv_data) == 0) { | |
916 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); | |
917 | message->status = -EIO; | |
5daa3ba0 | 918 | giveback(drv_data); |
e0c9905e SS |
919 | return; |
920 | } | |
9708c121 SS |
921 | drv_data->n_bytes = chip->n_bytes; |
922 | drv_data->dma_width = chip->dma_width; | |
e0c9905e SS |
923 | drv_data->cs_control = chip->cs_control; |
924 | drv_data->tx = (void *)transfer->tx_buf; | |
925 | drv_data->tx_end = drv_data->tx + transfer->len; | |
926 | drv_data->rx = transfer->rx_buf; | |
927 | drv_data->rx_end = drv_data->rx + transfer->len; | |
928 | drv_data->rx_dma = transfer->rx_dma; | |
929 | drv_data->tx_dma = transfer->tx_dma; | |
8d94cc50 | 930 | drv_data->len = transfer->len & DCMD_LENGTH; |
e0c9905e SS |
931 | drv_data->write = drv_data->tx ? chip->write : null_writer; |
932 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
9708c121 SS |
933 | |
934 | /* Change speed and bit per word on a per transfer */ | |
8d94cc50 | 935 | cr0 = chip->cr0; |
9708c121 SS |
936 | if (transfer->speed_hz || transfer->bits_per_word) { |
937 | ||
9708c121 SS |
938 | bits = chip->bits_per_word; |
939 | speed = chip->speed_hz; | |
940 | ||
941 | if (transfer->speed_hz) | |
942 | speed = transfer->speed_hz; | |
943 | ||
944 | if (transfer->bits_per_word) | |
945 | bits = transfer->bits_per_word; | |
946 | ||
2f1a74e5 | 947 | clk_div = ssp_get_clk_div(ssp, speed); |
9708c121 SS |
948 | |
949 | if (bits <= 8) { | |
950 | drv_data->n_bytes = 1; | |
951 | drv_data->dma_width = DCMD_WIDTH1; | |
952 | drv_data->read = drv_data->read != null_reader ? | |
953 | u8_reader : null_reader; | |
954 | drv_data->write = drv_data->write != null_writer ? | |
955 | u8_writer : null_writer; | |
956 | } else if (bits <= 16) { | |
957 | drv_data->n_bytes = 2; | |
958 | drv_data->dma_width = DCMD_WIDTH2; | |
959 | drv_data->read = drv_data->read != null_reader ? | |
960 | u16_reader : null_reader; | |
961 | drv_data->write = drv_data->write != null_writer ? | |
962 | u16_writer : null_writer; | |
963 | } else if (bits <= 32) { | |
964 | drv_data->n_bytes = 4; | |
965 | drv_data->dma_width = DCMD_WIDTH4; | |
966 | drv_data->read = drv_data->read != null_reader ? | |
967 | u32_reader : null_reader; | |
968 | drv_data->write = drv_data->write != null_writer ? | |
969 | u32_writer : null_writer; | |
970 | } | |
8d94cc50 SS |
971 | /* if bits/word is changed in dma mode, then must check the |
972 | * thresholds and burst also */ | |
973 | if (chip->enable_dma) { | |
974 | if (set_dma_burst_and_threshold(chip, message->spi, | |
975 | bits, &dma_burst, | |
976 | &dma_thresh)) | |
977 | if (printk_ratelimit()) | |
978 | dev_warn(&message->spi->dev, | |
7e964455 | 979 | "pump_transfers: " |
8d94cc50 SS |
980 | "DMA burst size reduced to " |
981 | "match bits_per_word\n"); | |
982 | } | |
9708c121 SS |
983 | |
984 | cr0 = clk_div | |
985 | | SSCR0_Motorola | |
5daa3ba0 | 986 | | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) |
9708c121 SS |
987 | | SSCR0_SSE |
988 | | (bits > 16 ? SSCR0_EDSS : 0); | |
9708c121 SS |
989 | } |
990 | ||
e0c9905e SS |
991 | message->state = RUNNING_STATE; |
992 | ||
7e964455 NF |
993 | /* Try to map dma buffer and do a dma transfer if successful, but |
994 | * only if the length is non-zero and less than MAX_DMA_LEN. | |
995 | * | |
996 | * Zero-length non-descriptor DMA is illegal on PXA2xx; force use | |
997 | * of PIO instead. Care is needed above because the transfer may | |
998 | * have have been passed with buffers that are already dma mapped. | |
999 | * A zero-length transfer in PIO mode will not try to write/read | |
1000 | * to/from the buffers | |
1001 | * | |
1002 | * REVISIT large transfers are exactly where we most want to be | |
1003 | * using DMA. If this happens much, split those transfers into | |
1004 | * multiple DMA segments rather than forcing PIO. | |
1005 | */ | |
1006 | drv_data->dma_mapped = 0; | |
1007 | if (drv_data->len > 0 && drv_data->len <= MAX_DMA_LEN) | |
1008 | drv_data->dma_mapped = map_dma_buffers(drv_data); | |
1009 | if (drv_data->dma_mapped) { | |
e0c9905e SS |
1010 | |
1011 | /* Ensure we have the correct interrupt handler */ | |
1012 | drv_data->transfer_handler = dma_transfer; | |
1013 | ||
1014 | /* Setup rx DMA Channel */ | |
1015 | DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; | |
1016 | DSADR(drv_data->rx_channel) = drv_data->ssdr_physical; | |
1017 | DTADR(drv_data->rx_channel) = drv_data->rx_dma; | |
1018 | if (drv_data->rx == drv_data->null_dma_buf) | |
1019 | /* No target address increment */ | |
1020 | DCMD(drv_data->rx_channel) = DCMD_FLOWSRC | |
9708c121 | 1021 | | drv_data->dma_width |
8d94cc50 | 1022 | | dma_burst |
e0c9905e SS |
1023 | | drv_data->len; |
1024 | else | |
1025 | DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR | |
1026 | | DCMD_FLOWSRC | |
9708c121 | 1027 | | drv_data->dma_width |
8d94cc50 | 1028 | | dma_burst |
e0c9905e SS |
1029 | | drv_data->len; |
1030 | ||
1031 | /* Setup tx DMA Channel */ | |
1032 | DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; | |
1033 | DSADR(drv_data->tx_channel) = drv_data->tx_dma; | |
1034 | DTADR(drv_data->tx_channel) = drv_data->ssdr_physical; | |
1035 | if (drv_data->tx == drv_data->null_dma_buf) | |
1036 | /* No source address increment */ | |
1037 | DCMD(drv_data->tx_channel) = DCMD_FLOWTRG | |
9708c121 | 1038 | | drv_data->dma_width |
8d94cc50 | 1039 | | dma_burst |
e0c9905e SS |
1040 | | drv_data->len; |
1041 | else | |
1042 | DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR | |
1043 | | DCMD_FLOWTRG | |
9708c121 | 1044 | | drv_data->dma_width |
8d94cc50 | 1045 | | dma_burst |
e0c9905e SS |
1046 | | drv_data->len; |
1047 | ||
1048 | /* Enable dma end irqs on SSP to detect end of transfer */ | |
1049 | if (drv_data->ssp_type == PXA25x_SSP) | |
1050 | DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN; | |
1051 | ||
8d94cc50 SS |
1052 | /* Clear status and start DMA engine */ |
1053 | cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; | |
e0c9905e SS |
1054 | write_SSSR(drv_data->clear_sr, reg); |
1055 | DCSR(drv_data->rx_channel) |= DCSR_RUN; | |
1056 | DCSR(drv_data->tx_channel) |= DCSR_RUN; | |
e0c9905e SS |
1057 | } else { |
1058 | /* Ensure we have the correct interrupt handler */ | |
1059 | drv_data->transfer_handler = interrupt_transfer; | |
1060 | ||
8d94cc50 SS |
1061 | /* Clear status */ |
1062 | cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; | |
e0c9905e | 1063 | write_SSSR(drv_data->clear_sr, reg); |
8d94cc50 SS |
1064 | } |
1065 | ||
1066 | /* see if we need to reload the config registers */ | |
1067 | if ((read_SSCR0(reg) != cr0) | |
1068 | || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) != | |
1069 | (cr1 & SSCR1_CHANGE_MASK)) { | |
1070 | ||
b97c74bd | 1071 | /* stop the SSP, and update the other bits */ |
8d94cc50 | 1072 | write_SSCR0(cr0 & ~SSCR0_SSE, reg); |
e0c9905e SS |
1073 | if (drv_data->ssp_type != PXA25x_SSP) |
1074 | write_SSTO(chip->timeout, reg); | |
b97c74bd NF |
1075 | /* first set CR1 without interrupt and service enables */ |
1076 | write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg); | |
1077 | /* restart the SSP */ | |
8d94cc50 | 1078 | write_SSCR0(cr0, reg); |
b97c74bd | 1079 | |
8d94cc50 SS |
1080 | } else { |
1081 | if (drv_data->ssp_type != PXA25x_SSP) | |
1082 | write_SSTO(chip->timeout, reg); | |
e0c9905e | 1083 | } |
b97c74bd NF |
1084 | |
1085 | /* FIXME, need to handle cs polarity, | |
1086 | * this driver uses struct pxa2xx_spi_chip.cs_control to | |
1087 | * specify a CS handling function, and it ignores most | |
1088 | * struct spi_device.mode[s], including SPI_CS_HIGH */ | |
1089 | drv_data->cs_control(PXA2XX_CS_ASSERT); | |
1090 | ||
1091 | /* after chip select, release the data by enabling service | |
1092 | * requests and interrupts, without changing any mode bits */ | |
1093 | write_SSCR1(cr1, reg); | |
e0c9905e SS |
1094 | } |
1095 | ||
6d5aefb8 | 1096 | static void pump_messages(struct work_struct *work) |
e0c9905e | 1097 | { |
6d5aefb8 DH |
1098 | struct driver_data *drv_data = |
1099 | container_of(work, struct driver_data, pump_messages); | |
e0c9905e SS |
1100 | unsigned long flags; |
1101 | ||
1102 | /* Lock queue and check for queue work */ | |
1103 | spin_lock_irqsave(&drv_data->lock, flags); | |
1104 | if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) { | |
1105 | drv_data->busy = 0; | |
1106 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1107 | return; | |
1108 | } | |
1109 | ||
1110 | /* Make sure we are not already running a message */ | |
1111 | if (drv_data->cur_msg) { | |
1112 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1113 | return; | |
1114 | } | |
1115 | ||
1116 | /* Extract head of queue */ | |
1117 | drv_data->cur_msg = list_entry(drv_data->queue.next, | |
1118 | struct spi_message, queue); | |
1119 | list_del_init(&drv_data->cur_msg->queue); | |
e0c9905e SS |
1120 | |
1121 | /* Initial message state*/ | |
1122 | drv_data->cur_msg->state = START_STATE; | |
1123 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
1124 | struct spi_transfer, | |
1125 | transfer_list); | |
1126 | ||
8d94cc50 SS |
1127 | /* prepare to setup the SSP, in pump_transfers, using the per |
1128 | * chip configuration */ | |
e0c9905e | 1129 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); |
e0c9905e SS |
1130 | |
1131 | /* Mark as busy and launch transfers */ | |
1132 | tasklet_schedule(&drv_data->pump_transfers); | |
5daa3ba0 SS |
1133 | |
1134 | drv_data->busy = 1; | |
1135 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
e0c9905e SS |
1136 | } |
1137 | ||
1138 | static int transfer(struct spi_device *spi, struct spi_message *msg) | |
1139 | { | |
1140 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
1141 | unsigned long flags; | |
1142 | ||
1143 | spin_lock_irqsave(&drv_data->lock, flags); | |
1144 | ||
1145 | if (drv_data->run == QUEUE_STOPPED) { | |
1146 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1147 | return -ESHUTDOWN; | |
1148 | } | |
1149 | ||
1150 | msg->actual_length = 0; | |
1151 | msg->status = -EINPROGRESS; | |
1152 | msg->state = START_STATE; | |
1153 | ||
1154 | list_add_tail(&msg->queue, &drv_data->queue); | |
1155 | ||
1156 | if (drv_data->run == QUEUE_RUNNING && !drv_data->busy) | |
1157 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
1158 | ||
1159 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1160 | ||
1161 | return 0; | |
1162 | } | |
1163 | ||
dccd573b DB |
1164 | /* the spi->mode bits understood by this driver: */ |
1165 | #define MODEBITS (SPI_CPOL | SPI_CPHA) | |
1166 | ||
e0c9905e SS |
1167 | static int setup(struct spi_device *spi) |
1168 | { | |
1169 | struct pxa2xx_spi_chip *chip_info = NULL; | |
1170 | struct chip_data *chip; | |
1171 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
2f1a74e5 | 1172 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1173 | unsigned int clk_div; |
1174 | ||
1175 | if (!spi->bits_per_word) | |
1176 | spi->bits_per_word = 8; | |
1177 | ||
1178 | if (drv_data->ssp_type != PXA25x_SSP | |
8d94cc50 SS |
1179 | && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) { |
1180 | dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " | |
1181 | "b/w not 4-32 for type non-PXA25x_SSP\n", | |
1182 | drv_data->ssp_type, spi->bits_per_word); | |
e0c9905e | 1183 | return -EINVAL; |
8d94cc50 SS |
1184 | } |
1185 | else if (drv_data->ssp_type == PXA25x_SSP | |
1186 | && (spi->bits_per_word < 4 | |
1187 | || spi->bits_per_word > 16)) { | |
1188 | dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " | |
1189 | "b/w not 4-16 for type PXA25x_SSP\n", | |
1190 | drv_data->ssp_type, spi->bits_per_word); | |
e0c9905e | 1191 | return -EINVAL; |
8d94cc50 | 1192 | } |
e0c9905e | 1193 | |
dccd573b DB |
1194 | if (spi->mode & ~MODEBITS) { |
1195 | dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n", | |
1196 | spi->mode & ~MODEBITS); | |
1197 | return -EINVAL; | |
1198 | } | |
1199 | ||
8d94cc50 | 1200 | /* Only alloc on first setup */ |
e0c9905e | 1201 | chip = spi_get_ctldata(spi); |
8d94cc50 | 1202 | if (!chip) { |
e0c9905e | 1203 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
8d94cc50 SS |
1204 | if (!chip) { |
1205 | dev_err(&spi->dev, | |
1206 | "failed setup: can't allocate chip data\n"); | |
e0c9905e | 1207 | return -ENOMEM; |
8d94cc50 | 1208 | } |
e0c9905e SS |
1209 | |
1210 | chip->cs_control = null_cs_control; | |
1211 | chip->enable_dma = 0; | |
8d94cc50 | 1212 | chip->timeout = 1000; |
e0c9905e SS |
1213 | chip->threshold = SSCR1_RxTresh(1) | SSCR1_TxTresh(1); |
1214 | chip->dma_burst_size = drv_data->master_info->enable_dma ? | |
1215 | DCMD_BURST8 : 0; | |
e0c9905e SS |
1216 | } |
1217 | ||
8d94cc50 SS |
1218 | /* protocol drivers may change the chip settings, so... |
1219 | * if chip_info exists, use it */ | |
1220 | chip_info = spi->controller_data; | |
1221 | ||
e0c9905e | 1222 | /* chip_info isn't always needed */ |
8d94cc50 | 1223 | chip->cr1 = 0; |
e0c9905e SS |
1224 | if (chip_info) { |
1225 | if (chip_info->cs_control) | |
1226 | chip->cs_control = chip_info->cs_control; | |
1227 | ||
8d94cc50 | 1228 | chip->timeout = chip_info->timeout; |
e0c9905e | 1229 | |
8d94cc50 SS |
1230 | chip->threshold = (SSCR1_RxTresh(chip_info->rx_threshold) & |
1231 | SSCR1_RFT) | | |
1232 | (SSCR1_TxTresh(chip_info->tx_threshold) & | |
1233 | SSCR1_TFT); | |
e0c9905e SS |
1234 | |
1235 | chip->enable_dma = chip_info->dma_burst_size != 0 | |
1236 | && drv_data->master_info->enable_dma; | |
1237 | chip->dma_threshold = 0; | |
1238 | ||
e0c9905e SS |
1239 | if (chip_info->enable_loopback) |
1240 | chip->cr1 = SSCR1_LBM; | |
1241 | } | |
1242 | ||
8d94cc50 SS |
1243 | /* set dma burst and threshold outside of chip_info path so that if |
1244 | * chip_info goes away after setting chip->enable_dma, the | |
1245 | * burst and threshold can still respond to changes in bits_per_word */ | |
1246 | if (chip->enable_dma) { | |
1247 | /* set up legal burst and threshold for dma */ | |
1248 | if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word, | |
1249 | &chip->dma_burst_size, | |
1250 | &chip->dma_threshold)) { | |
1251 | dev_warn(&spi->dev, "in setup: DMA burst size reduced " | |
1252 | "to match bits_per_word\n"); | |
1253 | } | |
1254 | } | |
1255 | ||
2f1a74e5 | 1256 | clk_div = ssp_get_clk_div(ssp, spi->max_speed_hz); |
9708c121 | 1257 | chip->speed_hz = spi->max_speed_hz; |
e0c9905e SS |
1258 | |
1259 | chip->cr0 = clk_div | |
1260 | | SSCR0_Motorola | |
5daa3ba0 SS |
1261 | | SSCR0_DataSize(spi->bits_per_word > 16 ? |
1262 | spi->bits_per_word - 16 : spi->bits_per_word) | |
e0c9905e SS |
1263 | | SSCR0_SSE |
1264 | | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0); | |
7f6ee1ad JC |
1265 | chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); |
1266 | chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) | |
1267 | | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); | |
e0c9905e SS |
1268 | |
1269 | /* NOTE: PXA25x_SSP _could_ use external clocking ... */ | |
1270 | if (drv_data->ssp_type != PXA25x_SSP) | |
2f1a74e5 | 1271 | dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d\n", |
e0c9905e | 1272 | spi->bits_per_word, |
2f1a74e5 | 1273 | clk_get_rate(ssp->clk) |
e0c9905e SS |
1274 | / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)), |
1275 | spi->mode & 0x3); | |
1276 | else | |
2f1a74e5 | 1277 | dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d\n", |
e0c9905e | 1278 | spi->bits_per_word, |
2f1a74e5 | 1279 | clk_get_rate(ssp->clk) |
e0c9905e SS |
1280 | / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)), |
1281 | spi->mode & 0x3); | |
1282 | ||
1283 | if (spi->bits_per_word <= 8) { | |
1284 | chip->n_bytes = 1; | |
1285 | chip->dma_width = DCMD_WIDTH1; | |
1286 | chip->read = u8_reader; | |
1287 | chip->write = u8_writer; | |
1288 | } else if (spi->bits_per_word <= 16) { | |
1289 | chip->n_bytes = 2; | |
1290 | chip->dma_width = DCMD_WIDTH2; | |
1291 | chip->read = u16_reader; | |
1292 | chip->write = u16_writer; | |
1293 | } else if (spi->bits_per_word <= 32) { | |
1294 | chip->cr0 |= SSCR0_EDSS; | |
1295 | chip->n_bytes = 4; | |
1296 | chip->dma_width = DCMD_WIDTH4; | |
1297 | chip->read = u32_reader; | |
1298 | chip->write = u32_writer; | |
1299 | } else { | |
1300 | dev_err(&spi->dev, "invalid wordsize\n"); | |
e0c9905e SS |
1301 | return -ENODEV; |
1302 | } | |
9708c121 | 1303 | chip->bits_per_word = spi->bits_per_word; |
e0c9905e SS |
1304 | |
1305 | spi_set_ctldata(spi, chip); | |
1306 | ||
1307 | return 0; | |
1308 | } | |
1309 | ||
0ffa0285 | 1310 | static void cleanup(struct spi_device *spi) |
e0c9905e | 1311 | { |
0ffa0285 | 1312 | struct chip_data *chip = spi_get_ctldata(spi); |
e0c9905e SS |
1313 | |
1314 | kfree(chip); | |
1315 | } | |
1316 | ||
d1e44d9c | 1317 | static int __init init_queue(struct driver_data *drv_data) |
e0c9905e SS |
1318 | { |
1319 | INIT_LIST_HEAD(&drv_data->queue); | |
1320 | spin_lock_init(&drv_data->lock); | |
1321 | ||
1322 | drv_data->run = QUEUE_STOPPED; | |
1323 | drv_data->busy = 0; | |
1324 | ||
1325 | tasklet_init(&drv_data->pump_transfers, | |
1326 | pump_transfers, (unsigned long)drv_data); | |
1327 | ||
6d5aefb8 | 1328 | INIT_WORK(&drv_data->pump_messages, pump_messages); |
e0c9905e | 1329 | drv_data->workqueue = create_singlethread_workqueue( |
49dce689 | 1330 | drv_data->master->dev.parent->bus_id); |
e0c9905e SS |
1331 | if (drv_data->workqueue == NULL) |
1332 | return -EBUSY; | |
1333 | ||
1334 | return 0; | |
1335 | } | |
1336 | ||
1337 | static int start_queue(struct driver_data *drv_data) | |
1338 | { | |
1339 | unsigned long flags; | |
1340 | ||
1341 | spin_lock_irqsave(&drv_data->lock, flags); | |
1342 | ||
1343 | if (drv_data->run == QUEUE_RUNNING || drv_data->busy) { | |
1344 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1345 | return -EBUSY; | |
1346 | } | |
1347 | ||
1348 | drv_data->run = QUEUE_RUNNING; | |
1349 | drv_data->cur_msg = NULL; | |
1350 | drv_data->cur_transfer = NULL; | |
1351 | drv_data->cur_chip = NULL; | |
1352 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1353 | ||
1354 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
1355 | ||
1356 | return 0; | |
1357 | } | |
1358 | ||
1359 | static int stop_queue(struct driver_data *drv_data) | |
1360 | { | |
1361 | unsigned long flags; | |
1362 | unsigned limit = 500; | |
1363 | int status = 0; | |
1364 | ||
1365 | spin_lock_irqsave(&drv_data->lock, flags); | |
1366 | ||
1367 | /* This is a bit lame, but is optimized for the common execution path. | |
1368 | * A wait_queue on the drv_data->busy could be used, but then the common | |
1369 | * execution path (pump_messages) would be required to call wake_up or | |
1370 | * friends on every SPI message. Do this instead */ | |
1371 | drv_data->run = QUEUE_STOPPED; | |
1372 | while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) { | |
1373 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1374 | msleep(10); | |
1375 | spin_lock_irqsave(&drv_data->lock, flags); | |
1376 | } | |
1377 | ||
1378 | if (!list_empty(&drv_data->queue) || drv_data->busy) | |
1379 | status = -EBUSY; | |
1380 | ||
1381 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1382 | ||
1383 | return status; | |
1384 | } | |
1385 | ||
1386 | static int destroy_queue(struct driver_data *drv_data) | |
1387 | { | |
1388 | int status; | |
1389 | ||
1390 | status = stop_queue(drv_data); | |
8d94cc50 SS |
1391 | /* we are unloading the module or failing to load (only two calls |
1392 | * to this routine), and neither call can handle a return value. | |
1393 | * However, destroy_workqueue calls flush_workqueue, and that will | |
1394 | * block until all work is done. If the reason that stop_queue | |
1395 | * timed out is that the work will never finish, then it does no | |
1396 | * good to call destroy_workqueue, so return anyway. */ | |
e0c9905e SS |
1397 | if (status != 0) |
1398 | return status; | |
1399 | ||
1400 | destroy_workqueue(drv_data->workqueue); | |
1401 | ||
1402 | return 0; | |
1403 | } | |
1404 | ||
d1e44d9c | 1405 | static int __init pxa2xx_spi_probe(struct platform_device *pdev) |
e0c9905e SS |
1406 | { |
1407 | struct device *dev = &pdev->dev; | |
1408 | struct pxa2xx_spi_master *platform_info; | |
1409 | struct spi_master *master; | |
cf43369d | 1410 | struct driver_data *drv_data = NULL; |
2f1a74e5 | 1411 | struct ssp_device *ssp; |
e0c9905e SS |
1412 | int status = 0; |
1413 | ||
1414 | platform_info = dev->platform_data; | |
1415 | ||
2f1a74e5 | 1416 | ssp = ssp_request(pdev->id, pdev->name); |
1417 | if (ssp == NULL) { | |
1418 | dev_err(&pdev->dev, "failed to request SSP%d\n", pdev->id); | |
e0c9905e SS |
1419 | return -ENODEV; |
1420 | } | |
1421 | ||
1422 | /* Allocate master with space for drv_data and null dma buffer */ | |
1423 | master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); | |
1424 | if (!master) { | |
1425 | dev_err(&pdev->dev, "can not alloc spi_master\n"); | |
2f1a74e5 | 1426 | ssp_free(ssp); |
e0c9905e SS |
1427 | return -ENOMEM; |
1428 | } | |
1429 | drv_data = spi_master_get_devdata(master); | |
1430 | drv_data->master = master; | |
1431 | drv_data->master_info = platform_info; | |
1432 | drv_data->pdev = pdev; | |
2f1a74e5 | 1433 | drv_data->ssp = ssp; |
e0c9905e SS |
1434 | |
1435 | master->bus_num = pdev->id; | |
1436 | master->num_chipselect = platform_info->num_chipselect; | |
1437 | master->cleanup = cleanup; | |
1438 | master->setup = setup; | |
1439 | master->transfer = transfer; | |
1440 | ||
2f1a74e5 | 1441 | drv_data->ssp_type = ssp->type; |
e0c9905e SS |
1442 | drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data + |
1443 | sizeof(struct driver_data)), 8); | |
1444 | ||
2f1a74e5 | 1445 | drv_data->ioaddr = ssp->mmio_base; |
1446 | drv_data->ssdr_physical = ssp->phys_base + SSDR; | |
1447 | if (ssp->type == PXA25x_SSP) { | |
e0c9905e SS |
1448 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; |
1449 | drv_data->dma_cr1 = 0; | |
1450 | drv_data->clear_sr = SSSR_ROR; | |
1451 | drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1452 | } else { | |
1453 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; | |
1454 | drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE; | |
1455 | drv_data->clear_sr = SSSR_ROR | SSSR_TINT; | |
1456 | drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1457 | } | |
1458 | ||
2f1a74e5 | 1459 | status = request_irq(ssp->irq, ssp_int, 0, dev->bus_id, drv_data); |
e0c9905e SS |
1460 | if (status < 0) { |
1461 | dev_err(&pdev->dev, "can not get IRQ\n"); | |
1462 | goto out_error_master_alloc; | |
1463 | } | |
1464 | ||
1465 | /* Setup DMA if requested */ | |
1466 | drv_data->tx_channel = -1; | |
1467 | drv_data->rx_channel = -1; | |
1468 | if (platform_info->enable_dma) { | |
1469 | ||
1470 | /* Get two DMA channels (rx and tx) */ | |
1471 | drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx", | |
1472 | DMA_PRIO_HIGH, | |
1473 | dma_handler, | |
1474 | drv_data); | |
1475 | if (drv_data->rx_channel < 0) { | |
1476 | dev_err(dev, "problem (%d) requesting rx channel\n", | |
1477 | drv_data->rx_channel); | |
1478 | status = -ENODEV; | |
1479 | goto out_error_irq_alloc; | |
1480 | } | |
1481 | drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx", | |
1482 | DMA_PRIO_MEDIUM, | |
1483 | dma_handler, | |
1484 | drv_data); | |
1485 | if (drv_data->tx_channel < 0) { | |
1486 | dev_err(dev, "problem (%d) requesting tx channel\n", | |
1487 | drv_data->tx_channel); | |
1488 | status = -ENODEV; | |
1489 | goto out_error_dma_alloc; | |
1490 | } | |
1491 | ||
2f1a74e5 | 1492 | DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel; |
1493 | DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel; | |
e0c9905e SS |
1494 | } |
1495 | ||
1496 | /* Enable SOC clock */ | |
2f1a74e5 | 1497 | clk_enable(ssp->clk); |
e0c9905e SS |
1498 | |
1499 | /* Load default SSP configuration */ | |
1500 | write_SSCR0(0, drv_data->ioaddr); | |
1501 | write_SSCR1(SSCR1_RxTresh(4) | SSCR1_TxTresh(12), drv_data->ioaddr); | |
1502 | write_SSCR0(SSCR0_SerClkDiv(2) | |
1503 | | SSCR0_Motorola | |
1504 | | SSCR0_DataSize(8), | |
1505 | drv_data->ioaddr); | |
1506 | if (drv_data->ssp_type != PXA25x_SSP) | |
1507 | write_SSTO(0, drv_data->ioaddr); | |
1508 | write_SSPSP(0, drv_data->ioaddr); | |
1509 | ||
1510 | /* Initial and start queue */ | |
1511 | status = init_queue(drv_data); | |
1512 | if (status != 0) { | |
1513 | dev_err(&pdev->dev, "problem initializing queue\n"); | |
1514 | goto out_error_clock_enabled; | |
1515 | } | |
1516 | status = start_queue(drv_data); | |
1517 | if (status != 0) { | |
1518 | dev_err(&pdev->dev, "problem starting queue\n"); | |
1519 | goto out_error_clock_enabled; | |
1520 | } | |
1521 | ||
1522 | /* Register with the SPI framework */ | |
1523 | platform_set_drvdata(pdev, drv_data); | |
1524 | status = spi_register_master(master); | |
1525 | if (status != 0) { | |
1526 | dev_err(&pdev->dev, "problem registering spi master\n"); | |
1527 | goto out_error_queue_alloc; | |
1528 | } | |
1529 | ||
1530 | return status; | |
1531 | ||
1532 | out_error_queue_alloc: | |
1533 | destroy_queue(drv_data); | |
1534 | ||
1535 | out_error_clock_enabled: | |
2f1a74e5 | 1536 | clk_disable(ssp->clk); |
e0c9905e SS |
1537 | |
1538 | out_error_dma_alloc: | |
1539 | if (drv_data->tx_channel != -1) | |
1540 | pxa_free_dma(drv_data->tx_channel); | |
1541 | if (drv_data->rx_channel != -1) | |
1542 | pxa_free_dma(drv_data->rx_channel); | |
1543 | ||
1544 | out_error_irq_alloc: | |
2f1a74e5 | 1545 | free_irq(ssp->irq, drv_data); |
e0c9905e SS |
1546 | |
1547 | out_error_master_alloc: | |
1548 | spi_master_put(master); | |
2f1a74e5 | 1549 | ssp_free(ssp); |
e0c9905e SS |
1550 | return status; |
1551 | } | |
1552 | ||
1553 | static int pxa2xx_spi_remove(struct platform_device *pdev) | |
1554 | { | |
1555 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
2f1a74e5 | 1556 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1557 | int status = 0; |
1558 | ||
1559 | if (!drv_data) | |
1560 | return 0; | |
1561 | ||
1562 | /* Remove the queue */ | |
1563 | status = destroy_queue(drv_data); | |
1564 | if (status != 0) | |
8d94cc50 SS |
1565 | /* the kernel does not check the return status of this |
1566 | * this routine (mod->exit, within the kernel). Therefore | |
1567 | * nothing is gained by returning from here, the module is | |
1568 | * going away regardless, and we should not leave any more | |
1569 | * resources allocated than necessary. We cannot free the | |
1570 | * message memory in drv_data->queue, but we can release the | |
1571 | * resources below. I think the kernel should honor -EBUSY | |
1572 | * returns but... */ | |
1573 | dev_err(&pdev->dev, "pxa2xx_spi_remove: workqueue will not " | |
1574 | "complete, message memory not freed\n"); | |
e0c9905e SS |
1575 | |
1576 | /* Disable the SSP at the peripheral and SOC level */ | |
1577 | write_SSCR0(0, drv_data->ioaddr); | |
2f1a74e5 | 1578 | clk_disable(ssp->clk); |
e0c9905e SS |
1579 | |
1580 | /* Release DMA */ | |
1581 | if (drv_data->master_info->enable_dma) { | |
2f1a74e5 | 1582 | DRCMR(ssp->drcmr_rx) = 0; |
1583 | DRCMR(ssp->drcmr_tx) = 0; | |
e0c9905e SS |
1584 | pxa_free_dma(drv_data->tx_channel); |
1585 | pxa_free_dma(drv_data->rx_channel); | |
1586 | } | |
1587 | ||
1588 | /* Release IRQ */ | |
2f1a74e5 | 1589 | free_irq(ssp->irq, drv_data); |
1590 | ||
1591 | /* Release SSP */ | |
1592 | ssp_free(ssp); | |
e0c9905e SS |
1593 | |
1594 | /* Disconnect from the SPI framework */ | |
1595 | spi_unregister_master(drv_data->master); | |
1596 | ||
1597 | /* Prevent double remove */ | |
1598 | platform_set_drvdata(pdev, NULL); | |
1599 | ||
1600 | return 0; | |
1601 | } | |
1602 | ||
1603 | static void pxa2xx_spi_shutdown(struct platform_device *pdev) | |
1604 | { | |
1605 | int status = 0; | |
1606 | ||
1607 | if ((status = pxa2xx_spi_remove(pdev)) != 0) | |
1608 | dev_err(&pdev->dev, "shutdown failed with %d\n", status); | |
1609 | } | |
1610 | ||
1611 | #ifdef CONFIG_PM | |
e0c9905e SS |
1612 | |
1613 | static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state) | |
1614 | { | |
1615 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
2f1a74e5 | 1616 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1617 | int status = 0; |
1618 | ||
e0c9905e SS |
1619 | status = stop_queue(drv_data); |
1620 | if (status != 0) | |
1621 | return status; | |
1622 | write_SSCR0(0, drv_data->ioaddr); | |
2f1a74e5 | 1623 | clk_disable(ssp->clk); |
e0c9905e SS |
1624 | |
1625 | return 0; | |
1626 | } | |
1627 | ||
1628 | static int pxa2xx_spi_resume(struct platform_device *pdev) | |
1629 | { | |
1630 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
2f1a74e5 | 1631 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1632 | int status = 0; |
1633 | ||
1634 | /* Enable the SSP clock */ | |
0cf942d7 | 1635 | clk_enable(ssp->clk); |
e0c9905e SS |
1636 | |
1637 | /* Start the queue running */ | |
1638 | status = start_queue(drv_data); | |
1639 | if (status != 0) { | |
1640 | dev_err(&pdev->dev, "problem starting queue (%d)\n", status); | |
1641 | return status; | |
1642 | } | |
1643 | ||
1644 | return 0; | |
1645 | } | |
1646 | #else | |
1647 | #define pxa2xx_spi_suspend NULL | |
1648 | #define pxa2xx_spi_resume NULL | |
1649 | #endif /* CONFIG_PM */ | |
1650 | ||
1651 | static struct platform_driver driver = { | |
1652 | .driver = { | |
1653 | .name = "pxa2xx-spi", | |
e0c9905e SS |
1654 | .owner = THIS_MODULE, |
1655 | }, | |
d1e44d9c | 1656 | .remove = pxa2xx_spi_remove, |
e0c9905e SS |
1657 | .shutdown = pxa2xx_spi_shutdown, |
1658 | .suspend = pxa2xx_spi_suspend, | |
1659 | .resume = pxa2xx_spi_resume, | |
1660 | }; | |
1661 | ||
1662 | static int __init pxa2xx_spi_init(void) | |
1663 | { | |
d1e44d9c | 1664 | return platform_driver_probe(&driver, pxa2xx_spi_probe); |
e0c9905e SS |
1665 | } |
1666 | module_init(pxa2xx_spi_init); | |
1667 | ||
1668 | static void __exit pxa2xx_spi_exit(void) | |
1669 | { | |
1670 | platform_driver_unregister(&driver); | |
1671 | } | |
1672 | module_exit(pxa2xx_spi_exit); |