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e0c9905e SS |
1 | /* |
2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
19 | #include <linux/init.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/device.h> | |
22 | #include <linux/ioport.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/dma-mapping.h> | |
27 | #include <linux/spi/spi.h> | |
28 | #include <linux/workqueue.h> | |
e0c9905e | 29 | #include <linux/delay.h> |
2f1a74e5 | 30 | #include <linux/clk.h> |
e0c9905e SS |
31 | |
32 | #include <asm/io.h> | |
33 | #include <asm/irq.h> | |
34 | #include <asm/hardware.h> | |
35 | #include <asm/delay.h> | |
36 | #include <asm/dma.h> | |
37 | ||
38 | #include <asm/arch/hardware.h> | |
39 | #include <asm/arch/pxa-regs.h> | |
0aea1fd5 | 40 | #include <asm/arch/regs-ssp.h> |
2f1a74e5 | 41 | #include <asm/arch/ssp.h> |
e0c9905e SS |
42 | #include <asm/arch/pxa2xx_spi.h> |
43 | ||
44 | MODULE_AUTHOR("Stephen Street"); | |
037cdafe | 45 | MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); |
e0c9905e | 46 | MODULE_LICENSE("GPL"); |
7e38c3c4 | 47 | MODULE_ALIAS("platform:pxa2xx-spi"); |
e0c9905e SS |
48 | |
49 | #define MAX_BUSES 3 | |
50 | ||
51 | #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR) | |
52 | #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK) | |
53 | #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0) | |
54 | ||
b97c74bd NF |
55 | /* |
56 | * for testing SSCR1 changes that require SSP restart, basically | |
57 | * everything except the service and interrupt enables, the pxa270 developer | |
58 | * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this | |
59 | * list, but the PXA255 dev man says all bits without really meaning the | |
60 | * service and interrupt enables | |
61 | */ | |
62 | #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ | |
8d94cc50 | 63 | | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ |
b97c74bd NF |
64 | | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ |
65 | | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ | |
66 | | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ | |
67 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
8d94cc50 | 68 | |
e0c9905e SS |
69 | #define DEFINE_SSP_REG(reg, off) \ |
70 | static inline u32 read_##reg(void *p) { return __raw_readl(p + (off)); } \ | |
71 | static inline void write_##reg(u32 v, void *p) { __raw_writel(v, p + (off)); } | |
72 | ||
73 | DEFINE_SSP_REG(SSCR0, 0x00) | |
74 | DEFINE_SSP_REG(SSCR1, 0x04) | |
75 | DEFINE_SSP_REG(SSSR, 0x08) | |
76 | DEFINE_SSP_REG(SSITR, 0x0c) | |
77 | DEFINE_SSP_REG(SSDR, 0x10) | |
78 | DEFINE_SSP_REG(SSTO, 0x28) | |
79 | DEFINE_SSP_REG(SSPSP, 0x2c) | |
80 | ||
81 | #define START_STATE ((void*)0) | |
82 | #define RUNNING_STATE ((void*)1) | |
83 | #define DONE_STATE ((void*)2) | |
84 | #define ERROR_STATE ((void*)-1) | |
85 | ||
86 | #define QUEUE_RUNNING 0 | |
87 | #define QUEUE_STOPPED 1 | |
88 | ||
89 | struct driver_data { | |
90 | /* Driver model hookup */ | |
91 | struct platform_device *pdev; | |
92 | ||
2f1a74e5 | 93 | /* SSP Info */ |
94 | struct ssp_device *ssp; | |
95 | ||
e0c9905e SS |
96 | /* SPI framework hookup */ |
97 | enum pxa_ssp_type ssp_type; | |
98 | struct spi_master *master; | |
99 | ||
100 | /* PXA hookup */ | |
101 | struct pxa2xx_spi_master *master_info; | |
102 | ||
103 | /* DMA setup stuff */ | |
104 | int rx_channel; | |
105 | int tx_channel; | |
106 | u32 *null_dma_buf; | |
107 | ||
108 | /* SSP register addresses */ | |
109 | void *ioaddr; | |
110 | u32 ssdr_physical; | |
111 | ||
112 | /* SSP masks*/ | |
113 | u32 dma_cr1; | |
114 | u32 int_cr1; | |
115 | u32 clear_sr; | |
116 | u32 mask_sr; | |
117 | ||
118 | /* Driver message queue */ | |
119 | struct workqueue_struct *workqueue; | |
120 | struct work_struct pump_messages; | |
121 | spinlock_t lock; | |
122 | struct list_head queue; | |
123 | int busy; | |
124 | int run; | |
125 | ||
126 | /* Message Transfer pump */ | |
127 | struct tasklet_struct pump_transfers; | |
128 | ||
129 | /* Current message transfer state info */ | |
130 | struct spi_message* cur_msg; | |
131 | struct spi_transfer* cur_transfer; | |
132 | struct chip_data *cur_chip; | |
133 | size_t len; | |
134 | void *tx; | |
135 | void *tx_end; | |
136 | void *rx; | |
137 | void *rx_end; | |
138 | int dma_mapped; | |
139 | dma_addr_t rx_dma; | |
140 | dma_addr_t tx_dma; | |
141 | size_t rx_map_len; | |
142 | size_t tx_map_len; | |
9708c121 SS |
143 | u8 n_bytes; |
144 | u32 dma_width; | |
e0c9905e | 145 | int cs_change; |
8d94cc50 SS |
146 | int (*write)(struct driver_data *drv_data); |
147 | int (*read)(struct driver_data *drv_data); | |
e0c9905e SS |
148 | irqreturn_t (*transfer_handler)(struct driver_data *drv_data); |
149 | void (*cs_control)(u32 command); | |
150 | }; | |
151 | ||
152 | struct chip_data { | |
153 | u32 cr0; | |
154 | u32 cr1; | |
e0c9905e SS |
155 | u32 psp; |
156 | u32 timeout; | |
157 | u8 n_bytes; | |
158 | u32 dma_width; | |
159 | u32 dma_burst_size; | |
160 | u32 threshold; | |
161 | u32 dma_threshold; | |
162 | u8 enable_dma; | |
9708c121 SS |
163 | u8 bits_per_word; |
164 | u32 speed_hz; | |
8d94cc50 SS |
165 | int (*write)(struct driver_data *drv_data); |
166 | int (*read)(struct driver_data *drv_data); | |
e0c9905e SS |
167 | void (*cs_control)(u32 command); |
168 | }; | |
169 | ||
6d5aefb8 | 170 | static void pump_messages(struct work_struct *work); |
e0c9905e SS |
171 | |
172 | static int flush(struct driver_data *drv_data) | |
173 | { | |
174 | unsigned long limit = loops_per_jiffy << 1; | |
175 | ||
176 | void *reg = drv_data->ioaddr; | |
177 | ||
178 | do { | |
179 | while (read_SSSR(reg) & SSSR_RNE) { | |
180 | read_SSDR(reg); | |
181 | } | |
182 | } while ((read_SSSR(reg) & SSSR_BSY) && limit--); | |
183 | write_SSSR(SSSR_ROR, reg); | |
184 | ||
185 | return limit; | |
186 | } | |
187 | ||
e0c9905e SS |
188 | static void null_cs_control(u32 command) |
189 | { | |
190 | } | |
191 | ||
8d94cc50 | 192 | static int null_writer(struct driver_data *drv_data) |
e0c9905e SS |
193 | { |
194 | void *reg = drv_data->ioaddr; | |
9708c121 | 195 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 196 | |
8d94cc50 SS |
197 | if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00) |
198 | || (drv_data->tx == drv_data->tx_end)) | |
199 | return 0; | |
200 | ||
201 | write_SSDR(0, reg); | |
202 | drv_data->tx += n_bytes; | |
203 | ||
204 | return 1; | |
e0c9905e SS |
205 | } |
206 | ||
8d94cc50 | 207 | static int null_reader(struct driver_data *drv_data) |
e0c9905e SS |
208 | { |
209 | void *reg = drv_data->ioaddr; | |
9708c121 | 210 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e SS |
211 | |
212 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 213 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
214 | read_SSDR(reg); |
215 | drv_data->rx += n_bytes; | |
216 | } | |
8d94cc50 SS |
217 | |
218 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
219 | } |
220 | ||
8d94cc50 | 221 | static int u8_writer(struct driver_data *drv_data) |
e0c9905e SS |
222 | { |
223 | void *reg = drv_data->ioaddr; | |
224 | ||
8d94cc50 SS |
225 | if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00) |
226 | || (drv_data->tx == drv_data->tx_end)) | |
227 | return 0; | |
228 | ||
229 | write_SSDR(*(u8 *)(drv_data->tx), reg); | |
230 | ++drv_data->tx; | |
231 | ||
232 | return 1; | |
e0c9905e SS |
233 | } |
234 | ||
8d94cc50 | 235 | static int u8_reader(struct driver_data *drv_data) |
e0c9905e SS |
236 | { |
237 | void *reg = drv_data->ioaddr; | |
238 | ||
239 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 240 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
241 | *(u8 *)(drv_data->rx) = read_SSDR(reg); |
242 | ++drv_data->rx; | |
243 | } | |
8d94cc50 SS |
244 | |
245 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
246 | } |
247 | ||
8d94cc50 | 248 | static int u16_writer(struct driver_data *drv_data) |
e0c9905e SS |
249 | { |
250 | void *reg = drv_data->ioaddr; | |
251 | ||
8d94cc50 SS |
252 | if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00) |
253 | || (drv_data->tx == drv_data->tx_end)) | |
254 | return 0; | |
255 | ||
256 | write_SSDR(*(u16 *)(drv_data->tx), reg); | |
257 | drv_data->tx += 2; | |
258 | ||
259 | return 1; | |
e0c9905e SS |
260 | } |
261 | ||
8d94cc50 | 262 | static int u16_reader(struct driver_data *drv_data) |
e0c9905e SS |
263 | { |
264 | void *reg = drv_data->ioaddr; | |
265 | ||
266 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 267 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
268 | *(u16 *)(drv_data->rx) = read_SSDR(reg); |
269 | drv_data->rx += 2; | |
270 | } | |
8d94cc50 SS |
271 | |
272 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e | 273 | } |
8d94cc50 SS |
274 | |
275 | static int u32_writer(struct driver_data *drv_data) | |
e0c9905e SS |
276 | { |
277 | void *reg = drv_data->ioaddr; | |
278 | ||
8d94cc50 SS |
279 | if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00) |
280 | || (drv_data->tx == drv_data->tx_end)) | |
281 | return 0; | |
282 | ||
283 | write_SSDR(*(u32 *)(drv_data->tx), reg); | |
284 | drv_data->tx += 4; | |
285 | ||
286 | return 1; | |
e0c9905e SS |
287 | } |
288 | ||
8d94cc50 | 289 | static int u32_reader(struct driver_data *drv_data) |
e0c9905e SS |
290 | { |
291 | void *reg = drv_data->ioaddr; | |
292 | ||
293 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 294 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
295 | *(u32 *)(drv_data->rx) = read_SSDR(reg); |
296 | drv_data->rx += 4; | |
297 | } | |
8d94cc50 SS |
298 | |
299 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
300 | } |
301 | ||
302 | static void *next_transfer(struct driver_data *drv_data) | |
303 | { | |
304 | struct spi_message *msg = drv_data->cur_msg; | |
305 | struct spi_transfer *trans = drv_data->cur_transfer; | |
306 | ||
307 | /* Move to next transfer */ | |
308 | if (trans->transfer_list.next != &msg->transfers) { | |
309 | drv_data->cur_transfer = | |
310 | list_entry(trans->transfer_list.next, | |
311 | struct spi_transfer, | |
312 | transfer_list); | |
313 | return RUNNING_STATE; | |
314 | } else | |
315 | return DONE_STATE; | |
316 | } | |
317 | ||
318 | static int map_dma_buffers(struct driver_data *drv_data) | |
319 | { | |
320 | struct spi_message *msg = drv_data->cur_msg; | |
321 | struct device *dev = &msg->spi->dev; | |
322 | ||
323 | if (!drv_data->cur_chip->enable_dma) | |
324 | return 0; | |
325 | ||
326 | if (msg->is_dma_mapped) | |
327 | return drv_data->rx_dma && drv_data->tx_dma; | |
328 | ||
329 | if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx)) | |
330 | return 0; | |
331 | ||
332 | /* Modify setup if rx buffer is null */ | |
333 | if (drv_data->rx == NULL) { | |
334 | *drv_data->null_dma_buf = 0; | |
335 | drv_data->rx = drv_data->null_dma_buf; | |
336 | drv_data->rx_map_len = 4; | |
337 | } else | |
338 | drv_data->rx_map_len = drv_data->len; | |
339 | ||
340 | ||
341 | /* Modify setup if tx buffer is null */ | |
342 | if (drv_data->tx == NULL) { | |
343 | *drv_data->null_dma_buf = 0; | |
344 | drv_data->tx = drv_data->null_dma_buf; | |
345 | drv_data->tx_map_len = 4; | |
346 | } else | |
347 | drv_data->tx_map_len = drv_data->len; | |
348 | ||
349 | /* Stream map the rx buffer */ | |
350 | drv_data->rx_dma = dma_map_single(dev, drv_data->rx, | |
351 | drv_data->rx_map_len, | |
352 | DMA_FROM_DEVICE); | |
353 | if (dma_mapping_error(drv_data->rx_dma)) | |
354 | return 0; | |
355 | ||
356 | /* Stream map the tx buffer */ | |
357 | drv_data->tx_dma = dma_map_single(dev, drv_data->tx, | |
358 | drv_data->tx_map_len, | |
359 | DMA_TO_DEVICE); | |
360 | ||
361 | if (dma_mapping_error(drv_data->tx_dma)) { | |
362 | dma_unmap_single(dev, drv_data->rx_dma, | |
363 | drv_data->rx_map_len, DMA_FROM_DEVICE); | |
364 | return 0; | |
365 | } | |
366 | ||
367 | return 1; | |
368 | } | |
369 | ||
370 | static void unmap_dma_buffers(struct driver_data *drv_data) | |
371 | { | |
372 | struct device *dev; | |
373 | ||
374 | if (!drv_data->dma_mapped) | |
375 | return; | |
376 | ||
377 | if (!drv_data->cur_msg->is_dma_mapped) { | |
378 | dev = &drv_data->cur_msg->spi->dev; | |
379 | dma_unmap_single(dev, drv_data->rx_dma, | |
380 | drv_data->rx_map_len, DMA_FROM_DEVICE); | |
381 | dma_unmap_single(dev, drv_data->tx_dma, | |
382 | drv_data->tx_map_len, DMA_TO_DEVICE); | |
383 | } | |
384 | ||
385 | drv_data->dma_mapped = 0; | |
386 | } | |
387 | ||
388 | /* caller already set message->status; dma and pio irqs are blocked */ | |
5daa3ba0 | 389 | static void giveback(struct driver_data *drv_data) |
e0c9905e SS |
390 | { |
391 | struct spi_transfer* last_transfer; | |
5daa3ba0 SS |
392 | unsigned long flags; |
393 | struct spi_message *msg; | |
e0c9905e | 394 | |
5daa3ba0 SS |
395 | spin_lock_irqsave(&drv_data->lock, flags); |
396 | msg = drv_data->cur_msg; | |
397 | drv_data->cur_msg = NULL; | |
398 | drv_data->cur_transfer = NULL; | |
399 | drv_data->cur_chip = NULL; | |
400 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
401 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
402 | ||
403 | last_transfer = list_entry(msg->transfers.prev, | |
e0c9905e SS |
404 | struct spi_transfer, |
405 | transfer_list); | |
406 | ||
407 | if (!last_transfer->cs_change) | |
408 | drv_data->cs_control(PXA2XX_CS_DEASSERT); | |
409 | ||
5daa3ba0 SS |
410 | msg->state = NULL; |
411 | if (msg->complete) | |
412 | msg->complete(msg->context); | |
e0c9905e SS |
413 | } |
414 | ||
415 | static int wait_ssp_rx_stall(void *ioaddr) | |
416 | { | |
417 | unsigned long limit = loops_per_jiffy << 1; | |
418 | ||
419 | while ((read_SSSR(ioaddr) & SSSR_BSY) && limit--) | |
420 | cpu_relax(); | |
421 | ||
422 | return limit; | |
423 | } | |
424 | ||
425 | static int wait_dma_channel_stop(int channel) | |
426 | { | |
427 | unsigned long limit = loops_per_jiffy << 1; | |
428 | ||
429 | while (!(DCSR(channel) & DCSR_STOPSTATE) && limit--) | |
430 | cpu_relax(); | |
431 | ||
432 | return limit; | |
433 | } | |
434 | ||
8d94cc50 | 435 | void dma_error_stop(struct driver_data *drv_data, const char *msg) |
e0c9905e | 436 | { |
e0c9905e | 437 | void *reg = drv_data->ioaddr; |
e0c9905e | 438 | |
8d94cc50 SS |
439 | /* Stop and reset */ |
440 | DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; | |
441 | DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; | |
442 | write_SSSR(drv_data->clear_sr, reg); | |
443 | write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); | |
444 | if (drv_data->ssp_type != PXA25x_SSP) | |
445 | write_SSTO(0, reg); | |
446 | flush(drv_data); | |
447 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | |
e0c9905e | 448 | |
8d94cc50 | 449 | unmap_dma_buffers(drv_data); |
e0c9905e | 450 | |
8d94cc50 | 451 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 452 | |
8d94cc50 SS |
453 | drv_data->cur_msg->state = ERROR_STATE; |
454 | tasklet_schedule(&drv_data->pump_transfers); | |
455 | } | |
456 | ||
457 | static void dma_transfer_complete(struct driver_data *drv_data) | |
458 | { | |
459 | void *reg = drv_data->ioaddr; | |
460 | struct spi_message *msg = drv_data->cur_msg; | |
461 | ||
462 | /* Clear and disable interrupts on SSP and DMA channels*/ | |
463 | write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); | |
464 | write_SSSR(drv_data->clear_sr, reg); | |
465 | DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; | |
466 | DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; | |
467 | ||
468 | if (wait_dma_channel_stop(drv_data->rx_channel) == 0) | |
469 | dev_err(&drv_data->pdev->dev, | |
470 | "dma_handler: dma rx channel stop failed\n"); | |
471 | ||
472 | if (wait_ssp_rx_stall(drv_data->ioaddr) == 0) | |
473 | dev_err(&drv_data->pdev->dev, | |
474 | "dma_transfer: ssp rx stall failed\n"); | |
475 | ||
476 | unmap_dma_buffers(drv_data); | |
477 | ||
478 | /* update the buffer pointer for the amount completed in dma */ | |
479 | drv_data->rx += drv_data->len - | |
480 | (DCMD(drv_data->rx_channel) & DCMD_LENGTH); | |
481 | ||
482 | /* read trailing data from fifo, it does not matter how many | |
483 | * bytes are in the fifo just read until buffer is full | |
484 | * or fifo is empty, which ever occurs first */ | |
485 | drv_data->read(drv_data); | |
486 | ||
487 | /* return count of what was actually read */ | |
488 | msg->actual_length += drv_data->len - | |
489 | (drv_data->rx_end - drv_data->rx); | |
490 | ||
491 | /* Release chip select if requested, transfer delays are | |
492 | * handled in pump_transfers */ | |
493 | if (drv_data->cs_change) | |
494 | drv_data->cs_control(PXA2XX_CS_DEASSERT); | |
495 | ||
496 | /* Move to next transfer */ | |
497 | msg->state = next_transfer(drv_data); | |
498 | ||
499 | /* Schedule transfer tasklet */ | |
500 | tasklet_schedule(&drv_data->pump_transfers); | |
501 | } | |
502 | ||
503 | static void dma_handler(int channel, void *data) | |
504 | { | |
505 | struct driver_data *drv_data = data; | |
506 | u32 irq_status = DCSR(channel) & DMA_INT_MASK; | |
507 | ||
508 | if (irq_status & DCSR_BUSERR) { | |
e0c9905e SS |
509 | |
510 | if (channel == drv_data->tx_channel) | |
8d94cc50 SS |
511 | dma_error_stop(drv_data, |
512 | "dma_handler: " | |
513 | "bad bus address on tx channel"); | |
e0c9905e | 514 | else |
8d94cc50 SS |
515 | dma_error_stop(drv_data, |
516 | "dma_handler: " | |
517 | "bad bus address on rx channel"); | |
518 | return; | |
e0c9905e SS |
519 | } |
520 | ||
521 | /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */ | |
8d94cc50 SS |
522 | if ((channel == drv_data->tx_channel) |
523 | && (irq_status & DCSR_ENDINTR) | |
524 | && (drv_data->ssp_type == PXA25x_SSP)) { | |
e0c9905e SS |
525 | |
526 | /* Wait for rx to stall */ | |
527 | if (wait_ssp_rx_stall(drv_data->ioaddr) == 0) | |
528 | dev_err(&drv_data->pdev->dev, | |
529 | "dma_handler: ssp rx stall failed\n"); | |
530 | ||
8d94cc50 SS |
531 | /* finish this transfer, start the next */ |
532 | dma_transfer_complete(drv_data); | |
e0c9905e SS |
533 | } |
534 | } | |
535 | ||
536 | static irqreturn_t dma_transfer(struct driver_data *drv_data) | |
537 | { | |
538 | u32 irq_status; | |
e0c9905e SS |
539 | void *reg = drv_data->ioaddr; |
540 | ||
541 | irq_status = read_SSSR(reg) & drv_data->mask_sr; | |
542 | if (irq_status & SSSR_ROR) { | |
8d94cc50 | 543 | dma_error_stop(drv_data, "dma_transfer: fifo overrun"); |
e0c9905e SS |
544 | return IRQ_HANDLED; |
545 | } | |
546 | ||
547 | /* Check for false positive timeout */ | |
8d94cc50 SS |
548 | if ((irq_status & SSSR_TINT) |
549 | && (DCSR(drv_data->tx_channel) & DCSR_RUN)) { | |
e0c9905e SS |
550 | write_SSSR(SSSR_TINT, reg); |
551 | return IRQ_HANDLED; | |
552 | } | |
553 | ||
554 | if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) { | |
555 | ||
8d94cc50 SS |
556 | /* Clear and disable timeout interrupt, do the rest in |
557 | * dma_transfer_complete */ | |
e0c9905e SS |
558 | if (drv_data->ssp_type != PXA25x_SSP) |
559 | write_SSTO(0, reg); | |
e0c9905e | 560 | |
8d94cc50 SS |
561 | /* finish this transfer, start the next */ |
562 | dma_transfer_complete(drv_data); | |
e0c9905e SS |
563 | |
564 | return IRQ_HANDLED; | |
565 | } | |
566 | ||
567 | /* Opps problem detected */ | |
568 | return IRQ_NONE; | |
569 | } | |
570 | ||
8d94cc50 | 571 | static void int_error_stop(struct driver_data *drv_data, const char* msg) |
e0c9905e | 572 | { |
e0c9905e | 573 | void *reg = drv_data->ioaddr; |
e0c9905e | 574 | |
8d94cc50 SS |
575 | /* Stop and reset SSP */ |
576 | write_SSSR(drv_data->clear_sr, reg); | |
577 | write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); | |
578 | if (drv_data->ssp_type != PXA25x_SSP) | |
579 | write_SSTO(0, reg); | |
580 | flush(drv_data); | |
581 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | |
e0c9905e | 582 | |
8d94cc50 | 583 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 584 | |
8d94cc50 SS |
585 | drv_data->cur_msg->state = ERROR_STATE; |
586 | tasklet_schedule(&drv_data->pump_transfers); | |
587 | } | |
5daa3ba0 | 588 | |
8d94cc50 SS |
589 | static void int_transfer_complete(struct driver_data *drv_data) |
590 | { | |
591 | void *reg = drv_data->ioaddr; | |
e0c9905e | 592 | |
8d94cc50 SS |
593 | /* Stop SSP */ |
594 | write_SSSR(drv_data->clear_sr, reg); | |
595 | write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); | |
596 | if (drv_data->ssp_type != PXA25x_SSP) | |
597 | write_SSTO(0, reg); | |
e0c9905e | 598 | |
8d94cc50 SS |
599 | /* Update total byte transfered return count actual bytes read */ |
600 | drv_data->cur_msg->actual_length += drv_data->len - | |
601 | (drv_data->rx_end - drv_data->rx); | |
e0c9905e | 602 | |
8d94cc50 SS |
603 | /* Release chip select if requested, transfer delays are |
604 | * handled in pump_transfers */ | |
605 | if (drv_data->cs_change) | |
606 | drv_data->cs_control(PXA2XX_CS_DEASSERT); | |
e0c9905e | 607 | |
8d94cc50 SS |
608 | /* Move to next transfer */ |
609 | drv_data->cur_msg->state = next_transfer(drv_data); | |
e0c9905e | 610 | |
8d94cc50 SS |
611 | /* Schedule transfer tasklet */ |
612 | tasklet_schedule(&drv_data->pump_transfers); | |
613 | } | |
e0c9905e | 614 | |
8d94cc50 SS |
615 | static irqreturn_t interrupt_transfer(struct driver_data *drv_data) |
616 | { | |
617 | void *reg = drv_data->ioaddr; | |
e0c9905e | 618 | |
8d94cc50 SS |
619 | u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ? |
620 | drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; | |
e0c9905e | 621 | |
8d94cc50 | 622 | u32 irq_status = read_SSSR(reg) & irq_mask; |
e0c9905e | 623 | |
8d94cc50 SS |
624 | if (irq_status & SSSR_ROR) { |
625 | int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); | |
626 | return IRQ_HANDLED; | |
627 | } | |
e0c9905e | 628 | |
8d94cc50 SS |
629 | if (irq_status & SSSR_TINT) { |
630 | write_SSSR(SSSR_TINT, reg); | |
631 | if (drv_data->read(drv_data)) { | |
632 | int_transfer_complete(drv_data); | |
633 | return IRQ_HANDLED; | |
634 | } | |
635 | } | |
e0c9905e | 636 | |
8d94cc50 SS |
637 | /* Drain rx fifo, Fill tx fifo and prevent overruns */ |
638 | do { | |
639 | if (drv_data->read(drv_data)) { | |
640 | int_transfer_complete(drv_data); | |
641 | return IRQ_HANDLED; | |
642 | } | |
643 | } while (drv_data->write(drv_data)); | |
e0c9905e | 644 | |
8d94cc50 SS |
645 | if (drv_data->read(drv_data)) { |
646 | int_transfer_complete(drv_data); | |
647 | return IRQ_HANDLED; | |
648 | } | |
e0c9905e | 649 | |
8d94cc50 SS |
650 | if (drv_data->tx == drv_data->tx_end) { |
651 | write_SSCR1(read_SSCR1(reg) & ~SSCR1_TIE, reg); | |
652 | /* PXA25x_SSP has no timeout, read trailing bytes */ | |
653 | if (drv_data->ssp_type == PXA25x_SSP) { | |
654 | if (!wait_ssp_rx_stall(reg)) | |
655 | { | |
656 | int_error_stop(drv_data, "interrupt_transfer: " | |
657 | "rx stall failed"); | |
658 | return IRQ_HANDLED; | |
659 | } | |
660 | if (!drv_data->read(drv_data)) | |
661 | { | |
662 | int_error_stop(drv_data, | |
663 | "interrupt_transfer: " | |
664 | "trailing byte read failed"); | |
665 | return IRQ_HANDLED; | |
666 | } | |
667 | int_transfer_complete(drv_data); | |
e0c9905e | 668 | } |
e0c9905e SS |
669 | } |
670 | ||
5daa3ba0 SS |
671 | /* We did something */ |
672 | return IRQ_HANDLED; | |
e0c9905e SS |
673 | } |
674 | ||
7d12e780 | 675 | static irqreturn_t ssp_int(int irq, void *dev_id) |
e0c9905e | 676 | { |
c7bec5ab | 677 | struct driver_data *drv_data = dev_id; |
5daa3ba0 | 678 | void *reg = drv_data->ioaddr; |
e0c9905e SS |
679 | |
680 | if (!drv_data->cur_msg) { | |
5daa3ba0 SS |
681 | |
682 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | |
683 | write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); | |
684 | if (drv_data->ssp_type != PXA25x_SSP) | |
685 | write_SSTO(0, reg); | |
686 | write_SSSR(drv_data->clear_sr, reg); | |
687 | ||
e0c9905e | 688 | dev_err(&drv_data->pdev->dev, "bad message state " |
8d94cc50 | 689 | "in interrupt handler\n"); |
5daa3ba0 | 690 | |
e0c9905e SS |
691 | /* Never fail */ |
692 | return IRQ_HANDLED; | |
693 | } | |
694 | ||
695 | return drv_data->transfer_handler(drv_data); | |
696 | } | |
697 | ||
8d94cc50 SS |
698 | int set_dma_burst_and_threshold(struct chip_data *chip, struct spi_device *spi, |
699 | u8 bits_per_word, u32 *burst_code, | |
700 | u32 *threshold) | |
701 | { | |
702 | struct pxa2xx_spi_chip *chip_info = | |
703 | (struct pxa2xx_spi_chip *)spi->controller_data; | |
704 | int bytes_per_word; | |
705 | int burst_bytes; | |
706 | int thresh_words; | |
707 | int req_burst_size; | |
708 | int retval = 0; | |
709 | ||
710 | /* Set the threshold (in registers) to equal the same amount of data | |
711 | * as represented by burst size (in bytes). The computation below | |
712 | * is (burst_size rounded up to nearest 8 byte, word or long word) | |
713 | * divided by (bytes/register); the tx threshold is the inverse of | |
714 | * the rx, so that there will always be enough data in the rx fifo | |
715 | * to satisfy a burst, and there will always be enough space in the | |
716 | * tx fifo to accept a burst (a tx burst will overwrite the fifo if | |
717 | * there is not enough space), there must always remain enough empty | |
718 | * space in the rx fifo for any data loaded to the tx fifo. | |
719 | * Whenever burst_size (in bytes) equals bits/word, the fifo threshold | |
720 | * will be 8, or half the fifo; | |
721 | * The threshold can only be set to 2, 4 or 8, but not 16, because | |
722 | * to burst 16 to the tx fifo, the fifo would have to be empty; | |
723 | * however, the minimum fifo trigger level is 1, and the tx will | |
724 | * request service when the fifo is at this level, with only 15 spaces. | |
725 | */ | |
726 | ||
727 | /* find bytes/word */ | |
728 | if (bits_per_word <= 8) | |
729 | bytes_per_word = 1; | |
730 | else if (bits_per_word <= 16) | |
731 | bytes_per_word = 2; | |
732 | else | |
733 | bytes_per_word = 4; | |
734 | ||
735 | /* use struct pxa2xx_spi_chip->dma_burst_size if available */ | |
736 | if (chip_info) | |
737 | req_burst_size = chip_info->dma_burst_size; | |
738 | else { | |
739 | switch (chip->dma_burst_size) { | |
740 | default: | |
741 | /* if the default burst size is not set, | |
742 | * do it now */ | |
743 | chip->dma_burst_size = DCMD_BURST8; | |
744 | case DCMD_BURST8: | |
745 | req_burst_size = 8; | |
746 | break; | |
747 | case DCMD_BURST16: | |
748 | req_burst_size = 16; | |
749 | break; | |
750 | case DCMD_BURST32: | |
751 | req_burst_size = 32; | |
752 | break; | |
753 | } | |
754 | } | |
755 | if (req_burst_size <= 8) { | |
756 | *burst_code = DCMD_BURST8; | |
757 | burst_bytes = 8; | |
758 | } else if (req_burst_size <= 16) { | |
759 | if (bytes_per_word == 1) { | |
760 | /* don't burst more than 1/2 the fifo */ | |
761 | *burst_code = DCMD_BURST8; | |
762 | burst_bytes = 8; | |
763 | retval = 1; | |
764 | } else { | |
765 | *burst_code = DCMD_BURST16; | |
766 | burst_bytes = 16; | |
767 | } | |
768 | } else { | |
769 | if (bytes_per_word == 1) { | |
770 | /* don't burst more than 1/2 the fifo */ | |
771 | *burst_code = DCMD_BURST8; | |
772 | burst_bytes = 8; | |
773 | retval = 1; | |
774 | } else if (bytes_per_word == 2) { | |
775 | /* don't burst more than 1/2 the fifo */ | |
776 | *burst_code = DCMD_BURST16; | |
777 | burst_bytes = 16; | |
778 | retval = 1; | |
779 | } else { | |
780 | *burst_code = DCMD_BURST32; | |
781 | burst_bytes = 32; | |
782 | } | |
783 | } | |
784 | ||
785 | thresh_words = burst_bytes / bytes_per_word; | |
786 | ||
787 | /* thresh_words will be between 2 and 8 */ | |
788 | *threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT) | |
789 | | (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT); | |
790 | ||
791 | return retval; | |
792 | } | |
793 | ||
2f1a74e5 | 794 | static unsigned int ssp_get_clk_div(struct ssp_device *ssp, int rate) |
795 | { | |
796 | unsigned long ssp_clk = clk_get_rate(ssp->clk); | |
797 | ||
798 | if (ssp->type == PXA25x_SSP) | |
799 | return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8; | |
800 | else | |
801 | return ((ssp_clk / rate - 1) & 0xfff) << 8; | |
802 | } | |
803 | ||
e0c9905e SS |
804 | static void pump_transfers(unsigned long data) |
805 | { | |
806 | struct driver_data *drv_data = (struct driver_data *)data; | |
807 | struct spi_message *message = NULL; | |
808 | struct spi_transfer *transfer = NULL; | |
809 | struct spi_transfer *previous = NULL; | |
810 | struct chip_data *chip = NULL; | |
2f1a74e5 | 811 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e | 812 | void *reg = drv_data->ioaddr; |
9708c121 SS |
813 | u32 clk_div = 0; |
814 | u8 bits = 0; | |
815 | u32 speed = 0; | |
816 | u32 cr0; | |
8d94cc50 SS |
817 | u32 cr1; |
818 | u32 dma_thresh = drv_data->cur_chip->dma_threshold; | |
819 | u32 dma_burst = drv_data->cur_chip->dma_burst_size; | |
e0c9905e SS |
820 | |
821 | /* Get current state information */ | |
822 | message = drv_data->cur_msg; | |
823 | transfer = drv_data->cur_transfer; | |
824 | chip = drv_data->cur_chip; | |
825 | ||
826 | /* Handle for abort */ | |
827 | if (message->state == ERROR_STATE) { | |
828 | message->status = -EIO; | |
5daa3ba0 | 829 | giveback(drv_data); |
e0c9905e SS |
830 | return; |
831 | } | |
832 | ||
833 | /* Handle end of message */ | |
834 | if (message->state == DONE_STATE) { | |
835 | message->status = 0; | |
5daa3ba0 | 836 | giveback(drv_data); |
e0c9905e SS |
837 | return; |
838 | } | |
839 | ||
840 | /* Delay if requested at end of transfer*/ | |
841 | if (message->state == RUNNING_STATE) { | |
842 | previous = list_entry(transfer->transfer_list.prev, | |
843 | struct spi_transfer, | |
844 | transfer_list); | |
845 | if (previous->delay_usecs) | |
846 | udelay(previous->delay_usecs); | |
847 | } | |
848 | ||
8d94cc50 SS |
849 | /* Check transfer length */ |
850 | if (transfer->len > 8191) | |
851 | { | |
852 | dev_warn(&drv_data->pdev->dev, "pump_transfers: transfer " | |
853 | "length greater than 8191\n"); | |
854 | message->status = -EINVAL; | |
855 | giveback(drv_data); | |
856 | return; | |
857 | } | |
858 | ||
e0c9905e SS |
859 | /* Setup the transfer state based on the type of transfer */ |
860 | if (flush(drv_data) == 0) { | |
861 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); | |
862 | message->status = -EIO; | |
5daa3ba0 | 863 | giveback(drv_data); |
e0c9905e SS |
864 | return; |
865 | } | |
9708c121 SS |
866 | drv_data->n_bytes = chip->n_bytes; |
867 | drv_data->dma_width = chip->dma_width; | |
e0c9905e SS |
868 | drv_data->cs_control = chip->cs_control; |
869 | drv_data->tx = (void *)transfer->tx_buf; | |
870 | drv_data->tx_end = drv_data->tx + transfer->len; | |
871 | drv_data->rx = transfer->rx_buf; | |
872 | drv_data->rx_end = drv_data->rx + transfer->len; | |
873 | drv_data->rx_dma = transfer->rx_dma; | |
874 | drv_data->tx_dma = transfer->tx_dma; | |
8d94cc50 | 875 | drv_data->len = transfer->len & DCMD_LENGTH; |
e0c9905e SS |
876 | drv_data->write = drv_data->tx ? chip->write : null_writer; |
877 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
878 | drv_data->cs_change = transfer->cs_change; | |
9708c121 SS |
879 | |
880 | /* Change speed and bit per word on a per transfer */ | |
8d94cc50 | 881 | cr0 = chip->cr0; |
9708c121 SS |
882 | if (transfer->speed_hz || transfer->bits_per_word) { |
883 | ||
9708c121 SS |
884 | bits = chip->bits_per_word; |
885 | speed = chip->speed_hz; | |
886 | ||
887 | if (transfer->speed_hz) | |
888 | speed = transfer->speed_hz; | |
889 | ||
890 | if (transfer->bits_per_word) | |
891 | bits = transfer->bits_per_word; | |
892 | ||
2f1a74e5 | 893 | clk_div = ssp_get_clk_div(ssp, speed); |
9708c121 SS |
894 | |
895 | if (bits <= 8) { | |
896 | drv_data->n_bytes = 1; | |
897 | drv_data->dma_width = DCMD_WIDTH1; | |
898 | drv_data->read = drv_data->read != null_reader ? | |
899 | u8_reader : null_reader; | |
900 | drv_data->write = drv_data->write != null_writer ? | |
901 | u8_writer : null_writer; | |
902 | } else if (bits <= 16) { | |
903 | drv_data->n_bytes = 2; | |
904 | drv_data->dma_width = DCMD_WIDTH2; | |
905 | drv_data->read = drv_data->read != null_reader ? | |
906 | u16_reader : null_reader; | |
907 | drv_data->write = drv_data->write != null_writer ? | |
908 | u16_writer : null_writer; | |
909 | } else if (bits <= 32) { | |
910 | drv_data->n_bytes = 4; | |
911 | drv_data->dma_width = DCMD_WIDTH4; | |
912 | drv_data->read = drv_data->read != null_reader ? | |
913 | u32_reader : null_reader; | |
914 | drv_data->write = drv_data->write != null_writer ? | |
915 | u32_writer : null_writer; | |
916 | } | |
8d94cc50 SS |
917 | /* if bits/word is changed in dma mode, then must check the |
918 | * thresholds and burst also */ | |
919 | if (chip->enable_dma) { | |
920 | if (set_dma_burst_and_threshold(chip, message->spi, | |
921 | bits, &dma_burst, | |
922 | &dma_thresh)) | |
923 | if (printk_ratelimit()) | |
924 | dev_warn(&message->spi->dev, | |
925 | "pump_transfer: " | |
926 | "DMA burst size reduced to " | |
927 | "match bits_per_word\n"); | |
928 | } | |
9708c121 SS |
929 | |
930 | cr0 = clk_div | |
931 | | SSCR0_Motorola | |
5daa3ba0 | 932 | | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) |
9708c121 SS |
933 | | SSCR0_SSE |
934 | | (bits > 16 ? SSCR0_EDSS : 0); | |
9708c121 SS |
935 | } |
936 | ||
e0c9905e SS |
937 | message->state = RUNNING_STATE; |
938 | ||
939 | /* Try to map dma buffer and do a dma transfer if successful */ | |
940 | if ((drv_data->dma_mapped = map_dma_buffers(drv_data))) { | |
941 | ||
942 | /* Ensure we have the correct interrupt handler */ | |
943 | drv_data->transfer_handler = dma_transfer; | |
944 | ||
945 | /* Setup rx DMA Channel */ | |
946 | DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; | |
947 | DSADR(drv_data->rx_channel) = drv_data->ssdr_physical; | |
948 | DTADR(drv_data->rx_channel) = drv_data->rx_dma; | |
949 | if (drv_data->rx == drv_data->null_dma_buf) | |
950 | /* No target address increment */ | |
951 | DCMD(drv_data->rx_channel) = DCMD_FLOWSRC | |
9708c121 | 952 | | drv_data->dma_width |
8d94cc50 | 953 | | dma_burst |
e0c9905e SS |
954 | | drv_data->len; |
955 | else | |
956 | DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR | |
957 | | DCMD_FLOWSRC | |
9708c121 | 958 | | drv_data->dma_width |
8d94cc50 | 959 | | dma_burst |
e0c9905e SS |
960 | | drv_data->len; |
961 | ||
962 | /* Setup tx DMA Channel */ | |
963 | DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; | |
964 | DSADR(drv_data->tx_channel) = drv_data->tx_dma; | |
965 | DTADR(drv_data->tx_channel) = drv_data->ssdr_physical; | |
966 | if (drv_data->tx == drv_data->null_dma_buf) | |
967 | /* No source address increment */ | |
968 | DCMD(drv_data->tx_channel) = DCMD_FLOWTRG | |
9708c121 | 969 | | drv_data->dma_width |
8d94cc50 | 970 | | dma_burst |
e0c9905e SS |
971 | | drv_data->len; |
972 | else | |
973 | DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR | |
974 | | DCMD_FLOWTRG | |
9708c121 | 975 | | drv_data->dma_width |
8d94cc50 | 976 | | dma_burst |
e0c9905e SS |
977 | | drv_data->len; |
978 | ||
979 | /* Enable dma end irqs on SSP to detect end of transfer */ | |
980 | if (drv_data->ssp_type == PXA25x_SSP) | |
981 | DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN; | |
982 | ||
8d94cc50 SS |
983 | /* Clear status and start DMA engine */ |
984 | cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; | |
e0c9905e SS |
985 | write_SSSR(drv_data->clear_sr, reg); |
986 | DCSR(drv_data->rx_channel) |= DCSR_RUN; | |
987 | DCSR(drv_data->tx_channel) |= DCSR_RUN; | |
e0c9905e SS |
988 | } else { |
989 | /* Ensure we have the correct interrupt handler */ | |
990 | drv_data->transfer_handler = interrupt_transfer; | |
991 | ||
8d94cc50 SS |
992 | /* Clear status */ |
993 | cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; | |
e0c9905e | 994 | write_SSSR(drv_data->clear_sr, reg); |
8d94cc50 SS |
995 | } |
996 | ||
997 | /* see if we need to reload the config registers */ | |
998 | if ((read_SSCR0(reg) != cr0) | |
999 | || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) != | |
1000 | (cr1 & SSCR1_CHANGE_MASK)) { | |
1001 | ||
b97c74bd | 1002 | /* stop the SSP, and update the other bits */ |
8d94cc50 | 1003 | write_SSCR0(cr0 & ~SSCR0_SSE, reg); |
e0c9905e SS |
1004 | if (drv_data->ssp_type != PXA25x_SSP) |
1005 | write_SSTO(chip->timeout, reg); | |
b97c74bd NF |
1006 | /* first set CR1 without interrupt and service enables */ |
1007 | write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg); | |
1008 | /* restart the SSP */ | |
8d94cc50 | 1009 | write_SSCR0(cr0, reg); |
b97c74bd | 1010 | |
8d94cc50 SS |
1011 | } else { |
1012 | if (drv_data->ssp_type != PXA25x_SSP) | |
1013 | write_SSTO(chip->timeout, reg); | |
e0c9905e | 1014 | } |
b97c74bd NF |
1015 | |
1016 | /* FIXME, need to handle cs polarity, | |
1017 | * this driver uses struct pxa2xx_spi_chip.cs_control to | |
1018 | * specify a CS handling function, and it ignores most | |
1019 | * struct spi_device.mode[s], including SPI_CS_HIGH */ | |
1020 | drv_data->cs_control(PXA2XX_CS_ASSERT); | |
1021 | ||
1022 | /* after chip select, release the data by enabling service | |
1023 | * requests and interrupts, without changing any mode bits */ | |
1024 | write_SSCR1(cr1, reg); | |
e0c9905e SS |
1025 | } |
1026 | ||
6d5aefb8 | 1027 | static void pump_messages(struct work_struct *work) |
e0c9905e | 1028 | { |
6d5aefb8 DH |
1029 | struct driver_data *drv_data = |
1030 | container_of(work, struct driver_data, pump_messages); | |
e0c9905e SS |
1031 | unsigned long flags; |
1032 | ||
1033 | /* Lock queue and check for queue work */ | |
1034 | spin_lock_irqsave(&drv_data->lock, flags); | |
1035 | if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) { | |
1036 | drv_data->busy = 0; | |
1037 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1038 | return; | |
1039 | } | |
1040 | ||
1041 | /* Make sure we are not already running a message */ | |
1042 | if (drv_data->cur_msg) { | |
1043 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1044 | return; | |
1045 | } | |
1046 | ||
1047 | /* Extract head of queue */ | |
1048 | drv_data->cur_msg = list_entry(drv_data->queue.next, | |
1049 | struct spi_message, queue); | |
1050 | list_del_init(&drv_data->cur_msg->queue); | |
e0c9905e SS |
1051 | |
1052 | /* Initial message state*/ | |
1053 | drv_data->cur_msg->state = START_STATE; | |
1054 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
1055 | struct spi_transfer, | |
1056 | transfer_list); | |
1057 | ||
8d94cc50 SS |
1058 | /* prepare to setup the SSP, in pump_transfers, using the per |
1059 | * chip configuration */ | |
e0c9905e | 1060 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); |
e0c9905e SS |
1061 | |
1062 | /* Mark as busy and launch transfers */ | |
1063 | tasklet_schedule(&drv_data->pump_transfers); | |
5daa3ba0 SS |
1064 | |
1065 | drv_data->busy = 1; | |
1066 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
e0c9905e SS |
1067 | } |
1068 | ||
1069 | static int transfer(struct spi_device *spi, struct spi_message *msg) | |
1070 | { | |
1071 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
1072 | unsigned long flags; | |
1073 | ||
1074 | spin_lock_irqsave(&drv_data->lock, flags); | |
1075 | ||
1076 | if (drv_data->run == QUEUE_STOPPED) { | |
1077 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1078 | return -ESHUTDOWN; | |
1079 | } | |
1080 | ||
1081 | msg->actual_length = 0; | |
1082 | msg->status = -EINPROGRESS; | |
1083 | msg->state = START_STATE; | |
1084 | ||
1085 | list_add_tail(&msg->queue, &drv_data->queue); | |
1086 | ||
1087 | if (drv_data->run == QUEUE_RUNNING && !drv_data->busy) | |
1088 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
1089 | ||
1090 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1091 | ||
1092 | return 0; | |
1093 | } | |
1094 | ||
dccd573b DB |
1095 | /* the spi->mode bits understood by this driver: */ |
1096 | #define MODEBITS (SPI_CPOL | SPI_CPHA) | |
1097 | ||
e0c9905e SS |
1098 | static int setup(struct spi_device *spi) |
1099 | { | |
1100 | struct pxa2xx_spi_chip *chip_info = NULL; | |
1101 | struct chip_data *chip; | |
1102 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
2f1a74e5 | 1103 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1104 | unsigned int clk_div; |
1105 | ||
1106 | if (!spi->bits_per_word) | |
1107 | spi->bits_per_word = 8; | |
1108 | ||
1109 | if (drv_data->ssp_type != PXA25x_SSP | |
8d94cc50 SS |
1110 | && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) { |
1111 | dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " | |
1112 | "b/w not 4-32 for type non-PXA25x_SSP\n", | |
1113 | drv_data->ssp_type, spi->bits_per_word); | |
e0c9905e | 1114 | return -EINVAL; |
8d94cc50 SS |
1115 | } |
1116 | else if (drv_data->ssp_type == PXA25x_SSP | |
1117 | && (spi->bits_per_word < 4 | |
1118 | || spi->bits_per_word > 16)) { | |
1119 | dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " | |
1120 | "b/w not 4-16 for type PXA25x_SSP\n", | |
1121 | drv_data->ssp_type, spi->bits_per_word); | |
e0c9905e | 1122 | return -EINVAL; |
8d94cc50 | 1123 | } |
e0c9905e | 1124 | |
dccd573b DB |
1125 | if (spi->mode & ~MODEBITS) { |
1126 | dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n", | |
1127 | spi->mode & ~MODEBITS); | |
1128 | return -EINVAL; | |
1129 | } | |
1130 | ||
8d94cc50 | 1131 | /* Only alloc on first setup */ |
e0c9905e | 1132 | chip = spi_get_ctldata(spi); |
8d94cc50 | 1133 | if (!chip) { |
e0c9905e | 1134 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
8d94cc50 SS |
1135 | if (!chip) { |
1136 | dev_err(&spi->dev, | |
1137 | "failed setup: can't allocate chip data\n"); | |
e0c9905e | 1138 | return -ENOMEM; |
8d94cc50 | 1139 | } |
e0c9905e SS |
1140 | |
1141 | chip->cs_control = null_cs_control; | |
1142 | chip->enable_dma = 0; | |
8d94cc50 | 1143 | chip->timeout = 1000; |
e0c9905e SS |
1144 | chip->threshold = SSCR1_RxTresh(1) | SSCR1_TxTresh(1); |
1145 | chip->dma_burst_size = drv_data->master_info->enable_dma ? | |
1146 | DCMD_BURST8 : 0; | |
e0c9905e SS |
1147 | } |
1148 | ||
8d94cc50 SS |
1149 | /* protocol drivers may change the chip settings, so... |
1150 | * if chip_info exists, use it */ | |
1151 | chip_info = spi->controller_data; | |
1152 | ||
e0c9905e | 1153 | /* chip_info isn't always needed */ |
8d94cc50 | 1154 | chip->cr1 = 0; |
e0c9905e SS |
1155 | if (chip_info) { |
1156 | if (chip_info->cs_control) | |
1157 | chip->cs_control = chip_info->cs_control; | |
1158 | ||
8d94cc50 | 1159 | chip->timeout = chip_info->timeout; |
e0c9905e | 1160 | |
8d94cc50 SS |
1161 | chip->threshold = (SSCR1_RxTresh(chip_info->rx_threshold) & |
1162 | SSCR1_RFT) | | |
1163 | (SSCR1_TxTresh(chip_info->tx_threshold) & | |
1164 | SSCR1_TFT); | |
e0c9905e SS |
1165 | |
1166 | chip->enable_dma = chip_info->dma_burst_size != 0 | |
1167 | && drv_data->master_info->enable_dma; | |
1168 | chip->dma_threshold = 0; | |
1169 | ||
e0c9905e SS |
1170 | if (chip_info->enable_loopback) |
1171 | chip->cr1 = SSCR1_LBM; | |
1172 | } | |
1173 | ||
8d94cc50 SS |
1174 | /* set dma burst and threshold outside of chip_info path so that if |
1175 | * chip_info goes away after setting chip->enable_dma, the | |
1176 | * burst and threshold can still respond to changes in bits_per_word */ | |
1177 | if (chip->enable_dma) { | |
1178 | /* set up legal burst and threshold for dma */ | |
1179 | if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word, | |
1180 | &chip->dma_burst_size, | |
1181 | &chip->dma_threshold)) { | |
1182 | dev_warn(&spi->dev, "in setup: DMA burst size reduced " | |
1183 | "to match bits_per_word\n"); | |
1184 | } | |
1185 | } | |
1186 | ||
2f1a74e5 | 1187 | clk_div = ssp_get_clk_div(ssp, spi->max_speed_hz); |
9708c121 | 1188 | chip->speed_hz = spi->max_speed_hz; |
e0c9905e SS |
1189 | |
1190 | chip->cr0 = clk_div | |
1191 | | SSCR0_Motorola | |
5daa3ba0 SS |
1192 | | SSCR0_DataSize(spi->bits_per_word > 16 ? |
1193 | spi->bits_per_word - 16 : spi->bits_per_word) | |
e0c9905e SS |
1194 | | SSCR0_SSE |
1195 | | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0); | |
7f6ee1ad JC |
1196 | chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); |
1197 | chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) | |
1198 | | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); | |
e0c9905e SS |
1199 | |
1200 | /* NOTE: PXA25x_SSP _could_ use external clocking ... */ | |
1201 | if (drv_data->ssp_type != PXA25x_SSP) | |
2f1a74e5 | 1202 | dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d\n", |
e0c9905e | 1203 | spi->bits_per_word, |
2f1a74e5 | 1204 | clk_get_rate(ssp->clk) |
e0c9905e SS |
1205 | / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)), |
1206 | spi->mode & 0x3); | |
1207 | else | |
2f1a74e5 | 1208 | dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d\n", |
e0c9905e | 1209 | spi->bits_per_word, |
2f1a74e5 | 1210 | clk_get_rate(ssp->clk) |
e0c9905e SS |
1211 | / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)), |
1212 | spi->mode & 0x3); | |
1213 | ||
1214 | if (spi->bits_per_word <= 8) { | |
1215 | chip->n_bytes = 1; | |
1216 | chip->dma_width = DCMD_WIDTH1; | |
1217 | chip->read = u8_reader; | |
1218 | chip->write = u8_writer; | |
1219 | } else if (spi->bits_per_word <= 16) { | |
1220 | chip->n_bytes = 2; | |
1221 | chip->dma_width = DCMD_WIDTH2; | |
1222 | chip->read = u16_reader; | |
1223 | chip->write = u16_writer; | |
1224 | } else if (spi->bits_per_word <= 32) { | |
1225 | chip->cr0 |= SSCR0_EDSS; | |
1226 | chip->n_bytes = 4; | |
1227 | chip->dma_width = DCMD_WIDTH4; | |
1228 | chip->read = u32_reader; | |
1229 | chip->write = u32_writer; | |
1230 | } else { | |
1231 | dev_err(&spi->dev, "invalid wordsize\n"); | |
e0c9905e SS |
1232 | return -ENODEV; |
1233 | } | |
9708c121 | 1234 | chip->bits_per_word = spi->bits_per_word; |
e0c9905e SS |
1235 | |
1236 | spi_set_ctldata(spi, chip); | |
1237 | ||
1238 | return 0; | |
1239 | } | |
1240 | ||
0ffa0285 | 1241 | static void cleanup(struct spi_device *spi) |
e0c9905e | 1242 | { |
0ffa0285 | 1243 | struct chip_data *chip = spi_get_ctldata(spi); |
e0c9905e SS |
1244 | |
1245 | kfree(chip); | |
1246 | } | |
1247 | ||
d1e44d9c | 1248 | static int __init init_queue(struct driver_data *drv_data) |
e0c9905e SS |
1249 | { |
1250 | INIT_LIST_HEAD(&drv_data->queue); | |
1251 | spin_lock_init(&drv_data->lock); | |
1252 | ||
1253 | drv_data->run = QUEUE_STOPPED; | |
1254 | drv_data->busy = 0; | |
1255 | ||
1256 | tasklet_init(&drv_data->pump_transfers, | |
1257 | pump_transfers, (unsigned long)drv_data); | |
1258 | ||
6d5aefb8 | 1259 | INIT_WORK(&drv_data->pump_messages, pump_messages); |
e0c9905e | 1260 | drv_data->workqueue = create_singlethread_workqueue( |
49dce689 | 1261 | drv_data->master->dev.parent->bus_id); |
e0c9905e SS |
1262 | if (drv_data->workqueue == NULL) |
1263 | return -EBUSY; | |
1264 | ||
1265 | return 0; | |
1266 | } | |
1267 | ||
1268 | static int start_queue(struct driver_data *drv_data) | |
1269 | { | |
1270 | unsigned long flags; | |
1271 | ||
1272 | spin_lock_irqsave(&drv_data->lock, flags); | |
1273 | ||
1274 | if (drv_data->run == QUEUE_RUNNING || drv_data->busy) { | |
1275 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1276 | return -EBUSY; | |
1277 | } | |
1278 | ||
1279 | drv_data->run = QUEUE_RUNNING; | |
1280 | drv_data->cur_msg = NULL; | |
1281 | drv_data->cur_transfer = NULL; | |
1282 | drv_data->cur_chip = NULL; | |
1283 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1284 | ||
1285 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
1286 | ||
1287 | return 0; | |
1288 | } | |
1289 | ||
1290 | static int stop_queue(struct driver_data *drv_data) | |
1291 | { | |
1292 | unsigned long flags; | |
1293 | unsigned limit = 500; | |
1294 | int status = 0; | |
1295 | ||
1296 | spin_lock_irqsave(&drv_data->lock, flags); | |
1297 | ||
1298 | /* This is a bit lame, but is optimized for the common execution path. | |
1299 | * A wait_queue on the drv_data->busy could be used, but then the common | |
1300 | * execution path (pump_messages) would be required to call wake_up or | |
1301 | * friends on every SPI message. Do this instead */ | |
1302 | drv_data->run = QUEUE_STOPPED; | |
1303 | while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) { | |
1304 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1305 | msleep(10); | |
1306 | spin_lock_irqsave(&drv_data->lock, flags); | |
1307 | } | |
1308 | ||
1309 | if (!list_empty(&drv_data->queue) || drv_data->busy) | |
1310 | status = -EBUSY; | |
1311 | ||
1312 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1313 | ||
1314 | return status; | |
1315 | } | |
1316 | ||
1317 | static int destroy_queue(struct driver_data *drv_data) | |
1318 | { | |
1319 | int status; | |
1320 | ||
1321 | status = stop_queue(drv_data); | |
8d94cc50 SS |
1322 | /* we are unloading the module or failing to load (only two calls |
1323 | * to this routine), and neither call can handle a return value. | |
1324 | * However, destroy_workqueue calls flush_workqueue, and that will | |
1325 | * block until all work is done. If the reason that stop_queue | |
1326 | * timed out is that the work will never finish, then it does no | |
1327 | * good to call destroy_workqueue, so return anyway. */ | |
e0c9905e SS |
1328 | if (status != 0) |
1329 | return status; | |
1330 | ||
1331 | destroy_workqueue(drv_data->workqueue); | |
1332 | ||
1333 | return 0; | |
1334 | } | |
1335 | ||
d1e44d9c | 1336 | static int __init pxa2xx_spi_probe(struct platform_device *pdev) |
e0c9905e SS |
1337 | { |
1338 | struct device *dev = &pdev->dev; | |
1339 | struct pxa2xx_spi_master *platform_info; | |
1340 | struct spi_master *master; | |
1341 | struct driver_data *drv_data = 0; | |
2f1a74e5 | 1342 | struct ssp_device *ssp; |
e0c9905e SS |
1343 | int status = 0; |
1344 | ||
1345 | platform_info = dev->platform_data; | |
1346 | ||
2f1a74e5 | 1347 | ssp = ssp_request(pdev->id, pdev->name); |
1348 | if (ssp == NULL) { | |
1349 | dev_err(&pdev->dev, "failed to request SSP%d\n", pdev->id); | |
e0c9905e SS |
1350 | return -ENODEV; |
1351 | } | |
1352 | ||
1353 | /* Allocate master with space for drv_data and null dma buffer */ | |
1354 | master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); | |
1355 | if (!master) { | |
1356 | dev_err(&pdev->dev, "can not alloc spi_master\n"); | |
2f1a74e5 | 1357 | ssp_free(ssp); |
e0c9905e SS |
1358 | return -ENOMEM; |
1359 | } | |
1360 | drv_data = spi_master_get_devdata(master); | |
1361 | drv_data->master = master; | |
1362 | drv_data->master_info = platform_info; | |
1363 | drv_data->pdev = pdev; | |
2f1a74e5 | 1364 | drv_data->ssp = ssp; |
e0c9905e SS |
1365 | |
1366 | master->bus_num = pdev->id; | |
1367 | master->num_chipselect = platform_info->num_chipselect; | |
1368 | master->cleanup = cleanup; | |
1369 | master->setup = setup; | |
1370 | master->transfer = transfer; | |
1371 | ||
2f1a74e5 | 1372 | drv_data->ssp_type = ssp->type; |
e0c9905e SS |
1373 | drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data + |
1374 | sizeof(struct driver_data)), 8); | |
1375 | ||
2f1a74e5 | 1376 | drv_data->ioaddr = ssp->mmio_base; |
1377 | drv_data->ssdr_physical = ssp->phys_base + SSDR; | |
1378 | if (ssp->type == PXA25x_SSP) { | |
e0c9905e SS |
1379 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; |
1380 | drv_data->dma_cr1 = 0; | |
1381 | drv_data->clear_sr = SSSR_ROR; | |
1382 | drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1383 | } else { | |
1384 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; | |
1385 | drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE; | |
1386 | drv_data->clear_sr = SSSR_ROR | SSSR_TINT; | |
1387 | drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1388 | } | |
1389 | ||
2f1a74e5 | 1390 | status = request_irq(ssp->irq, ssp_int, 0, dev->bus_id, drv_data); |
e0c9905e SS |
1391 | if (status < 0) { |
1392 | dev_err(&pdev->dev, "can not get IRQ\n"); | |
1393 | goto out_error_master_alloc; | |
1394 | } | |
1395 | ||
1396 | /* Setup DMA if requested */ | |
1397 | drv_data->tx_channel = -1; | |
1398 | drv_data->rx_channel = -1; | |
1399 | if (platform_info->enable_dma) { | |
1400 | ||
1401 | /* Get two DMA channels (rx and tx) */ | |
1402 | drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx", | |
1403 | DMA_PRIO_HIGH, | |
1404 | dma_handler, | |
1405 | drv_data); | |
1406 | if (drv_data->rx_channel < 0) { | |
1407 | dev_err(dev, "problem (%d) requesting rx channel\n", | |
1408 | drv_data->rx_channel); | |
1409 | status = -ENODEV; | |
1410 | goto out_error_irq_alloc; | |
1411 | } | |
1412 | drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx", | |
1413 | DMA_PRIO_MEDIUM, | |
1414 | dma_handler, | |
1415 | drv_data); | |
1416 | if (drv_data->tx_channel < 0) { | |
1417 | dev_err(dev, "problem (%d) requesting tx channel\n", | |
1418 | drv_data->tx_channel); | |
1419 | status = -ENODEV; | |
1420 | goto out_error_dma_alloc; | |
1421 | } | |
1422 | ||
2f1a74e5 | 1423 | DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel; |
1424 | DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel; | |
e0c9905e SS |
1425 | } |
1426 | ||
1427 | /* Enable SOC clock */ | |
2f1a74e5 | 1428 | clk_enable(ssp->clk); |
e0c9905e SS |
1429 | |
1430 | /* Load default SSP configuration */ | |
1431 | write_SSCR0(0, drv_data->ioaddr); | |
1432 | write_SSCR1(SSCR1_RxTresh(4) | SSCR1_TxTresh(12), drv_data->ioaddr); | |
1433 | write_SSCR0(SSCR0_SerClkDiv(2) | |
1434 | | SSCR0_Motorola | |
1435 | | SSCR0_DataSize(8), | |
1436 | drv_data->ioaddr); | |
1437 | if (drv_data->ssp_type != PXA25x_SSP) | |
1438 | write_SSTO(0, drv_data->ioaddr); | |
1439 | write_SSPSP(0, drv_data->ioaddr); | |
1440 | ||
1441 | /* Initial and start queue */ | |
1442 | status = init_queue(drv_data); | |
1443 | if (status != 0) { | |
1444 | dev_err(&pdev->dev, "problem initializing queue\n"); | |
1445 | goto out_error_clock_enabled; | |
1446 | } | |
1447 | status = start_queue(drv_data); | |
1448 | if (status != 0) { | |
1449 | dev_err(&pdev->dev, "problem starting queue\n"); | |
1450 | goto out_error_clock_enabled; | |
1451 | } | |
1452 | ||
1453 | /* Register with the SPI framework */ | |
1454 | platform_set_drvdata(pdev, drv_data); | |
1455 | status = spi_register_master(master); | |
1456 | if (status != 0) { | |
1457 | dev_err(&pdev->dev, "problem registering spi master\n"); | |
1458 | goto out_error_queue_alloc; | |
1459 | } | |
1460 | ||
1461 | return status; | |
1462 | ||
1463 | out_error_queue_alloc: | |
1464 | destroy_queue(drv_data); | |
1465 | ||
1466 | out_error_clock_enabled: | |
2f1a74e5 | 1467 | clk_disable(ssp->clk); |
e0c9905e SS |
1468 | |
1469 | out_error_dma_alloc: | |
1470 | if (drv_data->tx_channel != -1) | |
1471 | pxa_free_dma(drv_data->tx_channel); | |
1472 | if (drv_data->rx_channel != -1) | |
1473 | pxa_free_dma(drv_data->rx_channel); | |
1474 | ||
1475 | out_error_irq_alloc: | |
2f1a74e5 | 1476 | free_irq(ssp->irq, drv_data); |
e0c9905e SS |
1477 | |
1478 | out_error_master_alloc: | |
1479 | spi_master_put(master); | |
2f1a74e5 | 1480 | ssp_free(ssp); |
e0c9905e SS |
1481 | return status; |
1482 | } | |
1483 | ||
1484 | static int pxa2xx_spi_remove(struct platform_device *pdev) | |
1485 | { | |
1486 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
2f1a74e5 | 1487 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1488 | int status = 0; |
1489 | ||
1490 | if (!drv_data) | |
1491 | return 0; | |
1492 | ||
1493 | /* Remove the queue */ | |
1494 | status = destroy_queue(drv_data); | |
1495 | if (status != 0) | |
8d94cc50 SS |
1496 | /* the kernel does not check the return status of this |
1497 | * this routine (mod->exit, within the kernel). Therefore | |
1498 | * nothing is gained by returning from here, the module is | |
1499 | * going away regardless, and we should not leave any more | |
1500 | * resources allocated than necessary. We cannot free the | |
1501 | * message memory in drv_data->queue, but we can release the | |
1502 | * resources below. I think the kernel should honor -EBUSY | |
1503 | * returns but... */ | |
1504 | dev_err(&pdev->dev, "pxa2xx_spi_remove: workqueue will not " | |
1505 | "complete, message memory not freed\n"); | |
e0c9905e SS |
1506 | |
1507 | /* Disable the SSP at the peripheral and SOC level */ | |
1508 | write_SSCR0(0, drv_data->ioaddr); | |
2f1a74e5 | 1509 | clk_disable(ssp->clk); |
e0c9905e SS |
1510 | |
1511 | /* Release DMA */ | |
1512 | if (drv_data->master_info->enable_dma) { | |
2f1a74e5 | 1513 | DRCMR(ssp->drcmr_rx) = 0; |
1514 | DRCMR(ssp->drcmr_tx) = 0; | |
e0c9905e SS |
1515 | pxa_free_dma(drv_data->tx_channel); |
1516 | pxa_free_dma(drv_data->rx_channel); | |
1517 | } | |
1518 | ||
1519 | /* Release IRQ */ | |
2f1a74e5 | 1520 | free_irq(ssp->irq, drv_data); |
1521 | ||
1522 | /* Release SSP */ | |
1523 | ssp_free(ssp); | |
e0c9905e SS |
1524 | |
1525 | /* Disconnect from the SPI framework */ | |
1526 | spi_unregister_master(drv_data->master); | |
1527 | ||
1528 | /* Prevent double remove */ | |
1529 | platform_set_drvdata(pdev, NULL); | |
1530 | ||
1531 | return 0; | |
1532 | } | |
1533 | ||
1534 | static void pxa2xx_spi_shutdown(struct platform_device *pdev) | |
1535 | { | |
1536 | int status = 0; | |
1537 | ||
1538 | if ((status = pxa2xx_spi_remove(pdev)) != 0) | |
1539 | dev_err(&pdev->dev, "shutdown failed with %d\n", status); | |
1540 | } | |
1541 | ||
1542 | #ifdef CONFIG_PM | |
e0c9905e SS |
1543 | |
1544 | static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state) | |
1545 | { | |
1546 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
2f1a74e5 | 1547 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1548 | int status = 0; |
1549 | ||
e0c9905e SS |
1550 | status = stop_queue(drv_data); |
1551 | if (status != 0) | |
1552 | return status; | |
1553 | write_SSCR0(0, drv_data->ioaddr); | |
2f1a74e5 | 1554 | clk_disable(ssp->clk); |
e0c9905e SS |
1555 | |
1556 | return 0; | |
1557 | } | |
1558 | ||
1559 | static int pxa2xx_spi_resume(struct platform_device *pdev) | |
1560 | { | |
1561 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
2f1a74e5 | 1562 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1563 | int status = 0; |
1564 | ||
1565 | /* Enable the SSP clock */ | |
2f1a74e5 | 1566 | clk_disable(ssp->clk); |
e0c9905e SS |
1567 | |
1568 | /* Start the queue running */ | |
1569 | status = start_queue(drv_data); | |
1570 | if (status != 0) { | |
1571 | dev_err(&pdev->dev, "problem starting queue (%d)\n", status); | |
1572 | return status; | |
1573 | } | |
1574 | ||
1575 | return 0; | |
1576 | } | |
1577 | #else | |
1578 | #define pxa2xx_spi_suspend NULL | |
1579 | #define pxa2xx_spi_resume NULL | |
1580 | #endif /* CONFIG_PM */ | |
1581 | ||
1582 | static struct platform_driver driver = { | |
1583 | .driver = { | |
1584 | .name = "pxa2xx-spi", | |
e0c9905e SS |
1585 | .owner = THIS_MODULE, |
1586 | }, | |
d1e44d9c | 1587 | .remove = pxa2xx_spi_remove, |
e0c9905e SS |
1588 | .shutdown = pxa2xx_spi_shutdown, |
1589 | .suspend = pxa2xx_spi_suspend, | |
1590 | .resume = pxa2xx_spi_resume, | |
1591 | }; | |
1592 | ||
1593 | static int __init pxa2xx_spi_init(void) | |
1594 | { | |
d1e44d9c | 1595 | return platform_driver_probe(&driver, pxa2xx_spi_probe); |
e0c9905e SS |
1596 | } |
1597 | module_init(pxa2xx_spi_init); | |
1598 | ||
1599 | static void __exit pxa2xx_spi_exit(void) | |
1600 | { | |
1601 | platform_driver_unregister(&driver); | |
1602 | } | |
1603 | module_exit(pxa2xx_spi_exit); |