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e0c9905e SS |
1 | /* |
2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
19 | #include <linux/init.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/device.h> | |
22 | #include <linux/ioport.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/dma-mapping.h> | |
27 | #include <linux/spi/spi.h> | |
28 | #include <linux/workqueue.h> | |
e0c9905e | 29 | #include <linux/delay.h> |
2f1a74e5 | 30 | #include <linux/clk.h> |
e0c9905e SS |
31 | |
32 | #include <asm/io.h> | |
33 | #include <asm/irq.h> | |
e0c9905e | 34 | #include <asm/delay.h> |
e0c9905e | 35 | |
dcea83ad | 36 | #include <mach/dma.h> |
a09e64fb RK |
37 | #include <mach/hardware.h> |
38 | #include <mach/pxa-regs.h> | |
39 | #include <mach/regs-ssp.h> | |
40 | #include <mach/ssp.h> | |
41 | #include <mach/pxa2xx_spi.h> | |
e0c9905e SS |
42 | |
43 | MODULE_AUTHOR("Stephen Street"); | |
037cdafe | 44 | MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); |
e0c9905e | 45 | MODULE_LICENSE("GPL"); |
7e38c3c4 | 46 | MODULE_ALIAS("platform:pxa2xx-spi"); |
e0c9905e SS |
47 | |
48 | #define MAX_BUSES 3 | |
49 | ||
f1f640a9 VS |
50 | #define RX_THRESH_DFLT 8 |
51 | #define TX_THRESH_DFLT 8 | |
52 | #define TIMOUT_DFLT 1000 | |
53 | ||
7e964455 NF |
54 | #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR) |
55 | #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK) | |
20b918dc | 56 | #define IS_DMA_ALIGNED(x) ((((u32)(x)) & 0x07) == 0) |
7e964455 | 57 | #define MAX_DMA_LEN 8191 |
e0c9905e | 58 | |
b97c74bd NF |
59 | /* |
60 | * for testing SSCR1 changes that require SSP restart, basically | |
61 | * everything except the service and interrupt enables, the pxa270 developer | |
62 | * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this | |
63 | * list, but the PXA255 dev man says all bits without really meaning the | |
64 | * service and interrupt enables | |
65 | */ | |
66 | #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ | |
8d94cc50 | 67 | | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ |
b97c74bd NF |
68 | | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ |
69 | | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ | |
70 | | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ | |
71 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
8d94cc50 | 72 | |
e0c9905e | 73 | #define DEFINE_SSP_REG(reg, off) \ |
cf43369d DB |
74 | static inline u32 read_##reg(void const __iomem *p) \ |
75 | { return __raw_readl(p + (off)); } \ | |
76 | \ | |
77 | static inline void write_##reg(u32 v, void __iomem *p) \ | |
78 | { __raw_writel(v, p + (off)); } | |
e0c9905e SS |
79 | |
80 | DEFINE_SSP_REG(SSCR0, 0x00) | |
81 | DEFINE_SSP_REG(SSCR1, 0x04) | |
82 | DEFINE_SSP_REG(SSSR, 0x08) | |
83 | DEFINE_SSP_REG(SSITR, 0x0c) | |
84 | DEFINE_SSP_REG(SSDR, 0x10) | |
85 | DEFINE_SSP_REG(SSTO, 0x28) | |
86 | DEFINE_SSP_REG(SSPSP, 0x2c) | |
87 | ||
88 | #define START_STATE ((void*)0) | |
89 | #define RUNNING_STATE ((void*)1) | |
90 | #define DONE_STATE ((void*)2) | |
91 | #define ERROR_STATE ((void*)-1) | |
92 | ||
93 | #define QUEUE_RUNNING 0 | |
94 | #define QUEUE_STOPPED 1 | |
95 | ||
96 | struct driver_data { | |
97 | /* Driver model hookup */ | |
98 | struct platform_device *pdev; | |
99 | ||
2f1a74e5 | 100 | /* SSP Info */ |
101 | struct ssp_device *ssp; | |
102 | ||
e0c9905e SS |
103 | /* SPI framework hookup */ |
104 | enum pxa_ssp_type ssp_type; | |
105 | struct spi_master *master; | |
106 | ||
107 | /* PXA hookup */ | |
108 | struct pxa2xx_spi_master *master_info; | |
109 | ||
110 | /* DMA setup stuff */ | |
111 | int rx_channel; | |
112 | int tx_channel; | |
113 | u32 *null_dma_buf; | |
114 | ||
115 | /* SSP register addresses */ | |
cf43369d | 116 | void __iomem *ioaddr; |
e0c9905e SS |
117 | u32 ssdr_physical; |
118 | ||
119 | /* SSP masks*/ | |
120 | u32 dma_cr1; | |
121 | u32 int_cr1; | |
122 | u32 clear_sr; | |
123 | u32 mask_sr; | |
124 | ||
125 | /* Driver message queue */ | |
126 | struct workqueue_struct *workqueue; | |
127 | struct work_struct pump_messages; | |
128 | spinlock_t lock; | |
129 | struct list_head queue; | |
130 | int busy; | |
131 | int run; | |
132 | ||
133 | /* Message Transfer pump */ | |
134 | struct tasklet_struct pump_transfers; | |
135 | ||
136 | /* Current message transfer state info */ | |
137 | struct spi_message* cur_msg; | |
138 | struct spi_transfer* cur_transfer; | |
139 | struct chip_data *cur_chip; | |
140 | size_t len; | |
141 | void *tx; | |
142 | void *tx_end; | |
143 | void *rx; | |
144 | void *rx_end; | |
145 | int dma_mapped; | |
146 | dma_addr_t rx_dma; | |
147 | dma_addr_t tx_dma; | |
148 | size_t rx_map_len; | |
149 | size_t tx_map_len; | |
9708c121 SS |
150 | u8 n_bytes; |
151 | u32 dma_width; | |
8d94cc50 SS |
152 | int (*write)(struct driver_data *drv_data); |
153 | int (*read)(struct driver_data *drv_data); | |
e0c9905e SS |
154 | irqreturn_t (*transfer_handler)(struct driver_data *drv_data); |
155 | void (*cs_control)(u32 command); | |
156 | }; | |
157 | ||
158 | struct chip_data { | |
159 | u32 cr0; | |
160 | u32 cr1; | |
e0c9905e SS |
161 | u32 psp; |
162 | u32 timeout; | |
163 | u8 n_bytes; | |
164 | u32 dma_width; | |
165 | u32 dma_burst_size; | |
166 | u32 threshold; | |
167 | u32 dma_threshold; | |
168 | u8 enable_dma; | |
9708c121 SS |
169 | u8 bits_per_word; |
170 | u32 speed_hz; | |
8d94cc50 SS |
171 | int (*write)(struct driver_data *drv_data); |
172 | int (*read)(struct driver_data *drv_data); | |
e0c9905e SS |
173 | void (*cs_control)(u32 command); |
174 | }; | |
175 | ||
6d5aefb8 | 176 | static void pump_messages(struct work_struct *work); |
e0c9905e SS |
177 | |
178 | static int flush(struct driver_data *drv_data) | |
179 | { | |
180 | unsigned long limit = loops_per_jiffy << 1; | |
181 | ||
cf43369d | 182 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
183 | |
184 | do { | |
185 | while (read_SSSR(reg) & SSSR_RNE) { | |
186 | read_SSDR(reg); | |
187 | } | |
188 | } while ((read_SSSR(reg) & SSSR_BSY) && limit--); | |
189 | write_SSSR(SSSR_ROR, reg); | |
190 | ||
191 | return limit; | |
192 | } | |
193 | ||
e0c9905e SS |
194 | static void null_cs_control(u32 command) |
195 | { | |
196 | } | |
197 | ||
8d94cc50 | 198 | static int null_writer(struct driver_data *drv_data) |
e0c9905e | 199 | { |
cf43369d | 200 | void __iomem *reg = drv_data->ioaddr; |
9708c121 | 201 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 202 | |
8d94cc50 SS |
203 | if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00) |
204 | || (drv_data->tx == drv_data->tx_end)) | |
205 | return 0; | |
206 | ||
207 | write_SSDR(0, reg); | |
208 | drv_data->tx += n_bytes; | |
209 | ||
210 | return 1; | |
e0c9905e SS |
211 | } |
212 | ||
8d94cc50 | 213 | static int null_reader(struct driver_data *drv_data) |
e0c9905e | 214 | { |
cf43369d | 215 | void __iomem *reg = drv_data->ioaddr; |
9708c121 | 216 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e SS |
217 | |
218 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 219 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
220 | read_SSDR(reg); |
221 | drv_data->rx += n_bytes; | |
222 | } | |
8d94cc50 SS |
223 | |
224 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
225 | } |
226 | ||
8d94cc50 | 227 | static int u8_writer(struct driver_data *drv_data) |
e0c9905e | 228 | { |
cf43369d | 229 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 230 | |
8d94cc50 SS |
231 | if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00) |
232 | || (drv_data->tx == drv_data->tx_end)) | |
233 | return 0; | |
234 | ||
235 | write_SSDR(*(u8 *)(drv_data->tx), reg); | |
236 | ++drv_data->tx; | |
237 | ||
238 | return 1; | |
e0c9905e SS |
239 | } |
240 | ||
8d94cc50 | 241 | static int u8_reader(struct driver_data *drv_data) |
e0c9905e | 242 | { |
cf43369d | 243 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
244 | |
245 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 246 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
247 | *(u8 *)(drv_data->rx) = read_SSDR(reg); |
248 | ++drv_data->rx; | |
249 | } | |
8d94cc50 SS |
250 | |
251 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
252 | } |
253 | ||
8d94cc50 | 254 | static int u16_writer(struct driver_data *drv_data) |
e0c9905e | 255 | { |
cf43369d | 256 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 257 | |
8d94cc50 SS |
258 | if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00) |
259 | || (drv_data->tx == drv_data->tx_end)) | |
260 | return 0; | |
261 | ||
262 | write_SSDR(*(u16 *)(drv_data->tx), reg); | |
263 | drv_data->tx += 2; | |
264 | ||
265 | return 1; | |
e0c9905e SS |
266 | } |
267 | ||
8d94cc50 | 268 | static int u16_reader(struct driver_data *drv_data) |
e0c9905e | 269 | { |
cf43369d | 270 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
271 | |
272 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 273 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
274 | *(u16 *)(drv_data->rx) = read_SSDR(reg); |
275 | drv_data->rx += 2; | |
276 | } | |
8d94cc50 SS |
277 | |
278 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e | 279 | } |
8d94cc50 SS |
280 | |
281 | static int u32_writer(struct driver_data *drv_data) | |
e0c9905e | 282 | { |
cf43369d | 283 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 284 | |
8d94cc50 SS |
285 | if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00) |
286 | || (drv_data->tx == drv_data->tx_end)) | |
287 | return 0; | |
288 | ||
289 | write_SSDR(*(u32 *)(drv_data->tx), reg); | |
290 | drv_data->tx += 4; | |
291 | ||
292 | return 1; | |
e0c9905e SS |
293 | } |
294 | ||
8d94cc50 | 295 | static int u32_reader(struct driver_data *drv_data) |
e0c9905e | 296 | { |
cf43369d | 297 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
298 | |
299 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 300 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
301 | *(u32 *)(drv_data->rx) = read_SSDR(reg); |
302 | drv_data->rx += 4; | |
303 | } | |
8d94cc50 SS |
304 | |
305 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
306 | } |
307 | ||
308 | static void *next_transfer(struct driver_data *drv_data) | |
309 | { | |
310 | struct spi_message *msg = drv_data->cur_msg; | |
311 | struct spi_transfer *trans = drv_data->cur_transfer; | |
312 | ||
313 | /* Move to next transfer */ | |
314 | if (trans->transfer_list.next != &msg->transfers) { | |
315 | drv_data->cur_transfer = | |
316 | list_entry(trans->transfer_list.next, | |
317 | struct spi_transfer, | |
318 | transfer_list); | |
319 | return RUNNING_STATE; | |
320 | } else | |
321 | return DONE_STATE; | |
322 | } | |
323 | ||
324 | static int map_dma_buffers(struct driver_data *drv_data) | |
325 | { | |
326 | struct spi_message *msg = drv_data->cur_msg; | |
327 | struct device *dev = &msg->spi->dev; | |
328 | ||
329 | if (!drv_data->cur_chip->enable_dma) | |
330 | return 0; | |
331 | ||
332 | if (msg->is_dma_mapped) | |
333 | return drv_data->rx_dma && drv_data->tx_dma; | |
334 | ||
335 | if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx)) | |
336 | return 0; | |
337 | ||
338 | /* Modify setup if rx buffer is null */ | |
339 | if (drv_data->rx == NULL) { | |
340 | *drv_data->null_dma_buf = 0; | |
341 | drv_data->rx = drv_data->null_dma_buf; | |
342 | drv_data->rx_map_len = 4; | |
343 | } else | |
344 | drv_data->rx_map_len = drv_data->len; | |
345 | ||
346 | ||
347 | /* Modify setup if tx buffer is null */ | |
348 | if (drv_data->tx == NULL) { | |
349 | *drv_data->null_dma_buf = 0; | |
350 | drv_data->tx = drv_data->null_dma_buf; | |
351 | drv_data->tx_map_len = 4; | |
352 | } else | |
353 | drv_data->tx_map_len = drv_data->len; | |
354 | ||
393df744 NF |
355 | /* Stream map the tx buffer. Always do DMA_TO_DEVICE first |
356 | * so we flush the cache *before* invalidating it, in case | |
357 | * the tx and rx buffers overlap. | |
358 | */ | |
e0c9905e | 359 | drv_data->tx_dma = dma_map_single(dev, drv_data->tx, |
393df744 NF |
360 | drv_data->tx_map_len, DMA_TO_DEVICE); |
361 | if (dma_mapping_error(dev, drv_data->tx_dma)) | |
362 | return 0; | |
e0c9905e | 363 | |
393df744 NF |
364 | /* Stream map the rx buffer */ |
365 | drv_data->rx_dma = dma_map_single(dev, drv_data->rx, | |
e0c9905e | 366 | drv_data->rx_map_len, DMA_FROM_DEVICE); |
393df744 NF |
367 | if (dma_mapping_error(dev, drv_data->rx_dma)) { |
368 | dma_unmap_single(dev, drv_data->tx_dma, | |
369 | drv_data->tx_map_len, DMA_TO_DEVICE); | |
e0c9905e SS |
370 | return 0; |
371 | } | |
372 | ||
373 | return 1; | |
374 | } | |
375 | ||
376 | static void unmap_dma_buffers(struct driver_data *drv_data) | |
377 | { | |
378 | struct device *dev; | |
379 | ||
380 | if (!drv_data->dma_mapped) | |
381 | return; | |
382 | ||
383 | if (!drv_data->cur_msg->is_dma_mapped) { | |
384 | dev = &drv_data->cur_msg->spi->dev; | |
385 | dma_unmap_single(dev, drv_data->rx_dma, | |
386 | drv_data->rx_map_len, DMA_FROM_DEVICE); | |
387 | dma_unmap_single(dev, drv_data->tx_dma, | |
388 | drv_data->tx_map_len, DMA_TO_DEVICE); | |
389 | } | |
390 | ||
391 | drv_data->dma_mapped = 0; | |
392 | } | |
393 | ||
394 | /* caller already set message->status; dma and pio irqs are blocked */ | |
5daa3ba0 | 395 | static void giveback(struct driver_data *drv_data) |
e0c9905e SS |
396 | { |
397 | struct spi_transfer* last_transfer; | |
5daa3ba0 SS |
398 | unsigned long flags; |
399 | struct spi_message *msg; | |
e0c9905e | 400 | |
5daa3ba0 SS |
401 | spin_lock_irqsave(&drv_data->lock, flags); |
402 | msg = drv_data->cur_msg; | |
403 | drv_data->cur_msg = NULL; | |
404 | drv_data->cur_transfer = NULL; | |
405 | drv_data->cur_chip = NULL; | |
406 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
407 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
408 | ||
409 | last_transfer = list_entry(msg->transfers.prev, | |
e0c9905e SS |
410 | struct spi_transfer, |
411 | transfer_list); | |
412 | ||
8423597d NF |
413 | /* Delay if requested before any change in chip select */ |
414 | if (last_transfer->delay_usecs) | |
415 | udelay(last_transfer->delay_usecs); | |
416 | ||
417 | /* Drop chip select UNLESS cs_change is true or we are returning | |
418 | * a message with an error, or next message is for another chip | |
419 | */ | |
e0c9905e SS |
420 | if (!last_transfer->cs_change) |
421 | drv_data->cs_control(PXA2XX_CS_DEASSERT); | |
8423597d NF |
422 | else { |
423 | struct spi_message *next_msg; | |
424 | ||
425 | /* Holding of cs was hinted, but we need to make sure | |
426 | * the next message is for the same chip. Don't waste | |
427 | * time with the following tests unless this was hinted. | |
428 | * | |
429 | * We cannot postpone this until pump_messages, because | |
430 | * after calling msg->complete (below) the driver that | |
431 | * sent the current message could be unloaded, which | |
432 | * could invalidate the cs_control() callback... | |
433 | */ | |
434 | ||
435 | /* get a pointer to the next message, if any */ | |
436 | spin_lock_irqsave(&drv_data->lock, flags); | |
437 | if (list_empty(&drv_data->queue)) | |
438 | next_msg = NULL; | |
439 | else | |
440 | next_msg = list_entry(drv_data->queue.next, | |
441 | struct spi_message, queue); | |
442 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
443 | ||
444 | /* see if the next and current messages point | |
445 | * to the same chip | |
446 | */ | |
447 | if (next_msg && next_msg->spi != msg->spi) | |
448 | next_msg = NULL; | |
449 | if (!next_msg || msg->state == ERROR_STATE) | |
450 | drv_data->cs_control(PXA2XX_CS_DEASSERT); | |
451 | } | |
e0c9905e | 452 | |
5daa3ba0 SS |
453 | msg->state = NULL; |
454 | if (msg->complete) | |
455 | msg->complete(msg->context); | |
e0c9905e SS |
456 | } |
457 | ||
cf43369d | 458 | static int wait_ssp_rx_stall(void const __iomem *ioaddr) |
e0c9905e SS |
459 | { |
460 | unsigned long limit = loops_per_jiffy << 1; | |
461 | ||
462 | while ((read_SSSR(ioaddr) & SSSR_BSY) && limit--) | |
463 | cpu_relax(); | |
464 | ||
465 | return limit; | |
466 | } | |
467 | ||
468 | static int wait_dma_channel_stop(int channel) | |
469 | { | |
470 | unsigned long limit = loops_per_jiffy << 1; | |
471 | ||
472 | while (!(DCSR(channel) & DCSR_STOPSTATE) && limit--) | |
473 | cpu_relax(); | |
474 | ||
475 | return limit; | |
476 | } | |
477 | ||
cf43369d | 478 | static void dma_error_stop(struct driver_data *drv_data, const char *msg) |
e0c9905e | 479 | { |
cf43369d | 480 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 481 | |
8d94cc50 SS |
482 | /* Stop and reset */ |
483 | DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; | |
484 | DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; | |
485 | write_SSSR(drv_data->clear_sr, reg); | |
486 | write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); | |
487 | if (drv_data->ssp_type != PXA25x_SSP) | |
488 | write_SSTO(0, reg); | |
489 | flush(drv_data); | |
490 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | |
e0c9905e | 491 | |
8d94cc50 | 492 | unmap_dma_buffers(drv_data); |
e0c9905e | 493 | |
8d94cc50 | 494 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 495 | |
8d94cc50 SS |
496 | drv_data->cur_msg->state = ERROR_STATE; |
497 | tasklet_schedule(&drv_data->pump_transfers); | |
498 | } | |
499 | ||
500 | static void dma_transfer_complete(struct driver_data *drv_data) | |
501 | { | |
cf43369d | 502 | void __iomem *reg = drv_data->ioaddr; |
8d94cc50 SS |
503 | struct spi_message *msg = drv_data->cur_msg; |
504 | ||
505 | /* Clear and disable interrupts on SSP and DMA channels*/ | |
506 | write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); | |
507 | write_SSSR(drv_data->clear_sr, reg); | |
508 | DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; | |
509 | DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; | |
510 | ||
511 | if (wait_dma_channel_stop(drv_data->rx_channel) == 0) | |
512 | dev_err(&drv_data->pdev->dev, | |
513 | "dma_handler: dma rx channel stop failed\n"); | |
514 | ||
515 | if (wait_ssp_rx_stall(drv_data->ioaddr) == 0) | |
516 | dev_err(&drv_data->pdev->dev, | |
517 | "dma_transfer: ssp rx stall failed\n"); | |
518 | ||
519 | unmap_dma_buffers(drv_data); | |
520 | ||
521 | /* update the buffer pointer for the amount completed in dma */ | |
522 | drv_data->rx += drv_data->len - | |
523 | (DCMD(drv_data->rx_channel) & DCMD_LENGTH); | |
524 | ||
525 | /* read trailing data from fifo, it does not matter how many | |
526 | * bytes are in the fifo just read until buffer is full | |
527 | * or fifo is empty, which ever occurs first */ | |
528 | drv_data->read(drv_data); | |
529 | ||
530 | /* return count of what was actually read */ | |
531 | msg->actual_length += drv_data->len - | |
532 | (drv_data->rx_end - drv_data->rx); | |
533 | ||
8423597d NF |
534 | /* Transfer delays and chip select release are |
535 | * handled in pump_transfers or giveback | |
536 | */ | |
8d94cc50 SS |
537 | |
538 | /* Move to next transfer */ | |
539 | msg->state = next_transfer(drv_data); | |
540 | ||
541 | /* Schedule transfer tasklet */ | |
542 | tasklet_schedule(&drv_data->pump_transfers); | |
543 | } | |
544 | ||
545 | static void dma_handler(int channel, void *data) | |
546 | { | |
547 | struct driver_data *drv_data = data; | |
548 | u32 irq_status = DCSR(channel) & DMA_INT_MASK; | |
549 | ||
550 | if (irq_status & DCSR_BUSERR) { | |
e0c9905e SS |
551 | |
552 | if (channel == drv_data->tx_channel) | |
8d94cc50 SS |
553 | dma_error_stop(drv_data, |
554 | "dma_handler: " | |
555 | "bad bus address on tx channel"); | |
e0c9905e | 556 | else |
8d94cc50 SS |
557 | dma_error_stop(drv_data, |
558 | "dma_handler: " | |
559 | "bad bus address on rx channel"); | |
560 | return; | |
e0c9905e SS |
561 | } |
562 | ||
563 | /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */ | |
8d94cc50 SS |
564 | if ((channel == drv_data->tx_channel) |
565 | && (irq_status & DCSR_ENDINTR) | |
566 | && (drv_data->ssp_type == PXA25x_SSP)) { | |
e0c9905e SS |
567 | |
568 | /* Wait for rx to stall */ | |
569 | if (wait_ssp_rx_stall(drv_data->ioaddr) == 0) | |
570 | dev_err(&drv_data->pdev->dev, | |
571 | "dma_handler: ssp rx stall failed\n"); | |
572 | ||
8d94cc50 SS |
573 | /* finish this transfer, start the next */ |
574 | dma_transfer_complete(drv_data); | |
e0c9905e SS |
575 | } |
576 | } | |
577 | ||
578 | static irqreturn_t dma_transfer(struct driver_data *drv_data) | |
579 | { | |
580 | u32 irq_status; | |
cf43369d | 581 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
582 | |
583 | irq_status = read_SSSR(reg) & drv_data->mask_sr; | |
584 | if (irq_status & SSSR_ROR) { | |
8d94cc50 | 585 | dma_error_stop(drv_data, "dma_transfer: fifo overrun"); |
e0c9905e SS |
586 | return IRQ_HANDLED; |
587 | } | |
588 | ||
589 | /* Check for false positive timeout */ | |
8d94cc50 SS |
590 | if ((irq_status & SSSR_TINT) |
591 | && (DCSR(drv_data->tx_channel) & DCSR_RUN)) { | |
e0c9905e SS |
592 | write_SSSR(SSSR_TINT, reg); |
593 | return IRQ_HANDLED; | |
594 | } | |
595 | ||
596 | if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) { | |
597 | ||
8d94cc50 SS |
598 | /* Clear and disable timeout interrupt, do the rest in |
599 | * dma_transfer_complete */ | |
e0c9905e SS |
600 | if (drv_data->ssp_type != PXA25x_SSP) |
601 | write_SSTO(0, reg); | |
e0c9905e | 602 | |
8d94cc50 SS |
603 | /* finish this transfer, start the next */ |
604 | dma_transfer_complete(drv_data); | |
e0c9905e SS |
605 | |
606 | return IRQ_HANDLED; | |
607 | } | |
608 | ||
609 | /* Opps problem detected */ | |
610 | return IRQ_NONE; | |
611 | } | |
612 | ||
8d94cc50 | 613 | static void int_error_stop(struct driver_data *drv_data, const char* msg) |
e0c9905e | 614 | { |
cf43369d | 615 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 616 | |
8d94cc50 SS |
617 | /* Stop and reset SSP */ |
618 | write_SSSR(drv_data->clear_sr, reg); | |
619 | write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); | |
620 | if (drv_data->ssp_type != PXA25x_SSP) | |
621 | write_SSTO(0, reg); | |
622 | flush(drv_data); | |
623 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | |
e0c9905e | 624 | |
8d94cc50 | 625 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 626 | |
8d94cc50 SS |
627 | drv_data->cur_msg->state = ERROR_STATE; |
628 | tasklet_schedule(&drv_data->pump_transfers); | |
629 | } | |
5daa3ba0 | 630 | |
8d94cc50 SS |
631 | static void int_transfer_complete(struct driver_data *drv_data) |
632 | { | |
cf43369d | 633 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 634 | |
8d94cc50 SS |
635 | /* Stop SSP */ |
636 | write_SSSR(drv_data->clear_sr, reg); | |
637 | write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); | |
638 | if (drv_data->ssp_type != PXA25x_SSP) | |
639 | write_SSTO(0, reg); | |
e0c9905e | 640 | |
8d94cc50 SS |
641 | /* Update total byte transfered return count actual bytes read */ |
642 | drv_data->cur_msg->actual_length += drv_data->len - | |
643 | (drv_data->rx_end - drv_data->rx); | |
e0c9905e | 644 | |
8423597d NF |
645 | /* Transfer delays and chip select release are |
646 | * handled in pump_transfers or giveback | |
647 | */ | |
e0c9905e | 648 | |
8d94cc50 SS |
649 | /* Move to next transfer */ |
650 | drv_data->cur_msg->state = next_transfer(drv_data); | |
e0c9905e | 651 | |
8d94cc50 SS |
652 | /* Schedule transfer tasklet */ |
653 | tasklet_schedule(&drv_data->pump_transfers); | |
654 | } | |
e0c9905e | 655 | |
8d94cc50 SS |
656 | static irqreturn_t interrupt_transfer(struct driver_data *drv_data) |
657 | { | |
cf43369d | 658 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 659 | |
8d94cc50 SS |
660 | u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ? |
661 | drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; | |
e0c9905e | 662 | |
8d94cc50 | 663 | u32 irq_status = read_SSSR(reg) & irq_mask; |
e0c9905e | 664 | |
8d94cc50 SS |
665 | if (irq_status & SSSR_ROR) { |
666 | int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); | |
667 | return IRQ_HANDLED; | |
668 | } | |
e0c9905e | 669 | |
8d94cc50 SS |
670 | if (irq_status & SSSR_TINT) { |
671 | write_SSSR(SSSR_TINT, reg); | |
672 | if (drv_data->read(drv_data)) { | |
673 | int_transfer_complete(drv_data); | |
674 | return IRQ_HANDLED; | |
675 | } | |
676 | } | |
e0c9905e | 677 | |
8d94cc50 SS |
678 | /* Drain rx fifo, Fill tx fifo and prevent overruns */ |
679 | do { | |
680 | if (drv_data->read(drv_data)) { | |
681 | int_transfer_complete(drv_data); | |
682 | return IRQ_HANDLED; | |
683 | } | |
684 | } while (drv_data->write(drv_data)); | |
e0c9905e | 685 | |
8d94cc50 SS |
686 | if (drv_data->read(drv_data)) { |
687 | int_transfer_complete(drv_data); | |
688 | return IRQ_HANDLED; | |
689 | } | |
e0c9905e | 690 | |
8d94cc50 SS |
691 | if (drv_data->tx == drv_data->tx_end) { |
692 | write_SSCR1(read_SSCR1(reg) & ~SSCR1_TIE, reg); | |
693 | /* PXA25x_SSP has no timeout, read trailing bytes */ | |
694 | if (drv_data->ssp_type == PXA25x_SSP) { | |
695 | if (!wait_ssp_rx_stall(reg)) | |
696 | { | |
697 | int_error_stop(drv_data, "interrupt_transfer: " | |
698 | "rx stall failed"); | |
699 | return IRQ_HANDLED; | |
700 | } | |
701 | if (!drv_data->read(drv_data)) | |
702 | { | |
703 | int_error_stop(drv_data, | |
704 | "interrupt_transfer: " | |
705 | "trailing byte read failed"); | |
706 | return IRQ_HANDLED; | |
707 | } | |
708 | int_transfer_complete(drv_data); | |
e0c9905e | 709 | } |
e0c9905e SS |
710 | } |
711 | ||
5daa3ba0 SS |
712 | /* We did something */ |
713 | return IRQ_HANDLED; | |
e0c9905e SS |
714 | } |
715 | ||
7d12e780 | 716 | static irqreturn_t ssp_int(int irq, void *dev_id) |
e0c9905e | 717 | { |
c7bec5ab | 718 | struct driver_data *drv_data = dev_id; |
cf43369d | 719 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
720 | |
721 | if (!drv_data->cur_msg) { | |
5daa3ba0 SS |
722 | |
723 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | |
724 | write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); | |
725 | if (drv_data->ssp_type != PXA25x_SSP) | |
726 | write_SSTO(0, reg); | |
727 | write_SSSR(drv_data->clear_sr, reg); | |
728 | ||
e0c9905e | 729 | dev_err(&drv_data->pdev->dev, "bad message state " |
8d94cc50 | 730 | "in interrupt handler\n"); |
5daa3ba0 | 731 | |
e0c9905e SS |
732 | /* Never fail */ |
733 | return IRQ_HANDLED; | |
734 | } | |
735 | ||
736 | return drv_data->transfer_handler(drv_data); | |
737 | } | |
738 | ||
cf43369d DB |
739 | static int set_dma_burst_and_threshold(struct chip_data *chip, |
740 | struct spi_device *spi, | |
8d94cc50 SS |
741 | u8 bits_per_word, u32 *burst_code, |
742 | u32 *threshold) | |
743 | { | |
744 | struct pxa2xx_spi_chip *chip_info = | |
745 | (struct pxa2xx_spi_chip *)spi->controller_data; | |
746 | int bytes_per_word; | |
747 | int burst_bytes; | |
748 | int thresh_words; | |
749 | int req_burst_size; | |
750 | int retval = 0; | |
751 | ||
752 | /* Set the threshold (in registers) to equal the same amount of data | |
753 | * as represented by burst size (in bytes). The computation below | |
754 | * is (burst_size rounded up to nearest 8 byte, word or long word) | |
755 | * divided by (bytes/register); the tx threshold is the inverse of | |
756 | * the rx, so that there will always be enough data in the rx fifo | |
757 | * to satisfy a burst, and there will always be enough space in the | |
758 | * tx fifo to accept a burst (a tx burst will overwrite the fifo if | |
759 | * there is not enough space), there must always remain enough empty | |
760 | * space in the rx fifo for any data loaded to the tx fifo. | |
761 | * Whenever burst_size (in bytes) equals bits/word, the fifo threshold | |
762 | * will be 8, or half the fifo; | |
763 | * The threshold can only be set to 2, 4 or 8, but not 16, because | |
764 | * to burst 16 to the tx fifo, the fifo would have to be empty; | |
765 | * however, the minimum fifo trigger level is 1, and the tx will | |
766 | * request service when the fifo is at this level, with only 15 spaces. | |
767 | */ | |
768 | ||
769 | /* find bytes/word */ | |
770 | if (bits_per_word <= 8) | |
771 | bytes_per_word = 1; | |
772 | else if (bits_per_word <= 16) | |
773 | bytes_per_word = 2; | |
774 | else | |
775 | bytes_per_word = 4; | |
776 | ||
777 | /* use struct pxa2xx_spi_chip->dma_burst_size if available */ | |
778 | if (chip_info) | |
779 | req_burst_size = chip_info->dma_burst_size; | |
780 | else { | |
781 | switch (chip->dma_burst_size) { | |
782 | default: | |
783 | /* if the default burst size is not set, | |
784 | * do it now */ | |
785 | chip->dma_burst_size = DCMD_BURST8; | |
786 | case DCMD_BURST8: | |
787 | req_burst_size = 8; | |
788 | break; | |
789 | case DCMD_BURST16: | |
790 | req_burst_size = 16; | |
791 | break; | |
792 | case DCMD_BURST32: | |
793 | req_burst_size = 32; | |
794 | break; | |
795 | } | |
796 | } | |
797 | if (req_burst_size <= 8) { | |
798 | *burst_code = DCMD_BURST8; | |
799 | burst_bytes = 8; | |
800 | } else if (req_burst_size <= 16) { | |
801 | if (bytes_per_word == 1) { | |
802 | /* don't burst more than 1/2 the fifo */ | |
803 | *burst_code = DCMD_BURST8; | |
804 | burst_bytes = 8; | |
805 | retval = 1; | |
806 | } else { | |
807 | *burst_code = DCMD_BURST16; | |
808 | burst_bytes = 16; | |
809 | } | |
810 | } else { | |
811 | if (bytes_per_word == 1) { | |
812 | /* don't burst more than 1/2 the fifo */ | |
813 | *burst_code = DCMD_BURST8; | |
814 | burst_bytes = 8; | |
815 | retval = 1; | |
816 | } else if (bytes_per_word == 2) { | |
817 | /* don't burst more than 1/2 the fifo */ | |
818 | *burst_code = DCMD_BURST16; | |
819 | burst_bytes = 16; | |
820 | retval = 1; | |
821 | } else { | |
822 | *burst_code = DCMD_BURST32; | |
823 | burst_bytes = 32; | |
824 | } | |
825 | } | |
826 | ||
827 | thresh_words = burst_bytes / bytes_per_word; | |
828 | ||
829 | /* thresh_words will be between 2 and 8 */ | |
830 | *threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT) | |
831 | | (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT); | |
832 | ||
833 | return retval; | |
834 | } | |
835 | ||
2f1a74e5 | 836 | static unsigned int ssp_get_clk_div(struct ssp_device *ssp, int rate) |
837 | { | |
838 | unsigned long ssp_clk = clk_get_rate(ssp->clk); | |
839 | ||
840 | if (ssp->type == PXA25x_SSP) | |
841 | return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8; | |
842 | else | |
843 | return ((ssp_clk / rate - 1) & 0xfff) << 8; | |
844 | } | |
845 | ||
e0c9905e SS |
846 | static void pump_transfers(unsigned long data) |
847 | { | |
848 | struct driver_data *drv_data = (struct driver_data *)data; | |
849 | struct spi_message *message = NULL; | |
850 | struct spi_transfer *transfer = NULL; | |
851 | struct spi_transfer *previous = NULL; | |
852 | struct chip_data *chip = NULL; | |
2f1a74e5 | 853 | struct ssp_device *ssp = drv_data->ssp; |
cf43369d | 854 | void __iomem *reg = drv_data->ioaddr; |
9708c121 SS |
855 | u32 clk_div = 0; |
856 | u8 bits = 0; | |
857 | u32 speed = 0; | |
858 | u32 cr0; | |
8d94cc50 SS |
859 | u32 cr1; |
860 | u32 dma_thresh = drv_data->cur_chip->dma_threshold; | |
861 | u32 dma_burst = drv_data->cur_chip->dma_burst_size; | |
e0c9905e SS |
862 | |
863 | /* Get current state information */ | |
864 | message = drv_data->cur_msg; | |
865 | transfer = drv_data->cur_transfer; | |
866 | chip = drv_data->cur_chip; | |
867 | ||
868 | /* Handle for abort */ | |
869 | if (message->state == ERROR_STATE) { | |
870 | message->status = -EIO; | |
5daa3ba0 | 871 | giveback(drv_data); |
e0c9905e SS |
872 | return; |
873 | } | |
874 | ||
875 | /* Handle end of message */ | |
876 | if (message->state == DONE_STATE) { | |
877 | message->status = 0; | |
5daa3ba0 | 878 | giveback(drv_data); |
e0c9905e SS |
879 | return; |
880 | } | |
881 | ||
8423597d | 882 | /* Delay if requested at end of transfer before CS change */ |
e0c9905e SS |
883 | if (message->state == RUNNING_STATE) { |
884 | previous = list_entry(transfer->transfer_list.prev, | |
885 | struct spi_transfer, | |
886 | transfer_list); | |
887 | if (previous->delay_usecs) | |
888 | udelay(previous->delay_usecs); | |
8423597d NF |
889 | |
890 | /* Drop chip select only if cs_change is requested */ | |
891 | if (previous->cs_change) | |
892 | drv_data->cs_control(PXA2XX_CS_DEASSERT); | |
e0c9905e SS |
893 | } |
894 | ||
7e964455 NF |
895 | /* Check for transfers that need multiple DMA segments */ |
896 | if (transfer->len > MAX_DMA_LEN && chip->enable_dma) { | |
897 | ||
898 | /* reject already-mapped transfers; PIO won't always work */ | |
899 | if (message->is_dma_mapped | |
900 | || transfer->rx_dma || transfer->tx_dma) { | |
901 | dev_err(&drv_data->pdev->dev, | |
902 | "pump_transfers: mapped transfer length " | |
20b918dc | 903 | "of %u is greater than %d\n", |
7e964455 NF |
904 | transfer->len, MAX_DMA_LEN); |
905 | message->status = -EINVAL; | |
906 | giveback(drv_data); | |
907 | return; | |
908 | } | |
909 | ||
910 | /* warn ... we force this to PIO mode */ | |
911 | if (printk_ratelimit()) | |
912 | dev_warn(&message->spi->dev, "pump_transfers: " | |
913 | "DMA disabled for transfer length %ld " | |
914 | "greater than %d\n", | |
915 | (long)drv_data->len, MAX_DMA_LEN); | |
8d94cc50 SS |
916 | } |
917 | ||
e0c9905e SS |
918 | /* Setup the transfer state based on the type of transfer */ |
919 | if (flush(drv_data) == 0) { | |
920 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); | |
921 | message->status = -EIO; | |
5daa3ba0 | 922 | giveback(drv_data); |
e0c9905e SS |
923 | return; |
924 | } | |
9708c121 SS |
925 | drv_data->n_bytes = chip->n_bytes; |
926 | drv_data->dma_width = chip->dma_width; | |
e0c9905e SS |
927 | drv_data->cs_control = chip->cs_control; |
928 | drv_data->tx = (void *)transfer->tx_buf; | |
929 | drv_data->tx_end = drv_data->tx + transfer->len; | |
930 | drv_data->rx = transfer->rx_buf; | |
931 | drv_data->rx_end = drv_data->rx + transfer->len; | |
932 | drv_data->rx_dma = transfer->rx_dma; | |
933 | drv_data->tx_dma = transfer->tx_dma; | |
8d94cc50 | 934 | drv_data->len = transfer->len & DCMD_LENGTH; |
e0c9905e SS |
935 | drv_data->write = drv_data->tx ? chip->write : null_writer; |
936 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
9708c121 SS |
937 | |
938 | /* Change speed and bit per word on a per transfer */ | |
8d94cc50 | 939 | cr0 = chip->cr0; |
9708c121 SS |
940 | if (transfer->speed_hz || transfer->bits_per_word) { |
941 | ||
9708c121 SS |
942 | bits = chip->bits_per_word; |
943 | speed = chip->speed_hz; | |
944 | ||
945 | if (transfer->speed_hz) | |
946 | speed = transfer->speed_hz; | |
947 | ||
948 | if (transfer->bits_per_word) | |
949 | bits = transfer->bits_per_word; | |
950 | ||
2f1a74e5 | 951 | clk_div = ssp_get_clk_div(ssp, speed); |
9708c121 SS |
952 | |
953 | if (bits <= 8) { | |
954 | drv_data->n_bytes = 1; | |
955 | drv_data->dma_width = DCMD_WIDTH1; | |
956 | drv_data->read = drv_data->read != null_reader ? | |
957 | u8_reader : null_reader; | |
958 | drv_data->write = drv_data->write != null_writer ? | |
959 | u8_writer : null_writer; | |
960 | } else if (bits <= 16) { | |
961 | drv_data->n_bytes = 2; | |
962 | drv_data->dma_width = DCMD_WIDTH2; | |
963 | drv_data->read = drv_data->read != null_reader ? | |
964 | u16_reader : null_reader; | |
965 | drv_data->write = drv_data->write != null_writer ? | |
966 | u16_writer : null_writer; | |
967 | } else if (bits <= 32) { | |
968 | drv_data->n_bytes = 4; | |
969 | drv_data->dma_width = DCMD_WIDTH4; | |
970 | drv_data->read = drv_data->read != null_reader ? | |
971 | u32_reader : null_reader; | |
972 | drv_data->write = drv_data->write != null_writer ? | |
973 | u32_writer : null_writer; | |
974 | } | |
8d94cc50 SS |
975 | /* if bits/word is changed in dma mode, then must check the |
976 | * thresholds and burst also */ | |
977 | if (chip->enable_dma) { | |
978 | if (set_dma_burst_and_threshold(chip, message->spi, | |
979 | bits, &dma_burst, | |
980 | &dma_thresh)) | |
981 | if (printk_ratelimit()) | |
982 | dev_warn(&message->spi->dev, | |
7e964455 | 983 | "pump_transfers: " |
8d94cc50 SS |
984 | "DMA burst size reduced to " |
985 | "match bits_per_word\n"); | |
986 | } | |
9708c121 SS |
987 | |
988 | cr0 = clk_div | |
989 | | SSCR0_Motorola | |
5daa3ba0 | 990 | | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) |
9708c121 SS |
991 | | SSCR0_SSE |
992 | | (bits > 16 ? SSCR0_EDSS : 0); | |
9708c121 SS |
993 | } |
994 | ||
e0c9905e SS |
995 | message->state = RUNNING_STATE; |
996 | ||
7e964455 NF |
997 | /* Try to map dma buffer and do a dma transfer if successful, but |
998 | * only if the length is non-zero and less than MAX_DMA_LEN. | |
999 | * | |
1000 | * Zero-length non-descriptor DMA is illegal on PXA2xx; force use | |
1001 | * of PIO instead. Care is needed above because the transfer may | |
1002 | * have have been passed with buffers that are already dma mapped. | |
1003 | * A zero-length transfer in PIO mode will not try to write/read | |
1004 | * to/from the buffers | |
1005 | * | |
1006 | * REVISIT large transfers are exactly where we most want to be | |
1007 | * using DMA. If this happens much, split those transfers into | |
1008 | * multiple DMA segments rather than forcing PIO. | |
1009 | */ | |
1010 | drv_data->dma_mapped = 0; | |
1011 | if (drv_data->len > 0 && drv_data->len <= MAX_DMA_LEN) | |
1012 | drv_data->dma_mapped = map_dma_buffers(drv_data); | |
1013 | if (drv_data->dma_mapped) { | |
e0c9905e SS |
1014 | |
1015 | /* Ensure we have the correct interrupt handler */ | |
1016 | drv_data->transfer_handler = dma_transfer; | |
1017 | ||
1018 | /* Setup rx DMA Channel */ | |
1019 | DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; | |
1020 | DSADR(drv_data->rx_channel) = drv_data->ssdr_physical; | |
1021 | DTADR(drv_data->rx_channel) = drv_data->rx_dma; | |
1022 | if (drv_data->rx == drv_data->null_dma_buf) | |
1023 | /* No target address increment */ | |
1024 | DCMD(drv_data->rx_channel) = DCMD_FLOWSRC | |
9708c121 | 1025 | | drv_data->dma_width |
8d94cc50 | 1026 | | dma_burst |
e0c9905e SS |
1027 | | drv_data->len; |
1028 | else | |
1029 | DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR | |
1030 | | DCMD_FLOWSRC | |
9708c121 | 1031 | | drv_data->dma_width |
8d94cc50 | 1032 | | dma_burst |
e0c9905e SS |
1033 | | drv_data->len; |
1034 | ||
1035 | /* Setup tx DMA Channel */ | |
1036 | DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; | |
1037 | DSADR(drv_data->tx_channel) = drv_data->tx_dma; | |
1038 | DTADR(drv_data->tx_channel) = drv_data->ssdr_physical; | |
1039 | if (drv_data->tx == drv_data->null_dma_buf) | |
1040 | /* No source address increment */ | |
1041 | DCMD(drv_data->tx_channel) = DCMD_FLOWTRG | |
9708c121 | 1042 | | drv_data->dma_width |
8d94cc50 | 1043 | | dma_burst |
e0c9905e SS |
1044 | | drv_data->len; |
1045 | else | |
1046 | DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR | |
1047 | | DCMD_FLOWTRG | |
9708c121 | 1048 | | drv_data->dma_width |
8d94cc50 | 1049 | | dma_burst |
e0c9905e SS |
1050 | | drv_data->len; |
1051 | ||
1052 | /* Enable dma end irqs on SSP to detect end of transfer */ | |
1053 | if (drv_data->ssp_type == PXA25x_SSP) | |
1054 | DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN; | |
1055 | ||
8d94cc50 SS |
1056 | /* Clear status and start DMA engine */ |
1057 | cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; | |
e0c9905e SS |
1058 | write_SSSR(drv_data->clear_sr, reg); |
1059 | DCSR(drv_data->rx_channel) |= DCSR_RUN; | |
1060 | DCSR(drv_data->tx_channel) |= DCSR_RUN; | |
e0c9905e SS |
1061 | } else { |
1062 | /* Ensure we have the correct interrupt handler */ | |
1063 | drv_data->transfer_handler = interrupt_transfer; | |
1064 | ||
8d94cc50 SS |
1065 | /* Clear status */ |
1066 | cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; | |
e0c9905e | 1067 | write_SSSR(drv_data->clear_sr, reg); |
8d94cc50 SS |
1068 | } |
1069 | ||
1070 | /* see if we need to reload the config registers */ | |
1071 | if ((read_SSCR0(reg) != cr0) | |
1072 | || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) != | |
1073 | (cr1 & SSCR1_CHANGE_MASK)) { | |
1074 | ||
b97c74bd | 1075 | /* stop the SSP, and update the other bits */ |
8d94cc50 | 1076 | write_SSCR0(cr0 & ~SSCR0_SSE, reg); |
e0c9905e SS |
1077 | if (drv_data->ssp_type != PXA25x_SSP) |
1078 | write_SSTO(chip->timeout, reg); | |
b97c74bd NF |
1079 | /* first set CR1 without interrupt and service enables */ |
1080 | write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg); | |
1081 | /* restart the SSP */ | |
8d94cc50 | 1082 | write_SSCR0(cr0, reg); |
b97c74bd | 1083 | |
8d94cc50 SS |
1084 | } else { |
1085 | if (drv_data->ssp_type != PXA25x_SSP) | |
1086 | write_SSTO(chip->timeout, reg); | |
e0c9905e | 1087 | } |
b97c74bd NF |
1088 | |
1089 | /* FIXME, need to handle cs polarity, | |
1090 | * this driver uses struct pxa2xx_spi_chip.cs_control to | |
1091 | * specify a CS handling function, and it ignores most | |
1092 | * struct spi_device.mode[s], including SPI_CS_HIGH */ | |
1093 | drv_data->cs_control(PXA2XX_CS_ASSERT); | |
1094 | ||
1095 | /* after chip select, release the data by enabling service | |
1096 | * requests and interrupts, without changing any mode bits */ | |
1097 | write_SSCR1(cr1, reg); | |
e0c9905e SS |
1098 | } |
1099 | ||
6d5aefb8 | 1100 | static void pump_messages(struct work_struct *work) |
e0c9905e | 1101 | { |
6d5aefb8 DH |
1102 | struct driver_data *drv_data = |
1103 | container_of(work, struct driver_data, pump_messages); | |
e0c9905e SS |
1104 | unsigned long flags; |
1105 | ||
1106 | /* Lock queue and check for queue work */ | |
1107 | spin_lock_irqsave(&drv_data->lock, flags); | |
1108 | if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) { | |
1109 | drv_data->busy = 0; | |
1110 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1111 | return; | |
1112 | } | |
1113 | ||
1114 | /* Make sure we are not already running a message */ | |
1115 | if (drv_data->cur_msg) { | |
1116 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1117 | return; | |
1118 | } | |
1119 | ||
1120 | /* Extract head of queue */ | |
1121 | drv_data->cur_msg = list_entry(drv_data->queue.next, | |
1122 | struct spi_message, queue); | |
1123 | list_del_init(&drv_data->cur_msg->queue); | |
e0c9905e SS |
1124 | |
1125 | /* Initial message state*/ | |
1126 | drv_data->cur_msg->state = START_STATE; | |
1127 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
1128 | struct spi_transfer, | |
1129 | transfer_list); | |
1130 | ||
8d94cc50 SS |
1131 | /* prepare to setup the SSP, in pump_transfers, using the per |
1132 | * chip configuration */ | |
e0c9905e | 1133 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); |
e0c9905e SS |
1134 | |
1135 | /* Mark as busy and launch transfers */ | |
1136 | tasklet_schedule(&drv_data->pump_transfers); | |
5daa3ba0 SS |
1137 | |
1138 | drv_data->busy = 1; | |
1139 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
e0c9905e SS |
1140 | } |
1141 | ||
1142 | static int transfer(struct spi_device *spi, struct spi_message *msg) | |
1143 | { | |
1144 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
1145 | unsigned long flags; | |
1146 | ||
1147 | spin_lock_irqsave(&drv_data->lock, flags); | |
1148 | ||
1149 | if (drv_data->run == QUEUE_STOPPED) { | |
1150 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1151 | return -ESHUTDOWN; | |
1152 | } | |
1153 | ||
1154 | msg->actual_length = 0; | |
1155 | msg->status = -EINPROGRESS; | |
1156 | msg->state = START_STATE; | |
1157 | ||
1158 | list_add_tail(&msg->queue, &drv_data->queue); | |
1159 | ||
1160 | if (drv_data->run == QUEUE_RUNNING && !drv_data->busy) | |
1161 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
1162 | ||
1163 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1164 | ||
1165 | return 0; | |
1166 | } | |
1167 | ||
dccd573b DB |
1168 | /* the spi->mode bits understood by this driver: */ |
1169 | #define MODEBITS (SPI_CPOL | SPI_CPHA) | |
1170 | ||
e0c9905e SS |
1171 | static int setup(struct spi_device *spi) |
1172 | { | |
1173 | struct pxa2xx_spi_chip *chip_info = NULL; | |
1174 | struct chip_data *chip; | |
1175 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
2f1a74e5 | 1176 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e | 1177 | unsigned int clk_div; |
f1f640a9 VS |
1178 | uint tx_thres = TX_THRESH_DFLT; |
1179 | uint rx_thres = RX_THRESH_DFLT; | |
e0c9905e SS |
1180 | |
1181 | if (!spi->bits_per_word) | |
1182 | spi->bits_per_word = 8; | |
1183 | ||
1184 | if (drv_data->ssp_type != PXA25x_SSP | |
8d94cc50 SS |
1185 | && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) { |
1186 | dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " | |
1187 | "b/w not 4-32 for type non-PXA25x_SSP\n", | |
1188 | drv_data->ssp_type, spi->bits_per_word); | |
e0c9905e | 1189 | return -EINVAL; |
8d94cc50 SS |
1190 | } |
1191 | else if (drv_data->ssp_type == PXA25x_SSP | |
1192 | && (spi->bits_per_word < 4 | |
1193 | || spi->bits_per_word > 16)) { | |
1194 | dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " | |
1195 | "b/w not 4-16 for type PXA25x_SSP\n", | |
1196 | drv_data->ssp_type, spi->bits_per_word); | |
e0c9905e | 1197 | return -EINVAL; |
8d94cc50 | 1198 | } |
e0c9905e | 1199 | |
dccd573b DB |
1200 | if (spi->mode & ~MODEBITS) { |
1201 | dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n", | |
1202 | spi->mode & ~MODEBITS); | |
1203 | return -EINVAL; | |
1204 | } | |
1205 | ||
8d94cc50 | 1206 | /* Only alloc on first setup */ |
e0c9905e | 1207 | chip = spi_get_ctldata(spi); |
8d94cc50 | 1208 | if (!chip) { |
e0c9905e | 1209 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
8d94cc50 SS |
1210 | if (!chip) { |
1211 | dev_err(&spi->dev, | |
1212 | "failed setup: can't allocate chip data\n"); | |
e0c9905e | 1213 | return -ENOMEM; |
8d94cc50 | 1214 | } |
e0c9905e SS |
1215 | |
1216 | chip->cs_control = null_cs_control; | |
1217 | chip->enable_dma = 0; | |
f1f640a9 | 1218 | chip->timeout = TIMOUT_DFLT; |
e0c9905e SS |
1219 | chip->dma_burst_size = drv_data->master_info->enable_dma ? |
1220 | DCMD_BURST8 : 0; | |
e0c9905e SS |
1221 | } |
1222 | ||
8d94cc50 SS |
1223 | /* protocol drivers may change the chip settings, so... |
1224 | * if chip_info exists, use it */ | |
1225 | chip_info = spi->controller_data; | |
1226 | ||
e0c9905e | 1227 | /* chip_info isn't always needed */ |
8d94cc50 | 1228 | chip->cr1 = 0; |
e0c9905e SS |
1229 | if (chip_info) { |
1230 | if (chip_info->cs_control) | |
1231 | chip->cs_control = chip_info->cs_control; | |
f1f640a9 VS |
1232 | if (chip_info->timeout) |
1233 | chip->timeout = chip_info->timeout; | |
1234 | if (chip_info->tx_threshold) | |
1235 | tx_thres = chip_info->tx_threshold; | |
1236 | if (chip_info->rx_threshold) | |
1237 | rx_thres = chip_info->rx_threshold; | |
1238 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e | 1239 | chip->dma_threshold = 0; |
e0c9905e SS |
1240 | if (chip_info->enable_loopback) |
1241 | chip->cr1 = SSCR1_LBM; | |
1242 | } | |
1243 | ||
f1f640a9 VS |
1244 | chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | |
1245 | (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); | |
1246 | ||
8d94cc50 SS |
1247 | /* set dma burst and threshold outside of chip_info path so that if |
1248 | * chip_info goes away after setting chip->enable_dma, the | |
1249 | * burst and threshold can still respond to changes in bits_per_word */ | |
1250 | if (chip->enable_dma) { | |
1251 | /* set up legal burst and threshold for dma */ | |
1252 | if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word, | |
1253 | &chip->dma_burst_size, | |
1254 | &chip->dma_threshold)) { | |
1255 | dev_warn(&spi->dev, "in setup: DMA burst size reduced " | |
1256 | "to match bits_per_word\n"); | |
1257 | } | |
1258 | } | |
1259 | ||
2f1a74e5 | 1260 | clk_div = ssp_get_clk_div(ssp, spi->max_speed_hz); |
9708c121 | 1261 | chip->speed_hz = spi->max_speed_hz; |
e0c9905e SS |
1262 | |
1263 | chip->cr0 = clk_div | |
1264 | | SSCR0_Motorola | |
5daa3ba0 SS |
1265 | | SSCR0_DataSize(spi->bits_per_word > 16 ? |
1266 | spi->bits_per_word - 16 : spi->bits_per_word) | |
e0c9905e SS |
1267 | | SSCR0_SSE |
1268 | | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0); | |
7f6ee1ad JC |
1269 | chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); |
1270 | chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) | |
1271 | | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); | |
e0c9905e SS |
1272 | |
1273 | /* NOTE: PXA25x_SSP _could_ use external clocking ... */ | |
1274 | if (drv_data->ssp_type != PXA25x_SSP) | |
f1f640a9 | 1275 | dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d, %s\n", |
e0c9905e | 1276 | spi->bits_per_word, |
2f1a74e5 | 1277 | clk_get_rate(ssp->clk) |
e0c9905e | 1278 | / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)), |
f1f640a9 VS |
1279 | spi->mode & 0x3, |
1280 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e | 1281 | else |
f1f640a9 | 1282 | dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d, %s\n", |
e0c9905e | 1283 | spi->bits_per_word, |
f1f640a9 | 1284 | clk_get_rate(ssp->clk) / 2 |
e0c9905e | 1285 | / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)), |
f1f640a9 VS |
1286 | spi->mode & 0x3, |
1287 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e SS |
1288 | |
1289 | if (spi->bits_per_word <= 8) { | |
1290 | chip->n_bytes = 1; | |
1291 | chip->dma_width = DCMD_WIDTH1; | |
1292 | chip->read = u8_reader; | |
1293 | chip->write = u8_writer; | |
1294 | } else if (spi->bits_per_word <= 16) { | |
1295 | chip->n_bytes = 2; | |
1296 | chip->dma_width = DCMD_WIDTH2; | |
1297 | chip->read = u16_reader; | |
1298 | chip->write = u16_writer; | |
1299 | } else if (spi->bits_per_word <= 32) { | |
1300 | chip->cr0 |= SSCR0_EDSS; | |
1301 | chip->n_bytes = 4; | |
1302 | chip->dma_width = DCMD_WIDTH4; | |
1303 | chip->read = u32_reader; | |
1304 | chip->write = u32_writer; | |
1305 | } else { | |
1306 | dev_err(&spi->dev, "invalid wordsize\n"); | |
e0c9905e SS |
1307 | return -ENODEV; |
1308 | } | |
9708c121 | 1309 | chip->bits_per_word = spi->bits_per_word; |
e0c9905e SS |
1310 | |
1311 | spi_set_ctldata(spi, chip); | |
1312 | ||
1313 | return 0; | |
1314 | } | |
1315 | ||
0ffa0285 | 1316 | static void cleanup(struct spi_device *spi) |
e0c9905e | 1317 | { |
0ffa0285 | 1318 | struct chip_data *chip = spi_get_ctldata(spi); |
e0c9905e SS |
1319 | |
1320 | kfree(chip); | |
1321 | } | |
1322 | ||
d1e44d9c | 1323 | static int __init init_queue(struct driver_data *drv_data) |
e0c9905e SS |
1324 | { |
1325 | INIT_LIST_HEAD(&drv_data->queue); | |
1326 | spin_lock_init(&drv_data->lock); | |
1327 | ||
1328 | drv_data->run = QUEUE_STOPPED; | |
1329 | drv_data->busy = 0; | |
1330 | ||
1331 | tasklet_init(&drv_data->pump_transfers, | |
1332 | pump_transfers, (unsigned long)drv_data); | |
1333 | ||
6d5aefb8 | 1334 | INIT_WORK(&drv_data->pump_messages, pump_messages); |
e0c9905e | 1335 | drv_data->workqueue = create_singlethread_workqueue( |
49dce689 | 1336 | drv_data->master->dev.parent->bus_id); |
e0c9905e SS |
1337 | if (drv_data->workqueue == NULL) |
1338 | return -EBUSY; | |
1339 | ||
1340 | return 0; | |
1341 | } | |
1342 | ||
1343 | static int start_queue(struct driver_data *drv_data) | |
1344 | { | |
1345 | unsigned long flags; | |
1346 | ||
1347 | spin_lock_irqsave(&drv_data->lock, flags); | |
1348 | ||
1349 | if (drv_data->run == QUEUE_RUNNING || drv_data->busy) { | |
1350 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1351 | return -EBUSY; | |
1352 | } | |
1353 | ||
1354 | drv_data->run = QUEUE_RUNNING; | |
1355 | drv_data->cur_msg = NULL; | |
1356 | drv_data->cur_transfer = NULL; | |
1357 | drv_data->cur_chip = NULL; | |
1358 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1359 | ||
1360 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
1361 | ||
1362 | return 0; | |
1363 | } | |
1364 | ||
1365 | static int stop_queue(struct driver_data *drv_data) | |
1366 | { | |
1367 | unsigned long flags; | |
1368 | unsigned limit = 500; | |
1369 | int status = 0; | |
1370 | ||
1371 | spin_lock_irqsave(&drv_data->lock, flags); | |
1372 | ||
1373 | /* This is a bit lame, but is optimized for the common execution path. | |
1374 | * A wait_queue on the drv_data->busy could be used, but then the common | |
1375 | * execution path (pump_messages) would be required to call wake_up or | |
1376 | * friends on every SPI message. Do this instead */ | |
1377 | drv_data->run = QUEUE_STOPPED; | |
1378 | while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) { | |
1379 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1380 | msleep(10); | |
1381 | spin_lock_irqsave(&drv_data->lock, flags); | |
1382 | } | |
1383 | ||
1384 | if (!list_empty(&drv_data->queue) || drv_data->busy) | |
1385 | status = -EBUSY; | |
1386 | ||
1387 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1388 | ||
1389 | return status; | |
1390 | } | |
1391 | ||
1392 | static int destroy_queue(struct driver_data *drv_data) | |
1393 | { | |
1394 | int status; | |
1395 | ||
1396 | status = stop_queue(drv_data); | |
8d94cc50 SS |
1397 | /* we are unloading the module or failing to load (only two calls |
1398 | * to this routine), and neither call can handle a return value. | |
1399 | * However, destroy_workqueue calls flush_workqueue, and that will | |
1400 | * block until all work is done. If the reason that stop_queue | |
1401 | * timed out is that the work will never finish, then it does no | |
1402 | * good to call destroy_workqueue, so return anyway. */ | |
e0c9905e SS |
1403 | if (status != 0) |
1404 | return status; | |
1405 | ||
1406 | destroy_workqueue(drv_data->workqueue); | |
1407 | ||
1408 | return 0; | |
1409 | } | |
1410 | ||
d1e44d9c | 1411 | static int __init pxa2xx_spi_probe(struct platform_device *pdev) |
e0c9905e SS |
1412 | { |
1413 | struct device *dev = &pdev->dev; | |
1414 | struct pxa2xx_spi_master *platform_info; | |
1415 | struct spi_master *master; | |
65a00a20 | 1416 | struct driver_data *drv_data; |
2f1a74e5 | 1417 | struct ssp_device *ssp; |
65a00a20 | 1418 | int status; |
e0c9905e SS |
1419 | |
1420 | platform_info = dev->platform_data; | |
1421 | ||
2f1a74e5 | 1422 | ssp = ssp_request(pdev->id, pdev->name); |
1423 | if (ssp == NULL) { | |
1424 | dev_err(&pdev->dev, "failed to request SSP%d\n", pdev->id); | |
e0c9905e SS |
1425 | return -ENODEV; |
1426 | } | |
1427 | ||
1428 | /* Allocate master with space for drv_data and null dma buffer */ | |
1429 | master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); | |
1430 | if (!master) { | |
65a00a20 | 1431 | dev_err(&pdev->dev, "cannot alloc spi_master\n"); |
2f1a74e5 | 1432 | ssp_free(ssp); |
e0c9905e SS |
1433 | return -ENOMEM; |
1434 | } | |
1435 | drv_data = spi_master_get_devdata(master); | |
1436 | drv_data->master = master; | |
1437 | drv_data->master_info = platform_info; | |
1438 | drv_data->pdev = pdev; | |
2f1a74e5 | 1439 | drv_data->ssp = ssp; |
e0c9905e SS |
1440 | |
1441 | master->bus_num = pdev->id; | |
1442 | master->num_chipselect = platform_info->num_chipselect; | |
1443 | master->cleanup = cleanup; | |
1444 | master->setup = setup; | |
1445 | master->transfer = transfer; | |
1446 | ||
2f1a74e5 | 1447 | drv_data->ssp_type = ssp->type; |
e0c9905e SS |
1448 | drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data + |
1449 | sizeof(struct driver_data)), 8); | |
1450 | ||
2f1a74e5 | 1451 | drv_data->ioaddr = ssp->mmio_base; |
1452 | drv_data->ssdr_physical = ssp->phys_base + SSDR; | |
1453 | if (ssp->type == PXA25x_SSP) { | |
e0c9905e SS |
1454 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; |
1455 | drv_data->dma_cr1 = 0; | |
1456 | drv_data->clear_sr = SSSR_ROR; | |
1457 | drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1458 | } else { | |
1459 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; | |
1460 | drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE; | |
1461 | drv_data->clear_sr = SSSR_ROR | SSSR_TINT; | |
1462 | drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1463 | } | |
1464 | ||
2f1a74e5 | 1465 | status = request_irq(ssp->irq, ssp_int, 0, dev->bus_id, drv_data); |
e0c9905e | 1466 | if (status < 0) { |
65a00a20 | 1467 | dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); |
e0c9905e SS |
1468 | goto out_error_master_alloc; |
1469 | } | |
1470 | ||
1471 | /* Setup DMA if requested */ | |
1472 | drv_data->tx_channel = -1; | |
1473 | drv_data->rx_channel = -1; | |
1474 | if (platform_info->enable_dma) { | |
1475 | ||
1476 | /* Get two DMA channels (rx and tx) */ | |
1477 | drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx", | |
1478 | DMA_PRIO_HIGH, | |
1479 | dma_handler, | |
1480 | drv_data); | |
1481 | if (drv_data->rx_channel < 0) { | |
1482 | dev_err(dev, "problem (%d) requesting rx channel\n", | |
1483 | drv_data->rx_channel); | |
1484 | status = -ENODEV; | |
1485 | goto out_error_irq_alloc; | |
1486 | } | |
1487 | drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx", | |
1488 | DMA_PRIO_MEDIUM, | |
1489 | dma_handler, | |
1490 | drv_data); | |
1491 | if (drv_data->tx_channel < 0) { | |
1492 | dev_err(dev, "problem (%d) requesting tx channel\n", | |
1493 | drv_data->tx_channel); | |
1494 | status = -ENODEV; | |
1495 | goto out_error_dma_alloc; | |
1496 | } | |
1497 | ||
2f1a74e5 | 1498 | DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel; |
1499 | DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel; | |
e0c9905e SS |
1500 | } |
1501 | ||
1502 | /* Enable SOC clock */ | |
2f1a74e5 | 1503 | clk_enable(ssp->clk); |
e0c9905e SS |
1504 | |
1505 | /* Load default SSP configuration */ | |
1506 | write_SSCR0(0, drv_data->ioaddr); | |
f1f640a9 VS |
1507 | write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) | |
1508 | SSCR1_TxTresh(TX_THRESH_DFLT), | |
1509 | drv_data->ioaddr); | |
e0c9905e SS |
1510 | write_SSCR0(SSCR0_SerClkDiv(2) |
1511 | | SSCR0_Motorola | |
1512 | | SSCR0_DataSize(8), | |
1513 | drv_data->ioaddr); | |
1514 | if (drv_data->ssp_type != PXA25x_SSP) | |
1515 | write_SSTO(0, drv_data->ioaddr); | |
1516 | write_SSPSP(0, drv_data->ioaddr); | |
1517 | ||
1518 | /* Initial and start queue */ | |
1519 | status = init_queue(drv_data); | |
1520 | if (status != 0) { | |
1521 | dev_err(&pdev->dev, "problem initializing queue\n"); | |
1522 | goto out_error_clock_enabled; | |
1523 | } | |
1524 | status = start_queue(drv_data); | |
1525 | if (status != 0) { | |
1526 | dev_err(&pdev->dev, "problem starting queue\n"); | |
1527 | goto out_error_clock_enabled; | |
1528 | } | |
1529 | ||
1530 | /* Register with the SPI framework */ | |
1531 | platform_set_drvdata(pdev, drv_data); | |
1532 | status = spi_register_master(master); | |
1533 | if (status != 0) { | |
1534 | dev_err(&pdev->dev, "problem registering spi master\n"); | |
1535 | goto out_error_queue_alloc; | |
1536 | } | |
1537 | ||
1538 | return status; | |
1539 | ||
1540 | out_error_queue_alloc: | |
1541 | destroy_queue(drv_data); | |
1542 | ||
1543 | out_error_clock_enabled: | |
2f1a74e5 | 1544 | clk_disable(ssp->clk); |
e0c9905e SS |
1545 | |
1546 | out_error_dma_alloc: | |
1547 | if (drv_data->tx_channel != -1) | |
1548 | pxa_free_dma(drv_data->tx_channel); | |
1549 | if (drv_data->rx_channel != -1) | |
1550 | pxa_free_dma(drv_data->rx_channel); | |
1551 | ||
1552 | out_error_irq_alloc: | |
2f1a74e5 | 1553 | free_irq(ssp->irq, drv_data); |
e0c9905e SS |
1554 | |
1555 | out_error_master_alloc: | |
1556 | spi_master_put(master); | |
2f1a74e5 | 1557 | ssp_free(ssp); |
e0c9905e SS |
1558 | return status; |
1559 | } | |
1560 | ||
1561 | static int pxa2xx_spi_remove(struct platform_device *pdev) | |
1562 | { | |
1563 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
51e911e2 | 1564 | struct ssp_device *ssp; |
e0c9905e SS |
1565 | int status = 0; |
1566 | ||
1567 | if (!drv_data) | |
1568 | return 0; | |
51e911e2 | 1569 | ssp = drv_data->ssp; |
e0c9905e SS |
1570 | |
1571 | /* Remove the queue */ | |
1572 | status = destroy_queue(drv_data); | |
1573 | if (status != 0) | |
8d94cc50 SS |
1574 | /* the kernel does not check the return status of this |
1575 | * this routine (mod->exit, within the kernel). Therefore | |
1576 | * nothing is gained by returning from here, the module is | |
1577 | * going away regardless, and we should not leave any more | |
1578 | * resources allocated than necessary. We cannot free the | |
1579 | * message memory in drv_data->queue, but we can release the | |
1580 | * resources below. I think the kernel should honor -EBUSY | |
1581 | * returns but... */ | |
1582 | dev_err(&pdev->dev, "pxa2xx_spi_remove: workqueue will not " | |
1583 | "complete, message memory not freed\n"); | |
e0c9905e SS |
1584 | |
1585 | /* Disable the SSP at the peripheral and SOC level */ | |
1586 | write_SSCR0(0, drv_data->ioaddr); | |
2f1a74e5 | 1587 | clk_disable(ssp->clk); |
e0c9905e SS |
1588 | |
1589 | /* Release DMA */ | |
1590 | if (drv_data->master_info->enable_dma) { | |
2f1a74e5 | 1591 | DRCMR(ssp->drcmr_rx) = 0; |
1592 | DRCMR(ssp->drcmr_tx) = 0; | |
e0c9905e SS |
1593 | pxa_free_dma(drv_data->tx_channel); |
1594 | pxa_free_dma(drv_data->rx_channel); | |
1595 | } | |
1596 | ||
1597 | /* Release IRQ */ | |
2f1a74e5 | 1598 | free_irq(ssp->irq, drv_data); |
1599 | ||
1600 | /* Release SSP */ | |
1601 | ssp_free(ssp); | |
e0c9905e SS |
1602 | |
1603 | /* Disconnect from the SPI framework */ | |
1604 | spi_unregister_master(drv_data->master); | |
1605 | ||
1606 | /* Prevent double remove */ | |
1607 | platform_set_drvdata(pdev, NULL); | |
1608 | ||
1609 | return 0; | |
1610 | } | |
1611 | ||
1612 | static void pxa2xx_spi_shutdown(struct platform_device *pdev) | |
1613 | { | |
1614 | int status = 0; | |
1615 | ||
1616 | if ((status = pxa2xx_spi_remove(pdev)) != 0) | |
1617 | dev_err(&pdev->dev, "shutdown failed with %d\n", status); | |
1618 | } | |
1619 | ||
1620 | #ifdef CONFIG_PM | |
e0c9905e SS |
1621 | |
1622 | static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state) | |
1623 | { | |
1624 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
2f1a74e5 | 1625 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1626 | int status = 0; |
1627 | ||
e0c9905e SS |
1628 | status = stop_queue(drv_data); |
1629 | if (status != 0) | |
1630 | return status; | |
1631 | write_SSCR0(0, drv_data->ioaddr); | |
2f1a74e5 | 1632 | clk_disable(ssp->clk); |
e0c9905e SS |
1633 | |
1634 | return 0; | |
1635 | } | |
1636 | ||
1637 | static int pxa2xx_spi_resume(struct platform_device *pdev) | |
1638 | { | |
1639 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
2f1a74e5 | 1640 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1641 | int status = 0; |
1642 | ||
1643 | /* Enable the SSP clock */ | |
0cf942d7 | 1644 | clk_enable(ssp->clk); |
e0c9905e SS |
1645 | |
1646 | /* Start the queue running */ | |
1647 | status = start_queue(drv_data); | |
1648 | if (status != 0) { | |
1649 | dev_err(&pdev->dev, "problem starting queue (%d)\n", status); | |
1650 | return status; | |
1651 | } | |
1652 | ||
1653 | return 0; | |
1654 | } | |
1655 | #else | |
1656 | #define pxa2xx_spi_suspend NULL | |
1657 | #define pxa2xx_spi_resume NULL | |
1658 | #endif /* CONFIG_PM */ | |
1659 | ||
1660 | static struct platform_driver driver = { | |
1661 | .driver = { | |
1662 | .name = "pxa2xx-spi", | |
e0c9905e SS |
1663 | .owner = THIS_MODULE, |
1664 | }, | |
d1e44d9c | 1665 | .remove = pxa2xx_spi_remove, |
e0c9905e SS |
1666 | .shutdown = pxa2xx_spi_shutdown, |
1667 | .suspend = pxa2xx_spi_suspend, | |
1668 | .resume = pxa2xx_spi_resume, | |
1669 | }; | |
1670 | ||
1671 | static int __init pxa2xx_spi_init(void) | |
1672 | { | |
d1e44d9c | 1673 | return platform_driver_probe(&driver, pxa2xx_spi_probe); |
e0c9905e SS |
1674 | } |
1675 | module_init(pxa2xx_spi_init); | |
1676 | ||
1677 | static void __exit pxa2xx_spi_exit(void) | |
1678 | { | |
1679 | platform_driver_unregister(&driver); | |
1680 | } | |
1681 | module_exit(pxa2xx_spi_exit); |