[linux-2.6-block.git] / drivers / spi / atmel-quadspi.c

/*
 * Driver for Atmel QSPI Controller
 *
 * Copyright (C) 2015 Atmel Corporation
 * Copyright (C) 2018 Cryptera A/S
 *
 * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
 * Author: Piotr Bugalski <bugalski.piotr@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/spi/spi-mem.h>

/* QSPI register offsets */
#define QSPI_CR      0x0000  /* Control Register */
#define QSPI_MR      0x0004  /* Mode Register */
#define QSPI_RD      0x0008  /* Receive Data Register */
#define QSPI_TD      0x000c  /* Transmit Data Register */
#define QSPI_SR      0x0010  /* Status Register */
#define QSPI_IER     0x0014  /* Interrupt Enable Register */
#define QSPI_IDR     0x0018  /* Interrupt Disable Register */
#define QSPI_IMR     0x001c  /* Interrupt Mask Register */
#define QSPI_SCR     0x0020  /* Serial Clock Register */

#define QSPI_IAR     0x0030  /* Instruction Address Register */
#define QSPI_ICR     0x0034  /* Instruction Code Register */
#define QSPI_IFR     0x0038  /* Instruction Frame Register */

#define QSPI_SMR     0x0040  /* Scrambling Mode Register */
#define QSPI_SKR     0x0044  /* Scrambling Key Register */

#define QSPI_WPMR    0x00E4  /* Write Protection Mode Register */
#define QSPI_WPSR    0x00E8  /* Write Protection Status Register */

#define QSPI_VERSION 0x00FC  /* Version Register */


/* Bitfields in QSPI_CR (Control Register) */
#define QSPI_CR_QSPIEN                  BIT(0)
#define QSPI_CR_QSPIDIS                 BIT(1)
#define QSPI_CR_SWRST                   BIT(7)
#define QSPI_CR_LASTXFER                BIT(24)

/* Bitfields in QSPI_MR (Mode Register) */
#define QSPI_MR_SMM                     BIT(0)
#define QSPI_MR_LLB                     BIT(1)
#define QSPI_MR_WDRBT                   BIT(2)
#define QSPI_MR_SMRM                    BIT(3)
#define QSPI_MR_CSMODE_MASK             GENMASK(5, 4)
#define QSPI_MR_CSMODE_NOT_RELOADED     (0 << 4)
#define QSPI_MR_CSMODE_LASTXFER         (1 << 4)
#define QSPI_MR_CSMODE_SYSTEMATICALLY   (2 << 4)
#define QSPI_MR_NBBITS_MASK             GENMASK(11, 8)
#define QSPI_MR_NBBITS(n)               ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
#define QSPI_MR_DLYBCT_MASK             GENMASK(23, 16)
#define QSPI_MR_DLYBCT(n)               (((n) << 16) & QSPI_MR_DLYBCT_MASK)
#define QSPI_MR_DLYCS_MASK              GENMASK(31, 24)
#define QSPI_MR_DLYCS(n)                (((n) << 24) & QSPI_MR_DLYCS_MASK)

/* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR  */
#define QSPI_SR_RDRF                    BIT(0)
#define QSPI_SR_TDRE                    BIT(1)
#define QSPI_SR_TXEMPTY                 BIT(2)
#define QSPI_SR_OVRES                   BIT(3)
#define QSPI_SR_CSR                     BIT(8)
#define QSPI_SR_CSS                     BIT(9)
#define QSPI_SR_INSTRE                  BIT(10)
#define QSPI_SR_QSPIENS                 BIT(24)

#define QSPI_SR_CMD_COMPLETED	(QSPI_SR_INSTRE | QSPI_SR_CSR)

/* Bitfields in QSPI_SCR (Serial Clock Register) */
#define QSPI_SCR_CPOL                   BIT(0)
#define QSPI_SCR_CPHA                   BIT(1)
#define QSPI_SCR_SCBR_MASK              GENMASK(15, 8)
#define QSPI_SCR_SCBR(n)                (((n) << 8) & QSPI_SCR_SCBR_MASK)
#define QSPI_SCR_DLYBS_MASK             GENMASK(23, 16)
#define QSPI_SCR_DLYBS(n)               (((n) << 16) & QSPI_SCR_DLYBS_MASK)

/* Bitfields in QSPI_ICR (Instruction Code Register) */
#define QSPI_ICR_INST_MASK              GENMASK(7, 0)
#define QSPI_ICR_INST(inst)             (((inst) << 0) & QSPI_ICR_INST_MASK)
#define QSPI_ICR_OPT_MASK               GENMASK(23, 16)
#define QSPI_ICR_OPT(opt)               (((opt) << 16) & QSPI_ICR_OPT_MASK)

/* Bitfields in QSPI_IFR (Instruction Frame Register) */
#define QSPI_IFR_WIDTH_MASK             GENMASK(2, 0)
#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI   (0 << 0)
#define QSPI_IFR_WIDTH_DUAL_OUTPUT      (1 << 0)
#define QSPI_IFR_WIDTH_QUAD_OUTPUT      (2 << 0)
#define QSPI_IFR_WIDTH_DUAL_IO          (3 << 0)
#define QSPI_IFR_WIDTH_QUAD_IO          (4 << 0)
#define QSPI_IFR_WIDTH_DUAL_CMD         (5 << 0)
#define QSPI_IFR_WIDTH_QUAD_CMD         (6 << 0)
#define QSPI_IFR_INSTEN                 BIT(4)
#define QSPI_IFR_ADDREN                 BIT(5)
#define QSPI_IFR_OPTEN                  BIT(6)
#define QSPI_IFR_DATAEN                 BIT(7)
#define QSPI_IFR_OPTL_MASK              GENMASK(9, 8)
#define QSPI_IFR_OPTL_1BIT              (0 << 8)
#define QSPI_IFR_OPTL_2BIT              (1 << 8)
#define QSPI_IFR_OPTL_4BIT              (2 << 8)
#define QSPI_IFR_OPTL_8BIT              (3 << 8)
#define QSPI_IFR_ADDRL                  BIT(10)
#define QSPI_IFR_TFRTYP_MASK            GENMASK(13, 12)
#define QSPI_IFR_TFRTYP_TRSFR_READ      (0 << 12)
#define QSPI_IFR_TFRTYP_TRSFR_READ_MEM  (1 << 12)
#define QSPI_IFR_TFRTYP_TRSFR_WRITE     (2 << 12)
#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEM (3 << 13)
#define QSPI_IFR_CRM                    BIT(14)
#define QSPI_IFR_NBDUM_MASK             GENMASK(20, 16)
#define QSPI_IFR_NBDUM(n)               (((n) << 16) & QSPI_IFR_NBDUM_MASK)

/* Bitfields in QSPI_SMR (Scrambling Mode Register) */
#define QSPI_SMR_SCREN                  BIT(0)
#define QSPI_SMR_RVDIS                  BIT(1)

/* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
#define QSPI_WPMR_WPEN                  BIT(0)
#define QSPI_WPMR_WPKEY_MASK            GENMASK(31, 8)
#define QSPI_WPMR_WPKEY(wpkey)          (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)

/* Bitfields in QSPI_WPSR (Write Protection Status Register) */
#define QSPI_WPSR_WPVS                  BIT(0)
#define QSPI_WPSR_WPVSRC_MASK           GENMASK(15, 8)
#define QSPI_WPSR_WPVSRC(src)           (((src) << 8) & QSPI_WPSR_WPVSRC)


struct atmel_qspi {
	void __iomem		*regs;
	void __iomem		*mem;
	struct clk		*clk;
	struct platform_device	*pdev;
	u32			pending;
	u32			mr;
	struct completion	cmd_completion;
};

struct qspi_mode {
	u8 cmd_buswidth;
	u8 addr_buswidth;
	u8 data_buswidth;
	u32 config;
};

static const struct qspi_mode sama5d2_qspi_modes[] = {
	{ 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
	{ 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
	{ 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
	{ 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
	{ 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
	{ 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
	{ 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
};

static inline bool is_compatible(const struct spi_mem_op *op,
				 const struct qspi_mode *mode)
{
	if (op->cmd.buswidth != mode->cmd_buswidth)
		return false;

	if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
		return false;

	if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
		return false;

	return true;
}

static int find_mode(const struct spi_mem_op *op)
{
	u32 i;

	for (i = 0; i < ARRAY_SIZE(sama5d2_qspi_modes); i++)
		if (is_compatible(op, &sama5d2_qspi_modes[i]))
			return i;

	return -1;
}

static bool atmel_qspi_supports_op(struct spi_mem *mem,
				   const struct spi_mem_op *op)
{
	if (find_mode(op) < 0)
		return false;

	/* special case not supported by hardware */
	if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
		op->dummy.nbytes == 0)
		return false;

	return true;
}

static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
{
	struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->master);
	int mode;
	u32 dummy_cycles = 0;
	u32 iar, icr, ifr, sr;
	int err = 0;

	iar = 0;
	icr = QSPI_ICR_INST(op->cmd.opcode);
	ifr = QSPI_IFR_INSTEN;

	/*
	 * If the QSPI controller is set in regular SPI mode, set it in
	 * Serial Memory Mode (SMM).
	 */
	if (aq->mr != QSPI_MR_SMM) {
		writel_relaxed(QSPI_MR_SMM, aq->regs + QSPI_MR);
		aq->mr = QSPI_MR_SMM;
	}

	mode = find_mode(op);
	if (mode < 0)
		return -ENOTSUPP;

	ifr |= sama5d2_qspi_modes[mode].config;

	if (op->dummy.buswidth && op->dummy.nbytes)
		dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;

	if (op->addr.buswidth) {
		switch (op->addr.nbytes) {
		case 0:
			break;
		case 1:
			ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT;
			icr |= QSPI_ICR_OPT(op->addr.val & 0xff);
			break;
		case 2:
			if (dummy_cycles < 8 / op->addr.buswidth) {
				ifr &= ~QSPI_IFR_INSTEN;
				ifr |= QSPI_IFR_ADDREN;
				iar = (op->cmd.opcode << 16) |
					(op->addr.val & 0xffff);
			} else {
				ifr |= QSPI_IFR_ADDREN;
				iar = (op->addr.val << 8) & 0xffffff;
				dummy_cycles -= 8 / op->addr.buswidth;
			}
			break;
		case 3:
			ifr |= QSPI_IFR_ADDREN;
			iar = op->addr.val & 0xffffff;
			break;
		case 4:
			ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL;
			iar = op->addr.val & 0x7ffffff;
			break;
		default:
			return -ENOTSUPP;
		}
	}

	/* Set number of dummy cycles */
	if (dummy_cycles)
		ifr |= QSPI_IFR_NBDUM(dummy_cycles);

	/* Set data enable */
	if (op->data.nbytes)
		ifr |= QSPI_IFR_DATAEN;

	if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes)
		ifr |= QSPI_IFR_TFRTYP_TRSFR_READ;
	else
		ifr |= QSPI_IFR_TFRTYP_TRSFR_WRITE;

	/* Clear pending interrupts */
	(void)readl_relaxed(aq->regs + QSPI_SR);

	/* Set QSPI Instruction Frame registers */
	writel_relaxed(iar, aq->regs + QSPI_IAR);
	writel_relaxed(icr, aq->regs + QSPI_ICR);
	writel_relaxed(ifr, aq->regs + QSPI_IFR);

	/* Skip to the final steps if there is no data */
	if (op->data.nbytes) {
		/* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
		(void)readl_relaxed(aq->regs + QSPI_IFR);

		/* Send/Receive data */
		if (op->data.dir == SPI_MEM_DATA_IN)
			_memcpy_fromio(op->data.buf.in,
				aq->mem + iar, op->data.nbytes);
		else
			_memcpy_toio(aq->mem + iar,
				op->data.buf.out, op->data.nbytes);

		/* Release the chip-select */
		writel_relaxed(QSPI_CR_LASTXFER, aq->regs + QSPI_CR);
	}

	/* Poll INSTRuction End status */
	sr = readl_relaxed(aq->regs + QSPI_SR);
	if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
		return err;

	/* Wait for INSTRuction End interrupt */
	reinit_completion(&aq->cmd_completion);
	aq->pending = sr & QSPI_SR_CMD_COMPLETED;
	writel_relaxed(QSPI_SR_CMD_COMPLETED, aq->regs + QSPI_IER);
	if (!wait_for_completion_timeout(&aq->cmd_completion,
					 msecs_to_jiffies(1000)))
		err = -ETIMEDOUT;
	writel_relaxed(QSPI_SR_CMD_COMPLETED, aq->regs + QSPI_IDR);

	return err;
}

const char *atmel_qspi_get_name(struct spi_mem *spimem)
{
	return dev_name(spimem->spi->dev.parent);
}

static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
	.supports_op = atmel_qspi_supports_op,
	.exec_op = atmel_qspi_exec_op,
	.get_name = atmel_qspi_get_name
};

static int atmel_qspi_setup(struct spi_device *spi)
{
	struct spi_controller *ctrl = spi->master;
	struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
	unsigned long src_rate;
	u32 scr, scbr;

	if (ctrl->busy)
		return -EBUSY;

	if (!spi->max_speed_hz)
		return -EINVAL;

	src_rate = clk_get_rate(aq->clk);
	if (!src_rate)
		return -EINVAL;

	/* Compute the QSPI baudrate */
	scbr = DIV_ROUND_UP(src_rate, spi->max_speed_hz);
	if (scbr > 0)
		scbr--;

	scr = QSPI_SCR_SCBR(scbr);
	writel_relaxed(scr, aq->regs + QSPI_SCR);

	return 0;
}

static int atmel_qspi_init(struct atmel_qspi *aq)
{
	/* Reset the QSPI controller */
	writel_relaxed(QSPI_CR_SWRST, aq->regs + QSPI_CR);

	/* Set the QSPI controller by default in Serial Memory Mode */
	writel_relaxed(QSPI_MR_SMM, aq->regs + QSPI_MR);
	aq->mr = QSPI_MR_SMM;

	/* Enable the QSPI controller */
	writel_relaxed(QSPI_CR_QSPIEN, aq->regs + QSPI_CR);

	return 0;
}

static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id)
{
	struct atmel_qspi *aq = (struct atmel_qspi *)dev_id;
	u32 status, mask, pending;

	status = readl_relaxed(aq->regs + QSPI_SR);
	mask = readl_relaxed(aq->regs + QSPI_IMR);
	pending = status & mask;

	if (!pending)
		return IRQ_NONE;

	aq->pending |= pending;
	if ((aq->pending & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
		complete(&aq->cmd_completion);

	return IRQ_HANDLED;
}

static int atmel_qspi_probe(struct platform_device *pdev)
{
	struct spi_controller *ctrl;
	struct atmel_qspi *aq;
	struct resource *res;
	int irq, err = 0;

	ctrl = spi_alloc_master(&pdev->dev, sizeof(*aq));
	if (!ctrl)
		return -ENOMEM;

	ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;
	ctrl->setup = atmel_qspi_setup;
	ctrl->bus_num = -1;
	ctrl->mem_ops = &atmel_qspi_mem_ops;
	ctrl->num_chipselect = 1;
	ctrl->dev.of_node = pdev->dev.of_node;
	platform_set_drvdata(pdev, ctrl);

	aq = spi_controller_get_devdata(ctrl);

	init_completion(&aq->cmd_completion);
	aq->pdev = pdev;

	/* Map the registers */
	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
	aq->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(aq->regs)) {
		dev_err(&pdev->dev, "missing registers\n");
		err = PTR_ERR(aq->regs);
		goto exit;
	}

	/* Map the AHB memory */
	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mmap");
	aq->mem = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(aq->mem)) {
		dev_err(&pdev->dev, "missing AHB memory\n");
		err = PTR_ERR(aq->mem);
		goto exit;
	}

	/* Get the peripheral clock */
	aq->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(aq->clk)) {
		dev_err(&pdev->dev, "missing peripheral clock\n");
		err = PTR_ERR(aq->clk);
		goto exit;
	}

	/* Enable the peripheral clock */
	err = clk_prepare_enable(aq->clk);
	if (err) {
		dev_err(&pdev->dev, "failed to enable the peripheral clock\n");
		goto exit;
	}

	/* Request the IRQ */
	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(&pdev->dev, "missing IRQ\n");
		err = irq;
		goto disable_clk;
	}
	err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt,
			       0, dev_name(&pdev->dev), aq);
	if (err)
		goto disable_clk;

	err = atmel_qspi_init(aq);
	if (err)
		goto disable_clk;

	err = spi_register_controller(ctrl);
	if (err)
		goto disable_clk;

	return 0;

disable_clk:
	clk_disable_unprepare(aq->clk);
exit:
	spi_controller_put(ctrl);

	return err;
}

static int atmel_qspi_remove(struct platform_device *pdev)
{
	struct spi_controller *ctrl = platform_get_drvdata(pdev);
	struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);

	spi_unregister_controller(ctrl);
	writel_relaxed(QSPI_CR_QSPIDIS, aq->regs + QSPI_CR);
	clk_disable_unprepare(aq->clk);
	return 0;
}

static int __maybe_unused atmel_qspi_suspend(struct device *dev)
{
	struct atmel_qspi *aq = dev_get_drvdata(dev);

	clk_disable_unprepare(aq->clk);

	return 0;
}

static int __maybe_unused atmel_qspi_resume(struct device *dev)
{
	struct atmel_qspi *aq = dev_get_drvdata(dev);

	clk_prepare_enable(aq->clk);

	return atmel_qspi_init(aq);
}

static SIMPLE_DEV_PM_OPS(atmel_qspi_pm_ops, atmel_qspi_suspend,
			 atmel_qspi_resume);

static const struct of_device_id atmel_qspi_dt_ids[] = {
	{ .compatible = "atmel,sama5d2-qspi" },
	{ /* sentinel */ }
};

MODULE_DEVICE_TABLE(of, atmel_qspi_dt_ids);

static struct platform_driver atmel_qspi_driver = {
	.driver = {
		.name	= "atmel_qspi",
		.of_match_table	= atmel_qspi_dt_ids,
		.pm	= &atmel_qspi_pm_ops,
	},
	.probe		= atmel_qspi_probe,
	.remove		= atmel_qspi_remove,
};
module_platform_driver(atmel_qspi_driver);

MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>");
MODULE_AUTHOR("Piotr Bugalski <bugalski.piotr@gmail.com");
MODULE_DESCRIPTION("Atmel QSPI Controller driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
161aaab8 CP	1	/*
	2	* Driver for Atmel QSPI Controller
	3	*
	4	* Copyright (C) 2015 Atmel Corporation
d5433def	5	* Copyright (C) 2018 Cryptera A/S
161aaab8 CP	6	*
161aaab8 CP	7	* Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
d5433def	8	* Author: Piotr Bugalski <bugalski.piotr@gmail.com>
161aaab8 CP	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope that it will be useful, but WITHOUT
	15	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	16	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	17	* more details.
	18	*
	19	* You should have received a copy of the GNU General Public License along with
	20	* this program. If not, see <http://www.gnu.org/licenses/>.
	21	*
	22	* This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale.
	23	*/
	24
161aaab8	25	#include <linux/clk.h>
161aaab8 CP	26	#include <linux/delay.h>
	27	#include <linux/err.h>
	28	#include <linux/interrupt.h>
161aaab8	29	#include <linux/io.h>
3ae012e9 TA	30	#include <linux/kernel.h>
	31	#include <linux/module.h>
	32	#include <linux/of.h>
	33	#include <linux/platform_device.h>
d5433def	34	#include <linux/spi/spi-mem.h>
161aaab8 CP	35
	36	/* QSPI register offsets */
	37	#define QSPI_CR 0x0000 /* Control Register */
	38	#define QSPI_MR 0x0004 /* Mode Register */
	39	#define QSPI_RD 0x0008 /* Receive Data Register */
	40	#define QSPI_TD 0x000c /* Transmit Data Register */
	41	#define QSPI_SR 0x0010 /* Status Register */
	42	#define QSPI_IER 0x0014 /* Interrupt Enable Register */
	43	#define QSPI_IDR 0x0018 /* Interrupt Disable Register */
	44	#define QSPI_IMR 0x001c /* Interrupt Mask Register */
	45	#define QSPI_SCR 0x0020 /* Serial Clock Register */
	46
	47	#define QSPI_IAR 0x0030 /* Instruction Address Register */
	48	#define QSPI_ICR 0x0034 /* Instruction Code Register */
	49	#define QSPI_IFR 0x0038 /* Instruction Frame Register */
	50
	51	#define QSPI_SMR 0x0040 /* Scrambling Mode Register */
	52	#define QSPI_SKR 0x0044 /* Scrambling Key Register */
	53
	54	#define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */
	55	#define QSPI_WPSR 0x00E8 /* Write Protection Status Register */
	56
	57	#define QSPI_VERSION 0x00FC /* Version Register */
	58
	59
	60	/* Bitfields in QSPI_CR (Control Register) */
	61	#define QSPI_CR_QSPIEN BIT(0)
	62	#define QSPI_CR_QSPIDIS BIT(1)
	63	#define QSPI_CR_SWRST BIT(7)
	64	#define QSPI_CR_LASTXFER BIT(24)
	65
	66	/* Bitfields in QSPI_MR (Mode Register) */
b82ab1c2	67	#define QSPI_MR_SMM BIT(0)
161aaab8 CP	68	#define QSPI_MR_LLB BIT(1)
	69	#define QSPI_MR_WDRBT BIT(2)
	70	#define QSPI_MR_SMRM BIT(3)
	71	#define QSPI_MR_CSMODE_MASK GENMASK(5, 4)
	72	#define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4)
	73	#define QSPI_MR_CSMODE_LASTXFER (1 << 4)
	74	#define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4)
	75	#define QSPI_MR_NBBITS_MASK GENMASK(11, 8)
	76	#define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
	77	#define QSPI_MR_DLYBCT_MASK GENMASK(23, 16)
	78	#define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK)
	79	#define QSPI_MR_DLYCS_MASK GENMASK(31, 24)
	80	#define QSPI_MR_DLYCS(n) (((n) << 24) & QSPI_MR_DLYCS_MASK)
	81
	82	/* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */
	83	#define QSPI_SR_RDRF BIT(0)
	84	#define QSPI_SR_TDRE BIT(1)
	85	#define QSPI_SR_TXEMPTY BIT(2)
	86	#define QSPI_SR_OVRES BIT(3)
	87	#define QSPI_SR_CSR BIT(8)
	88	#define QSPI_SR_CSS BIT(9)
	89	#define QSPI_SR_INSTRE BIT(10)
	90	#define QSPI_SR_QSPIENS BIT(24)
	91
	92	#define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE \| QSPI_SR_CSR)
	93
	94	/* Bitfields in QSPI_SCR (Serial Clock Register) */
	95	#define QSPI_SCR_CPOL BIT(0)
	96	#define QSPI_SCR_CPHA BIT(1)
	97	#define QSPI_SCR_SCBR_MASK GENMASK(15, 8)
	98	#define QSPI_SCR_SCBR(n) (((n) << 8) & QSPI_SCR_SCBR_MASK)
	99	#define QSPI_SCR_DLYBS_MASK GENMASK(23, 16)
	100	#define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK)
	101
	102	/* Bitfields in QSPI_ICR (Instruction Code Register) */
	103	#define QSPI_ICR_INST_MASK GENMASK(7, 0)
	104	#define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK)
	105	#define QSPI_ICR_OPT_MASK GENMASK(23, 16)
	106	#define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK)
	107
	108	/* Bitfields in QSPI_IFR (Instruction Frame Register) */
	109	#define QSPI_IFR_WIDTH_MASK GENMASK(2, 0)
	110	#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0 << 0)
	111	#define QSPI_IFR_WIDTH_DUAL_OUTPUT (1 << 0)
	112	#define QSPI_IFR_WIDTH_QUAD_OUTPUT (2 << 0)
	113	#define QSPI_IFR_WIDTH_DUAL_IO (3 << 0)
	114	#define QSPI_IFR_WIDTH_QUAD_IO (4 << 0)
	115	#define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0)
	116	#define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0)
	117	#define QSPI_IFR_INSTEN BIT(4)
	118	#define QSPI_IFR_ADDREN BIT(5)
	119	#define QSPI_IFR_OPTEN BIT(6)
	120	#define QSPI_IFR_DATAEN BIT(7)
	121	#define QSPI_IFR_OPTL_MASK GENMASK(9, 8)
	122	#define QSPI_IFR_OPTL_1BIT (0 << 8)
	123	#define QSPI_IFR_OPTL_2BIT (1 << 8)
	124	#define QSPI_IFR_OPTL_4BIT (2 << 8)
	125	#define QSPI_IFR_OPTL_8BIT (3 << 8)
	126	#define QSPI_IFR_ADDRL BIT(10)
	127	#define QSPI_IFR_TFRTYP_MASK GENMASK(13, 12)
	128	#define QSPI_IFR_TFRTYP_TRSFR_READ (0 << 12)
	129	#define QSPI_IFR_TFRTYP_TRSFR_READ_MEM (1 << 12)
	130	#define QSPI_IFR_TFRTYP_TRSFR_WRITE (2 << 12)
	131	#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEM (3 << 13)
132	#define QSPI_IFR_CRM BIT(14)
133	#define QSPI_IFR_NBDUM_MASK GENMASK(20, 16)
134	#define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK)
135
136	/* Bitfields in QSPI_SMR (Scrambling Mode Register) */
137	#define QSPI_SMR_SCREN BIT(0)
138	#define QSPI_SMR_RVDIS BIT(1)
139
140	/* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
141	#define QSPI_WPMR_WPEN BIT(0)
142	#define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8)
143	#define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
144
145	/* Bitfields in QSPI_WPSR (Write Protection Status Register) */
146	#define QSPI_WPSR_WPVS BIT(0)
147	#define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8)
148	#define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC)
149
150
151	struct atmel_qspi {
152	void __iomem *regs;
153	void __iomem *mem;
154	struct clk *clk;
155	struct platform_device *pdev;
156	u32 pending;
9958c8c3	157	u32 mr;
161aaab8 CP	158	struct completion cmd_completion;
	159	};
	160
d5433def PB	161	struct qspi_mode {
	162	u8 cmd_buswidth;
	163	u8 addr_buswidth;
	164	u8 data_buswidth;
	165	u32 config;
	166	};
	167
	168	static const struct qspi_mode sama5d2_qspi_modes[] = {
	169	{ 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
	170	{ 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
	171	{ 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
	172	{ 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
	173	{ 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
	174	{ 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
	175	{ 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
	176	};
	177
d5433def PB	178	static inline bool is_compatible(const struct spi_mem_op *op,
	179	const struct qspi_mode *mode)
	180	{
	181	if (op->cmd.buswidth != mode->cmd_buswidth)
	182	return false;
	183
	184	if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
	185	return false;
	186
	187	if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
	188	return false;
	189
	190	return true;
	191	}
	192
	193	static int find_mode(const struct spi_mem_op *op)
	194	{
	195	u32 i;
	196
	197	for (i = 0; i < ARRAY_SIZE(sama5d2_qspi_modes); i++)
	198	if (is_compatible(op, &sama5d2_qspi_modes[i]))
	199	return i;
	200
	201	return -1;
	202	}
	203
	204	static bool atmel_qspi_supports_op(struct spi_mem *mem,
	205	const struct spi_mem_op *op)
	206	{
	207	if (find_mode(op) < 0)
	208	return false;
	209
	210	/* special case not supported by hardware */
	211	if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
	212	op->dummy.nbytes == 0)
	213	return false;
	214
	215	return true;
	216	}
	217
	218	static int atmel_qspi_exec_op(struct spi_mem mem, const struct spi_mem_op op)
	219	{
	220	struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->master);
	221	int mode;
	222	u32 dummy_cycles = 0;
	223	u32 iar, icr, ifr, sr;
	224	int err = 0;
	225
	226	iar = 0;
	227	icr = QSPI_ICR_INST(op->cmd.opcode);
	228	ifr = QSPI_IFR_INSTEN;
	229
9958c8c3 TA	230	/*
	231	* If the QSPI controller is set in regular SPI mode, set it in
	232	* Serial Memory Mode (SMM).
	233	*/
	234	if (aq->mr != QSPI_MR_SMM) {
18b6f6e1	235	writel_relaxed(QSPI_MR_SMM, aq->regs + QSPI_MR);
9958c8c3 TA	236	aq->mr = QSPI_MR_SMM;
9958c8c3 TA	237	}
d5433def PB	238
	239	mode = find_mode(op);
	240	if (mode < 0)
	241	return -ENOTSUPP;
	242
	243	ifr \|= sama5d2_qspi_modes[mode].config;
	244
	245	if (op->dummy.buswidth && op->dummy.nbytes)
	246	dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
	247
	248	if (op->addr.buswidth) {
	249	switch (op->addr.nbytes) {
	250	case 0:
	251	break;
	252	case 1:
	253	ifr \|= QSPI_IFR_OPTEN \| QSPI_IFR_OPTL_8BIT;
	254	icr \|= QSPI_ICR_OPT(op->addr.val & 0xff);
	255	break;
	256	case 2:
	257	if (dummy_cycles < 8 / op->addr.buswidth) {
	258	ifr &= ~QSPI_IFR_INSTEN;
	259	ifr \|= QSPI_IFR_ADDREN;
	260	iar = (op->cmd.opcode << 16) \|
	261	(op->addr.val & 0xffff);
	262	} else {
	263	ifr \|= QSPI_IFR_ADDREN;
	264	iar = (op->addr.val << 8) & 0xffffff;
	265	dummy_cycles -= 8 / op->addr.buswidth;
	266	}
	267	break;
	268	case 3:
	269	ifr \|= QSPI_IFR_ADDREN;
	270	iar = op->addr.val & 0xffffff;
	271	break;
	272	case 4:
	273	ifr \|= QSPI_IFR_ADDREN \| QSPI_IFR_ADDRL;
	274	iar = op->addr.val & 0x7ffffff;
	275	break;
	276	default:
	277	return -ENOTSUPP;
	278	}
	279	}
	280
	281	/* Set number of dummy cycles */
	282	if (dummy_cycles)
	283	ifr \|= QSPI_IFR_NBDUM(dummy_cycles);
	284
	285	/* Set data enable */
	286	if (op->data.nbytes)
	287	ifr \|= QSPI_IFR_DATAEN;
	288
	289	if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes)
	290	ifr \|= QSPI_IFR_TFRTYP_TRSFR_READ;
	291	else
	292	ifr \|= QSPI_IFR_TFRTYP_TRSFR_WRITE;
	293
	294	/* Clear pending interrupts */
18b6f6e1	295	(void)readl_relaxed(aq->regs + QSPI_SR);
d5433def PB	296
d5433def PB	297	/* Set QSPI Instruction Frame registers */
18b6f6e1 TA	298	writel_relaxed(iar, aq->regs + QSPI_IAR);
	299	writel_relaxed(icr, aq->regs + QSPI_ICR);
	300	writel_relaxed(ifr, aq->regs + QSPI_IFR);
d5433def PB	301
	302	/* Skip to the final steps if there is no data */
	303	if (op->data.nbytes) {
	304	/* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
18b6f6e1	305	(void)readl_relaxed(aq->regs + QSPI_IFR);
d5433def PB	306
	307	/* Send/Receive data */
	308	if (op->data.dir == SPI_MEM_DATA_IN)
	309	_memcpy_fromio(op->data.buf.in,
	310	aq->mem + iar, op->data.nbytes);
	311	else
	312	_memcpy_toio(aq->mem + iar,
	313	op->data.buf.out, op->data.nbytes);
	314
	315	/* Release the chip-select */
18b6f6e1	316	writel_relaxed(QSPI_CR_LASTXFER, aq->regs + QSPI_CR);
d5433def PB	317	}
	318
	319	/* Poll INSTRuction End status */
18b6f6e1	320	sr = readl_relaxed(aq->regs + QSPI_SR);
d5433def PB	321	if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
	322	return err;
	323
	324	/* Wait for INSTRuction End interrupt */
	325	reinit_completion(&aq->cmd_completion);
	326	aq->pending = sr & QSPI_SR_CMD_COMPLETED;
18b6f6e1	327	writel_relaxed(QSPI_SR_CMD_COMPLETED, aq->regs + QSPI_IER);
d5433def PB	328	if (!wait_for_completion_timeout(&aq->cmd_completion,
	329	msecs_to_jiffies(1000)))
	330	err = -ETIMEDOUT;
18b6f6e1	331	writel_relaxed(QSPI_SR_CMD_COMPLETED, aq->regs + QSPI_IDR);
d5433def PB	332
	333	return err;
	334	}
	335
	336	const char atmel_qspi_get_name(struct spi_mem spimem)
	337	{
	338	return dev_name(spimem->spi->dev.parent);
	339	}
	340
	341	static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
	342	.supports_op = atmel_qspi_supports_op,
	343	.exec_op = atmel_qspi_exec_op,
	344	.get_name = atmel_qspi_get_name
	345	};
	346
	347	static int atmel_qspi_setup(struct spi_device *spi)
	348	{
	349	struct spi_controller *ctrl = spi->master;
	350	struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
	351	unsigned long src_rate;
	352	u32 scr, scbr;
	353
	354	if (ctrl->busy)
	355	return -EBUSY;
	356
	357	if (!spi->max_speed_hz)
	358	return -EINVAL;
	359
	360	src_rate = clk_get_rate(aq->clk);
	361	if (!src_rate)
	362	return -EINVAL;
	363
	364	/* Compute the QSPI baudrate */
	365	scbr = DIV_ROUND_UP(src_rate, spi->max_speed_hz);
	366	if (scbr > 0)
	367	scbr--;
	368
	369	scr = QSPI_SCR_SCBR(scbr);
18b6f6e1	370	writel_relaxed(scr, aq->regs + QSPI_SCR);
d5433def PB	371
	372	return 0;
	373	}
	374
161aaab8 CP	375	static int atmel_qspi_init(struct atmel_qspi *aq)
161aaab8 CP	376	{
161aaab8	377	/* Reset the QSPI controller */
18b6f6e1	378	writel_relaxed(QSPI_CR_SWRST, aq->regs + QSPI_CR);
161aaab8	379
9958c8c3	380	/* Set the QSPI controller by default in Serial Memory Mode */
18b6f6e1	381	writel_relaxed(QSPI_MR_SMM, aq->regs + QSPI_MR);
9958c8c3 TA	382	aq->mr = QSPI_MR_SMM;
9958c8c3 TA	383
161aaab8	384	/* Enable the QSPI controller */
18b6f6e1	385	writel_relaxed(QSPI_CR_QSPIEN, aq->regs + QSPI_CR);
161aaab8 CP	386
	387	return 0;
	388	}
	389
	390	static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id)
	391	{
	392	struct atmel_qspi aq = (struct atmel_qspi )dev_id;
	393	u32 status, mask, pending;
	394
18b6f6e1 TA	395	status = readl_relaxed(aq->regs + QSPI_SR);
18b6f6e1 TA	396	mask = readl_relaxed(aq->regs + QSPI_IMR);
161aaab8 CP	397	pending = status & mask;
	398
	399	if (!pending)
	400	return IRQ_NONE;
	401
	402	aq->pending \|= pending;
	403	if ((aq->pending & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
	404	complete(&aq->cmd_completion);
	405
	406	return IRQ_HANDLED;
	407	}
	408
	409	static int atmel_qspi_probe(struct platform_device *pdev)
	410	{
2d30ac5e	411	struct spi_controller *ctrl;
161aaab8 CP	412	struct atmel_qspi *aq;
161aaab8 CP	413	struct resource *res;
161aaab8 CP	414	int irq, err = 0;
161aaab8 CP	415
2d30ac5e PB	416	ctrl = spi_alloc_master(&pdev->dev, sizeof(*aq));
	417	if (!ctrl)
	418	return -ENOMEM;
161aaab8	419
2d30ac5e PB	420	ctrl->mode_bits = SPI_RX_DUAL \| SPI_RX_QUAD \| SPI_TX_DUAL \| SPI_TX_QUAD;
	421	ctrl->setup = atmel_qspi_setup;
	422	ctrl->bus_num = -1;
	423	ctrl->mem_ops = &atmel_qspi_mem_ops;
	424	ctrl->num_chipselect = 1;
	425	ctrl->dev.of_node = pdev->dev.of_node;
	426	platform_set_drvdata(pdev, ctrl);
	427
	428	aq = spi_controller_get_devdata(ctrl);
161aaab8	429
161aaab8 CP	430	init_completion(&aq->cmd_completion);
	431	aq->pdev = pdev;
	432
	433	/* Map the registers */
	434	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
	435	aq->regs = devm_ioremap_resource(&pdev->dev, res);
	436	if (IS_ERR(aq->regs)) {
	437	dev_err(&pdev->dev, "missing registers\n");
	438	err = PTR_ERR(aq->regs);
	439	goto exit;
	440	}
	441
	442	/* Map the AHB memory */
	443	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mmap");
	444	aq->mem = devm_ioremap_resource(&pdev->dev, res);
	445	if (IS_ERR(aq->mem)) {
	446	dev_err(&pdev->dev, "missing AHB memory\n");
	447	err = PTR_ERR(aq->mem);
	448	goto exit;
	449	}
	450
	451	/* Get the peripheral clock */
	452	aq->clk = devm_clk_get(&pdev->dev, NULL);
	453	if (IS_ERR(aq->clk)) {
	454	dev_err(&pdev->dev, "missing peripheral clock\n");
	455	err = PTR_ERR(aq->clk);
	456	goto exit;
	457	}
	458
	459	/* Enable the peripheral clock */
	460	err = clk_prepare_enable(aq->clk);
	461	if (err) {
	462	dev_err(&pdev->dev, "failed to enable the peripheral clock\n");
	463	goto exit;
	464	}
	465
	466	/* Request the IRQ */
	467	irq = platform_get_irq(pdev, 0);
	468	if (irq < 0) {
	469	dev_err(&pdev->dev, "missing IRQ\n");
	470	err = irq;
	471	goto disable_clk;
	472	}
	473	err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt,
	474	0, dev_name(&pdev->dev), aq);
	475	if (err)
	476	goto disable_clk;
	477
161aaab8 CP	478	err = atmel_qspi_init(aq);
	479	if (err)
	480	goto disable_clk;
	481
2d30ac5e	482	err = spi_register_controller(ctrl);
161aaab8 CP	483	if (err)
	484	goto disable_clk;
	485
161aaab8 CP	486	return 0;
	487
	488	disable_clk:
	489	clk_disable_unprepare(aq->clk);
	490	exit:
2d30ac5e	491	spi_controller_put(ctrl);
161aaab8 CP	492
	493	return err;
	494	}
	495
	496	static int atmel_qspi_remove(struct platform_device *pdev)
	497	{
2d30ac5e PB	498	struct spi_controller *ctrl = platform_get_drvdata(pdev);
2d30ac5e PB	499	struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
161aaab8	500
2d30ac5e	501	spi_unregister_controller(ctrl);
18b6f6e1	502	writel_relaxed(QSPI_CR_QSPIDIS, aq->regs + QSPI_CR);
161aaab8 CP	503	clk_disable_unprepare(aq->clk);
	504	return 0;
	505	}
	506
de217c1c CB	507	static int __maybe_unused atmel_qspi_suspend(struct device *dev)
	508	{
	509	struct atmel_qspi *aq = dev_get_drvdata(dev);
	510
	511	clk_disable_unprepare(aq->clk);
	512
	513	return 0;
	514	}
	515
	516	static int __maybe_unused atmel_qspi_resume(struct device *dev)
	517	{
	518	struct atmel_qspi *aq = dev_get_drvdata(dev);
	519
	520	clk_prepare_enable(aq->clk);
	521
	522	return atmel_qspi_init(aq);
	523	}
	524
	525	static SIMPLE_DEV_PM_OPS(atmel_qspi_pm_ops, atmel_qspi_suspend,
	526	atmel_qspi_resume);
161aaab8 CP	527
	528	static const struct of_device_id atmel_qspi_dt_ids[] = {
	529	{ .compatible = "atmel,sama5d2-qspi" },
	530	{ /* sentinel */ }
	531	};
	532
	533	MODULE_DEVICE_TABLE(of, atmel_qspi_dt_ids);
	534
	535	static struct platform_driver atmel_qspi_driver = {
	536	.driver = {
	537	.name = "atmel_qspi",
	538	.of_match_table = atmel_qspi_dt_ids,
de217c1c	539	.pm = &atmel_qspi_pm_ops,
161aaab8 CP	540	},
	541	.probe = atmel_qspi_probe,
	542	.remove = atmel_qspi_remove,
	543	};
	544	module_platform_driver(atmel_qspi_driver);
	545
	546	MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>");
d5433def	547	MODULE_AUTHOR("Piotr Bugalski <bugalski.piotr@gmail.com");
161aaab8 CP	548	MODULE_DESCRIPTION("Atmel QSPI Controller driver");
161aaab8 CP	549	MODULE_LICENSE("GPL v2");