[linux-2.6-block.git] / drivers / spi / atmel-quadspi.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Driver for Atmel QSPI Controller
 *
 * Copyright (C) 2015 Atmel Corporation
 * Copyright (C) 2018 Cryptera A/S
 *
 * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
 * Author: Piotr Bugalski <bugalski.piotr@gmail.com>
 *
 * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/spi/spi-mem.h>

/* QSPI register offsets */
#define QSPI_CR      0x0000  /* Control Register */
#define QSPI_MR      0x0004  /* Mode Register */
#define QSPI_RD      0x0008  /* Receive Data Register */
#define QSPI_TD      0x000c  /* Transmit Data Register */
#define QSPI_SR      0x0010  /* Status Register */
#define QSPI_IER     0x0014  /* Interrupt Enable Register */
#define QSPI_IDR     0x0018  /* Interrupt Disable Register */
#define QSPI_IMR     0x001c  /* Interrupt Mask Register */
#define QSPI_SCR     0x0020  /* Serial Clock Register */

#define QSPI_IAR     0x0030  /* Instruction Address Register */
#define QSPI_ICR     0x0034  /* Instruction Code Register */
#define QSPI_WICR    0x0034  /* Write Instruction Code Register */
#define QSPI_IFR     0x0038  /* Instruction Frame Register */
#define QSPI_RICR    0x003C  /* Read Instruction Code Register */

#define QSPI_SMR     0x0040  /* Scrambling Mode Register */
#define QSPI_SKR     0x0044  /* Scrambling Key Register */

#define QSPI_WPMR    0x00E4  /* Write Protection Mode Register */
#define QSPI_WPSR    0x00E8  /* Write Protection Status Register */

#define QSPI_VERSION 0x00FC  /* Version Register */


/* Bitfields in QSPI_CR (Control Register) */
#define QSPI_CR_QSPIEN                  BIT(0)
#define QSPI_CR_QSPIDIS                 BIT(1)
#define QSPI_CR_SWRST                   BIT(7)
#define QSPI_CR_LASTXFER                BIT(24)

/* Bitfields in QSPI_MR (Mode Register) */
#define QSPI_MR_SMM                     BIT(0)
#define QSPI_MR_LLB                     BIT(1)
#define QSPI_MR_WDRBT                   BIT(2)
#define QSPI_MR_SMRM                    BIT(3)
#define QSPI_MR_CSMODE_MASK             GENMASK(5, 4)
#define QSPI_MR_CSMODE_NOT_RELOADED     (0 << 4)
#define QSPI_MR_CSMODE_LASTXFER         (1 << 4)
#define QSPI_MR_CSMODE_SYSTEMATICALLY   (2 << 4)
#define QSPI_MR_NBBITS_MASK             GENMASK(11, 8)
#define QSPI_MR_NBBITS(n)               ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
#define QSPI_MR_DLYBCT_MASK             GENMASK(23, 16)
#define QSPI_MR_DLYBCT(n)               (((n) << 16) & QSPI_MR_DLYBCT_MASK)
#define QSPI_MR_DLYCS_MASK              GENMASK(31, 24)
#define QSPI_MR_DLYCS(n)                (((n) << 24) & QSPI_MR_DLYCS_MASK)

/* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR  */
#define QSPI_SR_RDRF                    BIT(0)
#define QSPI_SR_TDRE                    BIT(1)
#define QSPI_SR_TXEMPTY                 BIT(2)
#define QSPI_SR_OVRES                   BIT(3)
#define QSPI_SR_CSR                     BIT(8)
#define QSPI_SR_CSS                     BIT(9)
#define QSPI_SR_INSTRE                  BIT(10)
#define QSPI_SR_QSPIENS                 BIT(24)

#define QSPI_SR_CMD_COMPLETED	(QSPI_SR_INSTRE | QSPI_SR_CSR)

/* Bitfields in QSPI_SCR (Serial Clock Register) */
#define QSPI_SCR_CPOL                   BIT(0)
#define QSPI_SCR_CPHA                   BIT(1)
#define QSPI_SCR_SCBR_MASK              GENMASK(15, 8)
#define QSPI_SCR_SCBR(n)                (((n) << 8) & QSPI_SCR_SCBR_MASK)
#define QSPI_SCR_DLYBS_MASK             GENMASK(23, 16)
#define QSPI_SCR_DLYBS(n)               (((n) << 16) & QSPI_SCR_DLYBS_MASK)

/* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */
#define QSPI_ICR_INST_MASK              GENMASK(7, 0)
#define QSPI_ICR_INST(inst)             (((inst) << 0) & QSPI_ICR_INST_MASK)
#define QSPI_ICR_OPT_MASK               GENMASK(23, 16)
#define QSPI_ICR_OPT(opt)               (((opt) << 16) & QSPI_ICR_OPT_MASK)

/* Bitfields in QSPI_IFR (Instruction Frame Register) */
#define QSPI_IFR_WIDTH_MASK             GENMASK(2, 0)
#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI   (0 << 0)
#define QSPI_IFR_WIDTH_DUAL_OUTPUT      (1 << 0)
#define QSPI_IFR_WIDTH_QUAD_OUTPUT      (2 << 0)
#define QSPI_IFR_WIDTH_DUAL_IO          (3 << 0)
#define QSPI_IFR_WIDTH_QUAD_IO          (4 << 0)
#define QSPI_IFR_WIDTH_DUAL_CMD         (5 << 0)
#define QSPI_IFR_WIDTH_QUAD_CMD         (6 << 0)
#define QSPI_IFR_INSTEN                 BIT(4)
#define QSPI_IFR_ADDREN                 BIT(5)
#define QSPI_IFR_OPTEN                  BIT(6)
#define QSPI_IFR_DATAEN                 BIT(7)
#define QSPI_IFR_OPTL_MASK              GENMASK(9, 8)
#define QSPI_IFR_OPTL_1BIT              (0 << 8)
#define QSPI_IFR_OPTL_2BIT              (1 << 8)
#define QSPI_IFR_OPTL_4BIT              (2 << 8)
#define QSPI_IFR_OPTL_8BIT              (3 << 8)
#define QSPI_IFR_ADDRL                  BIT(10)
#define QSPI_IFR_TFRTYP_MEM		BIT(12)
#define QSPI_IFR_SAMA5D2_WRITE_TRSFR	BIT(13)
#define QSPI_IFR_CRM                    BIT(14)
#define QSPI_IFR_NBDUM_MASK             GENMASK(20, 16)
#define QSPI_IFR_NBDUM(n)               (((n) << 16) & QSPI_IFR_NBDUM_MASK)
#define QSPI_IFR_APBTFRTYP_READ		BIT(24)	/* Defined in SAM9X60 */

/* Bitfields in QSPI_SMR (Scrambling Mode Register) */
#define QSPI_SMR_SCREN                  BIT(0)
#define QSPI_SMR_RVDIS                  BIT(1)

/* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
#define QSPI_WPMR_WPEN                  BIT(0)
#define QSPI_WPMR_WPKEY_MASK            GENMASK(31, 8)
#define QSPI_WPMR_WPKEY(wpkey)          (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)

/* Bitfields in QSPI_WPSR (Write Protection Status Register) */
#define QSPI_WPSR_WPVS                  BIT(0)
#define QSPI_WPSR_WPVSRC_MASK           GENMASK(15, 8)
#define QSPI_WPSR_WPVSRC(src)           (((src) << 8) & QSPI_WPSR_WPVSRC)

struct atmel_qspi_caps {
	bool has_qspick;
	bool has_ricr;
};

struct atmel_qspi {
	void __iomem		*regs;
	void __iomem		*mem;
	struct clk		*pclk;
	struct clk		*qspick;
	struct platform_device	*pdev;
	const struct atmel_qspi_caps *caps;
	u32			pending;
	u32			mr;
	u32			scr;
	struct completion	cmd_completion;
};

struct atmel_qspi_mode {
	u8 cmd_buswidth;
	u8 addr_buswidth;
	u8 data_buswidth;
	u32 config;
};

static const struct atmel_qspi_mode atmel_qspi_modes[] = {
	{ 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
	{ 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
	{ 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
	{ 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
	{ 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
	{ 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
	{ 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
};

static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
					    const struct atmel_qspi_mode *mode)
{
	if (op->cmd.buswidth != mode->cmd_buswidth)
		return false;

	if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
		return false;

	if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
		return false;

	return true;
}

static int atmel_qspi_find_mode(const struct spi_mem_op *op)
{
	u32 i;

	for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)
		if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
			return i;

	return -ENOTSUPP;
}

static bool atmel_qspi_supports_op(struct spi_mem *mem,
				   const struct spi_mem_op *op)
{
	if (atmel_qspi_find_mode(op) < 0)
		return false;

	/* special case not supported by hardware */
	if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
		op->dummy.nbytes == 0)
		return false;

	return true;
}

static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
			      const struct spi_mem_op *op, u32 *offset)
{
	u32 iar, icr, ifr;
	u32 dummy_cycles = 0;
	int mode;

	iar = 0;
	icr = QSPI_ICR_INST(op->cmd.opcode);
	ifr = QSPI_IFR_INSTEN;

	mode = atmel_qspi_find_mode(op);
	if (mode < 0)
		return mode;
	ifr |= atmel_qspi_modes[mode].config;

	if (op->dummy.buswidth && op->dummy.nbytes)
		dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;

	/*
	 * The controller allows 24 and 32-bit addressing while NAND-flash
	 * requires 16-bit long. Handling 8-bit long addresses is done using
	 * the option field. For the 16-bit addresses, the workaround depends
	 * of the number of requested dummy bits. If there are 8 or more dummy
	 * cycles, the address is shifted and sent with the first dummy byte.
	 * Otherwise opcode is disabled and the first byte of the address
	 * contains the command opcode (works only if the opcode and address
	 * use the same buswidth). The limitation is when the 16-bit address is
	 * used without enough dummy cycles and the opcode is using a different
	 * buswidth than the address.
	 */
	if (op->addr.buswidth) {
		switch (op->addr.nbytes) {
		case 0:
			break;
		case 1:
			ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT;
			icr |= QSPI_ICR_OPT(op->addr.val & 0xff);
			break;
		case 2:
			if (dummy_cycles < 8 / op->addr.buswidth) {
				ifr &= ~QSPI_IFR_INSTEN;
				ifr |= QSPI_IFR_ADDREN;
				iar = (op->cmd.opcode << 16) |
					(op->addr.val & 0xffff);
			} else {
				ifr |= QSPI_IFR_ADDREN;
				iar = (op->addr.val << 8) & 0xffffff;
				dummy_cycles -= 8 / op->addr.buswidth;
			}
			break;
		case 3:
			ifr |= QSPI_IFR_ADDREN;
			iar = op->addr.val & 0xffffff;
			break;
		case 4:
			ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL;
			iar = op->addr.val & 0x7ffffff;
			break;
		default:
			return -ENOTSUPP;
		}
	}

	/* offset of the data access in the QSPI memory space */
	*offset = iar;

	/* Set number of dummy cycles */
	if (dummy_cycles)
		ifr |= QSPI_IFR_NBDUM(dummy_cycles);

	/* Set data enable */
	if (op->data.nbytes)
		ifr |= QSPI_IFR_DATAEN;

	/*
	 * If the QSPI controller is set in regular SPI mode, set it in
	 * Serial Memory Mode (SMM).
	 */
	if (aq->mr != QSPI_MR_SMM) {
		writel_relaxed(QSPI_MR_SMM, aq->regs + QSPI_MR);
		aq->mr = QSPI_MR_SMM;
	}

	/* Clear pending interrupts */
	(void)readl_relaxed(aq->regs + QSPI_SR);

	if (aq->caps->has_ricr) {
		if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
			ifr |= QSPI_IFR_APBTFRTYP_READ;

		/* Set QSPI Instruction Frame registers */
		writel_relaxed(iar, aq->regs + QSPI_IAR);
		if (op->data.dir == SPI_MEM_DATA_IN)
			writel_relaxed(icr, aq->regs + QSPI_RICR);
		else
			writel_relaxed(icr, aq->regs + QSPI_WICR);
		writel_relaxed(ifr, aq->regs + QSPI_IFR);
	} else {
		if (op->data.dir == SPI_MEM_DATA_OUT)
			ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;

		/* Set QSPI Instruction Frame registers */
		writel_relaxed(iar, aq->regs + QSPI_IAR);
		writel_relaxed(icr, aq->regs + QSPI_ICR);
		writel_relaxed(ifr, aq->regs + QSPI_IFR);
	}

	return 0;
}

static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
{
	struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->master);
	u32 sr, offset;
	int err;

	err = atmel_qspi_set_cfg(aq, op, &offset);
	if (err)
		return err;

	/* Skip to the final steps if there is no data */
	if (op->data.nbytes) {
		/* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
		(void)readl_relaxed(aq->regs + QSPI_IFR);

		/* Send/Receive data */
		if (op->data.dir == SPI_MEM_DATA_IN)
			_memcpy_fromio(op->data.buf.in, aq->mem + offset,
				       op->data.nbytes);
		else
			_memcpy_toio(aq->mem + offset, op->data.buf.out,
				     op->data.nbytes);

		/* Release the chip-select */
		writel_relaxed(QSPI_CR_LASTXFER, aq->regs + QSPI_CR);
	}

	/* Poll INSTRuction End status */
	sr = readl_relaxed(aq->regs + QSPI_SR);
	if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
		return err;

	/* Wait for INSTRuction End interrupt */
	reinit_completion(&aq->cmd_completion);
	aq->pending = sr & QSPI_SR_CMD_COMPLETED;
	writel_relaxed(QSPI_SR_CMD_COMPLETED, aq->regs + QSPI_IER);
	if (!wait_for_completion_timeout(&aq->cmd_completion,
					 msecs_to_jiffies(1000)))
		err = -ETIMEDOUT;
	writel_relaxed(QSPI_SR_CMD_COMPLETED, aq->regs + QSPI_IDR);

	return err;
}

static const char *atmel_qspi_get_name(struct spi_mem *spimem)
{
	return dev_name(spimem->spi->dev.parent);
}

static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
	.supports_op = atmel_qspi_supports_op,
	.exec_op = atmel_qspi_exec_op,
	.get_name = atmel_qspi_get_name
};

static int atmel_qspi_setup(struct spi_device *spi)
{
	struct spi_controller *ctrl = spi->master;
	struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
	unsigned long src_rate;
	u32 scbr;

	if (ctrl->busy)
		return -EBUSY;

	if (!spi->max_speed_hz)
		return -EINVAL;

	src_rate = clk_get_rate(aq->pclk);
	if (!src_rate)
		return -EINVAL;

	/* Compute the QSPI baudrate */
	scbr = DIV_ROUND_UP(src_rate, spi->max_speed_hz);
	if (scbr > 0)
		scbr--;

	aq->scr = QSPI_SCR_SCBR(scbr);
	writel_relaxed(aq->scr, aq->regs + QSPI_SCR);

	return 0;
}

static void atmel_qspi_init(struct atmel_qspi *aq)
{
	/* Reset the QSPI controller */
	writel_relaxed(QSPI_CR_SWRST, aq->regs + QSPI_CR);

	/* Set the QSPI controller by default in Serial Memory Mode */
	writel_relaxed(QSPI_MR_SMM, aq->regs + QSPI_MR);
	aq->mr = QSPI_MR_SMM;

	/* Enable the QSPI controller */
	writel_relaxed(QSPI_CR_QSPIEN, aq->regs + QSPI_CR);
}

static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id)
{
	struct atmel_qspi *aq = dev_id;
	u32 status, mask, pending;

	status = readl_relaxed(aq->regs + QSPI_SR);
	mask = readl_relaxed(aq->regs + QSPI_IMR);
	pending = status & mask;

	if (!pending)
		return IRQ_NONE;

	aq->pending |= pending;
	if ((aq->pending & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
		complete(&aq->cmd_completion);

	return IRQ_HANDLED;
}

static int atmel_qspi_probe(struct platform_device *pdev)
{
	struct spi_controller *ctrl;
	struct atmel_qspi *aq;
	struct resource *res;
	int irq, err = 0;

	ctrl = spi_alloc_master(&pdev->dev, sizeof(*aq));
	if (!ctrl)
		return -ENOMEM;

	ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;
	ctrl->setup = atmel_qspi_setup;
	ctrl->bus_num = -1;
	ctrl->mem_ops = &atmel_qspi_mem_ops;
	ctrl->num_chipselect = 1;
	ctrl->dev.of_node = pdev->dev.of_node;
	platform_set_drvdata(pdev, ctrl);

	aq = spi_controller_get_devdata(ctrl);

	init_completion(&aq->cmd_completion);
	aq->pdev = pdev;

	/* Map the registers */
	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
	aq->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(aq->regs)) {
		dev_err(&pdev->dev, "missing registers\n");
		err = PTR_ERR(aq->regs);
		goto exit;
	}

	/* Map the AHB memory */
	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mmap");
	aq->mem = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(aq->mem)) {
		dev_err(&pdev->dev, "missing AHB memory\n");
		err = PTR_ERR(aq->mem);
		goto exit;
	}

	/* Get the peripheral clock */
	aq->pclk = devm_clk_get(&pdev->dev, "pclk");
	if (IS_ERR(aq->pclk))
		aq->pclk = devm_clk_get(&pdev->dev, NULL);

	if (IS_ERR(aq->pclk)) {
		dev_err(&pdev->dev, "missing peripheral clock\n");
		err = PTR_ERR(aq->pclk);
		goto exit;
	}

	/* Enable the peripheral clock */
	err = clk_prepare_enable(aq->pclk);
	if (err) {
		dev_err(&pdev->dev, "failed to enable the peripheral clock\n");
		goto exit;
	}

	aq->caps = of_device_get_match_data(&pdev->dev);
	if (!aq->caps) {
		dev_err(&pdev->dev, "Could not retrieve QSPI caps\n");
		err = -EINVAL;
		goto exit;
	}

	if (aq->caps->has_qspick) {
		/* Get the QSPI system clock */
		aq->qspick = devm_clk_get(&pdev->dev, "qspick");
		if (IS_ERR(aq->qspick)) {
			dev_err(&pdev->dev, "missing system clock\n");
			err = PTR_ERR(aq->qspick);
			goto disable_pclk;
		}

		/* Enable the QSPI system clock */
		err = clk_prepare_enable(aq->qspick);
		if (err) {
			dev_err(&pdev->dev,
				"failed to enable the QSPI system clock\n");
			goto disable_pclk;
		}
	}

	/* Request the IRQ */
	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(&pdev->dev, "missing IRQ\n");
		err = irq;
		goto disable_qspick;
	}
	err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt,
			       0, dev_name(&pdev->dev), aq);
	if (err)
		goto disable_qspick;

	atmel_qspi_init(aq);

	err = spi_register_controller(ctrl);
	if (err)
		goto disable_qspick;

	return 0;

disable_qspick:
	clk_disable_unprepare(aq->qspick);
disable_pclk:
	clk_disable_unprepare(aq->pclk);
exit:
	spi_controller_put(ctrl);

	return err;
}

static int atmel_qspi_remove(struct platform_device *pdev)
{
	struct spi_controller *ctrl = platform_get_drvdata(pdev);
	struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);

	spi_unregister_controller(ctrl);
	writel_relaxed(QSPI_CR_QSPIDIS, aq->regs + QSPI_CR);
	clk_disable_unprepare(aq->qspick);
	clk_disable_unprepare(aq->pclk);
	return 0;
}

static int __maybe_unused atmel_qspi_suspend(struct device *dev)
{
	struct spi_controller *ctrl = dev_get_drvdata(dev);
	struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);

	clk_disable_unprepare(aq->qspick);
	clk_disable_unprepare(aq->pclk);

	return 0;
}

static int __maybe_unused atmel_qspi_resume(struct device *dev)
{
	struct spi_controller *ctrl = dev_get_drvdata(dev);
	struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);

	clk_prepare_enable(aq->pclk);
	clk_prepare_enable(aq->qspick);

	atmel_qspi_init(aq);

	writel_relaxed(aq->scr, aq->regs + QSPI_SCR);

	return 0;
}

static SIMPLE_DEV_PM_OPS(atmel_qspi_pm_ops, atmel_qspi_suspend,
			 atmel_qspi_resume);

static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};

static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
	.has_qspick = true,
	.has_ricr = true,
};

static const struct of_device_id atmel_qspi_dt_ids[] = {
	{
		.compatible = "atmel,sama5d2-qspi",
		.data = &atmel_sama5d2_qspi_caps,
	},
	{
		.compatible = "microchip,sam9x60-qspi",
		.data = &atmel_sam9x60_qspi_caps,
	},
	{ /* sentinel */ }
};

MODULE_DEVICE_TABLE(of, atmel_qspi_dt_ids);

static struct platform_driver atmel_qspi_driver = {
	.driver = {
		.name	= "atmel_qspi",
		.of_match_table	= atmel_qspi_dt_ids,
		.pm	= &atmel_qspi_pm_ops,
	},
	.probe		= atmel_qspi_probe,
	.remove		= atmel_qspi_remove,
};
module_platform_driver(atmel_qspi_driver);

MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>");
MODULE_AUTHOR("Piotr Bugalski <bugalski.piotr@gmail.com");
MODULE_DESCRIPTION("Atmel QSPI Controller driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
cae417b2	1	// SPDX-License-Identifier: GPL-2.0
161aaab8 CP	2	/*
	3	* Driver for Atmel QSPI Controller
	4	*
	5	* Copyright (C) 2015 Atmel Corporation
d5433def	6	* Copyright (C) 2018 Cryptera A/S
161aaab8 CP	7	*
161aaab8 CP	8	* Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
d5433def	9	* Author: Piotr Bugalski <bugalski.piotr@gmail.com>
161aaab8	10	*
161aaab8 CP	11	* This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale.
	12	*/
	13
161aaab8	14	#include <linux/clk.h>
161aaab8 CP	15	#include <linux/delay.h>
	16	#include <linux/err.h>
	17	#include <linux/interrupt.h>
161aaab8	18	#include <linux/io.h>
3ae012e9 TA	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/of.h>
2e5c8888	22	#include <linux/of_platform.h>
3ae012e9	23	#include <linux/platform_device.h>
d5433def	24	#include <linux/spi/spi-mem.h>
161aaab8 CP	25
	26	/* QSPI register offsets */
	27	#define QSPI_CR 0x0000 /* Control Register */
	28	#define QSPI_MR 0x0004 /* Mode Register */
	29	#define QSPI_RD 0x0008 /* Receive Data Register */
	30	#define QSPI_TD 0x000c /* Transmit Data Register */
	31	#define QSPI_SR 0x0010 /* Status Register */
	32	#define QSPI_IER 0x0014 /* Interrupt Enable Register */
	33	#define QSPI_IDR 0x0018 /* Interrupt Disable Register */
	34	#define QSPI_IMR 0x001c /* Interrupt Mask Register */
	35	#define QSPI_SCR 0x0020 /* Serial Clock Register */
	36
	37	#define QSPI_IAR 0x0030 /* Instruction Address Register */
	38	#define QSPI_ICR 0x0034 /* Instruction Code Register */
2e5c8888	39	#define QSPI_WICR 0x0034 /* Write Instruction Code Register */
161aaab8	40	#define QSPI_IFR 0x0038 /* Instruction Frame Register */
2e5c8888	41	#define QSPI_RICR 0x003C /* Read Instruction Code Register */
161aaab8 CP	42
	43	#define QSPI_SMR 0x0040 /* Scrambling Mode Register */
	44	#define QSPI_SKR 0x0044 /* Scrambling Key Register */
	45
	46	#define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */
	47	#define QSPI_WPSR 0x00E8 /* Write Protection Status Register */
	48
	49	#define QSPI_VERSION 0x00FC /* Version Register */
	50
	51
	52	/* Bitfields in QSPI_CR (Control Register) */
	53	#define QSPI_CR_QSPIEN BIT(0)
	54	#define QSPI_CR_QSPIDIS BIT(1)
	55	#define QSPI_CR_SWRST BIT(7)
	56	#define QSPI_CR_LASTXFER BIT(24)
	57
	58	/* Bitfields in QSPI_MR (Mode Register) */
b82ab1c2	59	#define QSPI_MR_SMM BIT(0)
161aaab8 CP	60	#define QSPI_MR_LLB BIT(1)
	61	#define QSPI_MR_WDRBT BIT(2)
	62	#define QSPI_MR_SMRM BIT(3)
	63	#define QSPI_MR_CSMODE_MASK GENMASK(5, 4)
	64	#define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4)
	65	#define QSPI_MR_CSMODE_LASTXFER (1 << 4)
	66	#define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4)
	67	#define QSPI_MR_NBBITS_MASK GENMASK(11, 8)
	68	#define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
	69	#define QSPI_MR_DLYBCT_MASK GENMASK(23, 16)
	70	#define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK)
	71	#define QSPI_MR_DLYCS_MASK GENMASK(31, 24)
	72	#define QSPI_MR_DLYCS(n) (((n) << 24) & QSPI_MR_DLYCS_MASK)
	73
	74	/* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */
	75	#define QSPI_SR_RDRF BIT(0)
	76	#define QSPI_SR_TDRE BIT(1)
	77	#define QSPI_SR_TXEMPTY BIT(2)
	78	#define QSPI_SR_OVRES BIT(3)
	79	#define QSPI_SR_CSR BIT(8)
	80	#define QSPI_SR_CSS BIT(9)
	81	#define QSPI_SR_INSTRE BIT(10)
	82	#define QSPI_SR_QSPIENS BIT(24)
	83
	84	#define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE \| QSPI_SR_CSR)
	85
	86	/* Bitfields in QSPI_SCR (Serial Clock Register) */
	87	#define QSPI_SCR_CPOL BIT(0)
	88	#define QSPI_SCR_CPHA BIT(1)
	89	#define QSPI_SCR_SCBR_MASK GENMASK(15, 8)
	90	#define QSPI_SCR_SCBR(n) (((n) << 8) & QSPI_SCR_SCBR_MASK)
	91	#define QSPI_SCR_DLYBS_MASK GENMASK(23, 16)
	92	#define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK)
	93
2e5c8888	94	/* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */
161aaab8 CP	95	#define QSPI_ICR_INST_MASK GENMASK(7, 0)
	96	#define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK)
	97	#define QSPI_ICR_OPT_MASK GENMASK(23, 16)
	98	#define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK)
	99
	100	/* Bitfields in QSPI_IFR (Instruction Frame Register) */
	101	#define QSPI_IFR_WIDTH_MASK GENMASK(2, 0)
	102	#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0 << 0)
	103	#define QSPI_IFR_WIDTH_DUAL_OUTPUT (1 << 0)
	104	#define QSPI_IFR_WIDTH_QUAD_OUTPUT (2 << 0)
	105	#define QSPI_IFR_WIDTH_DUAL_IO (3 << 0)
	106	#define QSPI_IFR_WIDTH_QUAD_IO (4 << 0)
	107	#define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0)
	108	#define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0)
	109	#define QSPI_IFR_INSTEN BIT(4)
	110	#define QSPI_IFR_ADDREN BIT(5)
	111	#define QSPI_IFR_OPTEN BIT(6)
	112	#define QSPI_IFR_DATAEN BIT(7)
	113	#define QSPI_IFR_OPTL_MASK GENMASK(9, 8)
	114	#define QSPI_IFR_OPTL_1BIT (0 << 8)
	115	#define QSPI_IFR_OPTL_2BIT (1 << 8)
	116	#define QSPI_IFR_OPTL_4BIT (2 << 8)
	117	#define QSPI_IFR_OPTL_8BIT (3 << 8)
	118	#define QSPI_IFR_ADDRL BIT(10)
b456fd18 TA	119	#define QSPI_IFR_TFRTYP_MEM BIT(12)
b456fd18 TA	120	#define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13)
161aaab8 CP	121	#define QSPI_IFR_CRM BIT(14)
	122	#define QSPI_IFR_NBDUM_MASK GENMASK(20, 16)
	123	#define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK)
2e5c8888	124	#define QSPI_IFR_APBTFRTYP_READ BIT(24) /* Defined in SAM9X60 */
161aaab8 CP	125
	126	/* Bitfields in QSPI_SMR (Scrambling Mode Register) */
	127	#define QSPI_SMR_SCREN BIT(0)
	128	#define QSPI_SMR_RVDIS BIT(1)
	129
	130	/* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
	131	#define QSPI_WPMR_WPEN BIT(0)
	132	#define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8)
	133	#define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
	134
	135	/* Bitfields in QSPI_WPSR (Write Protection Status Register) */
	136	#define QSPI_WPSR_WPVS BIT(0)
	137	#define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8)
	138	#define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC)
	139
2e5c8888 TA	140	struct atmel_qspi_caps {
	141	bool has_qspick;
	142	bool has_ricr;
	143	};
161aaab8 CP	144
	145	struct atmel_qspi {
	146	void __iomem *regs;
	147	void __iomem *mem;
bd7905e2	148	struct clk *pclk;
2e5c8888	149	struct clk *qspick;
161aaab8	150	struct platform_device *pdev;
2e5c8888	151	const struct atmel_qspi_caps *caps;
161aaab8	152	u32 pending;
9958c8c3	153	u32 mr;
ab735611	154	u32 scr;
161aaab8 CP	155	struct completion cmd_completion;
	156	};
	157
1db6de22	158	struct atmel_qspi_mode {
d5433def PB	159	u8 cmd_buswidth;
	160	u8 addr_buswidth;
	161	u8 data_buswidth;
	162	u32 config;
	163	};
	164
2e5c8888	165	static const struct atmel_qspi_mode atmel_qspi_modes[] = {
d5433def PB	166	{ 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
	167	{ 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
	168	{ 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
	169	{ 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
	170	{ 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
	171	{ 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
	172	{ 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
	173	};
	174
1db6de22 TA	175	static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
1db6de22 TA	176	const struct atmel_qspi_mode *mode)
d5433def PB	177	{
	178	if (op->cmd.buswidth != mode->cmd_buswidth)
	179	return false;
	180
	181	if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
	182	return false;
	183
	184	if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
	185	return false;
	186
	187	return true;
	188	}
	189
1db6de22	190	static int atmel_qspi_find_mode(const struct spi_mem_op *op)
d5433def PB	191	{
	192	u32 i;
	193
2e5c8888 TA	194	for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)
2e5c8888 TA	195	if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
d5433def PB	196	return i;
d5433def PB	197
2aaa8dd0	198	return -ENOTSUPP;
d5433def PB	199	}
	200
	201	static bool atmel_qspi_supports_op(struct spi_mem *mem,
	202	const struct spi_mem_op *op)
	203	{
1db6de22	204	if (atmel_qspi_find_mode(op) < 0)
d5433def PB	205	return false;
	206
	207	/* special case not supported by hardware */
	208	if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
	209	op->dummy.nbytes == 0)
	210	return false;
	211
	212	return true;
	213	}
	214
2e5c8888 TA	215	static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
2e5c8888 TA	216	const struct spi_mem_op op, u32 offset)
d5433def	217	{
2e5c8888	218	u32 iar, icr, ifr;
d5433def	219	u32 dummy_cycles = 0;
2e5c8888	220	int mode;
d5433def PB	221
	222	iar = 0;
	223	icr = QSPI_ICR_INST(op->cmd.opcode);
	224	ifr = QSPI_IFR_INSTEN;
	225
1db6de22	226	mode = atmel_qspi_find_mode(op);
d5433def	227	if (mode < 0)
2aaa8dd0	228	return mode;
2e5c8888	229	ifr \|= atmel_qspi_modes[mode].config;
d5433def PB	230
	231	if (op->dummy.buswidth && op->dummy.nbytes)
	232	dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
	233
2e5c8888 TA	234	/*
	235	* The controller allows 24 and 32-bit addressing while NAND-flash
	236	* requires 16-bit long. Handling 8-bit long addresses is done using
	237	* the option field. For the 16-bit addresses, the workaround depends
	238	* of the number of requested dummy bits. If there are 8 or more dummy
	239	* cycles, the address is shifted and sent with the first dummy byte.
	240	* Otherwise opcode is disabled and the first byte of the address
	241	* contains the command opcode (works only if the opcode and address
	242	* use the same buswidth). The limitation is when the 16-bit address is
	243	* used without enough dummy cycles and the opcode is using a different
	244	* buswidth than the address.
	245	*/
d5433def PB	246	if (op->addr.buswidth) {
	247	switch (op->addr.nbytes) {
	248	case 0:
	249	break;
	250	case 1:
	251	ifr \|= QSPI_IFR_OPTEN \| QSPI_IFR_OPTL_8BIT;
	252	icr \|= QSPI_ICR_OPT(op->addr.val & 0xff);
	253	break;
	254	case 2:
	255	if (dummy_cycles < 8 / op->addr.buswidth) {
	256	ifr &= ~QSPI_IFR_INSTEN;
	257	ifr \|= QSPI_IFR_ADDREN;
	258	iar = (op->cmd.opcode << 16) \|
	259	(op->addr.val & 0xffff);
	260	} else {
	261	ifr \|= QSPI_IFR_ADDREN;
	262	iar = (op->addr.val << 8) & 0xffffff;
	263	dummy_cycles -= 8 / op->addr.buswidth;
	264	}
	265	break;
	266	case 3:
	267	ifr \|= QSPI_IFR_ADDREN;
	268	iar = op->addr.val & 0xffffff;
	269	break;
	270	case 4:
	271	ifr \|= QSPI_IFR_ADDREN \| QSPI_IFR_ADDRL;
	272	iar = op->addr.val & 0x7ffffff;
	273	break;
	274	default:
	275	return -ENOTSUPP;
	276	}
	277	}
	278
2e5c8888 TA	279	/* offset of the data access in the QSPI memory space */
	280	*offset = iar;
	281
d5433def PB	282	/* Set number of dummy cycles */
	283	if (dummy_cycles)
	284	ifr \|= QSPI_IFR_NBDUM(dummy_cycles);
	285
	286	/* Set data enable */
	287	if (op->data.nbytes)
	288	ifr \|= QSPI_IFR_DATAEN;
	289
2e5c8888 TA	290	/*
	291	* If the QSPI controller is set in regular SPI mode, set it in
	292	* Serial Memory Mode (SMM).
	293	*/
	294	if (aq->mr != QSPI_MR_SMM) {
	295	writel_relaxed(QSPI_MR_SMM, aq->regs + QSPI_MR);
	296	aq->mr = QSPI_MR_SMM;
	297	}
d5433def PB	298
d5433def PB	299	/* Clear pending interrupts */
18b6f6e1	300	(void)readl_relaxed(aq->regs + QSPI_SR);
d5433def	301
2e5c8888 TA	302	if (aq->caps->has_ricr) {
	303	if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
	304	ifr \|= QSPI_IFR_APBTFRTYP_READ;
	305
	306	/* Set QSPI Instruction Frame registers */
	307	writel_relaxed(iar, aq->regs + QSPI_IAR);
	308	if (op->data.dir == SPI_MEM_DATA_IN)
	309	writel_relaxed(icr, aq->regs + QSPI_RICR);
	310	else
	311	writel_relaxed(icr, aq->regs + QSPI_WICR);
	312	writel_relaxed(ifr, aq->regs + QSPI_IFR);
	313	} else {
	314	if (op->data.dir == SPI_MEM_DATA_OUT)
	315	ifr \|= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
	316
	317	/* Set QSPI Instruction Frame registers */
	318	writel_relaxed(iar, aq->regs + QSPI_IAR);
	319	writel_relaxed(icr, aq->regs + QSPI_ICR);
	320	writel_relaxed(ifr, aq->regs + QSPI_IFR);
	321	}
	322
	323	return 0;
	324	}
	325
	326	static int atmel_qspi_exec_op(struct spi_mem mem, const struct spi_mem_op op)
	327	{
	328	struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->master);
	329	u32 sr, offset;
	330	int err;
	331
	332	err = atmel_qspi_set_cfg(aq, op, &offset);
	333	if (err)
	334	return err;
d5433def PB	335
	336	/* Skip to the final steps if there is no data */
	337	if (op->data.nbytes) {
	338	/* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
18b6f6e1	339	(void)readl_relaxed(aq->regs + QSPI_IFR);
d5433def PB	340
	341	/* Send/Receive data */
	342	if (op->data.dir == SPI_MEM_DATA_IN)
2e5c8888 TA	343	_memcpy_fromio(op->data.buf.in, aq->mem + offset,
2e5c8888 TA	344	op->data.nbytes);
d5433def	345	else
2e5c8888 TA	346	_memcpy_toio(aq->mem + offset, op->data.buf.out,
2e5c8888 TA	347	op->data.nbytes);
d5433def PB	348
d5433def PB	349	/* Release the chip-select */
18b6f6e1	350	writel_relaxed(QSPI_CR_LASTXFER, aq->regs + QSPI_CR);
d5433def PB	351	}
	352
	353	/* Poll INSTRuction End status */
18b6f6e1	354	sr = readl_relaxed(aq->regs + QSPI_SR);
d5433def PB	355	if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
	356	return err;
	357
	358	/* Wait for INSTRuction End interrupt */
	359	reinit_completion(&aq->cmd_completion);
	360	aq->pending = sr & QSPI_SR_CMD_COMPLETED;
18b6f6e1	361	writel_relaxed(QSPI_SR_CMD_COMPLETED, aq->regs + QSPI_IER);
d5433def PB	362	if (!wait_for_completion_timeout(&aq->cmd_completion,
	363	msecs_to_jiffies(1000)))
	364	err = -ETIMEDOUT;
18b6f6e1	365	writel_relaxed(QSPI_SR_CMD_COMPLETED, aq->regs + QSPI_IDR);
d5433def PB	366
	367	return err;
	368	}
	369
55e3daca	370	static const char atmel_qspi_get_name(struct spi_mem spimem)
d5433def PB	371	{
	372	return dev_name(spimem->spi->dev.parent);
	373	}
	374
	375	static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
	376	.supports_op = atmel_qspi_supports_op,
	377	.exec_op = atmel_qspi_exec_op,
	378	.get_name = atmel_qspi_get_name
	379	};
	380
	381	static int atmel_qspi_setup(struct spi_device *spi)
	382	{
	383	struct spi_controller *ctrl = spi->master;
	384	struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
	385	unsigned long src_rate;
ab735611	386	u32 scbr;
d5433def PB	387
	388	if (ctrl->busy)
	389	return -EBUSY;
	390
	391	if (!spi->max_speed_hz)
	392	return -EINVAL;
	393
bd7905e2	394	src_rate = clk_get_rate(aq->pclk);
d5433def PB	395	if (!src_rate)
	396	return -EINVAL;
	397
	398	/* Compute the QSPI baudrate */
	399	scbr = DIV_ROUND_UP(src_rate, spi->max_speed_hz);
	400	if (scbr > 0)
	401	scbr--;
	402
ab735611 TA	403	aq->scr = QSPI_SCR_SCBR(scbr);
ab735611 TA	404	writel_relaxed(aq->scr, aq->regs + QSPI_SCR);
d5433def PB	405
	406	return 0;
	407	}
	408
5b74e9a3	409	static void atmel_qspi_init(struct atmel_qspi *aq)
161aaab8	410	{
161aaab8	411	/* Reset the QSPI controller */
18b6f6e1	412	writel_relaxed(QSPI_CR_SWRST, aq->regs + QSPI_CR);
161aaab8	413
9958c8c3	414	/* Set the QSPI controller by default in Serial Memory Mode */
18b6f6e1	415	writel_relaxed(QSPI_MR_SMM, aq->regs + QSPI_MR);
9958c8c3 TA	416	aq->mr = QSPI_MR_SMM;
9958c8c3 TA	417
161aaab8	418	/* Enable the QSPI controller */
18b6f6e1	419	writel_relaxed(QSPI_CR_QSPIEN, aq->regs + QSPI_CR);
161aaab8 CP	420	}
	421
	422	static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id)
	423	{
9ce4c512	424	struct atmel_qspi *aq = dev_id;
161aaab8 CP	425	u32 status, mask, pending;
161aaab8 CP	426
18b6f6e1 TA	427	status = readl_relaxed(aq->regs + QSPI_SR);
18b6f6e1 TA	428	mask = readl_relaxed(aq->regs + QSPI_IMR);
161aaab8 CP	429	pending = status & mask;
	430
	431	if (!pending)
	432	return IRQ_NONE;
	433
	434	aq->pending \|= pending;
	435	if ((aq->pending & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
	436	complete(&aq->cmd_completion);
	437
	438	return IRQ_HANDLED;
	439	}
	440
	441	static int atmel_qspi_probe(struct platform_device *pdev)
	442	{
2d30ac5e	443	struct spi_controller *ctrl;
161aaab8 CP	444	struct atmel_qspi *aq;
161aaab8 CP	445	struct resource *res;
161aaab8 CP	446	int irq, err = 0;
161aaab8 CP	447
2d30ac5e PB	448	ctrl = spi_alloc_master(&pdev->dev, sizeof(*aq));
	449	if (!ctrl)
	450	return -ENOMEM;
161aaab8	451
2d30ac5e PB	452	ctrl->mode_bits = SPI_RX_DUAL \| SPI_RX_QUAD \| SPI_TX_DUAL \| SPI_TX_QUAD;
	453	ctrl->setup = atmel_qspi_setup;
	454	ctrl->bus_num = -1;
	455	ctrl->mem_ops = &atmel_qspi_mem_ops;
	456	ctrl->num_chipselect = 1;
	457	ctrl->dev.of_node = pdev->dev.of_node;
	458	platform_set_drvdata(pdev, ctrl);
	459
	460	aq = spi_controller_get_devdata(ctrl);
161aaab8	461
161aaab8 CP	462	init_completion(&aq->cmd_completion);
	463	aq->pdev = pdev;
	464
	465	/* Map the registers */
	466	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
	467	aq->regs = devm_ioremap_resource(&pdev->dev, res);
	468	if (IS_ERR(aq->regs)) {
	469	dev_err(&pdev->dev, "missing registers\n");
	470	err = PTR_ERR(aq->regs);
	471	goto exit;
	472	}
	473
	474	/* Map the AHB memory */
	475	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mmap");
	476	aq->mem = devm_ioremap_resource(&pdev->dev, res);
	477	if (IS_ERR(aq->mem)) {
	478	dev_err(&pdev->dev, "missing AHB memory\n");
	479	err = PTR_ERR(aq->mem);
	480	goto exit;
	481	}
	482
	483	/* Get the peripheral clock */
bd7905e2 TA	484	aq->pclk = devm_clk_get(&pdev->dev, "pclk");
	485	if (IS_ERR(aq->pclk))
	486	aq->pclk = devm_clk_get(&pdev->dev, NULL);
	487
	488	if (IS_ERR(aq->pclk)) {
161aaab8	489	dev_err(&pdev->dev, "missing peripheral clock\n");
bd7905e2	490	err = PTR_ERR(aq->pclk);
161aaab8 CP	491	goto exit;
	492	}
	493
	494	/* Enable the peripheral clock */
bd7905e2	495	err = clk_prepare_enable(aq->pclk);
161aaab8 CP	496	if (err) {
	497	dev_err(&pdev->dev, "failed to enable the peripheral clock\n");
	498	goto exit;
	499	}
	500
2e5c8888 TA	501	aq->caps = of_device_get_match_data(&pdev->dev);
	502	if (!aq->caps) {
	503	dev_err(&pdev->dev, "Could not retrieve QSPI caps\n");
	504	err = -EINVAL;
	505	goto exit;
	506	}
	507
	508	if (aq->caps->has_qspick) {
	509	/* Get the QSPI system clock */
	510	aq->qspick = devm_clk_get(&pdev->dev, "qspick");
	511	if (IS_ERR(aq->qspick)) {
	512	dev_err(&pdev->dev, "missing system clock\n");
	513	err = PTR_ERR(aq->qspick);
	514	goto disable_pclk;
	515	}
	516
	517	/* Enable the QSPI system clock */
	518	err = clk_prepare_enable(aq->qspick);
	519	if (err) {
	520	dev_err(&pdev->dev,
	521	"failed to enable the QSPI system clock\n");
	522	goto disable_pclk;
	523	}
	524	}
	525
161aaab8 CP	526	/* Request the IRQ */
	527	irq = platform_get_irq(pdev, 0);
	528	if (irq < 0) {
	529	dev_err(&pdev->dev, "missing IRQ\n");
	530	err = irq;
2e5c8888	531	goto disable_qspick;
161aaab8 CP	532	}
	533	err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt,
	534	0, dev_name(&pdev->dev), aq);
	535	if (err)
2e5c8888	536	goto disable_qspick;
161aaab8	537
5b74e9a3	538	atmel_qspi_init(aq);
161aaab8	539
2d30ac5e	540	err = spi_register_controller(ctrl);
161aaab8	541	if (err)
2e5c8888	542	goto disable_qspick;
161aaab8	543
161aaab8 CP	544	return 0;
161aaab8 CP	545
2e5c8888 TA	546	disable_qspick:
2e5c8888 TA	547	clk_disable_unprepare(aq->qspick);
bd7905e2 TA	548	disable_pclk:
bd7905e2 TA	549	clk_disable_unprepare(aq->pclk);
161aaab8	550	exit:
2d30ac5e	551	spi_controller_put(ctrl);
161aaab8 CP	552
	553	return err;
	554	}
	555
	556	static int atmel_qspi_remove(struct platform_device *pdev)
	557	{
2d30ac5e PB	558	struct spi_controller *ctrl = platform_get_drvdata(pdev);
2d30ac5e PB	559	struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
161aaab8	560
2d30ac5e	561	spi_unregister_controller(ctrl);
18b6f6e1	562	writel_relaxed(QSPI_CR_QSPIDIS, aq->regs + QSPI_CR);
2e5c8888	563	clk_disable_unprepare(aq->qspick);
bd7905e2	564	clk_disable_unprepare(aq->pclk);
161aaab8 CP	565	return 0;
	566	}
	567
de217c1c CB	568	static int __maybe_unused atmel_qspi_suspend(struct device *dev)
de217c1c CB	569	{
e5c27498 CB	570	struct spi_controller *ctrl = dev_get_drvdata(dev);
e5c27498 CB	571	struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
de217c1c	572
2e5c8888	573	clk_disable_unprepare(aq->qspick);
bd7905e2	574	clk_disable_unprepare(aq->pclk);
de217c1c CB	575
	576	return 0;
	577	}
	578
	579	static int __maybe_unused atmel_qspi_resume(struct device *dev)
	580	{
e5c27498 CB	581	struct spi_controller *ctrl = dev_get_drvdata(dev);
e5c27498 CB	582	struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
de217c1c	583
bd7905e2	584	clk_prepare_enable(aq->pclk);
2e5c8888	585	clk_prepare_enable(aq->qspick);
de217c1c	586
5b74e9a3	587	atmel_qspi_init(aq);
ab735611 TA	588
	589	writel_relaxed(aq->scr, aq->regs + QSPI_SCR);
	590
5b74e9a3	591	return 0;
de217c1c CB	592	}
	593
	594	static SIMPLE_DEV_PM_OPS(atmel_qspi_pm_ops, atmel_qspi_suspend,
	595	atmel_qspi_resume);
161aaab8	596
2e5c8888 TA	597	static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
	598
	599	static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
	600	.has_qspick = true,
	601	.has_ricr = true,
	602	};
	603
161aaab8	604	static const struct of_device_id atmel_qspi_dt_ids[] = {
2e5c8888 TA	605	{
	606	.compatible = "atmel,sama5d2-qspi",
	607	.data = &atmel_sama5d2_qspi_caps,
	608	},
	609	{
	610	.compatible = "microchip,sam9x60-qspi",
	611	.data = &atmel_sam9x60_qspi_caps,
	612	},
161aaab8 CP	613	{ /* sentinel */ }
	614	};
	615
	616	MODULE_DEVICE_TABLE(of, atmel_qspi_dt_ids);
	617
	618	static struct platform_driver atmel_qspi_driver = {
	619	.driver = {
	620	.name = "atmel_qspi",
	621	.of_match_table = atmel_qspi_dt_ids,
de217c1c	622	.pm = &atmel_qspi_pm_ops,
161aaab8 CP	623	},
	624	.probe = atmel_qspi_probe,
	625	.remove = atmel_qspi_remove,
	626	};
	627	module_platform_driver(atmel_qspi_driver);
	628
	629	MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>");
d5433def	630	MODULE_AUTHOR("Piotr Bugalski <bugalski.piotr@gmail.com");
161aaab8 CP	631	MODULE_DESCRIPTION("Atmel QSPI Controller driver");
161aaab8 CP	632	MODULE_LICENSE("GPL v2");