Merge tag 'pm-6.4-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael...
[linux-block.git] / drivers / soundwire / stream.c
CommitLineData
89e59053
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1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2// Copyright(c) 2015-18 Intel Corporation.
3
4/*
5 * stream.c - SoundWire Bus stream operations.
6 */
7
8#include <linux/delay.h>
9#include <linux/device.h>
10#include <linux/init.h>
11#include <linux/module.h>
12#include <linux/mod_devicetable.h>
13#include <linux/slab.h>
f8101c74 14#include <linux/soundwire/sdw_registers.h>
89e59053 15#include <linux/soundwire/sdw.h>
bd29c00e 16#include <linux/soundwire/sdw_type.h>
4550569b 17#include <sound/soc.h>
89e59053
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18#include "bus.h"
19
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20/*
21 * Array of supported rows and columns as per MIPI SoundWire Specification 1.1
22 *
23 * The rows are arranged as per the array index value programmed
24 * in register. The index 15 has dummy value 0 in order to fill hole.
25 */
fe4b70f2 26int sdw_rows[SDW_FRAME_ROWS] = {48, 50, 60, 64, 75, 80, 125, 147,
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27 96, 100, 120, 128, 150, 160, 250, 0,
28 192, 200, 240, 256, 72, 144, 90, 180};
9026118f 29EXPORT_SYMBOL(sdw_rows);
99b8a5d6 30
fe4b70f2 31int sdw_cols[SDW_FRAME_COLS] = {2, 4, 6, 8, 10, 12, 14, 16};
9026118f 32EXPORT_SYMBOL(sdw_cols);
99b8a5d6 33
fe4b70f2 34int sdw_find_col_index(int col)
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35{
36 int i;
37
38 for (i = 0; i < SDW_FRAME_COLS; i++) {
fe4b70f2 39 if (sdw_cols[i] == col)
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40 return i;
41 }
42
43 pr_warn("Requested column not found, selecting lowest column no: 2\n");
44 return 0;
45}
fe4b70f2 46EXPORT_SYMBOL(sdw_find_col_index);
99b8a5d6 47
fe4b70f2 48int sdw_find_row_index(int row)
99b8a5d6
SK
49{
50 int i;
51
52 for (i = 0; i < SDW_FRAME_ROWS; i++) {
fe4b70f2 53 if (sdw_rows[i] == row)
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54 return i;
55 }
56
57 pr_warn("Requested row not found, selecting lowest row no: 48\n");
58 return 0;
59}
fe4b70f2 60EXPORT_SYMBOL(sdw_find_row_index);
897fe40e 61
f8101c74 62static int _sdw_program_slave_port_params(struct sdw_bus *bus,
1fe74a5e
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63 struct sdw_slave *slave,
64 struct sdw_transport_params *t_params,
65 enum sdw_dpn_type type)
f8101c74
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66{
67 u32 addr1, addr2, addr3, addr4;
68 int ret;
69 u16 wbuf;
70
71 if (bus->params.next_bank) {
72 addr1 = SDW_DPN_OFFSETCTRL2_B1(t_params->port_num);
73 addr2 = SDW_DPN_BLOCKCTRL3_B1(t_params->port_num);
74 addr3 = SDW_DPN_SAMPLECTRL2_B1(t_params->port_num);
75 addr4 = SDW_DPN_HCTRL_B1(t_params->port_num);
76 } else {
77 addr1 = SDW_DPN_OFFSETCTRL2_B0(t_params->port_num);
78 addr2 = SDW_DPN_BLOCKCTRL3_B0(t_params->port_num);
79 addr3 = SDW_DPN_SAMPLECTRL2_B0(t_params->port_num);
80 addr4 = SDW_DPN_HCTRL_B0(t_params->port_num);
81 }
82
83 /* Program DPN_OffsetCtrl2 registers */
545c3651 84 ret = sdw_write_no_pm(slave, addr1, t_params->offset2);
f8101c74 85 if (ret < 0) {
17ed5bef 86 dev_err(bus->dev, "DPN_OffsetCtrl2 register write failed\n");
f8101c74
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87 return ret;
88 }
89
90 /* Program DPN_BlockCtrl3 register */
545c3651 91 ret = sdw_write_no_pm(slave, addr2, t_params->blk_pkg_mode);
f8101c74 92 if (ret < 0) {
17ed5bef 93 dev_err(bus->dev, "DPN_BlockCtrl3 register write failed\n");
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94 return ret;
95 }
96
97 /*
98 * Data ports are FULL, SIMPLE and REDUCED. This function handles
7d3b3cdf 99 * FULL and REDUCED only and beyond this point only FULL is
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100 * handled, so bail out if we are not FULL data port type
101 */
102 if (type != SDW_DPN_FULL)
103 return ret;
104
105 /* Program DPN_SampleCtrl2 register */
41ff9174 106 wbuf = FIELD_GET(SDW_DPN_SAMPLECTRL_HIGH, t_params->sample_interval - 1);
f8101c74 107
545c3651 108 ret = sdw_write_no_pm(slave, addr3, wbuf);
f8101c74 109 if (ret < 0) {
17ed5bef 110 dev_err(bus->dev, "DPN_SampleCtrl2 register write failed\n");
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111 return ret;
112 }
113
114 /* Program DPN_HCtrl register */
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115 wbuf = FIELD_PREP(SDW_DPN_HCTRL_HSTART, t_params->hstart);
116 wbuf |= FIELD_PREP(SDW_DPN_HCTRL_HSTOP, t_params->hstop);
f8101c74 117
545c3651 118 ret = sdw_write_no_pm(slave, addr4, wbuf);
f8101c74 119 if (ret < 0)
17ed5bef 120 dev_err(bus->dev, "DPN_HCtrl register write failed\n");
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121
122 return ret;
123}
124
125static int sdw_program_slave_port_params(struct sdw_bus *bus,
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126 struct sdw_slave_runtime *s_rt,
127 struct sdw_port_runtime *p_rt)
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128{
129 struct sdw_transport_params *t_params = &p_rt->transport_params;
130 struct sdw_port_params *p_params = &p_rt->port_params;
131 struct sdw_slave_prop *slave_prop = &s_rt->slave->prop;
132 u32 addr1, addr2, addr3, addr4, addr5, addr6;
133 struct sdw_dpn_prop *dpn_prop;
134 int ret;
135 u8 wbuf;
136
24f08b3a
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137 if (s_rt->slave->is_mockup_device)
138 return 0;
139
f8101c74 140 dpn_prop = sdw_get_slave_dpn_prop(s_rt->slave,
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141 s_rt->direction,
142 t_params->port_num);
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143 if (!dpn_prop)
144 return -EINVAL;
145
146 addr1 = SDW_DPN_PORTCTRL(t_params->port_num);
147 addr2 = SDW_DPN_BLOCKCTRL1(t_params->port_num);
148
149 if (bus->params.next_bank) {
150 addr3 = SDW_DPN_SAMPLECTRL1_B1(t_params->port_num);
151 addr4 = SDW_DPN_OFFSETCTRL1_B1(t_params->port_num);
152 addr5 = SDW_DPN_BLOCKCTRL2_B1(t_params->port_num);
153 addr6 = SDW_DPN_LANECTRL_B1(t_params->port_num);
154
155 } else {
156 addr3 = SDW_DPN_SAMPLECTRL1_B0(t_params->port_num);
157 addr4 = SDW_DPN_OFFSETCTRL1_B0(t_params->port_num);
158 addr5 = SDW_DPN_BLOCKCTRL2_B0(t_params->port_num);
159 addr6 = SDW_DPN_LANECTRL_B0(t_params->port_num);
160 }
161
162 /* Program DPN_PortCtrl register */
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163 wbuf = FIELD_PREP(SDW_DPN_PORTCTRL_DATAMODE, p_params->data_mode);
164 wbuf |= FIELD_PREP(SDW_DPN_PORTCTRL_FLOWMODE, p_params->flow_mode);
f8101c74 165
545c3651 166 ret = sdw_update_no_pm(s_rt->slave, addr1, 0xF, wbuf);
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167 if (ret < 0) {
168 dev_err(&s_rt->slave->dev,
17ed5bef 169 "DPN_PortCtrl register write failed for port %d\n",
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170 t_params->port_num);
171 return ret;
172 }
173
a9107de4
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174 if (!dpn_prop->read_only_wordlength) {
175 /* Program DPN_BlockCtrl1 register */
545c3651 176 ret = sdw_write_no_pm(s_rt->slave, addr2, (p_params->bps - 1));
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177 if (ret < 0) {
178 dev_err(&s_rt->slave->dev,
179 "DPN_BlockCtrl1 register write failed for port %d\n",
180 t_params->port_num);
181 return ret;
182 }
f8101c74
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183 }
184
185 /* Program DPN_SampleCtrl1 register */
186 wbuf = (t_params->sample_interval - 1) & SDW_DPN_SAMPLECTRL_LOW;
545c3651 187 ret = sdw_write_no_pm(s_rt->slave, addr3, wbuf);
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188 if (ret < 0) {
189 dev_err(&s_rt->slave->dev,
17ed5bef 190 "DPN_SampleCtrl1 register write failed for port %d\n",
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191 t_params->port_num);
192 return ret;
193 }
194
195 /* Program DPN_OffsetCtrl1 registers */
545c3651 196 ret = sdw_write_no_pm(s_rt->slave, addr4, t_params->offset1);
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197 if (ret < 0) {
198 dev_err(&s_rt->slave->dev,
17ed5bef 199 "DPN_OffsetCtrl1 register write failed for port %d\n",
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200 t_params->port_num);
201 return ret;
202 }
203
204 /* Program DPN_BlockCtrl2 register*/
205 if (t_params->blk_grp_ctrl_valid) {
545c3651 206 ret = sdw_write_no_pm(s_rt->slave, addr5, t_params->blk_grp_ctrl);
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207 if (ret < 0) {
208 dev_err(&s_rt->slave->dev,
17ed5bef 209 "DPN_BlockCtrl2 reg write failed for port %d\n",
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210 t_params->port_num);
211 return ret;
212 }
213 }
214
215 /* program DPN_LaneCtrl register */
216 if (slave_prop->lane_control_support) {
545c3651 217 ret = sdw_write_no_pm(s_rt->slave, addr6, t_params->lane_ctrl);
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218 if (ret < 0) {
219 dev_err(&s_rt->slave->dev,
17ed5bef 220 "DPN_LaneCtrl register write failed for port %d\n",
f8101c74
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221 t_params->port_num);
222 return ret;
223 }
224 }
225
226 if (dpn_prop->type != SDW_DPN_SIMPLE) {
227 ret = _sdw_program_slave_port_params(bus, s_rt->slave,
1fe74a5e 228 t_params, dpn_prop->type);
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229 if (ret < 0)
230 dev_err(&s_rt->slave->dev,
17ed5bef 231 "Transport reg write failed for port: %d\n",
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232 t_params->port_num);
233 }
234
235 return ret;
236}
237
238static int sdw_program_master_port_params(struct sdw_bus *bus,
1fe74a5e 239 struct sdw_port_runtime *p_rt)
f8101c74
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240{
241 int ret;
242
243 /*
244 * we need to set transport and port parameters for the port.
7d3b3cdf 245 * Transport parameters refers to the sample interval, offsets and
f8101c74
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246 * hstart/stop etc of the data. Port parameters refers to word
247 * length, flow mode etc of the port
248 */
249 ret = bus->port_ops->dpn_set_port_transport_params(bus,
250 &p_rt->transport_params,
251 bus->params.next_bank);
252 if (ret < 0)
253 return ret;
254
255 return bus->port_ops->dpn_set_port_params(bus,
1fe74a5e
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256 &p_rt->port_params,
257 bus->params.next_bank);
f8101c74
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258}
259
260/**
261 * sdw_program_port_params() - Programs transport parameters of Master(s)
262 * and Slave(s)
263 *
264 * @m_rt: Master stream runtime
265 */
266static int sdw_program_port_params(struct sdw_master_runtime *m_rt)
267{
5920a29d 268 struct sdw_slave_runtime *s_rt;
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269 struct sdw_bus *bus = m_rt->bus;
270 struct sdw_port_runtime *p_rt;
271 int ret = 0;
272
273 /* Program transport & port parameters for Slave(s) */
274 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
275 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
276 ret = sdw_program_slave_port_params(bus, s_rt, p_rt);
277 if (ret < 0)
278 return ret;
279 }
280 }
281
282 /* Program transport & port parameters for Master(s) */
283 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
284 ret = sdw_program_master_port_params(bus, p_rt);
285 if (ret < 0)
286 return ret;
287 }
288
289 return 0;
290}
291
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292/**
293 * sdw_enable_disable_slave_ports: Enable/disable slave data port
294 *
295 * @bus: bus instance
296 * @s_rt: slave runtime
297 * @p_rt: port runtime
298 * @en: enable or disable operation
299 *
300 * This function only sets the enable/disable bits in the relevant bank, the
301 * actual enable/disable is done with a bank switch
302 */
303static int sdw_enable_disable_slave_ports(struct sdw_bus *bus,
1fe74a5e
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304 struct sdw_slave_runtime *s_rt,
305 struct sdw_port_runtime *p_rt,
306 bool en)
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307{
308 struct sdw_transport_params *t_params = &p_rt->transport_params;
309 u32 addr;
310 int ret;
311
312 if (bus->params.next_bank)
313 addr = SDW_DPN_CHANNELEN_B1(p_rt->num);
314 else
315 addr = SDW_DPN_CHANNELEN_B0(p_rt->num);
316
317 /*
318 * Since bus doesn't support sharing a port across two streams,
319 * it is safe to reset this register
320 */
321 if (en)
545c3651 322 ret = sdw_write_no_pm(s_rt->slave, addr, p_rt->ch_mask);
79df15b7 323 else
545c3651 324 ret = sdw_write_no_pm(s_rt->slave, addr, 0x0);
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325
326 if (ret < 0)
327 dev_err(&s_rt->slave->dev,
17ed5bef 328 "Slave chn_en reg write failed:%d port:%d\n",
79df15b7
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329 ret, t_params->port_num);
330
331 return ret;
332}
333
334static int sdw_enable_disable_master_ports(struct sdw_master_runtime *m_rt,
1fe74a5e
PLB
335 struct sdw_port_runtime *p_rt,
336 bool en)
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337{
338 struct sdw_transport_params *t_params = &p_rt->transport_params;
339 struct sdw_bus *bus = m_rt->bus;
340 struct sdw_enable_ch enable_ch;
a25eab29 341 int ret;
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342
343 enable_ch.port_num = p_rt->num;
344 enable_ch.ch_mask = p_rt->ch_mask;
345 enable_ch.enable = en;
346
347 /* Perform Master port channel(s) enable/disable */
348 if (bus->port_ops->dpn_port_enable_ch) {
349 ret = bus->port_ops->dpn_port_enable_ch(bus,
1fe74a5e
PLB
350 &enable_ch,
351 bus->params.next_bank);
79df15b7
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352 if (ret < 0) {
353 dev_err(bus->dev,
17ed5bef 354 "Master chn_en write failed:%d port:%d\n",
79df15b7
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355 ret, t_params->port_num);
356 return ret;
357 }
358 } else {
359 dev_err(bus->dev,
360 "dpn_port_enable_ch not supported, %s failed\n",
361 en ? "enable" : "disable");
362 return -EINVAL;
363 }
364
365 return 0;
366}
367
368/**
369 * sdw_enable_disable_ports() - Enable/disable port(s) for Master and
370 * Slave(s)
371 *
372 * @m_rt: Master stream runtime
373 * @en: mode (enable/disable)
374 */
375static int sdw_enable_disable_ports(struct sdw_master_runtime *m_rt, bool en)
376{
377 struct sdw_port_runtime *s_port, *m_port;
3a0be1a6 378 struct sdw_slave_runtime *s_rt;
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379 int ret = 0;
380
381 /* Enable/Disable Slave port(s) */
382 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
383 list_for_each_entry(s_port, &s_rt->port_list, port_node) {
384 ret = sdw_enable_disable_slave_ports(m_rt->bus, s_rt,
1fe74a5e 385 s_port, en);
79df15b7
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386 if (ret < 0)
387 return ret;
388 }
389 }
390
391 /* Enable/Disable Master port(s) */
392 list_for_each_entry(m_port, &m_rt->port_list, port_node) {
393 ret = sdw_enable_disable_master_ports(m_rt, m_port, en);
394 if (ret < 0)
395 return ret;
396 }
397
398 return 0;
399}
400
401static int sdw_do_port_prep(struct sdw_slave_runtime *s_rt,
1fe74a5e
PLB
402 struct sdw_prepare_ch prep_ch,
403 enum sdw_port_prep_ops cmd)
79df15b7 404{
bd29c00e
PLB
405 int ret = 0;
406 struct sdw_slave *slave = s_rt->slave;
79df15b7 407
bd29c00e
PLB
408 mutex_lock(&slave->sdw_dev_lock);
409
410 if (slave->probed) {
411 struct device *dev = &slave->dev;
412 struct sdw_driver *drv = drv_to_sdw_driver(dev->driver);
413
414 if (drv->ops && drv->ops->port_prep) {
415 ret = drv->ops->port_prep(slave, &prep_ch, cmd);
416 if (ret < 0)
417 dev_err(dev, "Slave Port Prep cmd %d failed: %d\n",
418 cmd, ret);
79df15b7
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419 }
420 }
421
bd29c00e
PLB
422 mutex_unlock(&slave->sdw_dev_lock);
423
424 return ret;
79df15b7
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425}
426
427static int sdw_prep_deprep_slave_ports(struct sdw_bus *bus,
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428 struct sdw_slave_runtime *s_rt,
429 struct sdw_port_runtime *p_rt,
430 bool prep)
79df15b7 431{
3a0be1a6 432 struct completion *port_ready;
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433 struct sdw_dpn_prop *dpn_prop;
434 struct sdw_prepare_ch prep_ch;
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435 bool intr = false;
436 int ret = 0, val;
437 u32 addr;
438
439 prep_ch.num = p_rt->num;
440 prep_ch.ch_mask = p_rt->ch_mask;
441
442 dpn_prop = sdw_get_slave_dpn_prop(s_rt->slave,
1fe74a5e
PLB
443 s_rt->direction,
444 prep_ch.num);
79df15b7
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445 if (!dpn_prop) {
446 dev_err(bus->dev,
17ed5bef 447 "Slave Port:%d properties not found\n", prep_ch.num);
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448 return -EINVAL;
449 }
450
451 prep_ch.prepare = prep;
452
453 prep_ch.bank = bus->params.next_bank;
454
dd87a72a
PLB
455 if (dpn_prop->imp_def_interrupts || !dpn_prop->simple_ch_prep_sm ||
456 bus->params.s_data_mode != SDW_PORT_DATA_MODE_NORMAL)
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457 intr = true;
458
459 /*
460 * Enable interrupt before Port prepare.
461 * For Port de-prepare, it is assumed that port
462 * was prepared earlier
463 */
464 if (prep && intr) {
465 ret = sdw_configure_dpn_intr(s_rt->slave, p_rt->num, prep,
8acbbfec 466 dpn_prop->imp_def_interrupts);
79df15b7
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467 if (ret < 0)
468 return ret;
469 }
470
471 /* Inform slave about the impending port prepare */
43f1a7f9 472 sdw_do_port_prep(s_rt, prep_ch, prep ? SDW_OPS_PORT_PRE_PREP : SDW_OPS_PORT_PRE_DEPREP);
79df15b7
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473
474 /* Prepare Slave port implementing CP_SM */
475 if (!dpn_prop->simple_ch_prep_sm) {
476 addr = SDW_DPN_PREPARECTRL(p_rt->num);
477
478 if (prep)
545c3651 479 ret = sdw_write_no_pm(s_rt->slave, addr, p_rt->ch_mask);
79df15b7 480 else
545c3651 481 ret = sdw_write_no_pm(s_rt->slave, addr, 0x0);
79df15b7
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482
483 if (ret < 0) {
484 dev_err(&s_rt->slave->dev,
17ed5bef 485 "Slave prep_ctrl reg write failed\n");
79df15b7
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486 return ret;
487 }
488
489 /* Wait for completion on port ready */
490 port_ready = &s_rt->slave->port_ready[prep_ch.num];
3d3e88e3
RF
491 wait_for_completion_timeout(port_ready,
492 msecs_to_jiffies(dpn_prop->ch_prep_timeout));
79df15b7 493
545c3651 494 val = sdw_read_no_pm(s_rt->slave, SDW_DPN_PREPARESTATUS(p_rt->num));
3d3e88e3
RF
495 if ((val < 0) || (val & p_rt->ch_mask)) {
496 ret = (val < 0) ? val : -ETIMEDOUT;
79df15b7 497 dev_err(&s_rt->slave->dev,
3d3e88e3
RF
498 "Chn prep failed for port %d: %d\n", prep_ch.num, ret);
499 return ret;
79df15b7
SK
500 }
501 }
502
503 /* Inform slaves about ports prepared */
43f1a7f9 504 sdw_do_port_prep(s_rt, prep_ch, prep ? SDW_OPS_PORT_POST_PREP : SDW_OPS_PORT_POST_DEPREP);
79df15b7
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505
506 /* Disable interrupt after Port de-prepare */
507 if (!prep && intr)
508 ret = sdw_configure_dpn_intr(s_rt->slave, p_rt->num, prep,
8acbbfec 509 dpn_prop->imp_def_interrupts);
79df15b7
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510
511 return ret;
512}
513
514static int sdw_prep_deprep_master_ports(struct sdw_master_runtime *m_rt,
1fe74a5e
PLB
515 struct sdw_port_runtime *p_rt,
516 bool prep)
79df15b7
SK
517{
518 struct sdw_transport_params *t_params = &p_rt->transport_params;
519 struct sdw_bus *bus = m_rt->bus;
520 const struct sdw_master_port_ops *ops = bus->port_ops;
521 struct sdw_prepare_ch prep_ch;
522 int ret = 0;
523
524 prep_ch.num = p_rt->num;
525 prep_ch.ch_mask = p_rt->ch_mask;
526 prep_ch.prepare = prep; /* Prepare/De-prepare */
527 prep_ch.bank = bus->params.next_bank;
528
529 /* Pre-prepare/Pre-deprepare port(s) */
530 if (ops->dpn_port_prep) {
531 ret = ops->dpn_port_prep(bus, &prep_ch);
532 if (ret < 0) {
17ed5bef 533 dev_err(bus->dev, "Port prepare failed for port:%d\n",
1fe74a5e 534 t_params->port_num);
79df15b7
SK
535 return ret;
536 }
537 }
538
539 return ret;
540}
541
542/**
543 * sdw_prep_deprep_ports() - Prepare/De-prepare port(s) for Master(s) and
544 * Slave(s)
545 *
546 * @m_rt: Master runtime handle
547 * @prep: Prepare or De-prepare
548 */
549static int sdw_prep_deprep_ports(struct sdw_master_runtime *m_rt, bool prep)
550{
3a0be1a6 551 struct sdw_slave_runtime *s_rt;
79df15b7
SK
552 struct sdw_port_runtime *p_rt;
553 int ret = 0;
554
555 /* Prepare/De-prepare Slave port(s) */
556 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
557 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
558 ret = sdw_prep_deprep_slave_ports(m_rt->bus, s_rt,
1fe74a5e 559 p_rt, prep);
79df15b7
SK
560 if (ret < 0)
561 return ret;
562 }
563 }
564
565 /* Prepare/De-prepare Master port(s) */
566 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
567 ret = sdw_prep_deprep_master_ports(m_rt, p_rt, prep);
568 if (ret < 0)
569 return ret;
570 }
571
572 return ret;
573}
574
99b8a5d6
SK
575/**
576 * sdw_notify_config() - Notify bus configuration
577 *
578 * @m_rt: Master runtime handle
579 *
580 * This function notifies the Master(s) and Slave(s) of the
581 * new bus configuration.
582 */
583static int sdw_notify_config(struct sdw_master_runtime *m_rt)
584{
585 struct sdw_slave_runtime *s_rt;
586 struct sdw_bus *bus = m_rt->bus;
587 struct sdw_slave *slave;
bd29c00e 588 int ret;
99b8a5d6
SK
589
590 if (bus->ops->set_bus_conf) {
591 ret = bus->ops->set_bus_conf(bus, &bus->params);
592 if (ret < 0)
593 return ret;
594 }
595
596 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
597 slave = s_rt->slave;
598
bd29c00e
PLB
599 mutex_lock(&slave->sdw_dev_lock);
600
601 if (slave->probed) {
602 struct device *dev = &slave->dev;
603 struct sdw_driver *drv = drv_to_sdw_driver(dev->driver);
604
605 if (drv->ops && drv->ops->bus_config) {
606 ret = drv->ops->bus_config(slave, &bus->params);
607 if (ret < 0) {
608 dev_err(dev, "Notify Slave: %d failed\n",
609 slave->dev_num);
610 mutex_unlock(&slave->sdw_dev_lock);
611 return ret;
612 }
60835022 613 }
99b8a5d6 614 }
bd29c00e
PLB
615
616 mutex_unlock(&slave->sdw_dev_lock);
99b8a5d6
SK
617 }
618
bd29c00e 619 return 0;
99b8a5d6
SK
620}
621
622/**
623 * sdw_program_params() - Program transport and port parameters for Master(s)
624 * and Slave(s)
625 *
626 * @bus: SDW bus instance
bfaa3549 627 * @prepare: true if sdw_program_params() is called by _prepare.
99b8a5d6 628 */
bfaa3549 629static int sdw_program_params(struct sdw_bus *bus, bool prepare)
99b8a5d6 630{
3a0be1a6 631 struct sdw_master_runtime *m_rt;
99b8a5d6
SK
632 int ret = 0;
633
634 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
bfaa3549
RW
635
636 /*
637 * this loop walks through all master runtimes for a
638 * bus, but the ports can only be configured while
639 * explicitly preparing a stream or handling an
640 * already-prepared stream otherwise.
641 */
642 if (!prepare &&
643 m_rt->stream->state == SDW_STREAM_CONFIGURED)
644 continue;
645
99b8a5d6
SK
646 ret = sdw_program_port_params(m_rt);
647 if (ret < 0) {
648 dev_err(bus->dev,
17ed5bef 649 "Program transport params failed: %d\n", ret);
99b8a5d6
SK
650 return ret;
651 }
652
653 ret = sdw_notify_config(m_rt);
654 if (ret < 0) {
62f0cec3
VK
655 dev_err(bus->dev,
656 "Notify bus config failed: %d\n", ret);
99b8a5d6
SK
657 return ret;
658 }
659
660 /* Enable port(s) on alternate bank for all active streams */
661 if (m_rt->stream->state != SDW_STREAM_ENABLED)
662 continue;
663
664 ret = sdw_enable_disable_ports(m_rt, true);
665 if (ret < 0) {
17ed5bef 666 dev_err(bus->dev, "Enable channel failed: %d\n", ret);
99b8a5d6
SK
667 return ret;
668 }
669 }
670
671 return ret;
672}
673
ce6e74d0 674static int sdw_bank_switch(struct sdw_bus *bus, int m_rt_count)
99b8a5d6
SK
675{
676 int col_index, row_index;
ce6e74d0 677 bool multi_link;
99b8a5d6 678 struct sdw_msg *wr_msg;
3a0be1a6
PLB
679 u8 *wbuf;
680 int ret;
99b8a5d6
SK
681 u16 addr;
682
683 wr_msg = kzalloc(sizeof(*wr_msg), GFP_KERNEL);
684 if (!wr_msg)
685 return -ENOMEM;
686
687 wbuf = kzalloc(sizeof(*wbuf), GFP_KERNEL);
688 if (!wbuf) {
689 ret = -ENOMEM;
690 goto error_1;
691 }
692
693 /* Get row and column index to program register */
694 col_index = sdw_find_col_index(bus->params.col);
695 row_index = sdw_find_row_index(bus->params.row);
696 wbuf[0] = col_index | (row_index << 3);
697
698 if (bus->params.next_bank)
699 addr = SDW_SCP_FRAMECTRL_B1;
700 else
701 addr = SDW_SCP_FRAMECTRL_B0;
702
703 sdw_fill_msg(wr_msg, NULL, addr, 1, SDW_BROADCAST_DEV_NUM,
1fe74a5e 704 SDW_MSG_FLAG_WRITE, wbuf);
99b8a5d6
SK
705 wr_msg->ssp_sync = true;
706
ce6e74d0
SN
707 /*
708 * Set the multi_link flag only when both the hardware supports
063ff4e5 709 * and hardware-based sync is required
ce6e74d0 710 */
063ff4e5 711 multi_link = bus->multi_link && (m_rt_count >= bus->hw_sync_min_links);
ce6e74d0
SN
712
713 if (multi_link)
45cb70f9 714 ret = sdw_transfer_defer(bus, wr_msg);
ce6e74d0
SN
715 else
716 ret = sdw_transfer(bus, wr_msg);
717
e6645314 718 if (ret < 0 && ret != -ENODATA) {
17ed5bef 719 dev_err(bus->dev, "Slave frame_ctrl reg write failed\n");
99b8a5d6
SK
720 goto error;
721 }
722
ce6e74d0 723 if (!multi_link) {
ce6e74d0 724 kfree(wbuf);
5ec0c872 725 kfree(wr_msg);
ce6e74d0
SN
726 bus->defer_msg.msg = NULL;
727 bus->params.curr_bank = !bus->params.curr_bank;
728 bus->params.next_bank = !bus->params.next_bank;
729 }
99b8a5d6
SK
730
731 return 0;
732
733error:
734 kfree(wbuf);
735error_1:
736 kfree(wr_msg);
3fbbf214 737 bus->defer_msg.msg = NULL;
99b8a5d6
SK
738 return ret;
739}
740
ce6e74d0
SN
741/**
742 * sdw_ml_sync_bank_switch: Multilink register bank switch
743 *
744 * @bus: SDW bus instance
745 *
746 * Caller function should free the buffers on error
747 */
748static int sdw_ml_sync_bank_switch(struct sdw_bus *bus)
749{
750 unsigned long time_left;
751
752 if (!bus->multi_link)
753 return 0;
754
755 /* Wait for completion of transfer */
756 time_left = wait_for_completion_timeout(&bus->defer_msg.complete,
757 bus->bank_switch_timeout);
758
759 if (!time_left) {
17ed5bef 760 dev_err(bus->dev, "Controller Timed out on bank switch\n");
ce6e74d0
SN
761 return -ETIMEDOUT;
762 }
763
764 bus->params.curr_bank = !bus->params.curr_bank;
765 bus->params.next_bank = !bus->params.next_bank;
766
767 if (bus->defer_msg.msg) {
768 kfree(bus->defer_msg.msg->buf);
769 kfree(bus->defer_msg.msg);
5ec0c872 770 bus->defer_msg.msg = NULL;
ce6e74d0
SN
771 }
772
773 return 0;
774}
775
99b8a5d6
SK
776static int do_bank_switch(struct sdw_stream_runtime *stream)
777{
3a0be1a6 778 struct sdw_master_runtime *m_rt;
99b8a5d6 779 const struct sdw_master_ops *ops;
3a0be1a6 780 struct sdw_bus *bus;
ce6e74d0 781 bool multi_link = false;
063ff4e5 782 int m_rt_count;
99b8a5d6
SK
783 int ret = 0;
784
063ff4e5
PLB
785 m_rt_count = stream->m_rt_count;
786
48949722
VK
787 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
788 bus = m_rt->bus;
789 ops = bus->ops;
790
063ff4e5 791 if (bus->multi_link && m_rt_count >= bus->hw_sync_min_links) {
ce6e74d0
SN
792 multi_link = true;
793 mutex_lock(&bus->msg_lock);
794 }
795
48949722
VK
796 /* Pre-bank switch */
797 if (ops->pre_bank_switch) {
798 ret = ops->pre_bank_switch(bus);
799 if (ret < 0) {
800 dev_err(bus->dev,
17ed5bef 801 "Pre bank switch op failed: %d\n", ret);
ce6e74d0 802 goto msg_unlock;
48949722
VK
803 }
804 }
805
ce6e74d0
SN
806 /*
807 * Perform Bank switch operation.
808 * For multi link cases, the actual bank switch is
809 * synchronized across all Masters and happens later as a
810 * part of post_bank_switch ops.
811 */
063ff4e5 812 ret = sdw_bank_switch(bus, m_rt_count);
99b8a5d6 813 if (ret < 0) {
17ed5bef 814 dev_err(bus->dev, "Bank switch failed: %d\n", ret);
ce6e74d0 815 goto error;
99b8a5d6
SK
816 }
817 }
818
ce6e74d0
SN
819 /*
820 * For multi link cases, it is expected that the bank switch is
821 * triggered by the post_bank_switch for the first Master in the list
822 * and for the other Masters the post_bank_switch() should return doing
823 * nothing.
824 */
48949722
VK
825 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
826 bus = m_rt->bus;
827 ops = bus->ops;
99b8a5d6 828
48949722
VK
829 /* Post-bank switch */
830 if (ops->post_bank_switch) {
831 ret = ops->post_bank_switch(bus);
832 if (ret < 0) {
833 dev_err(bus->dev,
62f0cec3
VK
834 "Post bank switch op failed: %d\n",
835 ret);
ce6e74d0 836 goto error;
48949722 837 }
063ff4e5 838 } else if (multi_link) {
ce6e74d0 839 dev_err(bus->dev,
17ed5bef 840 "Post bank switch ops not implemented\n");
a7ad7ce4 841 ret = -EINVAL;
ce6e74d0
SN
842 goto error;
843 }
844
845 /* Set the bank switch timeout to default, if not set */
846 if (!bus->bank_switch_timeout)
847 bus->bank_switch_timeout = DEFAULT_BANK_SWITCH_TIMEOUT;
848
849 /* Check if bank switch was successful */
850 ret = sdw_ml_sync_bank_switch(bus);
851 if (ret < 0) {
852 dev_err(bus->dev,
17ed5bef 853 "multi link bank switch failed: %d\n", ret);
ce6e74d0
SN
854 goto error;
855 }
856
063ff4e5 857 if (multi_link)
9315d904 858 mutex_unlock(&bus->msg_lock);
ce6e74d0
SN
859 }
860
861 return ret;
862
863error:
864 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
ce6e74d0 865 bus = m_rt->bus;
3fbbf214
TR
866 if (bus->defer_msg.msg) {
867 kfree(bus->defer_msg.msg->buf);
868 kfree(bus->defer_msg.msg);
5ec0c872 869 bus->defer_msg.msg = NULL;
3fbbf214 870 }
ce6e74d0
SN
871 }
872
873msg_unlock:
874
875 if (multi_link) {
876 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
877 bus = m_rt->bus;
878 if (mutex_is_locked(&bus->msg_lock))
879 mutex_unlock(&bus->msg_lock);
99b8a5d6
SK
880 }
881 }
882
883 return ret;
884}
885
6ccf3292
PLB
886static struct sdw_port_runtime *sdw_port_alloc(struct list_head *port_list)
887{
888 struct sdw_port_runtime *p_rt;
889
890 p_rt = kzalloc(sizeof(*p_rt), GFP_KERNEL);
891 if (!p_rt)
892 return NULL;
893
894 list_add_tail(&p_rt->port_node, port_list);
895
896 return p_rt;
897}
898
899static int sdw_port_config(struct sdw_port_runtime *p_rt,
900 struct sdw_port_config *port_config,
901 int port_index)
902{
903 p_rt->ch_mask = port_config[port_index].ch_mask;
904 p_rt->num = port_config[port_index].num;
905
906 /*
907 * TODO: Check port capabilities for requested configuration
908 */
909
910 return 0;
911}
912
913static void sdw_port_free(struct sdw_port_runtime *p_rt)
914{
915 list_del(&p_rt->port_node);
916 kfree(p_rt);
917}
918
f3016b89
PLB
919static bool sdw_slave_port_allocated(struct sdw_slave_runtime *s_rt)
920{
921 return !list_empty(&s_rt->port_list);
922}
923
c7aa9d77
PLB
924static void sdw_slave_port_free(struct sdw_slave *slave,
925 struct sdw_stream_runtime *stream)
926{
927 struct sdw_port_runtime *p_rt, *_p_rt;
928 struct sdw_master_runtime *m_rt;
929 struct sdw_slave_runtime *s_rt;
930
931 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
932 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
933 if (s_rt->slave != slave)
934 continue;
935
936 list_for_each_entry_safe(p_rt, _p_rt,
937 &s_rt->port_list, port_node) {
938 sdw_port_free(p_rt);
939 }
940 }
941 }
942}
943
944static int sdw_slave_port_alloc(struct sdw_slave *slave,
945 struct sdw_slave_runtime *s_rt,
946 unsigned int num_config)
947{
948 struct sdw_port_runtime *p_rt;
949 int i;
950
951 /* Iterate for number of ports to perform initialization */
952 for (i = 0; i < num_config; i++) {
953 p_rt = sdw_port_alloc(&s_rt->port_list);
954 if (!p_rt)
955 return -ENOMEM;
956 }
957
958 return 0;
959}
960
961static int sdw_slave_port_is_valid_range(struct device *dev, int num)
962{
963 if (!SDW_VALID_PORT_RANGE(num)) {
964 dev_err(dev, "SoundWire: Invalid port number :%d\n", num);
965 return -EINVAL;
966 }
967
968 return 0;
969}
970
971static int sdw_slave_port_config(struct sdw_slave *slave,
972 struct sdw_slave_runtime *s_rt,
973 struct sdw_port_config *port_config)
974{
975 struct sdw_port_runtime *p_rt;
976 int ret;
977 int i;
978
979 i = 0;
980 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
981 /*
982 * TODO: Check valid port range as defined by DisCo/
983 * slave
984 */
985 ret = sdw_slave_port_is_valid_range(&slave->dev, port_config[i].num);
986 if (ret < 0)
987 return ret;
988
989 ret = sdw_port_config(p_rt, port_config, i);
990 if (ret < 0)
991 return ret;
992 i++;
993 }
994
995 return 0;
996}
997
f3016b89
PLB
998static bool sdw_master_port_allocated(struct sdw_master_runtime *m_rt)
999{
1000 return !list_empty(&m_rt->port_list);
1001}
1002
c7aa9d77
PLB
1003static void sdw_master_port_free(struct sdw_master_runtime *m_rt)
1004{
1005 struct sdw_port_runtime *p_rt, *_p_rt;
1006
1007 list_for_each_entry_safe(p_rt, _p_rt, &m_rt->port_list, port_node) {
1008 sdw_port_free(p_rt);
1009 }
1010}
1011
1012static int sdw_master_port_alloc(struct sdw_master_runtime *m_rt,
1013 unsigned int num_ports)
1014{
1015 struct sdw_port_runtime *p_rt;
1016 int i;
1017
1018 /* Iterate for number of ports to perform initialization */
1019 for (i = 0; i < num_ports; i++) {
1020 p_rt = sdw_port_alloc(&m_rt->port_list);
1021 if (!p_rt)
1022 return -ENOMEM;
1023 }
1024
1025 return 0;
1026}
1027
1028static int sdw_master_port_config(struct sdw_master_runtime *m_rt,
1029 struct sdw_port_config *port_config)
1030{
1031 struct sdw_port_runtime *p_rt;
1032 int ret;
1033 int i;
1034
1035 i = 0;
1036 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
1037 ret = sdw_port_config(p_rt, port_config, i);
1038 if (ret < 0)
1039 return ret;
1040 i++;
1041 }
1042
1043 return 0;
1044}
1045
bf75ba4b 1046/**
edd5cf99 1047 * sdw_slave_rt_alloc() - Allocate a Slave runtime handle.
bf75ba4b
PLB
1048 *
1049 * @slave: Slave handle
42aad41e 1050 * @m_rt: Master runtime handle
bf75ba4b
PLB
1051 *
1052 * This function is to be called with bus_lock held.
1053 */
1054static struct sdw_slave_runtime
42aad41e
PLB
1055*sdw_slave_rt_alloc(struct sdw_slave *slave,
1056 struct sdw_master_runtime *m_rt)
bf75ba4b
PLB
1057{
1058 struct sdw_slave_runtime *s_rt;
1059
1060 s_rt = kzalloc(sizeof(*s_rt), GFP_KERNEL);
1061 if (!s_rt)
1062 return NULL;
1063
1064 INIT_LIST_HEAD(&s_rt->port_list);
bf75ba4b
PLB
1065 s_rt->slave = slave;
1066
42aad41e
PLB
1067 list_add_tail(&s_rt->m_rt_node, &m_rt->slave_rt_list);
1068
bf75ba4b
PLB
1069 return s_rt;
1070}
1071
edd5cf99
PLB
1072/**
1073 * sdw_slave_rt_config() - Configure a Slave runtime handle.
1074 *
1075 * @s_rt: Slave runtime handle
1076 * @stream_config: Stream configuration
1077 *
1078 * This function is to be called with bus_lock held.
1079 */
1080static int sdw_slave_rt_config(struct sdw_slave_runtime *s_rt,
1081 struct sdw_stream_config *stream_config)
1082{
1083 s_rt->ch_count = stream_config->ch_count;
1084 s_rt->direction = stream_config->direction;
1085
1086 return 0;
1087}
1088
5e1df543
PLB
1089static struct sdw_slave_runtime *sdw_slave_rt_find(struct sdw_slave *slave,
1090 struct sdw_stream_runtime *stream)
1091{
1092 struct sdw_slave_runtime *s_rt, *_s_rt;
1093 struct sdw_master_runtime *m_rt;
1094
1095 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1096 /* Retrieve Slave runtime handle */
1097 list_for_each_entry_safe(s_rt, _s_rt,
1098 &m_rt->slave_rt_list, m_rt_node) {
1099 if (s_rt->slave == slave)
1100 return s_rt;
1101 }
1102 }
1103 return NULL;
1104}
1105
00ce0d2a
PLB
1106/**
1107 * sdw_slave_rt_free() - Free Slave(s) runtime handle
1108 *
1109 * @slave: Slave handle.
1110 * @stream: Stream runtime handle.
1111 *
1112 * This function is to be called with bus_lock held.
1113 */
1114static void sdw_slave_rt_free(struct sdw_slave *slave,
1115 struct sdw_stream_runtime *stream)
1116{
5e1df543 1117 struct sdw_slave_runtime *s_rt;
00ce0d2a 1118
5e1df543
PLB
1119 s_rt = sdw_slave_rt_find(slave, stream);
1120 if (s_rt) {
1121 list_del(&s_rt->m_rt_node);
1122 kfree(s_rt);
00ce0d2a
PLB
1123 }
1124}
1125
48949722 1126static struct sdw_master_runtime
bb10659a 1127*sdw_master_rt_find(struct sdw_bus *bus,
1fe74a5e 1128 struct sdw_stream_runtime *stream)
48949722 1129{
3a0be1a6 1130 struct sdw_master_runtime *m_rt;
48949722
VK
1131
1132 /* Retrieve Bus handle if already available */
1133 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1134 if (m_rt->bus == bus)
1135 return m_rt;
1136 }
1137
1138 return NULL;
1139}
1140
89e59053 1141/**
bb10659a 1142 * sdw_master_rt_alloc() - Allocates a Master runtime handle
89e59053
SK
1143 *
1144 * @bus: SDW bus instance
89e59053
SK
1145 * @stream: Stream runtime handle.
1146 *
1147 * This function is to be called with bus_lock held.
1148 */
1149static struct sdw_master_runtime
bb10659a 1150*sdw_master_rt_alloc(struct sdw_bus *bus,
1fe74a5e 1151 struct sdw_stream_runtime *stream)
89e59053
SK
1152{
1153 struct sdw_master_runtime *m_rt;
1154
89e59053
SK
1155 m_rt = kzalloc(sizeof(*m_rt), GFP_KERNEL);
1156 if (!m_rt)
1157 return NULL;
1158
1159 /* Initialization of Master runtime handle */
bbe7379d 1160 INIT_LIST_HEAD(&m_rt->port_list);
89e59053 1161 INIT_LIST_HEAD(&m_rt->slave_rt_list);
48949722 1162 list_add_tail(&m_rt->stream_node, &stream->master_list);
89e59053
SK
1163
1164 list_add_tail(&m_rt->bus_node, &bus->m_rt_list);
1165
89e59053
SK
1166 m_rt->bus = bus;
1167 m_rt->stream = stream;
89e59053
SK
1168
1169 return m_rt;
1170}
1171
bb10659a
PLB
1172/**
1173 * sdw_master_rt_config() - Configure Master runtime handle
1174 *
1175 * @m_rt: Master runtime handle
1176 * @stream_config: Stream configuration
1177 *
1178 * This function is to be called with bus_lock held.
1179 */
1180
1181static int sdw_master_rt_config(struct sdw_master_runtime *m_rt,
1182 struct sdw_stream_config *stream_config)
1183{
1184 m_rt->ch_count = stream_config->ch_count;
1185 m_rt->direction = stream_config->direction;
1186
1187 return 0;
1188}
1189
89e59053 1190/**
00ce0d2a 1191 * sdw_master_rt_free() - Free Master runtime handle
89e59053 1192 *
48949722 1193 * @m_rt: Master runtime node
89e59053
SK
1194 * @stream: Stream runtime handle.
1195 *
1196 * This function is to be called with bus_lock held
1197 * It frees the Master runtime handle and associated Slave(s) runtime
00ce0d2a 1198 * handle. If this is called first then sdw_slave_rt_free() will have
89e59053
SK
1199 * no effect as Slave(s) runtime handle would already be freed up.
1200 */
00ce0d2a
PLB
1201static void sdw_master_rt_free(struct sdw_master_runtime *m_rt,
1202 struct sdw_stream_runtime *stream)
89e59053 1203{
89e59053
SK
1204 struct sdw_slave_runtime *s_rt, *_s_rt;
1205
8d6ccf5c 1206 list_for_each_entry_safe(s_rt, _s_rt, &m_rt->slave_rt_list, m_rt_node) {
c7aa9d77 1207 sdw_slave_port_free(s_rt->slave, stream);
00ce0d2a 1208 sdw_slave_rt_free(s_rt->slave, stream);
8d6ccf5c 1209 }
89e59053 1210
48949722 1211 list_del(&m_rt->stream_node);
89e59053 1212 list_del(&m_rt->bus_node);
48949722 1213 kfree(m_rt);
89e59053
SK
1214}
1215
89e59053
SK
1216/**
1217 * sdw_config_stream() - Configure the allocated stream
1218 *
1219 * @dev: SDW device
1220 * @stream: SoundWire stream
1221 * @stream_config: Stream configuration for audio stream
1222 * @is_slave: is API called from Slave or Master
1223 *
1224 * This function is to be called with bus_lock held.
1225 */
1226static int sdw_config_stream(struct device *dev,
1fe74a5e
PLB
1227 struct sdw_stream_runtime *stream,
1228 struct sdw_stream_config *stream_config,
1229 bool is_slave)
89e59053
SK
1230{
1231 /*
1232 * Update the stream rate, channel and bps based on data
1233 * source. For more than one data source (multilink),
1234 * match the rate, bps, stream type and increment number of channels.
1235 *
1236 * If rate/bps is zero, it means the values are not set, so skip
1237 * comparison and allow the value to be set and stored in stream
1238 */
1239 if (stream->params.rate &&
1fe74a5e 1240 stream->params.rate != stream_config->frame_rate) {
17ed5bef 1241 dev_err(dev, "rate not matching, stream:%s\n", stream->name);
89e59053
SK
1242 return -EINVAL;
1243 }
1244
1245 if (stream->params.bps &&
1fe74a5e 1246 stream->params.bps != stream_config->bps) {
17ed5bef 1247 dev_err(dev, "bps not matching, stream:%s\n", stream->name);
89e59053
SK
1248 return -EINVAL;
1249 }
1250
1251 stream->type = stream_config->type;
1252 stream->params.rate = stream_config->frame_rate;
1253 stream->params.bps = stream_config->bps;
1254
1255 /* TODO: Update this check during Device-device support */
1256 if (is_slave)
1257 stream->params.ch_count += stream_config->ch_count;
1258
1259 return 0;
1260}
1261
1262/**
7a908906 1263 * sdw_get_slave_dpn_prop() - Get Slave port capabilities
89e59053 1264 *
7a908906
PLB
1265 * @slave: Slave handle
1266 * @direction: Data direction.
1267 * @port_num: Port number
89e59053 1268 */
7a908906
PLB
1269struct sdw_dpn_prop *sdw_get_slave_dpn_prop(struct sdw_slave *slave,
1270 enum sdw_data_direction direction,
1271 unsigned int port_num)
89e59053 1272{
7a908906
PLB
1273 struct sdw_dpn_prop *dpn_prop;
1274 u8 num_ports;
1275 int i;
89e59053 1276
7a908906
PLB
1277 if (direction == SDW_DATA_DIR_TX) {
1278 num_ports = hweight32(slave->prop.source_ports);
1279 dpn_prop = slave->prop.src_dpn_prop;
1280 } else {
1281 num_ports = hweight32(slave->prop.sink_ports);
1282 dpn_prop = slave->prop.sink_dpn_prop;
ce6e74d0
SN
1283 }
1284
7a908906
PLB
1285 for (i = 0; i < num_ports; i++) {
1286 if (dpn_prop[i].num == port_num)
1287 return &dpn_prop[i];
89e59053
SK
1288 }
1289
7a908906
PLB
1290 return NULL;
1291}
bbe7379d 1292
7a908906
PLB
1293/**
1294 * sdw_acquire_bus_lock: Acquire bus lock for all Master runtime(s)
1295 *
1296 * @stream: SoundWire stream
1297 *
1298 * Acquire bus_lock for each of the master runtime(m_rt) part of this
1299 * stream to reconfigure the bus.
1300 * NOTE: This function is called from SoundWire stream ops and is
1301 * expected that a global lock is held before acquiring bus_lock.
1302 */
1303static void sdw_acquire_bus_lock(struct sdw_stream_runtime *stream)
1304{
1305 struct sdw_master_runtime *m_rt;
1306 struct sdw_bus *bus;
ce6e74d0 1307
7a908906
PLB
1308 /* Iterate for all Master(s) in Master list */
1309 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1310 bus = m_rt->bus;
3fef1a22 1311
7a908906
PLB
1312 mutex_lock(&bus->bus_lock);
1313 }
89e59053 1314}
89e59053
SK
1315
1316/**
7a908906 1317 * sdw_release_bus_lock: Release bus lock for all Master runtime(s)
89e59053 1318 *
89e59053 1319 * @stream: SoundWire stream
0aebe40b 1320 *
7a908906
PLB
1321 * Release the previously held bus_lock after reconfiguring the bus.
1322 * NOTE: This function is called from SoundWire stream ops and is
1323 * expected that a global lock is held before releasing bus_lock.
89e59053 1324 */
7a908906
PLB
1325static void sdw_release_bus_lock(struct sdw_stream_runtime *stream)
1326{
1327 struct sdw_master_runtime *m_rt;
1328 struct sdw_bus *bus;
1329
1330 /* Iterate for all Master(s) in Master list */
1331 list_for_each_entry_reverse(m_rt, &stream->master_list, stream_node) {
1332 bus = m_rt->bus;
1333 mutex_unlock(&bus->bus_lock);
1334 }
1335}
1336
1337static int _sdw_prepare_stream(struct sdw_stream_runtime *stream,
1338 bool update_params)
89e59053 1339{
89e59053 1340 struct sdw_master_runtime *m_rt;
7a908906
PLB
1341 struct sdw_bus *bus = NULL;
1342 struct sdw_master_prop *prop;
1343 struct sdw_bus_params params;
89e59053
SK
1344 int ret;
1345
7a908906
PLB
1346 /* Prepare Master(s) and Slave(s) port(s) associated with stream */
1347 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1348 bus = m_rt->bus;
1349 prop = &bus->prop;
1350 memcpy(&params, &bus->params, sizeof(params));
89e59053 1351
7a908906
PLB
1352 /* TODO: Support Asynchronous mode */
1353 if ((prop->max_clk_freq % stream->params.rate) != 0) {
1354 dev_err(bus->dev, "Async mode not supported\n");
1355 return -EINVAL;
1356 }
5c3eb9f7 1357
c7a8f049
PLB
1358 if (!update_params)
1359 goto program_params;
1360
48949722
VK
1361 /* Increment cumulative bus bandwidth */
1362 /* TODO: Update this during Device-Device support */
1363 bus->params.bandwidth += m_rt->stream->params.rate *
1364 m_rt->ch_count * m_rt->stream->params.bps;
1365
c7578c1d
VK
1366 /* Compute params */
1367 if (bus->compute_params) {
1368 ret = bus->compute_params(bus);
1369 if (ret < 0) {
6122d3be 1370 dev_err(bus->dev, "Compute params failed: %d\n",
c7578c1d 1371 ret);
acdae463 1372 goto restore_params;
c7578c1d
VK
1373 }
1374 }
1375
c7a8f049 1376program_params:
48949722 1377 /* Program params */
bfaa3549 1378 ret = sdw_program_params(bus, true);
48949722 1379 if (ret < 0) {
17ed5bef 1380 dev_err(bus->dev, "Program params failed: %d\n", ret);
48949722
VK
1381 goto restore_params;
1382 }
5c3eb9f7
SK
1383 }
1384
3a0be1a6
PLB
1385 if (!bus) {
1386 pr_err("Configuration error in %s\n", __func__);
1387 return -EINVAL;
1388 }
1389
5c3eb9f7
SK
1390 ret = do_bank_switch(stream);
1391 if (ret < 0) {
68d9bfb6 1392 pr_err("%s: do_bank_switch failed: %d\n", __func__, ret);
5c3eb9f7
SK
1393 goto restore_params;
1394 }
1395
48949722
VK
1396 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1397 bus = m_rt->bus;
1398
1399 /* Prepare port(s) on the new clock configuration */
1400 ret = sdw_prep_deprep_ports(m_rt, true);
1401 if (ret < 0) {
17ed5bef 1402 dev_err(bus->dev, "Prepare port(s) failed ret = %d\n",
1fe74a5e 1403 ret);
48949722
VK
1404 return ret;
1405 }
5c3eb9f7
SK
1406 }
1407
1408 stream->state = SDW_STREAM_PREPARED;
1409
1410 return ret;
1411
1412restore_params:
1413 memcpy(&bus->params, &params, sizeof(params));
1414 return ret;
1415}
1416
1417/**
1418 * sdw_prepare_stream() - Prepare SoundWire stream
1419 *
1420 * @stream: Soundwire stream
1421 *
34962fb8 1422 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
5c3eb9f7
SK
1423 */
1424int sdw_prepare_stream(struct sdw_stream_runtime *stream)
1425{
c7a8f049 1426 bool update_params = true;
c32464c9 1427 int ret;
5c3eb9f7
SK
1428
1429 if (!stream) {
17ed5bef 1430 pr_err("SoundWire: Handle not found for stream\n");
5c3eb9f7
SK
1431 return -EINVAL;
1432 }
1433
48949722 1434 sdw_acquire_bus_lock(stream);
5c3eb9f7 1435
c32464c9
BL
1436 if (stream->state == SDW_STREAM_PREPARED) {
1437 ret = 0;
1438 goto state_err;
1439 }
1440
59528807
PLB
1441 if (stream->state != SDW_STREAM_CONFIGURED &&
1442 stream->state != SDW_STREAM_DEPREPARED &&
1443 stream->state != SDW_STREAM_DISABLED) {
1444 pr_err("%s: %s: inconsistent state state %d\n",
1445 __func__, stream->name, stream->state);
1446 ret = -EINVAL;
1447 goto state_err;
1448 }
1449
c7a8f049
PLB
1450 /*
1451 * when the stream is DISABLED, this means sdw_prepare_stream()
1452 * is called as a result of an underflow or a resume operation.
1453 * In this case, the bus parameters shall not be recomputed, but
1454 * still need to be re-applied
1455 */
1456 if (stream->state == SDW_STREAM_DISABLED)
1457 update_params = false;
1458
1459 ret = _sdw_prepare_stream(stream, update_params);
5c3eb9f7 1460
59528807 1461state_err:
48949722 1462 sdw_release_bus_lock(stream);
5c3eb9f7
SK
1463 return ret;
1464}
1465EXPORT_SYMBOL(sdw_prepare_stream);
1466
1467static int _sdw_enable_stream(struct sdw_stream_runtime *stream)
1468{
3a0be1a6 1469 struct sdw_master_runtime *m_rt;
48949722 1470 struct sdw_bus *bus = NULL;
5c3eb9f7
SK
1471 int ret;
1472
48949722
VK
1473 /* Enable Master(s) and Slave(s) port(s) associated with stream */
1474 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1475 bus = m_rt->bus;
5c3eb9f7 1476
48949722 1477 /* Program params */
bfaa3549 1478 ret = sdw_program_params(bus, false);
48949722 1479 if (ret < 0) {
68d9bfb6 1480 dev_err(bus->dev, "%s: Program params failed: %d\n", __func__, ret);
48949722
VK
1481 return ret;
1482 }
1483
1484 /* Enable port(s) */
1485 ret = sdw_enable_disable_ports(m_rt, true);
1486 if (ret < 0) {
62f0cec3
VK
1487 dev_err(bus->dev,
1488 "Enable port(s) failed ret: %d\n", ret);
48949722
VK
1489 return ret;
1490 }
5c3eb9f7
SK
1491 }
1492
3a0be1a6
PLB
1493 if (!bus) {
1494 pr_err("Configuration error in %s\n", __func__);
1495 return -EINVAL;
1496 }
1497
5c3eb9f7
SK
1498 ret = do_bank_switch(stream);
1499 if (ret < 0) {
68d9bfb6 1500 pr_err("%s: do_bank_switch failed: %d\n", __func__, ret);
5c3eb9f7
SK
1501 return ret;
1502 }
1503
1504 stream->state = SDW_STREAM_ENABLED;
1505 return 0;
1506}
1507
1508/**
1509 * sdw_enable_stream() - Enable SoundWire stream
1510 *
1511 * @stream: Soundwire stream
1512 *
34962fb8 1513 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
5c3eb9f7
SK
1514 */
1515int sdw_enable_stream(struct sdw_stream_runtime *stream)
1516{
3a0be1a6 1517 int ret;
5c3eb9f7
SK
1518
1519 if (!stream) {
17ed5bef 1520 pr_err("SoundWire: Handle not found for stream\n");
5c3eb9f7
SK
1521 return -EINVAL;
1522 }
1523
48949722 1524 sdw_acquire_bus_lock(stream);
5c3eb9f7 1525
63fadaa2
PLB
1526 if (stream->state == SDW_STREAM_ENABLED) {
1527 ret = 0;
1528 goto state_err;
1529 }
1530
59528807
PLB
1531 if (stream->state != SDW_STREAM_PREPARED &&
1532 stream->state != SDW_STREAM_DISABLED) {
1533 pr_err("%s: %s: inconsistent state state %d\n",
1534 __func__, stream->name, stream->state);
1535 ret = -EINVAL;
1536 goto state_err;
1537 }
1538
5c3eb9f7 1539 ret = _sdw_enable_stream(stream);
5c3eb9f7 1540
59528807 1541state_err:
48949722 1542 sdw_release_bus_lock(stream);
5c3eb9f7
SK
1543 return ret;
1544}
1545EXPORT_SYMBOL(sdw_enable_stream);
1546
1547static int _sdw_disable_stream(struct sdw_stream_runtime *stream)
1548{
3a0be1a6 1549 struct sdw_master_runtime *m_rt;
5c3eb9f7
SK
1550 int ret;
1551
48949722 1552 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
3a0be1a6
PLB
1553 struct sdw_bus *bus = m_rt->bus;
1554
48949722
VK
1555 /* Disable port(s) */
1556 ret = sdw_enable_disable_ports(m_rt, false);
1557 if (ret < 0) {
17ed5bef 1558 dev_err(bus->dev, "Disable port(s) failed: %d\n", ret);
48949722
VK
1559 return ret;
1560 }
5c3eb9f7 1561 }
5c3eb9f7
SK
1562 stream->state = SDW_STREAM_DISABLED;
1563
48949722 1564 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
3a0be1a6
PLB
1565 struct sdw_bus *bus = m_rt->bus;
1566
48949722 1567 /* Program params */
bfaa3549 1568 ret = sdw_program_params(bus, false);
48949722 1569 if (ret < 0) {
68d9bfb6 1570 dev_err(bus->dev, "%s: Program params failed: %d\n", __func__, ret);
48949722
VK
1571 return ret;
1572 }
5c3eb9f7
SK
1573 }
1574
e0279b6b
PLB
1575 ret = do_bank_switch(stream);
1576 if (ret < 0) {
68d9bfb6 1577 pr_err("%s: do_bank_switch failed: %d\n", __func__, ret);
e0279b6b
PLB
1578 return ret;
1579 }
1580
1581 /* make sure alternate bank (previous current) is also disabled */
1582 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
3a0be1a6
PLB
1583 struct sdw_bus *bus = m_rt->bus;
1584
e0279b6b
PLB
1585 /* Disable port(s) */
1586 ret = sdw_enable_disable_ports(m_rt, false);
1587 if (ret < 0) {
1588 dev_err(bus->dev, "Disable port(s) failed: %d\n", ret);
1589 return ret;
1590 }
1591 }
1592
1593 return 0;
5c3eb9f7
SK
1594}
1595
1596/**
1597 * sdw_disable_stream() - Disable SoundWire stream
1598 *
1599 * @stream: Soundwire stream
1600 *
34962fb8 1601 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
5c3eb9f7
SK
1602 */
1603int sdw_disable_stream(struct sdw_stream_runtime *stream)
1604{
3a0be1a6 1605 int ret;
5c3eb9f7
SK
1606
1607 if (!stream) {
17ed5bef 1608 pr_err("SoundWire: Handle not found for stream\n");
5c3eb9f7
SK
1609 return -EINVAL;
1610 }
1611
48949722 1612 sdw_acquire_bus_lock(stream);
5c3eb9f7 1613
63fadaa2
PLB
1614 if (stream->state == SDW_STREAM_DISABLED) {
1615 ret = 0;
1616 goto state_err;
1617 }
1618
59528807
PLB
1619 if (stream->state != SDW_STREAM_ENABLED) {
1620 pr_err("%s: %s: inconsistent state state %d\n",
1621 __func__, stream->name, stream->state);
1622 ret = -EINVAL;
1623 goto state_err;
1624 }
1625
5c3eb9f7 1626 ret = _sdw_disable_stream(stream);
5c3eb9f7 1627
59528807 1628state_err:
48949722 1629 sdw_release_bus_lock(stream);
5c3eb9f7
SK
1630 return ret;
1631}
1632EXPORT_SYMBOL(sdw_disable_stream);
1633
1634static int _sdw_deprepare_stream(struct sdw_stream_runtime *stream)
1635{
3a0be1a6
PLB
1636 struct sdw_master_runtime *m_rt;
1637 struct sdw_bus *bus;
5c3eb9f7
SK
1638 int ret = 0;
1639
48949722
VK
1640 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1641 bus = m_rt->bus;
1642 /* De-prepare port(s) */
1643 ret = sdw_prep_deprep_ports(m_rt, false);
1644 if (ret < 0) {
62f0cec3
VK
1645 dev_err(bus->dev,
1646 "De-prepare port(s) failed: %d\n", ret);
48949722
VK
1647 return ret;
1648 }
5c3eb9f7 1649
48949722
VK
1650 /* TODO: Update this during Device-Device support */
1651 bus->params.bandwidth -= m_rt->stream->params.rate *
1652 m_rt->ch_count * m_rt->stream->params.bps;
5c3eb9f7 1653
9026118f
BL
1654 /* Compute params */
1655 if (bus->compute_params) {
1656 ret = bus->compute_params(bus);
1657 if (ret < 0) {
6122d3be 1658 dev_err(bus->dev, "Compute params failed: %d\n",
9026118f
BL
1659 ret);
1660 return ret;
1661 }
1662 }
1663
48949722 1664 /* Program params */
bfaa3549 1665 ret = sdw_program_params(bus, false);
48949722 1666 if (ret < 0) {
68d9bfb6 1667 dev_err(bus->dev, "%s: Program params failed: %d\n", __func__, ret);
48949722
VK
1668 return ret;
1669 }
5c3eb9f7
SK
1670 }
1671
48949722 1672 stream->state = SDW_STREAM_DEPREPARED;
5c3eb9f7
SK
1673 return do_bank_switch(stream);
1674}
1675
1676/**
1677 * sdw_deprepare_stream() - Deprepare SoundWire stream
1678 *
1679 * @stream: Soundwire stream
1680 *
34962fb8 1681 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
5c3eb9f7
SK
1682 */
1683int sdw_deprepare_stream(struct sdw_stream_runtime *stream)
1684{
3a0be1a6 1685 int ret;
5c3eb9f7
SK
1686
1687 if (!stream) {
17ed5bef 1688 pr_err("SoundWire: Handle not found for stream\n");
5c3eb9f7
SK
1689 return -EINVAL;
1690 }
1691
48949722 1692 sdw_acquire_bus_lock(stream);
59528807 1693
63fadaa2
PLB
1694 if (stream->state == SDW_STREAM_DEPREPARED) {
1695 ret = 0;
1696 goto state_err;
1697 }
1698
59528807
PLB
1699 if (stream->state != SDW_STREAM_PREPARED &&
1700 stream->state != SDW_STREAM_DISABLED) {
1701 pr_err("%s: %s: inconsistent state state %d\n",
1702 __func__, stream->name, stream->state);
1703 ret = -EINVAL;
1704 goto state_err;
1705 }
1706
5c3eb9f7 1707 ret = _sdw_deprepare_stream(stream);
5c3eb9f7 1708
59528807 1709state_err:
48949722 1710 sdw_release_bus_lock(stream);
5c3eb9f7
SK
1711 return ret;
1712}
1713EXPORT_SYMBOL(sdw_deprepare_stream);
4550569b
PLB
1714
1715static int set_stream(struct snd_pcm_substream *substream,
1716 struct sdw_stream_runtime *sdw_stream)
1717{
1718 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1719 struct snd_soc_dai *dai;
1720 int ret = 0;
1721 int i;
1722
1723 /* Set stream pointer on all DAIs */
1724 for_each_rtd_dais(rtd, i, dai) {
e8444560 1725 ret = snd_soc_dai_set_stream(dai, sdw_stream, substream->stream);
4550569b 1726 if (ret < 0) {
6122d3be 1727 dev_err(rtd->dev, "failed to set stream pointer on dai %s\n", dai->name);
4550569b
PLB
1728 break;
1729 }
1730 }
1731
1732 return ret;
1733}
1734
7a908906
PLB
1735/**
1736 * sdw_alloc_stream() - Allocate and return stream runtime
1737 *
1738 * @stream_name: SoundWire stream name
1739 *
1740 * Allocates a SoundWire stream runtime instance.
1741 * sdw_alloc_stream should be called only once per stream. Typically
1742 * invoked from ALSA/ASoC machine/platform driver.
1743 */
1744struct sdw_stream_runtime *sdw_alloc_stream(const char *stream_name)
1745{
1746 struct sdw_stream_runtime *stream;
1747
1748 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
1749 if (!stream)
1750 return NULL;
1751
1752 stream->name = stream_name;
1753 INIT_LIST_HEAD(&stream->master_list);
1754 stream->state = SDW_STREAM_ALLOCATED;
1755 stream->m_rt_count = 0;
1756
1757 return stream;
1758}
1759EXPORT_SYMBOL(sdw_alloc_stream);
1760
4550569b
PLB
1761/**
1762 * sdw_startup_stream() - Startup SoundWire stream
1763 *
3b71c690 1764 * @sdw_substream: Soundwire stream
4550569b
PLB
1765 *
1766 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
1767 */
1768int sdw_startup_stream(void *sdw_substream)
1769{
1770 struct snd_pcm_substream *substream = sdw_substream;
1771 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1772 struct sdw_stream_runtime *sdw_stream;
1773 char *name;
1774 int ret;
1775
1776 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1777 name = kasprintf(GFP_KERNEL, "%s-Playback", substream->name);
1778 else
1779 name = kasprintf(GFP_KERNEL, "%s-Capture", substream->name);
1780
1781 if (!name)
1782 return -ENOMEM;
1783
1784 sdw_stream = sdw_alloc_stream(name);
1785 if (!sdw_stream) {
6122d3be 1786 dev_err(rtd->dev, "alloc stream failed for substream DAI %s\n", substream->name);
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1787 ret = -ENOMEM;
1788 goto error;
1789 }
1790
1791 ret = set_stream(substream, sdw_stream);
1792 if (ret < 0)
1793 goto release_stream;
1794 return 0;
1795
1796release_stream:
1797 sdw_release_stream(sdw_stream);
1798 set_stream(substream, NULL);
1799error:
1800 kfree(name);
1801 return ret;
1802}
1803EXPORT_SYMBOL(sdw_startup_stream);
1804
1805/**
1806 * sdw_shutdown_stream() - Shutdown SoundWire stream
1807 *
3b71c690 1808 * @sdw_substream: Soundwire stream
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1809 *
1810 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
1811 */
1812void sdw_shutdown_stream(void *sdw_substream)
1813{
1814 struct snd_pcm_substream *substream = sdw_substream;
1815 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1816 struct sdw_stream_runtime *sdw_stream;
1817 struct snd_soc_dai *dai;
1818
1819 /* Find stream from first CPU DAI */
1820 dai = asoc_rtd_to_cpu(rtd, 0);
1821
e8444560 1822 sdw_stream = snd_soc_dai_get_stream(dai, substream->stream);
4550569b 1823
3471d2a1 1824 if (IS_ERR(sdw_stream)) {
6122d3be 1825 dev_err(rtd->dev, "no stream found for DAI %s\n", dai->name);
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1826 return;
1827 }
1828
1829 /* release memory */
1830 kfree(sdw_stream->name);
1831 sdw_release_stream(sdw_stream);
1832
1833 /* clear DAI data */
1834 set_stream(substream, NULL);
1835}
1836EXPORT_SYMBOL(sdw_shutdown_stream);
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1837
1838/**
1839 * sdw_release_stream() - Free the assigned stream runtime
1840 *
1841 * @stream: SoundWire stream runtime
1842 *
1843 * sdw_release_stream should be called only once per stream
1844 */
1845void sdw_release_stream(struct sdw_stream_runtime *stream)
1846{
1847 kfree(stream);
1848}
1849EXPORT_SYMBOL(sdw_release_stream);
1850
1851/**
1852 * sdw_stream_add_master() - Allocate and add master runtime to a stream
1853 *
1854 * @bus: SDW Bus instance
1855 * @stream_config: Stream configuration for audio stream
1856 * @port_config: Port configuration for audio stream
1857 * @num_ports: Number of ports
1858 * @stream: SoundWire stream
1859 */
1860int sdw_stream_add_master(struct sdw_bus *bus,
1861 struct sdw_stream_config *stream_config,
1862 struct sdw_port_config *port_config,
1863 unsigned int num_ports,
1864 struct sdw_stream_runtime *stream)
1865{
1866 struct sdw_master_runtime *m_rt;
ac3bc88c 1867 bool alloc_master_rt = true;
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1868 int ret;
1869
1870 mutex_lock(&bus->bus_lock);
1871
1872 /*
1873 * For multi link streams, add the second master only if
1874 * the bus supports it.
1875 * Check if bus->multi_link is set
1876 */
1877 if (!bus->multi_link && stream->m_rt_count > 0) {
1878 dev_err(bus->dev,
1879 "Multilink not supported, link %d\n", bus->link_id);
1880 ret = -EINVAL;
1881 goto unlock;
1882 }
1883
1884 /*
1885 * check if Master is already allocated (e.g. as a result of Slave adding
1886 * it first), if so skip allocation and go to configuration
1887 */
1888 m_rt = sdw_master_rt_find(bus, stream);
ac3bc88c
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1889 if (m_rt) {
1890 alloc_master_rt = false;
7a908906 1891 goto skip_alloc_master_rt;
ac3bc88c 1892 }
7a908906
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1893
1894 m_rt = sdw_master_rt_alloc(bus, stream);
1895 if (!m_rt) {
68d9bfb6
PLB
1896 dev_err(bus->dev, "%s: Master runtime alloc failed for stream:%s\n",
1897 __func__, stream->name);
7a908906
PLB
1898 ret = -ENOMEM;
1899 goto unlock;
1900 }
ac3bc88c
PLB
1901skip_alloc_master_rt:
1902
f3016b89
PLB
1903 if (sdw_master_port_allocated(m_rt))
1904 goto skip_alloc_master_port;
1905
ac3bc88c
PLB
1906 ret = sdw_master_port_alloc(m_rt, num_ports);
1907 if (ret)
1908 goto alloc_error;
1909
1910 stream->m_rt_count++;
7a908906 1911
f3016b89
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1912skip_alloc_master_port:
1913
7a908906
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1914 ret = sdw_master_rt_config(m_rt, stream_config);
1915 if (ret < 0)
1916 goto unlock;
1917
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1918 ret = sdw_config_stream(bus->dev, stream, stream_config, false);
1919 if (ret)
ac3bc88c 1920 goto unlock;
7a908906
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1921
1922 ret = sdw_master_port_config(m_rt, port_config);
7a908906
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1923
1924 goto unlock;
1925
ac3bc88c
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1926alloc_error:
1927 /*
1928 * we only cleanup what was allocated in this routine
1929 */
1930 if (alloc_master_rt)
1931 sdw_master_rt_free(m_rt, stream);
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1932unlock:
1933 mutex_unlock(&bus->bus_lock);
1934 return ret;
1935}
1936EXPORT_SYMBOL(sdw_stream_add_master);
1937
1938/**
1939 * sdw_stream_remove_master() - Remove master from sdw_stream
1940 *
1941 * @bus: SDW Bus instance
1942 * @stream: SoundWire stream
1943 *
1944 * This removes and frees port_rt and master_rt from a stream
1945 */
1946int sdw_stream_remove_master(struct sdw_bus *bus,
1947 struct sdw_stream_runtime *stream)
1948{
1949 struct sdw_master_runtime *m_rt, *_m_rt;
1950
1951 mutex_lock(&bus->bus_lock);
1952
1953 list_for_each_entry_safe(m_rt, _m_rt,
1954 &stream->master_list, stream_node) {
1955 if (m_rt->bus != bus)
1956 continue;
1957
1958 sdw_master_port_free(m_rt);
00ce0d2a 1959 sdw_master_rt_free(m_rt, stream);
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1960 stream->m_rt_count--;
1961 }
1962
1963 if (list_empty(&stream->master_list))
1964 stream->state = SDW_STREAM_RELEASED;
1965
1966 mutex_unlock(&bus->bus_lock);
1967
1968 return 0;
1969}
1970EXPORT_SYMBOL(sdw_stream_remove_master);
1971
1972/**
1973 * sdw_stream_add_slave() - Allocate and add master/slave runtime to a stream
1974 *
1975 * @slave: SDW Slave instance
1976 * @stream_config: Stream configuration for audio stream
1977 * @stream: SoundWire stream
1978 * @port_config: Port configuration for audio stream
1979 * @num_ports: Number of ports
1980 *
1981 * It is expected that Slave is added before adding Master
1982 * to the Stream.
1983 *
1984 */
1985int sdw_stream_add_slave(struct sdw_slave *slave,
1986 struct sdw_stream_config *stream_config,
1987 struct sdw_port_config *port_config,
1988 unsigned int num_ports,
1989 struct sdw_stream_runtime *stream)
1990{
1991 struct sdw_slave_runtime *s_rt;
1992 struct sdw_master_runtime *m_rt;
ac3bc88c
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1993 bool alloc_master_rt = true;
1994 bool alloc_slave_rt = true;
1995
7a908906
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1996 int ret;
1997
1998 mutex_lock(&slave->bus->bus_lock);
1999
2000 /*
2001 * check if Master is already allocated, if so skip allocation
2002 * and go to configuration
2003 */
2004 m_rt = sdw_master_rt_find(slave->bus, stream);
ac3bc88c
PLB
2005 if (m_rt) {
2006 alloc_master_rt = false;
7a908906 2007 goto skip_alloc_master_rt;
ac3bc88c 2008 }
7a908906
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2009
2010 /*
2011 * If this API is invoked by Slave first then m_rt is not valid.
2012 * So, allocate m_rt and add Slave to it.
2013 */
2014 m_rt = sdw_master_rt_alloc(slave->bus, stream);
2015 if (!m_rt) {
68d9bfb6
PLB
2016 dev_err(&slave->dev, "%s: Master runtime alloc failed for stream:%s\n",
2017 __func__, stream->name);
7a908906 2018 ret = -ENOMEM;
ac3bc88c 2019 goto unlock;
7a908906 2020 }
7a908906
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2021
2022skip_alloc_master_rt:
f3016b89
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2023 s_rt = sdw_slave_rt_find(slave, stream);
2024 if (s_rt)
2025 goto skip_alloc_slave_rt;
2026
42aad41e 2027 s_rt = sdw_slave_rt_alloc(slave, m_rt);
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2028 if (!s_rt) {
2029 dev_err(&slave->dev, "Slave runtime alloc failed for stream:%s\n", stream->name);
ac3bc88c 2030 alloc_slave_rt = false;
7a908906 2031 ret = -ENOMEM;
ac3bc88c 2032 goto alloc_error;
7a908906 2033 }
7a908906 2034
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2035skip_alloc_slave_rt:
2036 if (sdw_slave_port_allocated(s_rt))
2037 goto skip_port_alloc;
2038
ac3bc88c 2039 ret = sdw_slave_port_alloc(slave, s_rt, num_ports);
7a908906 2040 if (ret)
ac3bc88c 2041 goto alloc_error;
7a908906 2042
f3016b89 2043skip_port_alloc:
ac3bc88c 2044 ret = sdw_master_rt_config(m_rt, stream_config);
7a908906 2045 if (ret)
ac3bc88c 2046 goto unlock;
7a908906 2047
ac3bc88c 2048 ret = sdw_slave_rt_config(s_rt, stream_config);
7a908906 2049 if (ret)
ac3bc88c
PLB
2050 goto unlock;
2051
2052 ret = sdw_config_stream(&slave->dev, stream, stream_config, true);
2053 if (ret)
2054 goto unlock;
7a908906
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2055
2056 ret = sdw_slave_port_config(slave, s_rt, port_config);
2057 if (ret)
ac3bc88c 2058 goto unlock;
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2059
2060 /*
2061 * Change stream state to CONFIGURED on first Slave add.
2062 * Bus is not aware of number of Slave(s) in a stream at this
2063 * point so cannot depend on all Slave(s) to be added in order to
2064 * change stream state to CONFIGURED.
2065 */
2066 stream->state = SDW_STREAM_CONFIGURED;
ac3bc88c 2067 goto unlock;
7a908906 2068
ac3bc88c 2069alloc_error:
7a908906 2070 /*
ac3bc88c
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2071 * we only cleanup what was allocated in this routine. The 'else if'
2072 * is intentional, the 'master_rt_free' will call sdw_slave_rt_free()
2073 * internally.
7a908906 2074 */
ac3bc88c
PLB
2075 if (alloc_master_rt)
2076 sdw_master_rt_free(m_rt, stream);
2077 else if (alloc_slave_rt)
2078 sdw_slave_rt_free(slave, stream);
2079unlock:
7a908906
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2080 mutex_unlock(&slave->bus->bus_lock);
2081 return ret;
2082}
2083EXPORT_SYMBOL(sdw_stream_add_slave);
2084
2085/**
2086 * sdw_stream_remove_slave() - Remove slave from sdw_stream
2087 *
2088 * @slave: SDW Slave instance
2089 * @stream: SoundWire stream
2090 *
2091 * This removes and frees port_rt and slave_rt from a stream
2092 */
2093int sdw_stream_remove_slave(struct sdw_slave *slave,
2094 struct sdw_stream_runtime *stream)
2095{
2096 mutex_lock(&slave->bus->bus_lock);
2097
2098 sdw_slave_port_free(slave, stream);
00ce0d2a 2099 sdw_slave_rt_free(slave, stream);
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2100
2101 mutex_unlock(&slave->bus->bus_lock);
2102
2103 return 0;
2104}
2105EXPORT_SYMBOL(sdw_stream_remove_slave);