powerpc/mm: Drop the unnecessary region check
[linux-2.6-block.git] / drivers / soundwire / stream.c
CommitLineData
89e59053
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1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2// Copyright(c) 2015-18 Intel Corporation.
3
4/*
5 * stream.c - SoundWire Bus stream operations.
6 */
7
8#include <linux/delay.h>
9#include <linux/device.h>
10#include <linux/init.h>
11#include <linux/module.h>
12#include <linux/mod_devicetable.h>
13#include <linux/slab.h>
f8101c74 14#include <linux/soundwire/sdw_registers.h>
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15#include <linux/soundwire/sdw.h>
16#include "bus.h"
17
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18/*
19 * Array of supported rows and columns as per MIPI SoundWire Specification 1.1
20 *
21 * The rows are arranged as per the array index value programmed
22 * in register. The index 15 has dummy value 0 in order to fill hole.
23 */
24int rows[SDW_FRAME_ROWS] = {48, 50, 60, 64, 75, 80, 125, 147,
25 96, 100, 120, 128, 150, 160, 250, 0,
26 192, 200, 240, 256, 72, 144, 90, 180};
27
28int cols[SDW_FRAME_COLS] = {2, 4, 6, 8, 10, 12, 14, 16};
29
30static int sdw_find_col_index(int col)
31{
32 int i;
33
34 for (i = 0; i < SDW_FRAME_COLS; i++) {
35 if (cols[i] == col)
36 return i;
37 }
38
39 pr_warn("Requested column not found, selecting lowest column no: 2\n");
40 return 0;
41}
42
43static int sdw_find_row_index(int row)
44{
45 int i;
46
47 for (i = 0; i < SDW_FRAME_ROWS; i++) {
48 if (rows[i] == row)
49 return i;
50 }
51
52 pr_warn("Requested row not found, selecting lowest row no: 48\n");
53 return 0;
54}
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55static int _sdw_program_slave_port_params(struct sdw_bus *bus,
56 struct sdw_slave *slave,
57 struct sdw_transport_params *t_params,
58 enum sdw_dpn_type type)
59{
60 u32 addr1, addr2, addr3, addr4;
61 int ret;
62 u16 wbuf;
63
64 if (bus->params.next_bank) {
65 addr1 = SDW_DPN_OFFSETCTRL2_B1(t_params->port_num);
66 addr2 = SDW_DPN_BLOCKCTRL3_B1(t_params->port_num);
67 addr3 = SDW_DPN_SAMPLECTRL2_B1(t_params->port_num);
68 addr4 = SDW_DPN_HCTRL_B1(t_params->port_num);
69 } else {
70 addr1 = SDW_DPN_OFFSETCTRL2_B0(t_params->port_num);
71 addr2 = SDW_DPN_BLOCKCTRL3_B0(t_params->port_num);
72 addr3 = SDW_DPN_SAMPLECTRL2_B0(t_params->port_num);
73 addr4 = SDW_DPN_HCTRL_B0(t_params->port_num);
74 }
75
76 /* Program DPN_OffsetCtrl2 registers */
77 ret = sdw_write(slave, addr1, t_params->offset2);
78 if (ret < 0) {
79 dev_err(bus->dev, "DPN_OffsetCtrl2 register write failed");
80 return ret;
81 }
82
83 /* Program DPN_BlockCtrl3 register */
84 ret = sdw_write(slave, addr2, t_params->blk_pkg_mode);
85 if (ret < 0) {
86 dev_err(bus->dev, "DPN_BlockCtrl3 register write failed");
87 return ret;
88 }
89
90 /*
91 * Data ports are FULL, SIMPLE and REDUCED. This function handles
92 * FULL and REDUCED only and and beyond this point only FULL is
93 * handled, so bail out if we are not FULL data port type
94 */
95 if (type != SDW_DPN_FULL)
96 return ret;
97
98 /* Program DPN_SampleCtrl2 register */
99 wbuf = (t_params->sample_interval - 1);
100 wbuf &= SDW_DPN_SAMPLECTRL_HIGH;
101 wbuf >>= SDW_REG_SHIFT(SDW_DPN_SAMPLECTRL_HIGH);
102
103 ret = sdw_write(slave, addr3, wbuf);
104 if (ret < 0) {
105 dev_err(bus->dev, "DPN_SampleCtrl2 register write failed");
106 return ret;
107 }
108
109 /* Program DPN_HCtrl register */
110 wbuf = t_params->hstart;
111 wbuf <<= SDW_REG_SHIFT(SDW_DPN_HCTRL_HSTART);
112 wbuf |= t_params->hstop;
113
114 ret = sdw_write(slave, addr4, wbuf);
115 if (ret < 0)
116 dev_err(bus->dev, "DPN_HCtrl register write failed");
117
118 return ret;
119}
120
121static int sdw_program_slave_port_params(struct sdw_bus *bus,
122 struct sdw_slave_runtime *s_rt,
123 struct sdw_port_runtime *p_rt)
124{
125 struct sdw_transport_params *t_params = &p_rt->transport_params;
126 struct sdw_port_params *p_params = &p_rt->port_params;
127 struct sdw_slave_prop *slave_prop = &s_rt->slave->prop;
128 u32 addr1, addr2, addr3, addr4, addr5, addr6;
129 struct sdw_dpn_prop *dpn_prop;
130 int ret;
131 u8 wbuf;
132
133 dpn_prop = sdw_get_slave_dpn_prop(s_rt->slave,
134 s_rt->direction,
135 t_params->port_num);
136 if (!dpn_prop)
137 return -EINVAL;
138
139 addr1 = SDW_DPN_PORTCTRL(t_params->port_num);
140 addr2 = SDW_DPN_BLOCKCTRL1(t_params->port_num);
141
142 if (bus->params.next_bank) {
143 addr3 = SDW_DPN_SAMPLECTRL1_B1(t_params->port_num);
144 addr4 = SDW_DPN_OFFSETCTRL1_B1(t_params->port_num);
145 addr5 = SDW_DPN_BLOCKCTRL2_B1(t_params->port_num);
146 addr6 = SDW_DPN_LANECTRL_B1(t_params->port_num);
147
148 } else {
149 addr3 = SDW_DPN_SAMPLECTRL1_B0(t_params->port_num);
150 addr4 = SDW_DPN_OFFSETCTRL1_B0(t_params->port_num);
151 addr5 = SDW_DPN_BLOCKCTRL2_B0(t_params->port_num);
152 addr6 = SDW_DPN_LANECTRL_B0(t_params->port_num);
153 }
154
155 /* Program DPN_PortCtrl register */
156 wbuf = p_params->data_mode << SDW_REG_SHIFT(SDW_DPN_PORTCTRL_DATAMODE);
157 wbuf |= p_params->flow_mode;
158
159 ret = sdw_update(s_rt->slave, addr1, 0xF, wbuf);
160 if (ret < 0) {
161 dev_err(&s_rt->slave->dev,
162 "DPN_PortCtrl register write failed for port %d",
163 t_params->port_num);
164 return ret;
165 }
166
167 /* Program DPN_BlockCtrl1 register */
168 ret = sdw_write(s_rt->slave, addr2, (p_params->bps - 1));
169 if (ret < 0) {
170 dev_err(&s_rt->slave->dev,
171 "DPN_BlockCtrl1 register write failed for port %d",
172 t_params->port_num);
173 return ret;
174 }
175
176 /* Program DPN_SampleCtrl1 register */
177 wbuf = (t_params->sample_interval - 1) & SDW_DPN_SAMPLECTRL_LOW;
178 ret = sdw_write(s_rt->slave, addr3, wbuf);
179 if (ret < 0) {
180 dev_err(&s_rt->slave->dev,
181 "DPN_SampleCtrl1 register write failed for port %d",
182 t_params->port_num);
183 return ret;
184 }
185
186 /* Program DPN_OffsetCtrl1 registers */
187 ret = sdw_write(s_rt->slave, addr4, t_params->offset1);
188 if (ret < 0) {
189 dev_err(&s_rt->slave->dev,
190 "DPN_OffsetCtrl1 register write failed for port %d",
191 t_params->port_num);
192 return ret;
193 }
194
195 /* Program DPN_BlockCtrl2 register*/
196 if (t_params->blk_grp_ctrl_valid) {
197 ret = sdw_write(s_rt->slave, addr5, t_params->blk_grp_ctrl);
198 if (ret < 0) {
199 dev_err(&s_rt->slave->dev,
200 "DPN_BlockCtrl2 reg write failed for port %d",
201 t_params->port_num);
202 return ret;
203 }
204 }
205
206 /* program DPN_LaneCtrl register */
207 if (slave_prop->lane_control_support) {
208 ret = sdw_write(s_rt->slave, addr6, t_params->lane_ctrl);
209 if (ret < 0) {
210 dev_err(&s_rt->slave->dev,
211 "DPN_LaneCtrl register write failed for port %d",
212 t_params->port_num);
213 return ret;
214 }
215 }
216
217 if (dpn_prop->type != SDW_DPN_SIMPLE) {
218 ret = _sdw_program_slave_port_params(bus, s_rt->slave,
219 t_params, dpn_prop->type);
220 if (ret < 0)
221 dev_err(&s_rt->slave->dev,
222 "Transport reg write failed for port: %d",
223 t_params->port_num);
224 }
225
226 return ret;
227}
228
229static int sdw_program_master_port_params(struct sdw_bus *bus,
230 struct sdw_port_runtime *p_rt)
231{
232 int ret;
233
234 /*
235 * we need to set transport and port parameters for the port.
236 * Transport parameters refers to the smaple interval, offsets and
237 * hstart/stop etc of the data. Port parameters refers to word
238 * length, flow mode etc of the port
239 */
240 ret = bus->port_ops->dpn_set_port_transport_params(bus,
241 &p_rt->transport_params,
242 bus->params.next_bank);
243 if (ret < 0)
244 return ret;
245
246 return bus->port_ops->dpn_set_port_params(bus,
247 &p_rt->port_params,
248 bus->params.next_bank);
249}
250
251/**
252 * sdw_program_port_params() - Programs transport parameters of Master(s)
253 * and Slave(s)
254 *
255 * @m_rt: Master stream runtime
256 */
257static int sdw_program_port_params(struct sdw_master_runtime *m_rt)
258{
259 struct sdw_slave_runtime *s_rt = NULL;
260 struct sdw_bus *bus = m_rt->bus;
261 struct sdw_port_runtime *p_rt;
262 int ret = 0;
263
264 /* Program transport & port parameters for Slave(s) */
265 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
266 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
267 ret = sdw_program_slave_port_params(bus, s_rt, p_rt);
268 if (ret < 0)
269 return ret;
270 }
271 }
272
273 /* Program transport & port parameters for Master(s) */
274 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
275 ret = sdw_program_master_port_params(bus, p_rt);
276 if (ret < 0)
277 return ret;
278 }
279
280 return 0;
281}
282
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283/**
284 * sdw_enable_disable_slave_ports: Enable/disable slave data port
285 *
286 * @bus: bus instance
287 * @s_rt: slave runtime
288 * @p_rt: port runtime
289 * @en: enable or disable operation
290 *
291 * This function only sets the enable/disable bits in the relevant bank, the
292 * actual enable/disable is done with a bank switch
293 */
294static int sdw_enable_disable_slave_ports(struct sdw_bus *bus,
295 struct sdw_slave_runtime *s_rt,
296 struct sdw_port_runtime *p_rt, bool en)
297{
298 struct sdw_transport_params *t_params = &p_rt->transport_params;
299 u32 addr;
300 int ret;
301
302 if (bus->params.next_bank)
303 addr = SDW_DPN_CHANNELEN_B1(p_rt->num);
304 else
305 addr = SDW_DPN_CHANNELEN_B0(p_rt->num);
306
307 /*
308 * Since bus doesn't support sharing a port across two streams,
309 * it is safe to reset this register
310 */
311 if (en)
312 ret = sdw_update(s_rt->slave, addr, 0xFF, p_rt->ch_mask);
313 else
314 ret = sdw_update(s_rt->slave, addr, 0xFF, 0x0);
315
316 if (ret < 0)
317 dev_err(&s_rt->slave->dev,
318 "Slave chn_en reg write failed:%d port:%d",
319 ret, t_params->port_num);
320
321 return ret;
322}
323
324static int sdw_enable_disable_master_ports(struct sdw_master_runtime *m_rt,
325 struct sdw_port_runtime *p_rt, bool en)
326{
327 struct sdw_transport_params *t_params = &p_rt->transport_params;
328 struct sdw_bus *bus = m_rt->bus;
329 struct sdw_enable_ch enable_ch;
330 int ret = 0;
331
332 enable_ch.port_num = p_rt->num;
333 enable_ch.ch_mask = p_rt->ch_mask;
334 enable_ch.enable = en;
335
336 /* Perform Master port channel(s) enable/disable */
337 if (bus->port_ops->dpn_port_enable_ch) {
338 ret = bus->port_ops->dpn_port_enable_ch(bus,
339 &enable_ch, bus->params.next_bank);
340 if (ret < 0) {
341 dev_err(bus->dev,
342 "Master chn_en write failed:%d port:%d",
343 ret, t_params->port_num);
344 return ret;
345 }
346 } else {
347 dev_err(bus->dev,
348 "dpn_port_enable_ch not supported, %s failed\n",
349 en ? "enable" : "disable");
350 return -EINVAL;
351 }
352
353 return 0;
354}
355
356/**
357 * sdw_enable_disable_ports() - Enable/disable port(s) for Master and
358 * Slave(s)
359 *
360 * @m_rt: Master stream runtime
361 * @en: mode (enable/disable)
362 */
363static int sdw_enable_disable_ports(struct sdw_master_runtime *m_rt, bool en)
364{
365 struct sdw_port_runtime *s_port, *m_port;
366 struct sdw_slave_runtime *s_rt = NULL;
367 int ret = 0;
368
369 /* Enable/Disable Slave port(s) */
370 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
371 list_for_each_entry(s_port, &s_rt->port_list, port_node) {
372 ret = sdw_enable_disable_slave_ports(m_rt->bus, s_rt,
373 s_port, en);
374 if (ret < 0)
375 return ret;
376 }
377 }
378
379 /* Enable/Disable Master port(s) */
380 list_for_each_entry(m_port, &m_rt->port_list, port_node) {
381 ret = sdw_enable_disable_master_ports(m_rt, m_port, en);
382 if (ret < 0)
383 return ret;
384 }
385
386 return 0;
387}
388
389static int sdw_do_port_prep(struct sdw_slave_runtime *s_rt,
390 struct sdw_prepare_ch prep_ch, enum sdw_port_prep_ops cmd)
391{
392 const struct sdw_slave_ops *ops = s_rt->slave->ops;
393 int ret;
394
395 if (ops->port_prep) {
396 ret = ops->port_prep(s_rt->slave, &prep_ch, cmd);
397 if (ret < 0) {
398 dev_err(&s_rt->slave->dev,
399 "Slave Port Prep cmd %d failed: %d", cmd, ret);
400 return ret;
401 }
402 }
403
404 return 0;
405}
406
407static int sdw_prep_deprep_slave_ports(struct sdw_bus *bus,
408 struct sdw_slave_runtime *s_rt,
409 struct sdw_port_runtime *p_rt, bool prep)
410{
411 struct completion *port_ready = NULL;
412 struct sdw_dpn_prop *dpn_prop;
413 struct sdw_prepare_ch prep_ch;
414 unsigned int time_left;
415 bool intr = false;
416 int ret = 0, val;
417 u32 addr;
418
419 prep_ch.num = p_rt->num;
420 prep_ch.ch_mask = p_rt->ch_mask;
421
422 dpn_prop = sdw_get_slave_dpn_prop(s_rt->slave,
423 s_rt->direction,
424 prep_ch.num);
425 if (!dpn_prop) {
426 dev_err(bus->dev,
427 "Slave Port:%d properties not found", prep_ch.num);
428 return -EINVAL;
429 }
430
431 prep_ch.prepare = prep;
432
433 prep_ch.bank = bus->params.next_bank;
434
435 if (dpn_prop->device_interrupts || !dpn_prop->simple_ch_prep_sm)
436 intr = true;
437
438 /*
439 * Enable interrupt before Port prepare.
440 * For Port de-prepare, it is assumed that port
441 * was prepared earlier
442 */
443 if (prep && intr) {
444 ret = sdw_configure_dpn_intr(s_rt->slave, p_rt->num, prep,
445 dpn_prop->device_interrupts);
446 if (ret < 0)
447 return ret;
448 }
449
450 /* Inform slave about the impending port prepare */
451 sdw_do_port_prep(s_rt, prep_ch, SDW_OPS_PORT_PRE_PREP);
452
453 /* Prepare Slave port implementing CP_SM */
454 if (!dpn_prop->simple_ch_prep_sm) {
455 addr = SDW_DPN_PREPARECTRL(p_rt->num);
456
457 if (prep)
458 ret = sdw_update(s_rt->slave, addr,
459 0xFF, p_rt->ch_mask);
460 else
461 ret = sdw_update(s_rt->slave, addr, 0xFF, 0x0);
462
463 if (ret < 0) {
464 dev_err(&s_rt->slave->dev,
465 "Slave prep_ctrl reg write failed");
466 return ret;
467 }
468
469 /* Wait for completion on port ready */
470 port_ready = &s_rt->slave->port_ready[prep_ch.num];
471 time_left = wait_for_completion_timeout(port_ready,
472 msecs_to_jiffies(dpn_prop->ch_prep_timeout));
473
474 val = sdw_read(s_rt->slave, SDW_DPN_PREPARESTATUS(p_rt->num));
475 val &= p_rt->ch_mask;
476 if (!time_left || val) {
477 dev_err(&s_rt->slave->dev,
478 "Chn prep failed for port:%d", prep_ch.num);
479 return -ETIMEDOUT;
480 }
481 }
482
483 /* Inform slaves about ports prepared */
484 sdw_do_port_prep(s_rt, prep_ch, SDW_OPS_PORT_POST_PREP);
485
486 /* Disable interrupt after Port de-prepare */
487 if (!prep && intr)
488 ret = sdw_configure_dpn_intr(s_rt->slave, p_rt->num, prep,
489 dpn_prop->device_interrupts);
490
491 return ret;
492}
493
494static int sdw_prep_deprep_master_ports(struct sdw_master_runtime *m_rt,
495 struct sdw_port_runtime *p_rt, bool prep)
496{
497 struct sdw_transport_params *t_params = &p_rt->transport_params;
498 struct sdw_bus *bus = m_rt->bus;
499 const struct sdw_master_port_ops *ops = bus->port_ops;
500 struct sdw_prepare_ch prep_ch;
501 int ret = 0;
502
503 prep_ch.num = p_rt->num;
504 prep_ch.ch_mask = p_rt->ch_mask;
505 prep_ch.prepare = prep; /* Prepare/De-prepare */
506 prep_ch.bank = bus->params.next_bank;
507
508 /* Pre-prepare/Pre-deprepare port(s) */
509 if (ops->dpn_port_prep) {
510 ret = ops->dpn_port_prep(bus, &prep_ch);
511 if (ret < 0) {
512 dev_err(bus->dev, "Port prepare failed for port:%d",
513 t_params->port_num);
514 return ret;
515 }
516 }
517
518 return ret;
519}
520
521/**
522 * sdw_prep_deprep_ports() - Prepare/De-prepare port(s) for Master(s) and
523 * Slave(s)
524 *
525 * @m_rt: Master runtime handle
526 * @prep: Prepare or De-prepare
527 */
528static int sdw_prep_deprep_ports(struct sdw_master_runtime *m_rt, bool prep)
529{
530 struct sdw_slave_runtime *s_rt = NULL;
531 struct sdw_port_runtime *p_rt;
532 int ret = 0;
533
534 /* Prepare/De-prepare Slave port(s) */
535 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
536 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
537 ret = sdw_prep_deprep_slave_ports(m_rt->bus, s_rt,
538 p_rt, prep);
539 if (ret < 0)
540 return ret;
541 }
542 }
543
544 /* Prepare/De-prepare Master port(s) */
545 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
546 ret = sdw_prep_deprep_master_ports(m_rt, p_rt, prep);
547 if (ret < 0)
548 return ret;
549 }
550
551 return ret;
552}
553
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554/**
555 * sdw_notify_config() - Notify bus configuration
556 *
557 * @m_rt: Master runtime handle
558 *
559 * This function notifies the Master(s) and Slave(s) of the
560 * new bus configuration.
561 */
562static int sdw_notify_config(struct sdw_master_runtime *m_rt)
563{
564 struct sdw_slave_runtime *s_rt;
565 struct sdw_bus *bus = m_rt->bus;
566 struct sdw_slave *slave;
567 int ret = 0;
568
569 if (bus->ops->set_bus_conf) {
570 ret = bus->ops->set_bus_conf(bus, &bus->params);
571 if (ret < 0)
572 return ret;
573 }
574
575 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
576 slave = s_rt->slave;
577
578 if (slave->ops->bus_config) {
579 ret = slave->ops->bus_config(slave, &bus->params);
580 if (ret < 0)
581 dev_err(bus->dev, "Notify Slave: %d failed",
582 slave->dev_num);
583 return ret;
584 }
585 }
586
587 return ret;
588}
589
590/**
591 * sdw_program_params() - Program transport and port parameters for Master(s)
592 * and Slave(s)
593 *
594 * @bus: SDW bus instance
595 */
596static int sdw_program_params(struct sdw_bus *bus)
597{
598 struct sdw_master_runtime *m_rt = NULL;
599 int ret = 0;
600
601 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
602 ret = sdw_program_port_params(m_rt);
603 if (ret < 0) {
604 dev_err(bus->dev,
605 "Program transport params failed: %d", ret);
606 return ret;
607 }
608
609 ret = sdw_notify_config(m_rt);
610 if (ret < 0) {
611 dev_err(bus->dev, "Notify bus config failed: %d", ret);
612 return ret;
613 }
614
615 /* Enable port(s) on alternate bank for all active streams */
616 if (m_rt->stream->state != SDW_STREAM_ENABLED)
617 continue;
618
619 ret = sdw_enable_disable_ports(m_rt, true);
620 if (ret < 0) {
621 dev_err(bus->dev, "Enable channel failed: %d", ret);
622 return ret;
623 }
624 }
625
626 return ret;
627}
628
ce6e74d0 629static int sdw_bank_switch(struct sdw_bus *bus, int m_rt_count)
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630{
631 int col_index, row_index;
ce6e74d0 632 bool multi_link;
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633 struct sdw_msg *wr_msg;
634 u8 *wbuf = NULL;
635 int ret = 0;
636 u16 addr;
637
638 wr_msg = kzalloc(sizeof(*wr_msg), GFP_KERNEL);
639 if (!wr_msg)
640 return -ENOMEM;
641
ce6e74d0
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642 bus->defer_msg.msg = wr_msg;
643
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644 wbuf = kzalloc(sizeof(*wbuf), GFP_KERNEL);
645 if (!wbuf) {
646 ret = -ENOMEM;
647 goto error_1;
648 }
649
650 /* Get row and column index to program register */
651 col_index = sdw_find_col_index(bus->params.col);
652 row_index = sdw_find_row_index(bus->params.row);
653 wbuf[0] = col_index | (row_index << 3);
654
655 if (bus->params.next_bank)
656 addr = SDW_SCP_FRAMECTRL_B1;
657 else
658 addr = SDW_SCP_FRAMECTRL_B0;
659
660 sdw_fill_msg(wr_msg, NULL, addr, 1, SDW_BROADCAST_DEV_NUM,
661 SDW_MSG_FLAG_WRITE, wbuf);
662 wr_msg->ssp_sync = true;
663
ce6e74d0
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664 /*
665 * Set the multi_link flag only when both the hardware supports
666 * and there is a stream handled by multiple masters
667 */
668 multi_link = bus->multi_link && (m_rt_count > 1);
669
670 if (multi_link)
671 ret = sdw_transfer_defer(bus, wr_msg, &bus->defer_msg);
672 else
673 ret = sdw_transfer(bus, wr_msg);
674
99b8a5d6
SK
675 if (ret < 0) {
676 dev_err(bus->dev, "Slave frame_ctrl reg write failed");
677 goto error;
678 }
679
ce6e74d0
SN
680 if (!multi_link) {
681 kfree(wr_msg);
682 kfree(wbuf);
683 bus->defer_msg.msg = NULL;
684 bus->params.curr_bank = !bus->params.curr_bank;
685 bus->params.next_bank = !bus->params.next_bank;
686 }
99b8a5d6
SK
687
688 return 0;
689
690error:
691 kfree(wbuf);
692error_1:
693 kfree(wr_msg);
694 return ret;
695}
696
ce6e74d0
SN
697/**
698 * sdw_ml_sync_bank_switch: Multilink register bank switch
699 *
700 * @bus: SDW bus instance
701 *
702 * Caller function should free the buffers on error
703 */
704static int sdw_ml_sync_bank_switch(struct sdw_bus *bus)
705{
706 unsigned long time_left;
707
708 if (!bus->multi_link)
709 return 0;
710
711 /* Wait for completion of transfer */
712 time_left = wait_for_completion_timeout(&bus->defer_msg.complete,
713 bus->bank_switch_timeout);
714
715 if (!time_left) {
716 dev_err(bus->dev, "Controller Timed out on bank switch");
717 return -ETIMEDOUT;
718 }
719
720 bus->params.curr_bank = !bus->params.curr_bank;
721 bus->params.next_bank = !bus->params.next_bank;
722
723 if (bus->defer_msg.msg) {
724 kfree(bus->defer_msg.msg->buf);
725 kfree(bus->defer_msg.msg);
726 }
727
728 return 0;
729}
730
99b8a5d6
SK
731static int do_bank_switch(struct sdw_stream_runtime *stream)
732{
48949722 733 struct sdw_master_runtime *m_rt = NULL;
99b8a5d6 734 const struct sdw_master_ops *ops;
48949722 735 struct sdw_bus *bus = NULL;
ce6e74d0 736 bool multi_link = false;
99b8a5d6
SK
737 int ret = 0;
738
48949722
VK
739 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
740 bus = m_rt->bus;
741 ops = bus->ops;
742
ce6e74d0
SN
743 if (bus->multi_link) {
744 multi_link = true;
745 mutex_lock(&bus->msg_lock);
746 }
747
48949722
VK
748 /* Pre-bank switch */
749 if (ops->pre_bank_switch) {
750 ret = ops->pre_bank_switch(bus);
751 if (ret < 0) {
752 dev_err(bus->dev,
753 "Pre bank switch op failed: %d", ret);
ce6e74d0 754 goto msg_unlock;
48949722
VK
755 }
756 }
757
ce6e74d0
SN
758 /*
759 * Perform Bank switch operation.
760 * For multi link cases, the actual bank switch is
761 * synchronized across all Masters and happens later as a
762 * part of post_bank_switch ops.
763 */
764 ret = sdw_bank_switch(bus, stream->m_rt_count);
99b8a5d6 765 if (ret < 0) {
48949722 766 dev_err(bus->dev, "Bank switch failed: %d", ret);
ce6e74d0
SN
767 goto error;
768
99b8a5d6
SK
769 }
770 }
771
ce6e74d0
SN
772 /*
773 * For multi link cases, it is expected that the bank switch is
774 * triggered by the post_bank_switch for the first Master in the list
775 * and for the other Masters the post_bank_switch() should return doing
776 * nothing.
777 */
48949722
VK
778 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
779 bus = m_rt->bus;
780 ops = bus->ops;
99b8a5d6 781
48949722
VK
782 /* Post-bank switch */
783 if (ops->post_bank_switch) {
784 ret = ops->post_bank_switch(bus);
785 if (ret < 0) {
786 dev_err(bus->dev,
99b8a5d6 787 "Post bank switch op failed: %d", ret);
ce6e74d0 788 goto error;
48949722 789 }
ce6e74d0
SN
790 } else if (bus->multi_link && stream->m_rt_count > 1) {
791 dev_err(bus->dev,
792 "Post bank switch ops not implemented");
793 goto error;
794 }
795
796 /* Set the bank switch timeout to default, if not set */
797 if (!bus->bank_switch_timeout)
798 bus->bank_switch_timeout = DEFAULT_BANK_SWITCH_TIMEOUT;
799
800 /* Check if bank switch was successful */
801 ret = sdw_ml_sync_bank_switch(bus);
802 if (ret < 0) {
803 dev_err(bus->dev,
804 "multi link bank switch failed: %d", ret);
805 goto error;
806 }
807
808 mutex_unlock(&bus->msg_lock);
809 }
810
811 return ret;
812
813error:
814 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
815
816 bus = m_rt->bus;
817
818 kfree(bus->defer_msg.msg->buf);
819 kfree(bus->defer_msg.msg);
820 }
821
822msg_unlock:
823
824 if (multi_link) {
825 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
826 bus = m_rt->bus;
827 if (mutex_is_locked(&bus->msg_lock))
828 mutex_unlock(&bus->msg_lock);
99b8a5d6
SK
829 }
830 }
831
832 return ret;
833}
834
89e59053
SK
835/**
836 * sdw_release_stream() - Free the assigned stream runtime
837 *
838 * @stream: SoundWire stream runtime
839 *
840 * sdw_release_stream should be called only once per stream
841 */
842void sdw_release_stream(struct sdw_stream_runtime *stream)
843{
844 kfree(stream);
845}
846EXPORT_SYMBOL(sdw_release_stream);
847
848/**
849 * sdw_alloc_stream() - Allocate and return stream runtime
850 *
851 * @stream_name: SoundWire stream name
852 *
853 * Allocates a SoundWire stream runtime instance.
854 * sdw_alloc_stream should be called only once per stream. Typically
855 * invoked from ALSA/ASoC machine/platform driver.
856 */
857struct sdw_stream_runtime *sdw_alloc_stream(char *stream_name)
858{
859 struct sdw_stream_runtime *stream;
860
861 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
862 if (!stream)
863 return NULL;
864
865 stream->name = stream_name;
0c4a1049 866 INIT_LIST_HEAD(&stream->master_list);
89e59053 867 stream->state = SDW_STREAM_ALLOCATED;
9b5c132a 868 stream->m_rt_count = 0;
89e59053
SK
869
870 return stream;
871}
872EXPORT_SYMBOL(sdw_alloc_stream);
873
48949722
VK
874static struct sdw_master_runtime
875*sdw_find_master_rt(struct sdw_bus *bus,
876 struct sdw_stream_runtime *stream)
877{
878 struct sdw_master_runtime *m_rt = NULL;
879
880 /* Retrieve Bus handle if already available */
881 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
882 if (m_rt->bus == bus)
883 return m_rt;
884 }
885
886 return NULL;
887}
888
89e59053
SK
889/**
890 * sdw_alloc_master_rt() - Allocates and initialize Master runtime handle
891 *
892 * @bus: SDW bus instance
893 * @stream_config: Stream configuration
894 * @stream: Stream runtime handle.
895 *
896 * This function is to be called with bus_lock held.
897 */
898static struct sdw_master_runtime
899*sdw_alloc_master_rt(struct sdw_bus *bus,
900 struct sdw_stream_config *stream_config,
901 struct sdw_stream_runtime *stream)
902{
903 struct sdw_master_runtime *m_rt;
904
89e59053
SK
905 /*
906 * check if Master is already allocated (as a result of Slave adding
907 * it first), if so skip allocation and go to configure
908 */
48949722 909 m_rt = sdw_find_master_rt(bus, stream);
89e59053
SK
910 if (m_rt)
911 goto stream_config;
912
913 m_rt = kzalloc(sizeof(*m_rt), GFP_KERNEL);
914 if (!m_rt)
915 return NULL;
916
917 /* Initialization of Master runtime handle */
bbe7379d 918 INIT_LIST_HEAD(&m_rt->port_list);
89e59053 919 INIT_LIST_HEAD(&m_rt->slave_rt_list);
48949722 920 list_add_tail(&m_rt->stream_node, &stream->master_list);
89e59053
SK
921
922 list_add_tail(&m_rt->bus_node, &bus->m_rt_list);
923
924stream_config:
925 m_rt->ch_count = stream_config->ch_count;
926 m_rt->bus = bus;
927 m_rt->stream = stream;
928 m_rt->direction = stream_config->direction;
929
930 return m_rt;
931}
932
933/**
934 * sdw_alloc_slave_rt() - Allocate and initialize Slave runtime handle.
935 *
936 * @slave: Slave handle
937 * @stream_config: Stream configuration
938 * @stream: Stream runtime handle
939 *
940 * This function is to be called with bus_lock held.
941 */
942static struct sdw_slave_runtime
943*sdw_alloc_slave_rt(struct sdw_slave *slave,
944 struct sdw_stream_config *stream_config,
945 struct sdw_stream_runtime *stream)
946{
947 struct sdw_slave_runtime *s_rt = NULL;
948
949 s_rt = kzalloc(sizeof(*s_rt), GFP_KERNEL);
950 if (!s_rt)
951 return NULL;
952
bbe7379d 953 INIT_LIST_HEAD(&s_rt->port_list);
89e59053
SK
954 s_rt->ch_count = stream_config->ch_count;
955 s_rt->direction = stream_config->direction;
956 s_rt->slave = slave;
957
958 return s_rt;
959}
960
bbe7379d
SK
961static void sdw_master_port_release(struct sdw_bus *bus,
962 struct sdw_master_runtime *m_rt)
963{
964 struct sdw_port_runtime *p_rt, *_p_rt;
965
966 list_for_each_entry_safe(p_rt, _p_rt,
967 &m_rt->port_list, port_node) {
968 list_del(&p_rt->port_node);
969 kfree(p_rt);
970 }
971}
972
973static void sdw_slave_port_release(struct sdw_bus *bus,
974 struct sdw_slave *slave,
975 struct sdw_stream_runtime *stream)
976{
977 struct sdw_port_runtime *p_rt, *_p_rt;
48949722 978 struct sdw_master_runtime *m_rt;
bbe7379d
SK
979 struct sdw_slave_runtime *s_rt;
980
48949722
VK
981 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
982 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
bbe7379d 983
48949722
VK
984 if (s_rt->slave != slave)
985 continue;
986
987 list_for_each_entry_safe(p_rt, _p_rt,
988 &s_rt->port_list, port_node) {
989
990 list_del(&p_rt->port_node);
991 kfree(p_rt);
992 }
bbe7379d
SK
993 }
994 }
995}
996
89e59053
SK
997/**
998 * sdw_release_slave_stream() - Free Slave(s) runtime handle
999 *
1000 * @slave: Slave handle.
1001 * @stream: Stream runtime handle.
1002 *
1003 * This function is to be called with bus_lock held.
1004 */
1005static void sdw_release_slave_stream(struct sdw_slave *slave,
1006 struct sdw_stream_runtime *stream)
1007{
1008 struct sdw_slave_runtime *s_rt, *_s_rt;
48949722 1009 struct sdw_master_runtime *m_rt;
89e59053 1010
48949722
VK
1011 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1012 /* Retrieve Slave runtime handle */
1013 list_for_each_entry_safe(s_rt, _s_rt,
1014 &m_rt->slave_rt_list, m_rt_node) {
1015
1016 if (s_rt->slave == slave) {
1017 list_del(&s_rt->m_rt_node);
1018 kfree(s_rt);
1019 return;
1020 }
89e59053
SK
1021 }
1022 }
1023}
1024
1025/**
1026 * sdw_release_master_stream() - Free Master runtime handle
1027 *
48949722 1028 * @m_rt: Master runtime node
89e59053
SK
1029 * @stream: Stream runtime handle.
1030 *
1031 * This function is to be called with bus_lock held
1032 * It frees the Master runtime handle and associated Slave(s) runtime
1033 * handle. If this is called first then sdw_release_slave_stream() will have
1034 * no effect as Slave(s) runtime handle would already be freed up.
1035 */
48949722
VK
1036static void sdw_release_master_stream(struct sdw_master_runtime *m_rt,
1037 struct sdw_stream_runtime *stream)
89e59053 1038{
89e59053
SK
1039 struct sdw_slave_runtime *s_rt, *_s_rt;
1040
8d6ccf5c
SK
1041 list_for_each_entry_safe(s_rt, _s_rt, &m_rt->slave_rt_list, m_rt_node) {
1042 sdw_slave_port_release(s_rt->slave->bus, s_rt->slave, stream);
1043 sdw_release_slave_stream(s_rt->slave, stream);
1044 }
89e59053 1045
48949722 1046 list_del(&m_rt->stream_node);
89e59053 1047 list_del(&m_rt->bus_node);
48949722 1048 kfree(m_rt);
89e59053
SK
1049}
1050
1051/**
1052 * sdw_stream_remove_master() - Remove master from sdw_stream
1053 *
1054 * @bus: SDW Bus instance
1055 * @stream: SoundWire stream
1056 *
bbe7379d 1057 * This removes and frees port_rt and master_rt from a stream
89e59053
SK
1058 */
1059int sdw_stream_remove_master(struct sdw_bus *bus,
1060 struct sdw_stream_runtime *stream)
1061{
48949722
VK
1062 struct sdw_master_runtime *m_rt, *_m_rt;
1063
89e59053
SK
1064 mutex_lock(&bus->bus_lock);
1065
48949722
VK
1066 list_for_each_entry_safe(m_rt, _m_rt,
1067 &stream->master_list, stream_node) {
1068
1069 if (m_rt->bus != bus)
1070 continue;
1071
1072 sdw_master_port_release(bus, m_rt);
1073 sdw_release_master_stream(m_rt, stream);
ce6e74d0 1074 stream->m_rt_count--;
48949722
VK
1075 }
1076
1077 if (list_empty(&stream->master_list))
1078 stream->state = SDW_STREAM_RELEASED;
89e59053
SK
1079
1080 mutex_unlock(&bus->bus_lock);
1081
1082 return 0;
1083}
1084EXPORT_SYMBOL(sdw_stream_remove_master);
1085
1086/**
1087 * sdw_stream_remove_slave() - Remove slave from sdw_stream
1088 *
1089 * @slave: SDW Slave instance
1090 * @stream: SoundWire stream
1091 *
bbe7379d 1092 * This removes and frees port_rt and slave_rt from a stream
89e59053
SK
1093 */
1094int sdw_stream_remove_slave(struct sdw_slave *slave,
1095 struct sdw_stream_runtime *stream)
1096{
1097 mutex_lock(&slave->bus->bus_lock);
1098
bbe7379d 1099 sdw_slave_port_release(slave->bus, slave, stream);
89e59053
SK
1100 sdw_release_slave_stream(slave, stream);
1101
1102 mutex_unlock(&slave->bus->bus_lock);
1103
1104 return 0;
1105}
1106EXPORT_SYMBOL(sdw_stream_remove_slave);
1107
1108/**
1109 * sdw_config_stream() - Configure the allocated stream
1110 *
1111 * @dev: SDW device
1112 * @stream: SoundWire stream
1113 * @stream_config: Stream configuration for audio stream
1114 * @is_slave: is API called from Slave or Master
1115 *
1116 * This function is to be called with bus_lock held.
1117 */
1118static int sdw_config_stream(struct device *dev,
1119 struct sdw_stream_runtime *stream,
1120 struct sdw_stream_config *stream_config, bool is_slave)
1121{
1122 /*
1123 * Update the stream rate, channel and bps based on data
1124 * source. For more than one data source (multilink),
1125 * match the rate, bps, stream type and increment number of channels.
1126 *
1127 * If rate/bps is zero, it means the values are not set, so skip
1128 * comparison and allow the value to be set and stored in stream
1129 */
1130 if (stream->params.rate &&
1131 stream->params.rate != stream_config->frame_rate) {
1132 dev_err(dev, "rate not matching, stream:%s", stream->name);
1133 return -EINVAL;
1134 }
1135
1136 if (stream->params.bps &&
1137 stream->params.bps != stream_config->bps) {
1138 dev_err(dev, "bps not matching, stream:%s", stream->name);
1139 return -EINVAL;
1140 }
1141
1142 stream->type = stream_config->type;
1143 stream->params.rate = stream_config->frame_rate;
1144 stream->params.bps = stream_config->bps;
1145
1146 /* TODO: Update this check during Device-device support */
1147 if (is_slave)
1148 stream->params.ch_count += stream_config->ch_count;
1149
1150 return 0;
1151}
1152
bbe7379d
SK
1153static int sdw_is_valid_port_range(struct device *dev,
1154 struct sdw_port_runtime *p_rt)
1155{
1156 if (!SDW_VALID_PORT_RANGE(p_rt->num)) {
1157 dev_err(dev,
1158 "SoundWire: Invalid port number :%d", p_rt->num);
1159 return -EINVAL;
1160 }
1161
1162 return 0;
1163}
1164
1165static struct sdw_port_runtime *sdw_port_alloc(struct device *dev,
1166 struct sdw_port_config *port_config,
1167 int port_index)
1168{
1169 struct sdw_port_runtime *p_rt;
1170
1171 p_rt = kzalloc(sizeof(*p_rt), GFP_KERNEL);
1172 if (!p_rt)
1173 return NULL;
1174
1175 p_rt->ch_mask = port_config[port_index].ch_mask;
1176 p_rt->num = port_config[port_index].num;
1177
1178 return p_rt;
1179}
1180
1181static int sdw_master_port_config(struct sdw_bus *bus,
1182 struct sdw_master_runtime *m_rt,
1183 struct sdw_port_config *port_config,
1184 unsigned int num_ports)
1185{
1186 struct sdw_port_runtime *p_rt;
1187 int i;
1188
1189 /* Iterate for number of ports to perform initialization */
1190 for (i = 0; i < num_ports; i++) {
1191 p_rt = sdw_port_alloc(bus->dev, port_config, i);
1192 if (!p_rt)
1193 return -ENOMEM;
1194
1195 /*
1196 * TODO: Check port capabilities for requested
1197 * configuration (audio mode support)
1198 */
1199
1200 list_add_tail(&p_rt->port_node, &m_rt->port_list);
1201 }
1202
1203 return 0;
1204}
1205
1206static int sdw_slave_port_config(struct sdw_slave *slave,
1207 struct sdw_slave_runtime *s_rt,
1208 struct sdw_port_config *port_config,
1209 unsigned int num_config)
1210{
1211 struct sdw_port_runtime *p_rt;
1212 int i, ret;
1213
1214 /* Iterate for number of ports to perform initialization */
1215 for (i = 0; i < num_config; i++) {
1216 p_rt = sdw_port_alloc(&slave->dev, port_config, i);
1217 if (!p_rt)
1218 return -ENOMEM;
1219
1220 /*
1221 * TODO: Check valid port range as defined by DisCo/
1222 * slave
1223 */
1224 ret = sdw_is_valid_port_range(&slave->dev, p_rt);
1225 if (ret < 0) {
1226 kfree(p_rt);
1227 return ret;
1228 }
1229
1230 /*
1231 * TODO: Check port capabilities for requested
1232 * configuration (audio mode support)
1233 */
1234
1235 list_add_tail(&p_rt->port_node, &s_rt->port_list);
1236 }
1237
1238 return 0;
1239}
1240
89e59053
SK
1241/**
1242 * sdw_stream_add_master() - Allocate and add master runtime to a stream
1243 *
1244 * @bus: SDW Bus instance
1245 * @stream_config: Stream configuration for audio stream
bbe7379d
SK
1246 * @port_config: Port configuration for audio stream
1247 * @num_ports: Number of ports
89e59053
SK
1248 * @stream: SoundWire stream
1249 */
1250int sdw_stream_add_master(struct sdw_bus *bus,
1251 struct sdw_stream_config *stream_config,
bbe7379d
SK
1252 struct sdw_port_config *port_config,
1253 unsigned int num_ports,
89e59053
SK
1254 struct sdw_stream_runtime *stream)
1255{
1256 struct sdw_master_runtime *m_rt = NULL;
1257 int ret;
1258
1259 mutex_lock(&bus->bus_lock);
1260
ce6e74d0
SN
1261 /*
1262 * For multi link streams, add the second master only if
1263 * the bus supports it.
1264 * Check if bus->multi_link is set
1265 */
1266 if (!bus->multi_link && stream->m_rt_count > 0) {
1267 dev_err(bus->dev,
1268 "Multilink not supported, link %d", bus->link_id);
1269 ret = -EINVAL;
1270 goto unlock;
1271 }
1272
89e59053
SK
1273 m_rt = sdw_alloc_master_rt(bus, stream_config, stream);
1274 if (!m_rt) {
1275 dev_err(bus->dev,
1276 "Master runtime config failed for stream:%s",
1277 stream->name);
1278 ret = -ENOMEM;
3fef1a22 1279 goto unlock;
89e59053
SK
1280 }
1281
1282 ret = sdw_config_stream(bus->dev, stream, stream_config, false);
1283 if (ret)
1284 goto stream_error;
1285
bbe7379d
SK
1286 ret = sdw_master_port_config(bus, m_rt, port_config, num_ports);
1287 if (ret)
1288 goto stream_error;
1289
ce6e74d0
SN
1290 stream->m_rt_count++;
1291
3fef1a22
SN
1292 goto unlock;
1293
89e59053 1294stream_error:
48949722 1295 sdw_release_master_stream(m_rt, stream);
3fef1a22 1296unlock:
89e59053
SK
1297 mutex_unlock(&bus->bus_lock);
1298 return ret;
1299}
1300EXPORT_SYMBOL(sdw_stream_add_master);
1301
1302/**
1303 * sdw_stream_add_slave() - Allocate and add master/slave runtime to a stream
1304 *
1305 * @slave: SDW Slave instance
1306 * @stream_config: Stream configuration for audio stream
1307 * @stream: SoundWire stream
bbe7379d
SK
1308 * @port_config: Port configuration for audio stream
1309 * @num_ports: Number of ports
0aebe40b
SN
1310 *
1311 * It is expected that Slave is added before adding Master
1312 * to the Stream.
1313 *
89e59053
SK
1314 */
1315int sdw_stream_add_slave(struct sdw_slave *slave,
1316 struct sdw_stream_config *stream_config,
bbe7379d
SK
1317 struct sdw_port_config *port_config,
1318 unsigned int num_ports,
89e59053
SK
1319 struct sdw_stream_runtime *stream)
1320{
1321 struct sdw_slave_runtime *s_rt;
1322 struct sdw_master_runtime *m_rt;
1323 int ret;
1324
1325 mutex_lock(&slave->bus->bus_lock);
1326
1327 /*
1328 * If this API is invoked by Slave first then m_rt is not valid.
1329 * So, allocate m_rt and add Slave to it.
1330 */
1331 m_rt = sdw_alloc_master_rt(slave->bus, stream_config, stream);
1332 if (!m_rt) {
1333 dev_err(&slave->dev,
1334 "alloc master runtime failed for stream:%s",
1335 stream->name);
1336 ret = -ENOMEM;
1337 goto error;
1338 }
1339
1340 s_rt = sdw_alloc_slave_rt(slave, stream_config, stream);
1341 if (!s_rt) {
1342 dev_err(&slave->dev,
1343 "Slave runtime config failed for stream:%s",
1344 stream->name);
1345 ret = -ENOMEM;
1346 goto stream_error;
1347 }
1348
1349 ret = sdw_config_stream(&slave->dev, stream, stream_config, true);
1350 if (ret)
1351 goto stream_error;
1352
1353 list_add_tail(&s_rt->m_rt_node, &m_rt->slave_rt_list);
1354
bbe7379d
SK
1355 ret = sdw_slave_port_config(slave, s_rt, port_config, num_ports);
1356 if (ret)
1357 goto stream_error;
1358
0aebe40b
SN
1359 /*
1360 * Change stream state to CONFIGURED on first Slave add.
1361 * Bus is not aware of number of Slave(s) in a stream at this
1362 * point so cannot depend on all Slave(s) to be added in order to
1363 * change stream state to CONFIGURED.
1364 */
89e59053
SK
1365 stream->state = SDW_STREAM_CONFIGURED;
1366 goto error;
1367
1368stream_error:
1369 /*
1370 * we hit error so cleanup the stream, release all Slave(s) and
1371 * Master runtime
1372 */
48949722 1373 sdw_release_master_stream(m_rt, stream);
89e59053
SK
1374error:
1375 mutex_unlock(&slave->bus->bus_lock);
1376 return ret;
1377}
1378EXPORT_SYMBOL(sdw_stream_add_slave);
f8101c74
SK
1379
1380/**
1381 * sdw_get_slave_dpn_prop() - Get Slave port capabilities
1382 *
1383 * @slave: Slave handle
1384 * @direction: Data direction.
1385 * @port_num: Port number
1386 */
1387struct sdw_dpn_prop *sdw_get_slave_dpn_prop(struct sdw_slave *slave,
1388 enum sdw_data_direction direction,
1389 unsigned int port_num)
1390{
1391 struct sdw_dpn_prop *dpn_prop;
1392 u8 num_ports;
1393 int i;
1394
1395 if (direction == SDW_DATA_DIR_TX) {
1396 num_ports = hweight32(slave->prop.source_ports);
1397 dpn_prop = slave->prop.src_dpn_prop;
1398 } else {
1399 num_ports = hweight32(slave->prop.sink_ports);
1400 dpn_prop = slave->prop.sink_dpn_prop;
1401 }
1402
1403 for (i = 0; i < num_ports; i++) {
1404 dpn_prop = &dpn_prop[i];
1405
1406 if (dpn_prop->num == port_num)
1407 return &dpn_prop[i];
1408 }
1409
1410 return NULL;
1411}
5c3eb9f7 1412
0c4a1049
SK
1413/**
1414 * sdw_acquire_bus_lock: Acquire bus lock for all Master runtime(s)
1415 *
1416 * @stream: SoundWire stream
1417 *
1418 * Acquire bus_lock for each of the master runtime(m_rt) part of this
1419 * stream to reconfigure the bus.
1420 * NOTE: This function is called from SoundWire stream ops and is
1421 * expected that a global lock is held before acquiring bus_lock.
1422 */
1423static void sdw_acquire_bus_lock(struct sdw_stream_runtime *stream)
1424{
1425 struct sdw_master_runtime *m_rt = NULL;
1426 struct sdw_bus *bus = NULL;
1427
1428 /* Iterate for all Master(s) in Master list */
1429 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1430 bus = m_rt->bus;
1431
1432 mutex_lock(&bus->bus_lock);
1433 }
1434}
1435
1436/**
1437 * sdw_release_bus_lock: Release bus lock for all Master runtime(s)
1438 *
1439 * @stream: SoundWire stream
1440 *
1441 * Release the previously held bus_lock after reconfiguring the bus.
48949722
VK
1442 * NOTE: This function is called from SoundWire stream ops and is
1443 * expected that a global lock is held before releasing bus_lock.
0c4a1049
SK
1444 */
1445static void sdw_release_bus_lock(struct sdw_stream_runtime *stream)
1446{
1447 struct sdw_master_runtime *m_rt = NULL;
1448 struct sdw_bus *bus = NULL;
1449
1450 /* Iterate for all Master(s) in Master list */
1451 list_for_each_entry_reverse(m_rt, &stream->master_list, stream_node) {
1452 bus = m_rt->bus;
1453 mutex_unlock(&bus->bus_lock);
1454 }
1455}
1456
5c3eb9f7
SK
1457static int _sdw_prepare_stream(struct sdw_stream_runtime *stream)
1458{
48949722
VK
1459 struct sdw_master_runtime *m_rt = NULL;
1460 struct sdw_bus *bus = NULL;
5c3eb9f7
SK
1461 struct sdw_master_prop *prop = NULL;
1462 struct sdw_bus_params params;
1463 int ret;
1464
48949722
VK
1465 /* Prepare Master(s) and Slave(s) port(s) associated with stream */
1466 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1467 bus = m_rt->bus;
1468 prop = &bus->prop;
1469 memcpy(&params, &bus->params, sizeof(params));
5c3eb9f7 1470
48949722
VK
1471 /* TODO: Support Asynchronous mode */
1472 if ((prop->max_freq % stream->params.rate) != 0) {
1473 dev_err(bus->dev, "Async mode not supported");
1474 return -EINVAL;
1475 }
5c3eb9f7 1476
48949722
VK
1477 /* Increment cumulative bus bandwidth */
1478 /* TODO: Update this during Device-Device support */
1479 bus->params.bandwidth += m_rt->stream->params.rate *
1480 m_rt->ch_count * m_rt->stream->params.bps;
1481
1482 /* Program params */
1483 ret = sdw_program_params(bus);
1484 if (ret < 0) {
1485 dev_err(bus->dev, "Program params failed: %d", ret);
1486 goto restore_params;
1487 }
5c3eb9f7 1488
5c3eb9f7
SK
1489 }
1490
1491 ret = do_bank_switch(stream);
1492 if (ret < 0) {
1493 dev_err(bus->dev, "Bank switch failed: %d", ret);
1494 goto restore_params;
1495 }
1496
48949722
VK
1497 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1498 bus = m_rt->bus;
1499
1500 /* Prepare port(s) on the new clock configuration */
1501 ret = sdw_prep_deprep_ports(m_rt, true);
1502 if (ret < 0) {
1503 dev_err(bus->dev, "Prepare port(s) failed ret = %d",
1504 ret);
1505 return ret;
1506 }
5c3eb9f7
SK
1507 }
1508
1509 stream->state = SDW_STREAM_PREPARED;
1510
1511 return ret;
1512
1513restore_params:
1514 memcpy(&bus->params, &params, sizeof(params));
1515 return ret;
1516}
1517
1518/**
1519 * sdw_prepare_stream() - Prepare SoundWire stream
1520 *
1521 * @stream: Soundwire stream
1522 *
34962fb8 1523 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
5c3eb9f7
SK
1524 */
1525int sdw_prepare_stream(struct sdw_stream_runtime *stream)
1526{
1527 int ret = 0;
1528
1529 if (!stream) {
1530 pr_err("SoundWire: Handle not found for stream");
1531 return -EINVAL;
1532 }
1533
48949722 1534 sdw_acquire_bus_lock(stream);
5c3eb9f7
SK
1535
1536 ret = _sdw_prepare_stream(stream);
1537 if (ret < 0)
1538 pr_err("Prepare for stream:%s failed: %d", stream->name, ret);
1539
48949722 1540 sdw_release_bus_lock(stream);
5c3eb9f7
SK
1541 return ret;
1542}
1543EXPORT_SYMBOL(sdw_prepare_stream);
1544
1545static int _sdw_enable_stream(struct sdw_stream_runtime *stream)
1546{
48949722
VK
1547 struct sdw_master_runtime *m_rt = NULL;
1548 struct sdw_bus *bus = NULL;
5c3eb9f7
SK
1549 int ret;
1550
48949722
VK
1551 /* Enable Master(s) and Slave(s) port(s) associated with stream */
1552 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1553 bus = m_rt->bus;
5c3eb9f7 1554
48949722
VK
1555 /* Program params */
1556 ret = sdw_program_params(bus);
1557 if (ret < 0) {
1558 dev_err(bus->dev, "Program params failed: %d", ret);
1559 return ret;
1560 }
1561
1562 /* Enable port(s) */
1563 ret = sdw_enable_disable_ports(m_rt, true);
1564 if (ret < 0) {
1565 dev_err(bus->dev, "Enable port(s) failed ret: %d", ret);
1566 return ret;
1567 }
5c3eb9f7
SK
1568 }
1569
1570 ret = do_bank_switch(stream);
1571 if (ret < 0) {
1572 dev_err(bus->dev, "Bank switch failed: %d", ret);
1573 return ret;
1574 }
1575
1576 stream->state = SDW_STREAM_ENABLED;
1577 return 0;
1578}
1579
1580/**
1581 * sdw_enable_stream() - Enable SoundWire stream
1582 *
1583 * @stream: Soundwire stream
1584 *
34962fb8 1585 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
5c3eb9f7
SK
1586 */
1587int sdw_enable_stream(struct sdw_stream_runtime *stream)
1588{
1589 int ret = 0;
1590
1591 if (!stream) {
1592 pr_err("SoundWire: Handle not found for stream");
1593 return -EINVAL;
1594 }
1595
48949722 1596 sdw_acquire_bus_lock(stream);
5c3eb9f7
SK
1597
1598 ret = _sdw_enable_stream(stream);
1599 if (ret < 0)
1600 pr_err("Enable for stream:%s failed: %d", stream->name, ret);
1601
48949722 1602 sdw_release_bus_lock(stream);
5c3eb9f7
SK
1603 return ret;
1604}
1605EXPORT_SYMBOL(sdw_enable_stream);
1606
1607static int _sdw_disable_stream(struct sdw_stream_runtime *stream)
1608{
48949722
VK
1609 struct sdw_master_runtime *m_rt = NULL;
1610 struct sdw_bus *bus = NULL;
5c3eb9f7
SK
1611 int ret;
1612
48949722
VK
1613 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1614 bus = m_rt->bus;
1615 /* Disable port(s) */
1616 ret = sdw_enable_disable_ports(m_rt, false);
1617 if (ret < 0) {
1618 dev_err(bus->dev, "Disable port(s) failed: %d", ret);
1619 return ret;
1620 }
5c3eb9f7 1621 }
5c3eb9f7
SK
1622 stream->state = SDW_STREAM_DISABLED;
1623
48949722
VK
1624 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1625 bus = m_rt->bus;
1626 /* Program params */
1627 ret = sdw_program_params(bus);
1628 if (ret < 0) {
1629 dev_err(bus->dev, "Program params failed: %d", ret);
1630 return ret;
1631 }
5c3eb9f7
SK
1632 }
1633
1634 return do_bank_switch(stream);
1635}
1636
1637/**
1638 * sdw_disable_stream() - Disable SoundWire stream
1639 *
1640 * @stream: Soundwire stream
1641 *
34962fb8 1642 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
5c3eb9f7
SK
1643 */
1644int sdw_disable_stream(struct sdw_stream_runtime *stream)
1645{
1646 int ret = 0;
1647
1648 if (!stream) {
1649 pr_err("SoundWire: Handle not found for stream");
1650 return -EINVAL;
1651 }
1652
48949722 1653 sdw_acquire_bus_lock(stream);
5c3eb9f7
SK
1654
1655 ret = _sdw_disable_stream(stream);
1656 if (ret < 0)
1657 pr_err("Disable for stream:%s failed: %d", stream->name, ret);
1658
48949722 1659 sdw_release_bus_lock(stream);
5c3eb9f7
SK
1660 return ret;
1661}
1662EXPORT_SYMBOL(sdw_disable_stream);
1663
1664static int _sdw_deprepare_stream(struct sdw_stream_runtime *stream)
1665{
48949722
VK
1666 struct sdw_master_runtime *m_rt = NULL;
1667 struct sdw_bus *bus = NULL;
5c3eb9f7
SK
1668 int ret = 0;
1669
48949722
VK
1670 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1671 bus = m_rt->bus;
1672 /* De-prepare port(s) */
1673 ret = sdw_prep_deprep_ports(m_rt, false);
1674 if (ret < 0) {
1675 dev_err(bus->dev, "De-prepare port(s) failed: %d", ret);
1676 return ret;
1677 }
5c3eb9f7 1678
48949722
VK
1679 /* TODO: Update this during Device-Device support */
1680 bus->params.bandwidth -= m_rt->stream->params.rate *
1681 m_rt->ch_count * m_rt->stream->params.bps;
5c3eb9f7 1682
48949722
VK
1683 /* Program params */
1684 ret = sdw_program_params(bus);
1685 if (ret < 0) {
1686 dev_err(bus->dev, "Program params failed: %d", ret);
1687 return ret;
1688 }
5c3eb9f7 1689
5c3eb9f7
SK
1690 }
1691
48949722 1692 stream->state = SDW_STREAM_DEPREPARED;
5c3eb9f7
SK
1693 return do_bank_switch(stream);
1694}
1695
1696/**
1697 * sdw_deprepare_stream() - Deprepare SoundWire stream
1698 *
1699 * @stream: Soundwire stream
1700 *
34962fb8 1701 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
5c3eb9f7
SK
1702 */
1703int sdw_deprepare_stream(struct sdw_stream_runtime *stream)
1704{
1705 int ret = 0;
1706
1707 if (!stream) {
1708 pr_err("SoundWire: Handle not found for stream");
1709 return -EINVAL;
1710 }
1711
48949722 1712 sdw_acquire_bus_lock(stream);
5c3eb9f7
SK
1713 ret = _sdw_deprepare_stream(stream);
1714 if (ret < 0)
1715 pr_err("De-prepare for stream:%d failed: %d", ret, ret);
1716
48949722 1717 sdw_release_bus_lock(stream);
5c3eb9f7
SK
1718 return ret;
1719}
1720EXPORT_SYMBOL(sdw_deprepare_stream);