Commit | Line | Data |
---|---|---|
02efb49a SK |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // Copyright (c) 2019, Linaro Limited | |
3 | ||
4 | #include <linux/clk.h> | |
5 | #include <linux/completion.h> | |
6 | #include <linux/interrupt.h> | |
7 | #include <linux/io.h> | |
8 | #include <linux/kernel.h> | |
9 | #include <linux/module.h> | |
abd9a604 | 10 | #include <linux/debugfs.h> |
02efb49a SK |
11 | #include <linux/of.h> |
12 | #include <linux/of_irq.h> | |
74e79da9 | 13 | #include <linux/pm_runtime.h> |
02efb49a | 14 | #include <linux/regmap.h> |
33ba0178 | 15 | #include <linux/reset.h> |
02efb49a | 16 | #include <linux/slab.h> |
04d46a7b | 17 | #include <linux/pm_wakeirq.h> |
02efb49a SK |
18 | #include <linux/slimbus.h> |
19 | #include <linux/soundwire/sdw.h> | |
20 | #include <linux/soundwire/sdw_registers.h> | |
21 | #include <sound/pcm_params.h> | |
22 | #include <sound/soc.h> | |
23 | #include "bus.h" | |
24 | ||
74e79da9 SK |
25 | #define SWRM_COMP_SW_RESET 0x008 |
26 | #define SWRM_COMP_STATUS 0x014 | |
cf43cd33 SK |
27 | #define SWRM_LINK_MANAGER_EE 0x018 |
28 | #define SWRM_EE_CPU 1 | |
74e79da9 | 29 | #define SWRM_FRM_GEN_ENABLED BIT(0) |
208a03ee KK |
30 | #define SWRM_VERSION_1_3_0 0x01030000 |
31 | #define SWRM_VERSION_1_5_1 0x01050001 | |
32 | #define SWRM_VERSION_1_7_0 0x01070000 | |
312355a6 | 33 | #define SWRM_VERSION_2_0_0 0x02000000 |
02efb49a SK |
34 | #define SWRM_COMP_HW_VERSION 0x00 |
35 | #define SWRM_COMP_CFG_ADDR 0x04 | |
36 | #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK BIT(1) | |
37 | #define SWRM_COMP_CFG_ENABLE_MSK BIT(0) | |
38 | #define SWRM_COMP_PARAMS 0x100 | |
a661308c SK |
39 | #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH GENMASK(14, 10) |
40 | #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH GENMASK(19, 15) | |
02efb49a SK |
41 | #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0) |
42 | #define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5) | |
74e79da9 | 43 | #define SWRM_COMP_MASTER_ID 0x104 |
6378fe11 | 44 | #define SWRM_V1_3_INTERRUPT_STATUS 0x200 |
312355a6 | 45 | #define SWRM_V2_0_INTERRUPT_STATUS 0x5000 |
02efb49a | 46 | #define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0) |
c7d49c76 | 47 | #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ BIT(0) |
02efb49a SK |
48 | #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED BIT(1) |
49 | #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS BIT(2) | |
c7d49c76 SK |
50 | #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET BIT(3) |
51 | #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW BIT(4) | |
52 | #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW BIT(5) | |
53 | #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW BIT(6) | |
02efb49a | 54 | #define SWRM_INTERRUPT_STATUS_CMD_ERROR BIT(7) |
c7d49c76 SK |
55 | #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION BIT(8) |
56 | #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH BIT(9) | |
02efb49a | 57 | #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED BIT(10) |
312355a6 KK |
58 | #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED BIT(11) |
59 | #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL BIT(12) | |
e24d0b65 KK |
60 | #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2 BIT(13) |
61 | #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14) | |
62 | #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16) | |
16d568c8 | 63 | #define SWRM_INTERRUPT_STATUS_CMD_IGNORED_AND_EXEC_CONTINUED BIT(19) |
c7d49c76 | 64 | #define SWRM_INTERRUPT_MAX 17 |
6378fe11 KK |
65 | #define SWRM_V1_3_INTERRUPT_MASK_ADDR 0x204 |
66 | #define SWRM_V1_3_INTERRUPT_CLEAR 0x208 | |
312355a6 | 67 | #define SWRM_V2_0_INTERRUPT_CLEAR 0x5008 |
6378fe11 | 68 | #define SWRM_V1_3_INTERRUPT_CPU_EN 0x210 |
312355a6 | 69 | #define SWRM_V2_0_INTERRUPT_CPU_EN 0x5004 |
6378fe11 | 70 | #define SWRM_V1_3_CMD_FIFO_WR_CMD 0x300 |
312355a6 | 71 | #define SWRM_V2_0_CMD_FIFO_WR_CMD 0x5020 |
6378fe11 | 72 | #define SWRM_V1_3_CMD_FIFO_RD_CMD 0x304 |
312355a6 | 73 | #define SWRM_V2_0_CMD_FIFO_RD_CMD 0x5024 |
02efb49a | 74 | #define SWRM_CMD_FIFO_CMD 0x308 |
ddea6cf7 | 75 | #define SWRM_CMD_FIFO_FLUSH 0x1 |
6378fe11 | 76 | #define SWRM_V1_3_CMD_FIFO_STATUS 0x30C |
312355a6 | 77 | #define SWRM_V2_0_CMD_FIFO_STATUS 0x5050 |
a661308c SK |
78 | #define SWRM_RD_CMD_FIFO_CNT_MASK GENMASK(20, 16) |
79 | #define SWRM_WR_CMD_FIFO_CNT_MASK GENMASK(12, 8) | |
02efb49a | 80 | #define SWRM_CMD_FIFO_CFG_ADDR 0x314 |
542d3491 | 81 | #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE BIT(31) |
02efb49a | 82 | #define SWRM_RD_WR_CMD_RETRIES 0x7 |
6378fe11 | 83 | #define SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR 0x318 |
312355a6 | 84 | #define SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR 0x5040 |
ddea6cf7 | 85 | #define SWRM_RD_FIFO_CMD_ID_MASK GENMASK(11, 8) |
02efb49a | 86 | #define SWRM_ENUMERATOR_CFG_ADDR 0x500 |
a6e65819 SK |
87 | #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) (0x530 + 0x8 * (m)) |
88 | #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m) (0x534 + 0x8 * (m)) | |
02efb49a | 89 | #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m) (0x101C + 0x40 * (m)) |
02efb49a SK |
90 | #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK GENMASK(2, 0) |
91 | #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK GENMASK(7, 3) | |
a866a049 SK |
92 | #define SWRM_MCP_BUS_CTRL 0x1044 |
93 | #define SWRM_MCP_BUS_CLK_START BIT(1) | |
02efb49a SK |
94 | #define SWRM_MCP_CFG_ADDR 0x1048 |
95 | #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK GENMASK(21, 17) | |
02efb49a SK |
96 | #define SWRM_DEF_CMD_NO_PINGS 0x1f |
97 | #define SWRM_MCP_STATUS 0x104C | |
98 | #define SWRM_MCP_STATUS_BANK_NUM_MASK BIT(0) | |
99 | #define SWRM_MCP_SLV_STATUS 0x1090 | |
100 | #define SWRM_MCP_SLV_STATUS_MASK GENMASK(1, 0) | |
c7d49c76 | 101 | #define SWRM_MCP_SLV_STATUS_SZ 2 |
02efb49a | 102 | #define SWRM_DP_PORT_CTRL_BANK(n, m) (0x1124 + 0x100 * (n - 1) + 0x40 * m) |
128eaf93 SK |
103 | #define SWRM_DP_PORT_CTRL_2_BANK(n, m) (0x1128 + 0x100 * (n - 1) + 0x40 * m) |
104 | #define SWRM_DP_BLOCK_CTRL_1(n) (0x112C + 0x100 * (n - 1)) | |
105 | #define SWRM_DP_BLOCK_CTRL2_BANK(n, m) (0x1130 + 0x100 * (n - 1) + 0x40 * m) | |
106 | #define SWRM_DP_PORT_HCTRL_BANK(n, m) (0x1134 + 0x100 * (n - 1) + 0x40 * m) | |
5ffba1fb | 107 | #define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m) |
a8dffaa0 | 108 | #define SWRM_DP_SAMPLECTRL2_BANK(n, m) (0x113C + 0x100 * (n - 1) + 0x40 * m) |
128eaf93 | 109 | #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1)) |
6378fe11 | 110 | #define SWR_V1_3_MSTR_MAX_REG_ADDR 0x1740 |
312355a6 KK |
111 | #define SWR_V2_0_MSTR_MAX_REG_ADDR 0x50ac |
112 | ||
113 | #define SWRM_V2_0_CLK_CTRL 0x5060 | |
114 | #define SWRM_V2_0_CLK_CTRL_CLK_START BIT(0) | |
115 | #define SWRM_V2_0_LINK_STATUS 0x5064 | |
128eaf93 | 116 | |
02efb49a SK |
117 | #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18 |
118 | #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10 | |
119 | #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT 0x08 | |
120 | #define SWRM_AHB_BRIDGE_WR_DATA_0 0xc85 | |
121 | #define SWRM_AHB_BRIDGE_WR_ADDR_0 0xc89 | |
122 | #define SWRM_AHB_BRIDGE_RD_ADDR_0 0xc8d | |
123 | #define SWRM_AHB_BRIDGE_RD_DATA_0 0xc91 | |
124 | ||
125 | #define SWRM_REG_VAL_PACK(data, dev, id, reg) \ | |
126 | ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24)) | |
127 | ||
e24d0b65 KK |
128 | #define MAX_FREQ_NUM 1 |
129 | #define TIMEOUT_MS 100 | |
130 | #define QCOM_SWRM_MAX_RD_LEN 0x1 | |
131 | #define QCOM_SDW_MAX_PORTS 14 | |
132 | #define DEFAULT_CLK_FREQ 9600000 | |
133 | #define SWRM_MAX_DAIS 0xF | |
134 | #define SWR_INVALID_PARAM 0xFF | |
135 | #define SWR_HSTOP_MAX_VAL 0xF | |
136 | #define SWR_HSTART_MIN_VAL 0x0 | |
137 | #define SWR_BROADCAST_CMD_ID 0x0F | |
138 | #define SWR_MAX_CMD_ID 14 | |
139 | #define MAX_FIFO_RD_RETRY 3 | |
140 | #define SWR_OVERFLOW_RETRY_COUNT 30 | |
141 | #define SWRM_LINK_STATUS_RETRY_CNT 100 | |
74e79da9 SK |
142 | |
143 | enum { | |
144 | MASTER_ID_WSA = 1, | |
145 | MASTER_ID_RX, | |
146 | MASTER_ID_TX | |
147 | }; | |
02efb49a SK |
148 | |
149 | struct qcom_swrm_port_config { | |
a8dffaa0 | 150 | u16 si; |
02efb49a SK |
151 | u8 off1; |
152 | u8 off2; | |
5ffba1fb | 153 | u8 bp_mode; |
128eaf93 SK |
154 | u8 hstart; |
155 | u8 hstop; | |
156 | u8 word_length; | |
157 | u8 blk_group_count; | |
158 | u8 lane_control; | |
02efb49a SK |
159 | }; |
160 | ||
6378fe11 KK |
161 | /* |
162 | * Internal IDs for different register layouts. Only few registers differ per | |
163 | * each variant, so the list of IDs below does not include all of registers. | |
164 | */ | |
165 | enum { | |
166 | SWRM_REG_FRAME_GEN_ENABLED, | |
167 | SWRM_REG_INTERRUPT_STATUS, | |
168 | SWRM_REG_INTERRUPT_MASK_ADDR, | |
169 | SWRM_REG_INTERRUPT_CLEAR, | |
170 | SWRM_REG_INTERRUPT_CPU_EN, | |
171 | SWRM_REG_CMD_FIFO_WR_CMD, | |
172 | SWRM_REG_CMD_FIFO_RD_CMD, | |
173 | SWRM_REG_CMD_FIFO_STATUS, | |
174 | SWRM_REG_CMD_FIFO_RD_FIFO_ADDR, | |
175 | }; | |
176 | ||
02efb49a SK |
177 | struct qcom_swrm_ctrl { |
178 | struct sdw_bus bus; | |
179 | struct device *dev; | |
180 | struct regmap *regmap; | |
6378fe11 KK |
181 | u32 max_reg; |
182 | const unsigned int *reg_layout; | |
82f5c70c | 183 | void __iomem *mmio; |
33ba0178 | 184 | struct reset_control *audio_cgcr; |
abd9a604 SK |
185 | #ifdef CONFIG_DEBUG_FS |
186 | struct dentry *debugfs; | |
187 | #endif | |
ddea6cf7 | 188 | struct completion broadcast; |
06dd9673 | 189 | struct completion enumeration; |
02efb49a SK |
190 | /* Port alloc/free lock */ |
191 | struct mutex port_lock; | |
192 | struct clk *hclk; | |
02efb49a SK |
193 | int irq; |
194 | unsigned int version; | |
04d46a7b | 195 | int wake_irq; |
02efb49a SK |
196 | int num_din_ports; |
197 | int num_dout_ports; | |
8cb3b4e7 SK |
198 | int cols_index; |
199 | int rows_index; | |
02efb49a SK |
200 | unsigned long dout_port_mask; |
201 | unsigned long din_port_mask; | |
c7d49c76 | 202 | u32 intr_mask; |
ddea6cf7 SK |
203 | u8 rcmd_id; |
204 | u8 wcmd_id; | |
490937d4 KK |
205 | /* Port numbers are 1 - 14 */ |
206 | struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS + 1]; | |
02efb49a | 207 | struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS]; |
4ef3f2af | 208 | enum sdw_slave_status status[SDW_MAX_DEVICES + 1]; |
02efb49a SK |
209 | int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val); |
210 | int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val); | |
a6e65819 | 211 | u32 slave_status; |
a661308c SK |
212 | u32 wr_fifo_depth; |
213 | u32 rd_fifo_depth; | |
74e79da9 | 214 | bool clock_stop_not_supported; |
02efb49a SK |
215 | }; |
216 | ||
8cb3b4e7 SK |
217 | struct qcom_swrm_data { |
218 | u32 default_cols; | |
219 | u32 default_rows; | |
1fd0d85a | 220 | bool sw_clk_gate_required; |
6378fe11 KK |
221 | u32 max_reg; |
222 | const unsigned int *reg_layout; | |
223 | }; | |
224 | ||
225 | static const unsigned int swrm_v1_3_reg_layout[] = { | |
226 | [SWRM_REG_FRAME_GEN_ENABLED] = SWRM_COMP_STATUS, | |
227 | [SWRM_REG_INTERRUPT_STATUS] = SWRM_V1_3_INTERRUPT_STATUS, | |
228 | [SWRM_REG_INTERRUPT_MASK_ADDR] = SWRM_V1_3_INTERRUPT_MASK_ADDR, | |
229 | [SWRM_REG_INTERRUPT_CLEAR] = SWRM_V1_3_INTERRUPT_CLEAR, | |
230 | [SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V1_3_INTERRUPT_CPU_EN, | |
231 | [SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V1_3_CMD_FIFO_WR_CMD, | |
232 | [SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V1_3_CMD_FIFO_RD_CMD, | |
233 | [SWRM_REG_CMD_FIFO_STATUS] = SWRM_V1_3_CMD_FIFO_STATUS, | |
234 | [SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR, | |
8cb3b4e7 SK |
235 | }; |
236 | ||
35732a06 | 237 | static const struct qcom_swrm_data swrm_v1_3_data = { |
8cb3b4e7 SK |
238 | .default_rows = 48, |
239 | .default_cols = 16, | |
6378fe11 KK |
240 | .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR, |
241 | .reg_layout = swrm_v1_3_reg_layout, | |
8cb3b4e7 SK |
242 | }; |
243 | ||
35732a06 | 244 | static const struct qcom_swrm_data swrm_v1_5_data = { |
8cb3b4e7 SK |
245 | .default_rows = 50, |
246 | .default_cols = 16, | |
6378fe11 KK |
247 | .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR, |
248 | .reg_layout = swrm_v1_3_reg_layout, | |
8cb3b4e7 SK |
249 | }; |
250 | ||
3f4a7026 SRM |
251 | static const struct qcom_swrm_data swrm_v1_6_data = { |
252 | .default_rows = 50, | |
253 | .default_cols = 16, | |
254 | .sw_clk_gate_required = true, | |
6378fe11 KK |
255 | .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR, |
256 | .reg_layout = swrm_v1_3_reg_layout, | |
3f4a7026 SRM |
257 | }; |
258 | ||
312355a6 KK |
259 | static const unsigned int swrm_v2_0_reg_layout[] = { |
260 | [SWRM_REG_FRAME_GEN_ENABLED] = SWRM_V2_0_LINK_STATUS, | |
261 | [SWRM_REG_INTERRUPT_STATUS] = SWRM_V2_0_INTERRUPT_STATUS, | |
262 | [SWRM_REG_INTERRUPT_MASK_ADDR] = 0, /* Not present */ | |
263 | [SWRM_REG_INTERRUPT_CLEAR] = SWRM_V2_0_INTERRUPT_CLEAR, | |
264 | [SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V2_0_INTERRUPT_CPU_EN, | |
265 | [SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V2_0_CMD_FIFO_WR_CMD, | |
266 | [SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V2_0_CMD_FIFO_RD_CMD, | |
267 | [SWRM_REG_CMD_FIFO_STATUS] = SWRM_V2_0_CMD_FIFO_STATUS, | |
268 | [SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR, | |
269 | }; | |
270 | ||
271 | static const struct qcom_swrm_data swrm_v2_0_data = { | |
272 | .default_rows = 50, | |
273 | .default_cols = 16, | |
274 | .sw_clk_gate_required = true, | |
275 | .max_reg = SWR_V2_0_MSTR_MAX_REG_ADDR, | |
276 | .reg_layout = swrm_v2_0_reg_layout, | |
277 | }; | |
278 | ||
02efb49a SK |
279 | #define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus) |
280 | ||
d1df23fe | 281 | static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, |
02efb49a SK |
282 | u32 *val) |
283 | { | |
284 | struct regmap *wcd_regmap = ctrl->regmap; | |
285 | int ret; | |
286 | ||
287 | /* pg register + offset */ | |
288 | ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0, | |
289 | (u8 *)®, 4); | |
290 | if (ret < 0) | |
291 | return SDW_CMD_FAIL; | |
292 | ||
293 | ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0, | |
294 | val, 4); | |
295 | if (ret < 0) | |
296 | return SDW_CMD_FAIL; | |
297 | ||
298 | return SDW_CMD_OK; | |
299 | } | |
300 | ||
301 | static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl, | |
302 | int reg, int val) | |
303 | { | |
304 | struct regmap *wcd_regmap = ctrl->regmap; | |
305 | int ret; | |
306 | /* pg register + offset */ | |
307 | ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0, | |
308 | (u8 *)&val, 4); | |
309 | if (ret) | |
310 | return SDW_CMD_FAIL; | |
311 | ||
312 | /* write address register */ | |
313 | ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0, | |
314 | (u8 *)®, 4); | |
315 | if (ret) | |
316 | return SDW_CMD_FAIL; | |
317 | ||
318 | return SDW_CMD_OK; | |
319 | } | |
320 | ||
82f5c70c JM |
321 | static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, |
322 | u32 *val) | |
323 | { | |
324 | *val = readl(ctrl->mmio + reg); | |
325 | return SDW_CMD_OK; | |
326 | } | |
327 | ||
328 | static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg, | |
329 | int val) | |
330 | { | |
331 | writel(val, ctrl->mmio + reg); | |
332 | return SDW_CMD_OK; | |
333 | } | |
334 | ||
ddea6cf7 SK |
335 | static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data, |
336 | u8 dev_addr, u16 reg_addr) | |
02efb49a | 337 | { |
02efb49a | 338 | u32 val; |
ddea6cf7 | 339 | u8 id = *cmd_id; |
02efb49a | 340 | |
ddea6cf7 SK |
341 | if (id != SWR_BROADCAST_CMD_ID) { |
342 | if (id < SWR_MAX_CMD_ID) | |
343 | id += 1; | |
344 | else | |
345 | id = 0; | |
346 | *cmd_id = id; | |
347 | } | |
348 | val = SWRM_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr); | |
02efb49a | 349 | |
ddea6cf7 | 350 | return val; |
02efb49a SK |
351 | } |
352 | ||
6f76e791 | 353 | static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *ctrl) |
a661308c SK |
354 | { |
355 | u32 fifo_outstanding_data, value; | |
356 | int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT; | |
357 | ||
358 | do { | |
359 | /* Check for fifo underflow during read */ | |
6378fe11 KK |
360 | ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], |
361 | &value); | |
a661308c SK |
362 | fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value); |
363 | ||
364 | /* Check if read data is available in read fifo */ | |
365 | if (fifo_outstanding_data > 0) | |
366 | return 0; | |
367 | ||
368 | usleep_range(500, 510); | |
369 | } while (fifo_retry_count--); | |
370 | ||
371 | if (fifo_outstanding_data == 0) { | |
6f76e791 | 372 | dev_err_ratelimited(ctrl->dev, "%s err read underflow\n", __func__); |
a661308c SK |
373 | return -EIO; |
374 | } | |
375 | ||
376 | return 0; | |
377 | } | |
378 | ||
6f76e791 | 379 | static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *ctrl) |
a661308c SK |
380 | { |
381 | u32 fifo_outstanding_cmds, value; | |
382 | int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT; | |
383 | ||
384 | do { | |
385 | /* Check for fifo overflow during write */ | |
6378fe11 KK |
386 | ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], |
387 | &value); | |
a661308c SK |
388 | fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value); |
389 | ||
390 | /* Check for space in write fifo before writing */ | |
6f76e791 | 391 | if (fifo_outstanding_cmds < ctrl->wr_fifo_depth) |
a661308c SK |
392 | return 0; |
393 | ||
394 | usleep_range(500, 510); | |
395 | } while (fifo_retry_count--); | |
396 | ||
6f76e791 KK |
397 | if (fifo_outstanding_cmds == ctrl->wr_fifo_depth) { |
398 | dev_err_ratelimited(ctrl->dev, "%s err write overflow\n", __func__); | |
a661308c SK |
399 | return -EIO; |
400 | } | |
401 | ||
402 | return 0; | |
403 | } | |
ddea6cf7 | 404 | |
9ac4a444 SK |
405 | static bool swrm_wait_for_wr_fifo_done(struct qcom_swrm_ctrl *ctrl) |
406 | { | |
407 | u32 fifo_outstanding_cmds, value; | |
408 | int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT; | |
409 | ||
410 | /* Check for fifo overflow during write */ | |
411 | ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value); | |
412 | fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value); | |
413 | ||
414 | if (fifo_outstanding_cmds) { | |
415 | while (fifo_retry_count) { | |
416 | usleep_range(500, 510); | |
417 | ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value); | |
418 | fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value); | |
419 | fifo_retry_count--; | |
420 | if (fifo_outstanding_cmds == 0) | |
421 | return true; | |
422 | } | |
423 | } else { | |
424 | return true; | |
425 | } | |
426 | ||
427 | ||
428 | return false; | |
429 | } | |
430 | ||
6f76e791 | 431 | static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data, |
ddea6cf7 | 432 | u8 dev_addr, u16 reg_addr) |
02efb49a | 433 | { |
02efb49a | 434 | |
ddea6cf7 SK |
435 | u32 val; |
436 | int ret = 0; | |
437 | u8 cmd_id = 0x0; | |
02efb49a | 438 | |
ddea6cf7 SK |
439 | if (dev_addr == SDW_BROADCAST_DEV_NUM) { |
440 | cmd_id = SWR_BROADCAST_CMD_ID; | |
441 | val = swrm_get_packed_reg_val(&cmd_id, cmd_data, | |
442 | dev_addr, reg_addr); | |
443 | } else { | |
6f76e791 | 444 | val = swrm_get_packed_reg_val(&ctrl->wcmd_id, cmd_data, |
ddea6cf7 SK |
445 | dev_addr, reg_addr); |
446 | } | |
02efb49a | 447 | |
6f76e791 | 448 | if (swrm_wait_for_wr_fifo_avail(ctrl)) |
a661308c SK |
449 | return SDW_CMD_FAIL_OTHER; |
450 | ||
f936fa7a | 451 | if (cmd_id == SWR_BROADCAST_CMD_ID) |
6f76e791 | 452 | reinit_completion(&ctrl->broadcast); |
f936fa7a | 453 | |
ddea6cf7 | 454 | /* Its assumed that write is okay as we do not get any status back */ |
6378fe11 | 455 | ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val); |
ddea6cf7 | 456 | |
6f76e791 | 457 | if (ctrl->version <= SWRM_VERSION_1_3_0) |
ddea6cf7 SK |
458 | usleep_range(150, 155); |
459 | ||
460 | if (cmd_id == SWR_BROADCAST_CMD_ID) { | |
9ac4a444 | 461 | swrm_wait_for_wr_fifo_done(ctrl); |
ddea6cf7 SK |
462 | /* |
463 | * sleep for 10ms for MSM soundwire variant to allow broadcast | |
464 | * command to complete. | |
465 | */ | |
6f76e791 | 466 | ret = wait_for_completion_timeout(&ctrl->broadcast, |
ddea6cf7 SK |
467 | msecs_to_jiffies(TIMEOUT_MS)); |
468 | if (!ret) | |
469 | ret = SDW_CMD_IGNORED; | |
470 | else | |
471 | ret = SDW_CMD_OK; | |
02efb49a | 472 | |
02efb49a SK |
473 | } else { |
474 | ret = SDW_CMD_OK; | |
475 | } | |
ddea6cf7 SK |
476 | return ret; |
477 | } | |
02efb49a | 478 | |
6f76e791 | 479 | static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl, |
ddea6cf7 SK |
480 | u8 dev_addr, u16 reg_addr, |
481 | u32 len, u8 *rval) | |
482 | { | |
483 | u32 cmd_data, cmd_id, val, retry_attempt = 0; | |
484 | ||
6f76e791 | 485 | val = swrm_get_packed_reg_val(&ctrl->rcmd_id, len, dev_addr, reg_addr); |
ddea6cf7 | 486 | |
49a46731 SK |
487 | /* |
488 | * Check for outstanding cmd wrt. write fifo depth to avoid | |
489 | * overflow as read will also increase write fifo cnt. | |
490 | */ | |
6f76e791 | 491 | swrm_wait_for_wr_fifo_avail(ctrl); |
49a46731 | 492 | |
ddea6cf7 SK |
493 | /* wait for FIFO RD to complete to avoid overflow */ |
494 | usleep_range(100, 105); | |
6378fe11 | 495 | ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val); |
ddea6cf7 SK |
496 | /* wait for FIFO RD CMD complete to avoid overflow */ |
497 | usleep_range(250, 255); | |
498 | ||
6f76e791 | 499 | if (swrm_wait_for_rd_fifo_avail(ctrl)) |
a661308c SK |
500 | return SDW_CMD_FAIL_OTHER; |
501 | ||
ddea6cf7 | 502 | do { |
6378fe11 KK |
503 | ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR], |
504 | &cmd_data); | |
ddea6cf7 SK |
505 | rval[0] = cmd_data & 0xFF; |
506 | cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data); | |
507 | ||
6f76e791 | 508 | if (cmd_id != ctrl->rcmd_id) { |
ddea6cf7 SK |
509 | if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) { |
510 | /* wait 500 us before retry on fifo read failure */ | |
511 | usleep_range(500, 505); | |
6f76e791 | 512 | ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, |
ddea6cf7 | 513 | SWRM_CMD_FIFO_FLUSH); |
6378fe11 KK |
514 | ctrl->reg_write(ctrl, |
515 | ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], | |
516 | val); | |
ddea6cf7 SK |
517 | } |
518 | retry_attempt++; | |
519 | } else { | |
520 | return SDW_CMD_OK; | |
521 | } | |
02efb49a | 522 | |
ddea6cf7 | 523 | } while (retry_attempt < MAX_FIFO_RD_RETRY); |
02efb49a | 524 | |
6f76e791 | 525 | dev_err(ctrl->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\ |
ddea6cf7 | 526 | dev_num: 0x%x, cmd_data: 0x%x\n", |
6f76e791 | 527 | reg_addr, ctrl->rcmd_id, dev_addr, cmd_data); |
ddea6cf7 SK |
528 | |
529 | return SDW_CMD_IGNORED; | |
02efb49a SK |
530 | } |
531 | ||
c7d49c76 SK |
532 | static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl) |
533 | { | |
534 | u32 val, status; | |
535 | int dev_num; | |
536 | ||
537 | ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); | |
538 | ||
ed8d07ac | 539 | for (dev_num = 1; dev_num <= SDW_MAX_DEVICES; dev_num++) { |
c7d49c76 SK |
540 | status = (val >> (dev_num * SWRM_MCP_SLV_STATUS_SZ)); |
541 | ||
542 | if ((status & SWRM_MCP_SLV_STATUS_MASK) == SDW_SLAVE_ALERT) { | |
f84d41b2 | 543 | ctrl->status[dev_num] = status & SWRM_MCP_SLV_STATUS_MASK; |
c7d49c76 SK |
544 | return dev_num; |
545 | } | |
546 | } | |
547 | ||
548 | return -EINVAL; | |
549 | } | |
550 | ||
02efb49a SK |
551 | static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl) |
552 | { | |
553 | u32 val; | |
554 | int i; | |
555 | ||
556 | ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); | |
a6e65819 | 557 | ctrl->slave_status = val; |
02efb49a | 558 | |
8039b6f3 | 559 | for (i = 1; i <= SDW_MAX_DEVICES; i++) { |
02efb49a SK |
560 | u32 s; |
561 | ||
562 | s = (val >> (i * 2)); | |
563 | s &= SWRM_MCP_SLV_STATUS_MASK; | |
564 | ctrl->status[i] = s; | |
565 | } | |
566 | } | |
567 | ||
a6e65819 SK |
568 | static void qcom_swrm_set_slave_dev_num(struct sdw_bus *bus, |
569 | struct sdw_slave *slave, int devnum) | |
570 | { | |
571 | struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); | |
572 | u32 status; | |
573 | ||
574 | ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status); | |
575 | status = (status >> (devnum * SWRM_MCP_SLV_STATUS_SZ)); | |
576 | status &= SWRM_MCP_SLV_STATUS_MASK; | |
577 | ||
578 | if (status == SDW_SLAVE_ATTACHED) { | |
579 | if (slave) | |
580 | slave->dev_num = devnum; | |
581 | mutex_lock(&bus->bus_lock); | |
582 | set_bit(devnum, bus->assigned); | |
583 | mutex_unlock(&bus->bus_lock); | |
584 | } | |
585 | } | |
586 | ||
587 | static int qcom_swrm_enumerate(struct sdw_bus *bus) | |
588 | { | |
589 | struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); | |
590 | struct sdw_slave *slave, *_s; | |
591 | struct sdw_slave_id id; | |
592 | u32 val1, val2; | |
593 | bool found; | |
594 | u64 addr; | |
595 | int i; | |
596 | char *buf1 = (char *)&val1, *buf2 = (char *)&val2; | |
597 | ||
598 | for (i = 1; i <= SDW_MAX_DEVICES; i++) { | |
aa1262ca SK |
599 | /* do not continue if the status is Not Present */ |
600 | if (!ctrl->status[i]) | |
601 | continue; | |
602 | ||
a6e65819 SK |
603 | /*SCP_Devid5 - Devid 4*/ |
604 | ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1); | |
605 | ||
606 | /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/ | |
607 | ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2); | |
608 | ||
609 | if (!val1 && !val2) | |
610 | break; | |
611 | ||
612 | addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) | | |
613 | ((u64)buf1[2] << 24) | ((u64)buf1[1] << 32) | | |
614 | ((u64)buf1[0] << 40); | |
615 | ||
616 | sdw_extract_slave_id(bus, addr, &id); | |
617 | found = false; | |
4830bfa2 | 618 | ctrl->clock_stop_not_supported = false; |
a6e65819 SK |
619 | /* Now compare with entries */ |
620 | list_for_each_entry_safe(slave, _s, &bus->slaves, node) { | |
621 | if (sdw_compare_devid(slave, id) == 0) { | |
622 | qcom_swrm_set_slave_dev_num(bus, slave, i); | |
4830bfa2 SK |
623 | if (slave->prop.clk_stop_mode1) |
624 | ctrl->clock_stop_not_supported = true; | |
625 | ||
a6e65819 SK |
626 | found = true; |
627 | break; | |
628 | } | |
629 | } | |
630 | ||
631 | if (!found) { | |
632 | qcom_swrm_set_slave_dev_num(bus, NULL, i); | |
633 | sdw_slave_add(bus, &id, NULL); | |
634 | } | |
635 | } | |
636 | ||
06dd9673 | 637 | complete(&ctrl->enumeration); |
a6e65819 SK |
638 | return 0; |
639 | } | |
640 | ||
04d46a7b SK |
641 | static irqreturn_t qcom_swrm_wake_irq_handler(int irq, void *dev_id) |
642 | { | |
6f76e791 | 643 | struct qcom_swrm_ctrl *ctrl = dev_id; |
04d46a7b SK |
644 | int ret; |
645 | ||
9f9914b1 | 646 | ret = pm_runtime_get_sync(ctrl->dev); |
04d46a7b | 647 | if (ret < 0 && ret != -EACCES) { |
6f76e791 | 648 | dev_err_ratelimited(ctrl->dev, |
9f9914b1 | 649 | "pm_runtime_get_sync failed in %s, ret %d\n", |
04d46a7b | 650 | __func__, ret); |
9f9914b1 | 651 | pm_runtime_put_noidle(ctrl->dev); |
f6ee6c84 | 652 | return ret; |
04d46a7b SK |
653 | } |
654 | ||
6f76e791 KK |
655 | if (ctrl->wake_irq > 0) { |
656 | if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq))) | |
657 | disable_irq_nosync(ctrl->wake_irq); | |
04d46a7b SK |
658 | } |
659 | ||
6f76e791 KK |
660 | pm_runtime_mark_last_busy(ctrl->dev); |
661 | pm_runtime_put_autosuspend(ctrl->dev); | |
04d46a7b SK |
662 | |
663 | return IRQ_HANDLED; | |
664 | } | |
665 | ||
02efb49a SK |
666 | static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) |
667 | { | |
6f76e791 | 668 | struct qcom_swrm_ctrl *ctrl = dev_id; |
a6e65819 | 669 | u32 value, intr_sts, intr_sts_masked, slave_status; |
c7d49c76 | 670 | u32 i; |
b26b4874 | 671 | int devnum; |
c7d49c76 | 672 | int ret = IRQ_HANDLED; |
6f76e791 | 673 | clk_prepare_enable(ctrl->hclk); |
02efb49a | 674 | |
6378fe11 KK |
675 | ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS], |
676 | &intr_sts); | |
6f76e791 | 677 | intr_sts_masked = intr_sts & ctrl->intr_mask; |
02efb49a | 678 | |
c7d49c76 SK |
679 | do { |
680 | for (i = 0; i < SWRM_INTERRUPT_MAX; i++) { | |
681 | value = intr_sts_masked & BIT(i); | |
682 | if (!value) | |
683 | continue; | |
684 | ||
685 | switch (value) { | |
686 | case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ: | |
6f76e791 | 687 | devnum = qcom_swrm_get_alert_slave_dev_num(ctrl); |
c7d49c76 | 688 | if (devnum < 0) { |
6f76e791 | 689 | dev_err_ratelimited(ctrl->dev, |
c7d49c76 SK |
690 | "no slave alert found.spurious interrupt\n"); |
691 | } else { | |
6f76e791 | 692 | sdw_handle_slave_status(&ctrl->bus, ctrl->status); |
c7d49c76 SK |
693 | } |
694 | ||
695 | break; | |
696 | case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED: | |
697 | case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS: | |
6f76e791 KK |
698 | dev_dbg_ratelimited(ctrl->dev, "SWR new slave attached\n"); |
699 | ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &slave_status); | |
700 | if (ctrl->slave_status == slave_status) { | |
701 | dev_dbg(ctrl->dev, "Slave status not changed %x\n", | |
a6e65819 SK |
702 | slave_status); |
703 | } else { | |
6f76e791 KK |
704 | qcom_swrm_get_device_status(ctrl); |
705 | qcom_swrm_enumerate(&ctrl->bus); | |
706 | sdw_handle_slave_status(&ctrl->bus, ctrl->status); | |
a6e65819 | 707 | } |
c7d49c76 SK |
708 | break; |
709 | case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET: | |
6f76e791 | 710 | dev_err_ratelimited(ctrl->dev, |
c7d49c76 SK |
711 | "%s: SWR bus clsh detected\n", |
712 | __func__); | |
6f76e791 | 713 | ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; |
6378fe11 KK |
714 | ctrl->reg_write(ctrl, |
715 | ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], | |
716 | ctrl->intr_mask); | |
c7d49c76 SK |
717 | break; |
718 | case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW: | |
6378fe11 KK |
719 | ctrl->reg_read(ctrl, |
720 | ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], | |
721 | &value); | |
6f76e791 | 722 | dev_err_ratelimited(ctrl->dev, |
c7d49c76 SK |
723 | "%s: SWR read FIFO overflow fifo status 0x%x\n", |
724 | __func__, value); | |
725 | break; | |
726 | case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW: | |
6378fe11 KK |
727 | ctrl->reg_read(ctrl, |
728 | ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], | |
729 | &value); | |
6f76e791 | 730 | dev_err_ratelimited(ctrl->dev, |
c7d49c76 SK |
731 | "%s: SWR read FIFO underflow fifo status 0x%x\n", |
732 | __func__, value); | |
733 | break; | |
734 | case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW: | |
6378fe11 KK |
735 | ctrl->reg_read(ctrl, |
736 | ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], | |
737 | &value); | |
6f76e791 | 738 | dev_err(ctrl->dev, |
c7d49c76 SK |
739 | "%s: SWR write FIFO overflow fifo status %x\n", |
740 | __func__, value); | |
6f76e791 | 741 | ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); |
c7d49c76 SK |
742 | break; |
743 | case SWRM_INTERRUPT_STATUS_CMD_ERROR: | |
6378fe11 KK |
744 | ctrl->reg_read(ctrl, |
745 | ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], | |
746 | &value); | |
6f76e791 | 747 | dev_err_ratelimited(ctrl->dev, |
c7d49c76 SK |
748 | "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n", |
749 | __func__, value); | |
6f76e791 | 750 | ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); |
c7d49c76 SK |
751 | break; |
752 | case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION: | |
6f76e791 | 753 | dev_err_ratelimited(ctrl->dev, |
c7d49c76 SK |
754 | "%s: SWR Port collision detected\n", |
755 | __func__); | |
6f76e791 KK |
756 | ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION; |
757 | ctrl->reg_write(ctrl, | |
6378fe11 KK |
758 | ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], |
759 | ctrl->intr_mask); | |
c7d49c76 SK |
760 | break; |
761 | case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH: | |
6f76e791 | 762 | dev_err_ratelimited(ctrl->dev, |
c7d49c76 SK |
763 | "%s: SWR read enable valid mismatch\n", |
764 | __func__); | |
6f76e791 | 765 | ctrl->intr_mask &= |
c7d49c76 | 766 | ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH; |
6f76e791 | 767 | ctrl->reg_write(ctrl, |
6378fe11 KK |
768 | ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], |
769 | ctrl->intr_mask); | |
c7d49c76 SK |
770 | break; |
771 | case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED: | |
6f76e791 | 772 | complete(&ctrl->broadcast); |
c7d49c76 SK |
773 | break; |
774 | case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2: | |
775 | break; | |
776 | case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2: | |
777 | break; | |
778 | case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP: | |
779 | break; | |
16d568c8 KK |
780 | case SWRM_INTERRUPT_STATUS_CMD_IGNORED_AND_EXEC_CONTINUED: |
781 | ctrl->reg_read(ctrl, | |
782 | ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], | |
783 | &value); | |
784 | dev_err(ctrl->dev, | |
785 | "%s: SWR CMD ignored, fifo status %x\n", | |
786 | __func__, value); | |
787 | ||
788 | /* Wait 3.5ms to clear */ | |
789 | usleep_range(3500, 3505); | |
790 | break; | |
c7d49c76 | 791 | default: |
6f76e791 | 792 | dev_err_ratelimited(ctrl->dev, |
c7d49c76 SK |
793 | "%s: SWR unknown interrupt value: %d\n", |
794 | __func__, value); | |
795 | ret = IRQ_NONE; | |
796 | break; | |
797 | } | |
798 | } | |
6378fe11 KK |
799 | ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], |
800 | intr_sts); | |
801 | ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS], | |
802 | &intr_sts); | |
6f76e791 | 803 | intr_sts_masked = intr_sts & ctrl->intr_mask; |
c7d49c76 | 804 | } while (intr_sts_masked); |
02efb49a | 805 | |
6f76e791 | 806 | clk_disable_unprepare(ctrl->hclk); |
c7d49c76 | 807 | return ret; |
02efb49a | 808 | } |
ddea6cf7 | 809 | |
671ca2ef SK |
810 | static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *ctrl) |
811 | { | |
812 | int retry = SWRM_LINK_STATUS_RETRY_CNT; | |
813 | int comp_sts; | |
814 | ||
815 | do { | |
5d78c7d6 KK |
816 | ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_FRAME_GEN_ENABLED], |
817 | &comp_sts); | |
671ca2ef SK |
818 | if (comp_sts & SWRM_FRM_GEN_ENABLED) |
819 | return true; | |
820 | ||
821 | usleep_range(500, 510); | |
822 | } while (retry--); | |
823 | ||
824 | dev_err(ctrl->dev, "%s: link status not %s\n", __func__, | |
825 | comp_sts & SWRM_FRM_GEN_ENABLED ? "connected" : "disconnected"); | |
826 | ||
827 | return false; | |
828 | } | |
829 | ||
02efb49a SK |
830 | static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl) |
831 | { | |
832 | u32 val; | |
833 | ||
834 | /* Clear Rows and Cols */ | |
8cb3b4e7 SK |
835 | val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index); |
836 | val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index); | |
02efb49a | 837 | |
33ba0178 SRM |
838 | reset_control_reset(ctrl->audio_cgcr); |
839 | ||
02efb49a SK |
840 | ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val); |
841 | ||
a6e65819 SK |
842 | /* Enable Auto enumeration */ |
843 | ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1); | |
02efb49a | 844 | |
c7d49c76 | 845 | ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK; |
02efb49a | 846 | /* Mask soundwire interrupts */ |
312355a6 KK |
847 | if (ctrl->version < SWRM_VERSION_2_0_0) |
848 | ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], | |
849 | SWRM_INTERRUPT_STATUS_RMSK); | |
02efb49a SK |
850 | |
851 | /* Configure No pings */ | |
852 | ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val); | |
578ddced | 853 | u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK); |
02efb49a SK |
854 | ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val); |
855 | ||
312355a6 | 856 | if (ctrl->version == SWRM_VERSION_1_7_0) { |
cf43cd33 SK |
857 | ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); |
858 | ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, | |
859 | SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU); | |
312355a6 KK |
860 | } else if (ctrl->version >= SWRM_VERSION_2_0_0) { |
861 | ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); | |
862 | ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL, | |
863 | SWRM_V2_0_CLK_CTRL_CLK_START); | |
cf43cd33 SK |
864 | } else { |
865 | ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); | |
866 | } | |
867 | ||
02efb49a | 868 | /* Configure number of retries of a read/write cmd */ |
208a03ee | 869 | if (ctrl->version >= SWRM_VERSION_1_5_1) { |
542d3491 SK |
870 | ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, |
871 | SWRM_RD_WR_CMD_RETRIES | | |
872 | SWRM_CONTINUE_EXEC_ON_CMD_IGNORE); | |
873 | } else { | |
874 | ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, | |
875 | SWRM_RD_WR_CMD_RETRIES); | |
876 | } | |
02efb49a | 877 | |
671ca2ef SK |
878 | /* COMP Enable */ |
879 | ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, SWRM_COMP_CFG_ENABLE_MSK); | |
880 | ||
02efb49a SK |
881 | /* Set IRQ to PULSE */ |
882 | ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, | |
671ca2ef SK |
883 | SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK); |
884 | ||
885 | ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], | |
886 | 0xFFFFFFFF); | |
82f5c70c JM |
887 | |
888 | /* enable CPU IRQs */ | |
889 | if (ctrl->mmio) { | |
6378fe11 | 890 | ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], |
82f5c70c JM |
891 | SWRM_INTERRUPT_STATUS_RMSK); |
892 | } | |
671ca2ef SK |
893 | |
894 | /* Set IRQ to PULSE */ | |
895 | ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, | |
896 | SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK | | |
897 | SWRM_COMP_CFG_ENABLE_MSK); | |
898 | ||
899 | swrm_wait_for_frame_gen_enabled(ctrl); | |
a6e65819 | 900 | ctrl->slave_status = 0; |
a661308c SK |
901 | ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); |
902 | ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val); | |
903 | ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val); | |
904 | ||
02efb49a SK |
905 | return 0; |
906 | } | |
907 | ||
ce5e811e KK |
908 | static int qcom_swrm_read_prop(struct sdw_bus *bus) |
909 | { | |
910 | struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); | |
911 | ||
912 | if (ctrl->version >= SWRM_VERSION_2_0_0) { | |
913 | bus->multi_link = true; | |
914 | bus->hw_sync_min_links = 3; | |
915 | } | |
916 | ||
917 | return 0; | |
918 | } | |
919 | ||
02efb49a SK |
920 | static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus, |
921 | struct sdw_msg *msg) | |
922 | { | |
923 | struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); | |
924 | int ret, i, len; | |
925 | ||
926 | if (msg->flags == SDW_MSG_FLAG_READ) { | |
927 | for (i = 0; i < msg->len;) { | |
928 | if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN) | |
929 | len = msg->len - i; | |
930 | else | |
931 | len = QCOM_SWRM_MAX_RD_LEN; | |
932 | ||
933 | ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num, | |
934 | msg->addr + i, len, | |
935 | &msg->buf[i]); | |
936 | if (ret) | |
937 | return ret; | |
938 | ||
939 | i = i + len; | |
940 | } | |
941 | } else if (msg->flags == SDW_MSG_FLAG_WRITE) { | |
942 | for (i = 0; i < msg->len; i++) { | |
943 | ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i], | |
944 | msg->dev_num, | |
945 | msg->addr + i); | |
946 | if (ret) | |
947 | return SDW_CMD_IGNORED; | |
948 | } | |
949 | } | |
950 | ||
951 | return SDW_CMD_OK; | |
952 | } | |
953 | ||
954 | static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus) | |
955 | { | |
956 | u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank); | |
957 | struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); | |
958 | u32 val; | |
959 | ||
960 | ctrl->reg_read(ctrl, reg, &val); | |
961 | ||
8cb3b4e7 SK |
962 | u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK); |
963 | u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK); | |
02efb49a SK |
964 | |
965 | return ctrl->reg_write(ctrl, reg, val); | |
966 | } | |
967 | ||
968 | static int qcom_swrm_port_params(struct sdw_bus *bus, | |
969 | struct sdw_port_params *p_params, | |
970 | unsigned int bank) | |
971 | { | |
128eaf93 SK |
972 | struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); |
973 | ||
974 | return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num), | |
975 | p_params->bps - 1); | |
976 | ||
02efb49a SK |
977 | } |
978 | ||
979 | static int qcom_swrm_transport_params(struct sdw_bus *bus, | |
980 | struct sdw_transport_params *params, | |
981 | enum sdw_reg_bank bank) | |
982 | { | |
983 | struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); | |
128eaf93 | 984 | struct qcom_swrm_port_config *pcfg; |
02efb49a | 985 | u32 value; |
5ffba1fb SK |
986 | int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank); |
987 | int ret; | |
02efb49a | 988 | |
9916c02c | 989 | pcfg = &ctrl->pconfig[params->port_num]; |
128eaf93 SK |
990 | |
991 | value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT; | |
992 | value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT; | |
a8dffaa0 | 993 | value |= pcfg->si & 0xff; |
02efb49a | 994 | |
5ffba1fb | 995 | ret = ctrl->reg_write(ctrl, reg, value); |
e729e0fd SK |
996 | if (ret) |
997 | goto err; | |
5ffba1fb | 998 | |
a8dffaa0 KK |
999 | if (pcfg->si > 0xff) { |
1000 | value = (pcfg->si >> 8) & 0xff; | |
1001 | reg = SWRM_DP_SAMPLECTRL2_BANK(params->port_num, bank); | |
1002 | ret = ctrl->reg_write(ctrl, reg, value); | |
1003 | if (ret) | |
1004 | goto err; | |
1005 | } | |
1006 | ||
128eaf93 SK |
1007 | if (pcfg->lane_control != SWR_INVALID_PARAM) { |
1008 | reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank); | |
1009 | value = pcfg->lane_control; | |
1010 | ret = ctrl->reg_write(ctrl, reg, value); | |
e729e0fd SK |
1011 | if (ret) |
1012 | goto err; | |
128eaf93 | 1013 | } |
5ffba1fb | 1014 | |
128eaf93 SK |
1015 | if (pcfg->blk_group_count != SWR_INVALID_PARAM) { |
1016 | reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank); | |
1017 | value = pcfg->blk_group_count; | |
1018 | ret = ctrl->reg_write(ctrl, reg, value); | |
e729e0fd SK |
1019 | if (ret) |
1020 | goto err; | |
128eaf93 SK |
1021 | } |
1022 | ||
1023 | if (pcfg->hstart != SWR_INVALID_PARAM | |
1024 | && pcfg->hstop != SWR_INVALID_PARAM) { | |
1025 | reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank); | |
1026 | value = (pcfg->hstop << 4) | pcfg->hstart; | |
1027 | ret = ctrl->reg_write(ctrl, reg, value); | |
1028 | } else { | |
1029 | reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank); | |
1030 | value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL; | |
1031 | ret = ctrl->reg_write(ctrl, reg, value); | |
1032 | } | |
1033 | ||
e729e0fd SK |
1034 | if (ret) |
1035 | goto err; | |
1036 | ||
128eaf93 SK |
1037 | if (pcfg->bp_mode != SWR_INVALID_PARAM) { |
1038 | reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank); | |
1039 | ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode); | |
5ffba1fb SK |
1040 | } |
1041 | ||
e729e0fd | 1042 | err: |
5ffba1fb | 1043 | return ret; |
02efb49a SK |
1044 | } |
1045 | ||
1046 | static int qcom_swrm_port_enable(struct sdw_bus *bus, | |
1047 | struct sdw_enable_ch *enable_ch, | |
1048 | unsigned int bank) | |
1049 | { | |
1050 | u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank); | |
1051 | struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); | |
1052 | u32 val; | |
1053 | ||
1054 | ctrl->reg_read(ctrl, reg, &val); | |
1055 | ||
1056 | if (enable_ch->enable) | |
1057 | val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT); | |
1058 | else | |
1059 | val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT); | |
1060 | ||
1061 | return ctrl->reg_write(ctrl, reg, val); | |
1062 | } | |
1063 | ||
51fe3881 | 1064 | static const struct sdw_master_port_ops qcom_swrm_port_ops = { |
02efb49a SK |
1065 | .dpn_set_port_params = qcom_swrm_port_params, |
1066 | .dpn_set_port_transport_params = qcom_swrm_transport_params, | |
1067 | .dpn_port_enable_ch = qcom_swrm_port_enable, | |
1068 | }; | |
1069 | ||
51fe3881 | 1070 | static const struct sdw_master_ops qcom_swrm_ops = { |
ce5e811e | 1071 | .read_prop = qcom_swrm_read_prop, |
02efb49a SK |
1072 | .xfer_msg = qcom_swrm_xfer_msg, |
1073 | .pre_bank_switch = qcom_swrm_pre_bank_switch, | |
1074 | }; | |
1075 | ||
1076 | static int qcom_swrm_compute_params(struct sdw_bus *bus) | |
1077 | { | |
1078 | struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); | |
1079 | struct sdw_master_runtime *m_rt; | |
1080 | struct sdw_slave_runtime *s_rt; | |
1081 | struct sdw_port_runtime *p_rt; | |
1082 | struct qcom_swrm_port_config *pcfg; | |
eb5a9094 SK |
1083 | struct sdw_slave *slave; |
1084 | unsigned int m_port; | |
9916c02c | 1085 | int i = 1; |
02efb49a SK |
1086 | |
1087 | list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) { | |
1088 | list_for_each_entry(p_rt, &m_rt->port_list, port_node) { | |
9916c02c | 1089 | pcfg = &ctrl->pconfig[p_rt->num]; |
02efb49a | 1090 | p_rt->transport_params.port_num = p_rt->num; |
128eaf93 SK |
1091 | if (pcfg->word_length != SWR_INVALID_PARAM) { |
1092 | sdw_fill_port_params(&p_rt->port_params, | |
1093 | p_rt->num, pcfg->word_length + 1, | |
1094 | SDW_PORT_FLOW_MODE_ISOCH, | |
1095 | SDW_PORT_DATA_MODE_NORMAL); | |
1096 | } | |
1097 | ||
02efb49a SK |
1098 | } |
1099 | ||
1100 | list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { | |
eb5a9094 | 1101 | slave = s_rt->slave; |
02efb49a | 1102 | list_for_each_entry(p_rt, &s_rt->port_list, port_node) { |
eb5a9094 SK |
1103 | m_port = slave->m_port_map[p_rt->num]; |
1104 | /* port config starts at offset 0 so -1 from actual port number */ | |
1105 | if (m_port) | |
9916c02c | 1106 | pcfg = &ctrl->pconfig[m_port]; |
eb5a9094 SK |
1107 | else |
1108 | pcfg = &ctrl->pconfig[i]; | |
02efb49a SK |
1109 | p_rt->transport_params.port_num = p_rt->num; |
1110 | p_rt->transport_params.sample_interval = | |
1111 | pcfg->si + 1; | |
1112 | p_rt->transport_params.offset1 = pcfg->off1; | |
1113 | p_rt->transport_params.offset2 = pcfg->off2; | |
5ffba1fb | 1114 | p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode; |
128eaf93 SK |
1115 | p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count; |
1116 | ||
1117 | p_rt->transport_params.hstart = pcfg->hstart; | |
1118 | p_rt->transport_params.hstop = pcfg->hstop; | |
1119 | p_rt->transport_params.lane_ctrl = pcfg->lane_control; | |
1120 | if (pcfg->word_length != SWR_INVALID_PARAM) { | |
1121 | sdw_fill_port_params(&p_rt->port_params, | |
1122 | p_rt->num, | |
1123 | pcfg->word_length + 1, | |
1124 | SDW_PORT_FLOW_MODE_ISOCH, | |
1125 | SDW_PORT_DATA_MODE_NORMAL); | |
1126 | } | |
02efb49a SK |
1127 | i++; |
1128 | } | |
1129 | } | |
1130 | } | |
1131 | ||
1132 | return 0; | |
1133 | } | |
1134 | ||
1135 | static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = { | |
1136 | DEFAULT_CLK_FREQ, | |
1137 | }; | |
1138 | ||
02efb49a SK |
1139 | static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl, |
1140 | struct sdw_stream_runtime *stream) | |
1141 | { | |
1142 | struct sdw_master_runtime *m_rt; | |
1143 | struct sdw_port_runtime *p_rt; | |
1144 | unsigned long *port_mask; | |
1145 | ||
1146 | mutex_lock(&ctrl->port_lock); | |
1147 | ||
1148 | list_for_each_entry(m_rt, &stream->master_list, stream_node) { | |
1149 | if (m_rt->direction == SDW_DATA_DIR_RX) | |
1150 | port_mask = &ctrl->dout_port_mask; | |
1151 | else | |
1152 | port_mask = &ctrl->din_port_mask; | |
1153 | ||
1154 | list_for_each_entry(p_rt, &m_rt->port_list, port_node) | |
650dfdb8 | 1155 | clear_bit(p_rt->num, port_mask); |
02efb49a SK |
1156 | } |
1157 | ||
1158 | mutex_unlock(&ctrl->port_lock); | |
1159 | } | |
1160 | ||
1161 | static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl, | |
1162 | struct sdw_stream_runtime *stream, | |
1163 | struct snd_pcm_hw_params *params, | |
1164 | int direction) | |
1165 | { | |
1166 | struct sdw_port_config pconfig[QCOM_SDW_MAX_PORTS]; | |
1167 | struct sdw_stream_config sconfig; | |
1168 | struct sdw_master_runtime *m_rt; | |
1169 | struct sdw_slave_runtime *s_rt; | |
1170 | struct sdw_port_runtime *p_rt; | |
eb5a9094 | 1171 | struct sdw_slave *slave; |
02efb49a | 1172 | unsigned long *port_mask; |
5c68b66d | 1173 | int maxport, pn, nports = 0, ret = 0; |
eb5a9094 | 1174 | unsigned int m_port; |
02efb49a | 1175 | |
5bdc61ef KK |
1176 | if (direction == SNDRV_PCM_STREAM_CAPTURE) |
1177 | sconfig.direction = SDW_DATA_DIR_TX; | |
1178 | else | |
1179 | sconfig.direction = SDW_DATA_DIR_RX; | |
1180 | ||
1181 | /* hw parameters wil be ignored as we only support PDM */ | |
1182 | sconfig.ch_count = 1; | |
1183 | sconfig.frame_rate = params_rate(params); | |
1184 | sconfig.type = stream->type; | |
1185 | sconfig.bps = 1; | |
1186 | ||
02efb49a SK |
1187 | mutex_lock(&ctrl->port_lock); |
1188 | list_for_each_entry(m_rt, &stream->master_list, stream_node) { | |
ce5e811e KK |
1189 | /* |
1190 | * For streams with multiple masters: | |
1191 | * Allocate ports only for devices connected to this master. | |
1192 | * Such devices will have ports allocated by their own master | |
1193 | * and its qcom_swrm_stream_alloc_ports() call. | |
1194 | */ | |
1195 | if (ctrl->bus.id != m_rt->bus->id) | |
1196 | continue; | |
1197 | ||
02efb49a SK |
1198 | if (m_rt->direction == SDW_DATA_DIR_RX) { |
1199 | maxport = ctrl->num_dout_ports; | |
1200 | port_mask = &ctrl->dout_port_mask; | |
1201 | } else { | |
1202 | maxport = ctrl->num_din_ports; | |
1203 | port_mask = &ctrl->din_port_mask; | |
1204 | } | |
1205 | ||
1206 | list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { | |
eb5a9094 | 1207 | slave = s_rt->slave; |
02efb49a | 1208 | list_for_each_entry(p_rt, &s_rt->port_list, port_node) { |
eb5a9094 | 1209 | m_port = slave->m_port_map[p_rt->num]; |
02efb49a | 1210 | /* Port numbers start from 1 - 14*/ |
eb5a9094 SK |
1211 | if (m_port) |
1212 | pn = m_port; | |
1213 | else | |
1214 | pn = find_first_zero_bit(port_mask, maxport); | |
1215 | ||
650dfdb8 | 1216 | if (pn > maxport) { |
02efb49a SK |
1217 | dev_err(ctrl->dev, "All ports busy\n"); |
1218 | ret = -EBUSY; | |
5c68b66d | 1219 | goto out; |
02efb49a SK |
1220 | } |
1221 | set_bit(pn, port_mask); | |
650dfdb8 | 1222 | pconfig[nports].num = pn; |
02efb49a SK |
1223 | pconfig[nports].ch_mask = p_rt->ch_mask; |
1224 | nports++; | |
1225 | } | |
1226 | } | |
1227 | } | |
1228 | ||
02efb49a SK |
1229 | sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig, |
1230 | nports, stream); | |
5c68b66d | 1231 | out: |
02efb49a SK |
1232 | mutex_unlock(&ctrl->port_lock); |
1233 | ||
1234 | return ret; | |
1235 | } | |
1236 | ||
1237 | static int qcom_swrm_hw_params(struct snd_pcm_substream *substream, | |
1238 | struct snd_pcm_hw_params *params, | |
1239 | struct snd_soc_dai *dai) | |
1240 | { | |
1241 | struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); | |
1242 | struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; | |
1243 | int ret; | |
1244 | ||
1245 | ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params, | |
1246 | substream->stream); | |
1247 | if (ret) | |
1248 | qcom_swrm_stream_free_ports(ctrl, sruntime); | |
1249 | ||
1250 | return ret; | |
1251 | } | |
1252 | ||
1253 | static int qcom_swrm_hw_free(struct snd_pcm_substream *substream, | |
1254 | struct snd_soc_dai *dai) | |
1255 | { | |
1256 | struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); | |
1257 | struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; | |
1258 | ||
1259 | qcom_swrm_stream_free_ports(ctrl, sruntime); | |
1260 | sdw_stream_remove_master(&ctrl->bus, sruntime); | |
1261 | ||
1262 | return 0; | |
1263 | } | |
1264 | ||
1265 | static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai, | |
1266 | void *stream, int direction) | |
1267 | { | |
1268 | struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); | |
1269 | ||
1270 | ctrl->sruntime[dai->id] = stream; | |
1271 | ||
1272 | return 0; | |
1273 | } | |
1274 | ||
39ec6f99 SK |
1275 | static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction) |
1276 | { | |
1277 | struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); | |
1278 | ||
1279 | return ctrl->sruntime[dai->id]; | |
1280 | } | |
1281 | ||
02efb49a SK |
1282 | static int qcom_swrm_startup(struct snd_pcm_substream *substream, |
1283 | struct snd_soc_dai *dai) | |
1284 | { | |
1285 | struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); | |
15c7fab0 | 1286 | int ret; |
02efb49a | 1287 | |
9f9914b1 | 1288 | ret = pm_runtime_get_sync(ctrl->dev); |
74e79da9 SK |
1289 | if (ret < 0 && ret != -EACCES) { |
1290 | dev_err_ratelimited(ctrl->dev, | |
9f9914b1 | 1291 | "pm_runtime_get_sync failed in %s, ret %d\n", |
74e79da9 | 1292 | __func__, ret); |
9f9914b1 | 1293 | pm_runtime_put_noidle(ctrl->dev); |
74e79da9 SK |
1294 | return ret; |
1295 | } | |
1296 | ||
02efb49a SK |
1297 | return 0; |
1298 | } | |
1299 | ||
1300 | static void qcom_swrm_shutdown(struct snd_pcm_substream *substream, | |
1301 | struct snd_soc_dai *dai) | |
1302 | { | |
1303 | struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); | |
1304 | ||
9ac4a444 | 1305 | swrm_wait_for_wr_fifo_done(ctrl); |
74e79da9 SK |
1306 | pm_runtime_mark_last_busy(ctrl->dev); |
1307 | pm_runtime_put_autosuspend(ctrl->dev); | |
1308 | ||
02efb49a SK |
1309 | } |
1310 | ||
1311 | static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = { | |
1312 | .hw_params = qcom_swrm_hw_params, | |
1313 | .hw_free = qcom_swrm_hw_free, | |
1314 | .startup = qcom_swrm_startup, | |
1315 | .shutdown = qcom_swrm_shutdown, | |
e8444560 PLB |
1316 | .set_stream = qcom_swrm_set_sdw_stream, |
1317 | .get_stream = qcom_swrm_get_sdw_stream, | |
02efb49a SK |
1318 | }; |
1319 | ||
1320 | static const struct snd_soc_component_driver qcom_swrm_dai_component = { | |
1321 | .name = "soundwire", | |
1322 | }; | |
1323 | ||
1324 | static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl) | |
1325 | { | |
1326 | int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports; | |
1327 | struct snd_soc_dai_driver *dais; | |
1328 | struct snd_soc_pcm_stream *stream; | |
1329 | struct device *dev = ctrl->dev; | |
1330 | int i; | |
1331 | ||
1332 | /* PDM dais are only tested for now */ | |
1333 | dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL); | |
1334 | if (!dais) | |
1335 | return -ENOMEM; | |
1336 | ||
1337 | for (i = 0; i < num_dais; i++) { | |
1338 | dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i); | |
1339 | if (!dais[i].name) | |
1340 | return -ENOMEM; | |
1341 | ||
1342 | if (i < ctrl->num_dout_ports) | |
1343 | stream = &dais[i].playback; | |
1344 | else | |
1345 | stream = &dais[i].capture; | |
1346 | ||
1347 | stream->channels_min = 1; | |
1348 | stream->channels_max = 1; | |
1349 | stream->rates = SNDRV_PCM_RATE_48000; | |
1350 | stream->formats = SNDRV_PCM_FMTBIT_S16_LE; | |
1351 | ||
1352 | dais[i].ops = &qcom_swrm_pdm_dai_ops; | |
1353 | dais[i].id = i; | |
1354 | } | |
1355 | ||
1356 | return devm_snd_soc_register_component(ctrl->dev, | |
1357 | &qcom_swrm_dai_component, | |
1358 | dais, num_dais); | |
1359 | } | |
1360 | ||
1361 | static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl) | |
1362 | { | |
1363 | struct device_node *np = ctrl->dev->of_node; | |
1364 | u8 off1[QCOM_SDW_MAX_PORTS]; | |
1365 | u8 off2[QCOM_SDW_MAX_PORTS]; | |
a8dffaa0 | 1366 | u16 si[QCOM_SDW_MAX_PORTS]; |
5ffba1fb | 1367 | u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, }; |
128eaf93 SK |
1368 | u8 hstart[QCOM_SDW_MAX_PORTS]; |
1369 | u8 hstop[QCOM_SDW_MAX_PORTS]; | |
1370 | u8 word_length[QCOM_SDW_MAX_PORTS]; | |
1371 | u8 blk_group_count[QCOM_SDW_MAX_PORTS]; | |
1372 | u8 lane_control[QCOM_SDW_MAX_PORTS]; | |
02efb49a | 1373 | int i, ret, nports, val; |
a8dffaa0 | 1374 | bool si_16 = false; |
02efb49a SK |
1375 | |
1376 | ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); | |
1377 | ||
9972b90a VK |
1378 | ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val); |
1379 | ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val); | |
02efb49a SK |
1380 | |
1381 | ret = of_property_read_u32(np, "qcom,din-ports", &val); | |
1382 | if (ret) | |
1383 | return ret; | |
1384 | ||
1385 | if (val > ctrl->num_din_ports) | |
1386 | return -EINVAL; | |
1387 | ||
1388 | ctrl->num_din_ports = val; | |
1389 | ||
1390 | ret = of_property_read_u32(np, "qcom,dout-ports", &val); | |
1391 | if (ret) | |
1392 | return ret; | |
1393 | ||
1394 | if (val > ctrl->num_dout_ports) | |
1395 | return -EINVAL; | |
1396 | ||
1397 | ctrl->num_dout_ports = val; | |
1398 | ||
1399 | nports = ctrl->num_dout_ports + ctrl->num_din_ports; | |
2367e0ec KK |
1400 | if (nports > QCOM_SDW_MAX_PORTS) |
1401 | return -EINVAL; | |
1402 | ||
650dfdb8 SK |
1403 | /* Valid port numbers are from 1-14, so mask out port 0 explicitly */ |
1404 | set_bit(0, &ctrl->dout_port_mask); | |
1405 | set_bit(0, &ctrl->din_port_mask); | |
02efb49a SK |
1406 | |
1407 | ret = of_property_read_u8_array(np, "qcom,ports-offset1", | |
1408 | off1, nports); | |
1409 | if (ret) | |
1410 | return ret; | |
1411 | ||
1412 | ret = of_property_read_u8_array(np, "qcom,ports-offset2", | |
1413 | off2, nports); | |
1414 | if (ret) | |
1415 | return ret; | |
1416 | ||
1417 | ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low", | |
a8dffaa0 KK |
1418 | (u8 *)si, nports); |
1419 | if (ret) { | |
1420 | ret = of_property_read_u16_array(np, "qcom,ports-sinterval", | |
1421 | si, nports); | |
1422 | if (ret) | |
1423 | return ret; | |
1424 | si_16 = true; | |
1425 | } | |
02efb49a | 1426 | |
5ffba1fb SK |
1427 | ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode", |
1428 | bp_mode, nports); | |
da096fbc | 1429 | if (ret) { |
208a03ee | 1430 | if (ctrl->version <= SWRM_VERSION_1_3_0) |
da096fbc SK |
1431 | memset(bp_mode, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); |
1432 | else | |
1433 | return ret; | |
1434 | } | |
a5943e4f | 1435 | |
128eaf93 SK |
1436 | memset(hstart, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); |
1437 | of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports); | |
1438 | ||
1439 | memset(hstop, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); | |
1440 | of_property_read_u8_array(np, "qcom,ports-hstop", hstop, nports); | |
1441 | ||
1442 | memset(word_length, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); | |
1443 | of_property_read_u8_array(np, "qcom,ports-word-length", word_length, nports); | |
1444 | ||
1445 | memset(blk_group_count, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); | |
1446 | of_property_read_u8_array(np, "qcom,ports-block-group-count", blk_group_count, nports); | |
1447 | ||
1448 | memset(lane_control, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); | |
1449 | of_property_read_u8_array(np, "qcom,ports-lane-control", lane_control, nports); | |
1450 | ||
02efb49a | 1451 | for (i = 0; i < nports; i++) { |
9916c02c | 1452 | /* Valid port number range is from 1-14 */ |
a8dffaa0 KK |
1453 | if (si_16) |
1454 | ctrl->pconfig[i + 1].si = si[i]; | |
1455 | else | |
1456 | ctrl->pconfig[i + 1].si = ((u8 *)si)[i]; | |
9916c02c SK |
1457 | ctrl->pconfig[i + 1].off1 = off1[i]; |
1458 | ctrl->pconfig[i + 1].off2 = off2[i]; | |
1459 | ctrl->pconfig[i + 1].bp_mode = bp_mode[i]; | |
1460 | ctrl->pconfig[i + 1].hstart = hstart[i]; | |
1461 | ctrl->pconfig[i + 1].hstop = hstop[i]; | |
1462 | ctrl->pconfig[i + 1].word_length = word_length[i]; | |
1463 | ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i]; | |
1464 | ctrl->pconfig[i + 1].lane_control = lane_control[i]; | |
02efb49a SK |
1465 | } |
1466 | ||
1467 | return 0; | |
1468 | } | |
1469 | ||
abd9a604 SK |
1470 | #ifdef CONFIG_DEBUG_FS |
1471 | static int swrm_reg_show(struct seq_file *s_file, void *data) | |
1472 | { | |
6f76e791 | 1473 | struct qcom_swrm_ctrl *ctrl = s_file->private; |
74e79da9 SK |
1474 | int reg, reg_val, ret; |
1475 | ||
9f9914b1 | 1476 | ret = pm_runtime_get_sync(ctrl->dev); |
74e79da9 | 1477 | if (ret < 0 && ret != -EACCES) { |
6f76e791 | 1478 | dev_err_ratelimited(ctrl->dev, |
9f9914b1 | 1479 | "pm_runtime_get_sync failed in %s, ret %d\n", |
74e79da9 | 1480 | __func__, ret); |
9f9914b1 | 1481 | pm_runtime_put_noidle(ctrl->dev); |
f6ee6c84 | 1482 | return ret; |
74e79da9 | 1483 | } |
abd9a604 | 1484 | |
6378fe11 | 1485 | for (reg = 0; reg <= ctrl->max_reg; reg += 4) { |
6f76e791 | 1486 | ctrl->reg_read(ctrl, reg, ®_val); |
abd9a604 SK |
1487 | seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val); |
1488 | } | |
6f76e791 KK |
1489 | pm_runtime_mark_last_busy(ctrl->dev); |
1490 | pm_runtime_put_autosuspend(ctrl->dev); | |
74e79da9 | 1491 | |
abd9a604 SK |
1492 | |
1493 | return 0; | |
1494 | } | |
1495 | DEFINE_SHOW_ATTRIBUTE(swrm_reg); | |
1496 | #endif | |
1497 | ||
02efb49a SK |
1498 | static int qcom_swrm_probe(struct platform_device *pdev) |
1499 | { | |
1500 | struct device *dev = &pdev->dev; | |
1501 | struct sdw_master_prop *prop; | |
1502 | struct sdw_bus_params *params; | |
1503 | struct qcom_swrm_ctrl *ctrl; | |
8cb3b4e7 | 1504 | const struct qcom_swrm_data *data; |
02efb49a SK |
1505 | int ret; |
1506 | u32 val; | |
1507 | ||
1508 | ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); | |
1509 | if (!ctrl) | |
1510 | return -ENOMEM; | |
1511 | ||
8cb3b4e7 | 1512 | data = of_device_get_match_data(dev); |
6378fe11 KK |
1513 | ctrl->max_reg = data->max_reg; |
1514 | ctrl->reg_layout = data->reg_layout; | |
8cb3b4e7 SK |
1515 | ctrl->rows_index = sdw_find_row_index(data->default_rows); |
1516 | ctrl->cols_index = sdw_find_col_index(data->default_cols); | |
47edc010 | 1517 | #if IS_REACHABLE(CONFIG_SLIMBUS) |
02efb49a | 1518 | if (dev->parent->bus == &slimbus_bus) { |
5bd77324 JM |
1519 | #else |
1520 | if (false) { | |
1521 | #endif | |
d1df23fe | 1522 | ctrl->reg_read = qcom_swrm_ahb_reg_read; |
02efb49a SK |
1523 | ctrl->reg_write = qcom_swrm_ahb_reg_write; |
1524 | ctrl->regmap = dev_get_regmap(dev->parent, NULL); | |
1525 | if (!ctrl->regmap) | |
1526 | return -EINVAL; | |
1527 | } else { | |
82f5c70c JM |
1528 | ctrl->reg_read = qcom_swrm_cpu_reg_read; |
1529 | ctrl->reg_write = qcom_swrm_cpu_reg_write; | |
1530 | ctrl->mmio = devm_platform_ioremap_resource(pdev, 0); | |
1531 | if (IS_ERR(ctrl->mmio)) | |
1532 | return PTR_ERR(ctrl->mmio); | |
02efb49a SK |
1533 | } |
1534 | ||
1fd0d85a | 1535 | if (data->sw_clk_gate_required) { |
1cdbfd4c SK |
1536 | ctrl->audio_cgcr = devm_reset_control_get_optional_exclusive(dev, "swr_audio_cgcr"); |
1537 | if (IS_ERR(ctrl->audio_cgcr)) { | |
1fd0d85a SRM |
1538 | dev_err(dev, "Failed to get cgcr reset ctrl required for SW gating\n"); |
1539 | ret = PTR_ERR(ctrl->audio_cgcr); | |
1540 | goto err_init; | |
1541 | } | |
1542 | } | |
1543 | ||
02efb49a | 1544 | ctrl->irq = of_irq_get(dev->of_node, 0); |
91b5cfc0 PLB |
1545 | if (ctrl->irq < 0) { |
1546 | ret = ctrl->irq; | |
1547 | goto err_init; | |
1548 | } | |
02efb49a SK |
1549 | |
1550 | ctrl->hclk = devm_clk_get(dev, "iface"); | |
91b5cfc0 | 1551 | if (IS_ERR(ctrl->hclk)) { |
95b0f3aa | 1552 | ret = dev_err_probe(dev, PTR_ERR(ctrl->hclk), "unable to get iface clock\n"); |
91b5cfc0 PLB |
1553 | goto err_init; |
1554 | } | |
02efb49a SK |
1555 | |
1556 | clk_prepare_enable(ctrl->hclk); | |
1557 | ||
1558 | ctrl->dev = dev; | |
1559 | dev_set_drvdata(&pdev->dev, ctrl); | |
02efb49a | 1560 | mutex_init(&ctrl->port_lock); |
ddea6cf7 | 1561 | init_completion(&ctrl->broadcast); |
06dd9673 | 1562 | init_completion(&ctrl->enumeration); |
02efb49a | 1563 | |
02efb49a SK |
1564 | ctrl->bus.ops = &qcom_swrm_ops; |
1565 | ctrl->bus.port_ops = &qcom_swrm_port_ops; | |
1566 | ctrl->bus.compute_params = &qcom_swrm_compute_params; | |
74e79da9 | 1567 | ctrl->bus.clk_stop_timeout = 300; |
02efb49a SK |
1568 | |
1569 | ret = qcom_swrm_get_port_config(ctrl); | |
1570 | if (ret) | |
91b5cfc0 | 1571 | goto err_clk; |
02efb49a SK |
1572 | |
1573 | params = &ctrl->bus.params; | |
1574 | params->max_dr_freq = DEFAULT_CLK_FREQ; | |
1575 | params->curr_dr_freq = DEFAULT_CLK_FREQ; | |
8cb3b4e7 SK |
1576 | params->col = data->default_cols; |
1577 | params->row = data->default_rows; | |
02efb49a SK |
1578 | ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val); |
1579 | params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK; | |
1580 | params->next_bank = !params->curr_bank; | |
1581 | ||
1582 | prop = &ctrl->bus.prop; | |
1583 | prop->max_clk_freq = DEFAULT_CLK_FREQ; | |
1584 | prop->num_clk_gears = 0; | |
1585 | prop->num_clk_freq = MAX_FREQ_NUM; | |
1586 | prop->clk_freq = &qcom_swrm_freq_tbl[0]; | |
8cb3b4e7 SK |
1587 | prop->default_col = data->default_cols; |
1588 | prop->default_row = data->default_rows; | |
02efb49a SK |
1589 | |
1590 | ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version); | |
1591 | ||
1592 | ret = devm_request_threaded_irq(dev, ctrl->irq, NULL, | |
1593 | qcom_swrm_irq_handler, | |
4f1738f4 SZ |
1594 | IRQF_TRIGGER_RISING | |
1595 | IRQF_ONESHOT, | |
02efb49a SK |
1596 | "soundwire", ctrl); |
1597 | if (ret) { | |
1598 | dev_err(dev, "Failed to request soundwire irq\n"); | |
91b5cfc0 | 1599 | goto err_clk; |
02efb49a SK |
1600 | } |
1601 | ||
04d46a7b SK |
1602 | ctrl->wake_irq = of_irq_get(dev->of_node, 1); |
1603 | if (ctrl->wake_irq > 0) { | |
1604 | ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL, | |
1605 | qcom_swrm_wake_irq_handler, | |
1606 | IRQF_TRIGGER_HIGH | IRQF_ONESHOT, | |
1607 | "swr_wake_irq", ctrl); | |
1608 | if (ret) { | |
1609 | dev_err(dev, "Failed to request soundwire wake irq\n"); | |
1610 | goto err_init; | |
1611 | } | |
1612 | } | |
1613 | ||
6543ac13 PLB |
1614 | ctrl->bus.controller_id = -1; |
1615 | ||
a7ae05ef SK |
1616 | if (ctrl->version > SWRM_VERSION_1_3_0) { |
1617 | ctrl->reg_read(ctrl, SWRM_COMP_MASTER_ID, &val); | |
1618 | ctrl->bus.controller_id = val; | |
1619 | } | |
1620 | ||
5cab3ff2 | 1621 | ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode); |
02efb49a SK |
1622 | if (ret) { |
1623 | dev_err(dev, "Failed to register Soundwire controller (%d)\n", | |
1624 | ret); | |
91b5cfc0 | 1625 | goto err_clk; |
02efb49a SK |
1626 | } |
1627 | ||
1628 | qcom_swrm_init(ctrl); | |
06dd9673 SK |
1629 | wait_for_completion_timeout(&ctrl->enumeration, |
1630 | msecs_to_jiffies(TIMEOUT_MS)); | |
02efb49a SK |
1631 | ret = qcom_swrm_register_dais(ctrl); |
1632 | if (ret) | |
91b5cfc0 | 1633 | goto err_master_add; |
02efb49a SK |
1634 | |
1635 | dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n", | |
1636 | (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff, | |
1637 | ctrl->version & 0xffff); | |
1638 | ||
74e79da9 SK |
1639 | pm_runtime_set_autosuspend_delay(dev, 3000); |
1640 | pm_runtime_use_autosuspend(dev); | |
1641 | pm_runtime_mark_last_busy(dev); | |
1642 | pm_runtime_set_active(dev); | |
1643 | pm_runtime_enable(dev); | |
1644 | ||
abd9a604 SK |
1645 | #ifdef CONFIG_DEBUG_FS |
1646 | ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs); | |
1647 | debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl, | |
1648 | &swrm_reg_fops); | |
1649 | #endif | |
1650 | ||
02efb49a | 1651 | return 0; |
91b5cfc0 PLB |
1652 | |
1653 | err_master_add: | |
5cab3ff2 | 1654 | sdw_bus_master_delete(&ctrl->bus); |
91b5cfc0 | 1655 | err_clk: |
02efb49a | 1656 | clk_disable_unprepare(ctrl->hclk); |
91b5cfc0 | 1657 | err_init: |
02efb49a SK |
1658 | return ret; |
1659 | } | |
1660 | ||
fe12bec5 | 1661 | static void qcom_swrm_remove(struct platform_device *pdev) |
02efb49a SK |
1662 | { |
1663 | struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev); | |
1664 | ||
5cab3ff2 | 1665 | sdw_bus_master_delete(&ctrl->bus); |
02efb49a | 1666 | clk_disable_unprepare(ctrl->hclk); |
02efb49a SK |
1667 | } |
1668 | ||
266fa946 | 1669 | static int __maybe_unused swrm_runtime_resume(struct device *dev) |
74e79da9 SK |
1670 | { |
1671 | struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev); | |
1672 | int ret; | |
1673 | ||
04d46a7b SK |
1674 | if (ctrl->wake_irq > 0) { |
1675 | if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq))) | |
1676 | disable_irq_nosync(ctrl->wake_irq); | |
1677 | } | |
1678 | ||
74e79da9 SK |
1679 | clk_prepare_enable(ctrl->hclk); |
1680 | ||
1681 | if (ctrl->clock_stop_not_supported) { | |
1682 | reinit_completion(&ctrl->enumeration); | |
1683 | ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01); | |
1684 | usleep_range(100, 105); | |
1685 | ||
1686 | qcom_swrm_init(ctrl); | |
1687 | ||
1688 | usleep_range(100, 105); | |
1689 | if (!swrm_wait_for_frame_gen_enabled(ctrl)) | |
1690 | dev_err(ctrl->dev, "link failed to connect\n"); | |
1691 | ||
1692 | /* wait for hw enumeration to complete */ | |
1693 | wait_for_completion_timeout(&ctrl->enumeration, | |
1694 | msecs_to_jiffies(TIMEOUT_MS)); | |
1695 | qcom_swrm_get_device_status(ctrl); | |
1696 | sdw_handle_slave_status(&ctrl->bus, ctrl->status); | |
1697 | } else { | |
33ba0178 SRM |
1698 | reset_control_reset(ctrl->audio_cgcr); |
1699 | ||
312355a6 | 1700 | if (ctrl->version == SWRM_VERSION_1_7_0) { |
cf43cd33 SK |
1701 | ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); |
1702 | ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, | |
1703 | SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU); | |
312355a6 KK |
1704 | } else if (ctrl->version >= SWRM_VERSION_2_0_0) { |
1705 | ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); | |
1706 | ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL, | |
1707 | SWRM_V2_0_CLK_CTRL_CLK_START); | |
cf43cd33 SK |
1708 | } else { |
1709 | ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); | |
1710 | } | |
6378fe11 | 1711 | ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], |
74e79da9 SK |
1712 | SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET); |
1713 | ||
1714 | ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; | |
312355a6 KK |
1715 | if (ctrl->version < SWRM_VERSION_2_0_0) |
1716 | ctrl->reg_write(ctrl, | |
1717 | ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], | |
1718 | ctrl->intr_mask); | |
6378fe11 KK |
1719 | ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], |
1720 | ctrl->intr_mask); | |
74e79da9 SK |
1721 | |
1722 | usleep_range(100, 105); | |
1723 | if (!swrm_wait_for_frame_gen_enabled(ctrl)) | |
1724 | dev_err(ctrl->dev, "link failed to connect\n"); | |
1725 | ||
1726 | ret = sdw_bus_exit_clk_stop(&ctrl->bus); | |
1727 | if (ret < 0) | |
1728 | dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret); | |
1729 | } | |
1730 | ||
1731 | return 0; | |
1732 | } | |
1733 | ||
1734 | static int __maybe_unused swrm_runtime_suspend(struct device *dev) | |
1735 | { | |
1736 | struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev); | |
1737 | int ret; | |
1738 | ||
9ac4a444 | 1739 | swrm_wait_for_wr_fifo_done(ctrl); |
74e79da9 SK |
1740 | if (!ctrl->clock_stop_not_supported) { |
1741 | /* Mask bus clash interrupt */ | |
1742 | ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; | |
312355a6 KK |
1743 | if (ctrl->version < SWRM_VERSION_2_0_0) |
1744 | ctrl->reg_write(ctrl, | |
1745 | ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], | |
1746 | ctrl->intr_mask); | |
6378fe11 KK |
1747 | ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], |
1748 | ctrl->intr_mask); | |
74e79da9 SK |
1749 | /* Prepare slaves for clock stop */ |
1750 | ret = sdw_bus_prep_clk_stop(&ctrl->bus); | |
1751 | if (ret < 0 && ret != -ENODATA) { | |
1752 | dev_err(dev, "prepare clock stop failed %d", ret); | |
1753 | return ret; | |
1754 | } | |
1755 | ||
1756 | ret = sdw_bus_clk_stop(&ctrl->bus); | |
1757 | if (ret < 0 && ret != -ENODATA) { | |
1758 | dev_err(dev, "bus clock stop failed %d", ret); | |
1759 | return ret; | |
1760 | } | |
1761 | } | |
1762 | ||
1763 | clk_disable_unprepare(ctrl->hclk); | |
1764 | ||
1765 | usleep_range(300, 305); | |
1766 | ||
04d46a7b SK |
1767 | if (ctrl->wake_irq > 0) { |
1768 | if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq))) | |
1769 | enable_irq(ctrl->wake_irq); | |
1770 | } | |
1771 | ||
74e79da9 SK |
1772 | return 0; |
1773 | } | |
1774 | ||
1775 | static const struct dev_pm_ops swrm_dev_pm_ops = { | |
1776 | SET_RUNTIME_PM_OPS(swrm_runtime_suspend, swrm_runtime_resume, NULL) | |
1777 | }; | |
1778 | ||
02efb49a | 1779 | static const struct of_device_id qcom_swrm_of_match[] = { |
8cb3b4e7 SK |
1780 | { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data }, |
1781 | { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data }, | |
3f4a7026 | 1782 | { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data }, |
cf43cd33 | 1783 | { .compatible = "qcom,soundwire-v1.7.0", .data = &swrm_v1_5_data }, |
312355a6 | 1784 | { .compatible = "qcom,soundwire-v2.0.0", .data = &swrm_v2_0_data }, |
02efb49a SK |
1785 | {/* sentinel */}, |
1786 | }; | |
1787 | ||
1788 | MODULE_DEVICE_TABLE(of, qcom_swrm_of_match); | |
1789 | ||
1790 | static struct platform_driver qcom_swrm_driver = { | |
1791 | .probe = &qcom_swrm_probe, | |
fe12bec5 | 1792 | .remove_new = qcom_swrm_remove, |
02efb49a SK |
1793 | .driver = { |
1794 | .name = "qcom-soundwire", | |
1795 | .of_match_table = qcom_swrm_of_match, | |
74e79da9 | 1796 | .pm = &swrm_dev_pm_ops, |
02efb49a SK |
1797 | } |
1798 | }; | |
1799 | module_platform_driver(qcom_swrm_driver); | |
1800 | ||
1801 | MODULE_DESCRIPTION("Qualcomm soundwire driver"); | |
1802 | MODULE_LICENSE("GPL v2"); |