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02efb49a SK |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // Copyright (c) 2019, Linaro Limited | |
3 | ||
4 | #include <linux/clk.h> | |
5 | #include <linux/completion.h> | |
6 | #include <linux/interrupt.h> | |
7 | #include <linux/io.h> | |
8 | #include <linux/kernel.h> | |
9 | #include <linux/module.h> | |
abd9a604 | 10 | #include <linux/debugfs.h> |
02efb49a SK |
11 | #include <linux/of.h> |
12 | #include <linux/of_irq.h> | |
13 | #include <linux/of_device.h> | |
74e79da9 | 14 | #include <linux/pm_runtime.h> |
02efb49a | 15 | #include <linux/regmap.h> |
33ba0178 | 16 | #include <linux/reset.h> |
02efb49a | 17 | #include <linux/slab.h> |
04d46a7b | 18 | #include <linux/pm_wakeirq.h> |
02efb49a SK |
19 | #include <linux/slimbus.h> |
20 | #include <linux/soundwire/sdw.h> | |
21 | #include <linux/soundwire/sdw_registers.h> | |
22 | #include <sound/pcm_params.h> | |
23 | #include <sound/soc.h> | |
24 | #include "bus.h" | |
25 | ||
74e79da9 SK |
26 | #define SWRM_COMP_SW_RESET 0x008 |
27 | #define SWRM_COMP_STATUS 0x014 | |
cf43cd33 SK |
28 | #define SWRM_LINK_MANAGER_EE 0x018 |
29 | #define SWRM_EE_CPU 1 | |
74e79da9 | 30 | #define SWRM_FRM_GEN_ENABLED BIT(0) |
208a03ee KK |
31 | #define SWRM_VERSION_1_3_0 0x01030000 |
32 | #define SWRM_VERSION_1_5_1 0x01050001 | |
33 | #define SWRM_VERSION_1_7_0 0x01070000 | |
02efb49a SK |
34 | #define SWRM_COMP_HW_VERSION 0x00 |
35 | #define SWRM_COMP_CFG_ADDR 0x04 | |
36 | #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK BIT(1) | |
37 | #define SWRM_COMP_CFG_ENABLE_MSK BIT(0) | |
38 | #define SWRM_COMP_PARAMS 0x100 | |
a661308c SK |
39 | #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH GENMASK(14, 10) |
40 | #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH GENMASK(19, 15) | |
02efb49a SK |
41 | #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0) |
42 | #define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5) | |
74e79da9 | 43 | #define SWRM_COMP_MASTER_ID 0x104 |
02efb49a SK |
44 | #define SWRM_INTERRUPT_STATUS 0x200 |
45 | #define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0) | |
c7d49c76 | 46 | #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ BIT(0) |
02efb49a SK |
47 | #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED BIT(1) |
48 | #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS BIT(2) | |
c7d49c76 SK |
49 | #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET BIT(3) |
50 | #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW BIT(4) | |
51 | #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW BIT(5) | |
52 | #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW BIT(6) | |
02efb49a | 53 | #define SWRM_INTERRUPT_STATUS_CMD_ERROR BIT(7) |
c7d49c76 SK |
54 | #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION BIT(8) |
55 | #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH BIT(9) | |
02efb49a | 56 | #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED BIT(10) |
c7d49c76 SK |
57 | #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2 BIT(13) |
58 | #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14) | |
59 | #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16) | |
60 | #define SWRM_INTERRUPT_MAX 17 | |
02efb49a SK |
61 | #define SWRM_INTERRUPT_MASK_ADDR 0x204 |
62 | #define SWRM_INTERRUPT_CLEAR 0x208 | |
82f5c70c | 63 | #define SWRM_INTERRUPT_CPU_EN 0x210 |
02efb49a SK |
64 | #define SWRM_CMD_FIFO_WR_CMD 0x300 |
65 | #define SWRM_CMD_FIFO_RD_CMD 0x304 | |
66 | #define SWRM_CMD_FIFO_CMD 0x308 | |
ddea6cf7 | 67 | #define SWRM_CMD_FIFO_FLUSH 0x1 |
02efb49a | 68 | #define SWRM_CMD_FIFO_STATUS 0x30C |
a661308c SK |
69 | #define SWRM_RD_CMD_FIFO_CNT_MASK GENMASK(20, 16) |
70 | #define SWRM_WR_CMD_FIFO_CNT_MASK GENMASK(12, 8) | |
02efb49a | 71 | #define SWRM_CMD_FIFO_CFG_ADDR 0x314 |
542d3491 | 72 | #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE BIT(31) |
02efb49a SK |
73 | #define SWRM_RD_WR_CMD_RETRIES 0x7 |
74 | #define SWRM_CMD_FIFO_RD_FIFO_ADDR 0x318 | |
ddea6cf7 | 75 | #define SWRM_RD_FIFO_CMD_ID_MASK GENMASK(11, 8) |
02efb49a | 76 | #define SWRM_ENUMERATOR_CFG_ADDR 0x500 |
a6e65819 SK |
77 | #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) (0x530 + 0x8 * (m)) |
78 | #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m) (0x534 + 0x8 * (m)) | |
02efb49a | 79 | #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m) (0x101C + 0x40 * (m)) |
02efb49a SK |
80 | #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK GENMASK(2, 0) |
81 | #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK GENMASK(7, 3) | |
a866a049 SK |
82 | #define SWRM_MCP_BUS_CTRL 0x1044 |
83 | #define SWRM_MCP_BUS_CLK_START BIT(1) | |
02efb49a SK |
84 | #define SWRM_MCP_CFG_ADDR 0x1048 |
85 | #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK GENMASK(21, 17) | |
02efb49a SK |
86 | #define SWRM_DEF_CMD_NO_PINGS 0x1f |
87 | #define SWRM_MCP_STATUS 0x104C | |
88 | #define SWRM_MCP_STATUS_BANK_NUM_MASK BIT(0) | |
89 | #define SWRM_MCP_SLV_STATUS 0x1090 | |
90 | #define SWRM_MCP_SLV_STATUS_MASK GENMASK(1, 0) | |
c7d49c76 | 91 | #define SWRM_MCP_SLV_STATUS_SZ 2 |
02efb49a | 92 | #define SWRM_DP_PORT_CTRL_BANK(n, m) (0x1124 + 0x100 * (n - 1) + 0x40 * m) |
128eaf93 SK |
93 | #define SWRM_DP_PORT_CTRL_2_BANK(n, m) (0x1128 + 0x100 * (n - 1) + 0x40 * m) |
94 | #define SWRM_DP_BLOCK_CTRL_1(n) (0x112C + 0x100 * (n - 1)) | |
95 | #define SWRM_DP_BLOCK_CTRL2_BANK(n, m) (0x1130 + 0x100 * (n - 1) + 0x40 * m) | |
96 | #define SWRM_DP_PORT_HCTRL_BANK(n, m) (0x1134 + 0x100 * (n - 1) + 0x40 * m) | |
5ffba1fb | 97 | #define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m) |
128eaf93 | 98 | #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1)) |
abd9a604 | 99 | #define SWR_MSTR_MAX_REG_ADDR (0x1740) |
128eaf93 | 100 | |
02efb49a SK |
101 | #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18 |
102 | #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10 | |
103 | #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT 0x08 | |
104 | #define SWRM_AHB_BRIDGE_WR_DATA_0 0xc85 | |
105 | #define SWRM_AHB_BRIDGE_WR_ADDR_0 0xc89 | |
106 | #define SWRM_AHB_BRIDGE_RD_ADDR_0 0xc8d | |
107 | #define SWRM_AHB_BRIDGE_RD_DATA_0 0xc91 | |
108 | ||
109 | #define SWRM_REG_VAL_PACK(data, dev, id, reg) \ | |
110 | ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24)) | |
111 | ||
02efb49a | 112 | #define MAX_FREQ_NUM 1 |
74da2724 | 113 | #define TIMEOUT_MS 100 |
ddea6cf7 | 114 | #define QCOM_SWRM_MAX_RD_LEN 0x1 |
02efb49a SK |
115 | #define QCOM_SDW_MAX_PORTS 14 |
116 | #define DEFAULT_CLK_FREQ 9600000 | |
117 | #define SWRM_MAX_DAIS 0xF | |
128eaf93 SK |
118 | #define SWR_INVALID_PARAM 0xFF |
119 | #define SWR_HSTOP_MAX_VAL 0xF | |
120 | #define SWR_HSTART_MIN_VAL 0x0 | |
ddea6cf7 SK |
121 | #define SWR_BROADCAST_CMD_ID 0x0F |
122 | #define SWR_MAX_CMD_ID 14 | |
123 | #define MAX_FIFO_RD_RETRY 3 | |
a661308c | 124 | #define SWR_OVERFLOW_RETRY_COUNT 30 |
74e79da9 SK |
125 | #define SWRM_LINK_STATUS_RETRY_CNT 100 |
126 | ||
127 | enum { | |
128 | MASTER_ID_WSA = 1, | |
129 | MASTER_ID_RX, | |
130 | MASTER_ID_TX | |
131 | }; | |
02efb49a SK |
132 | |
133 | struct qcom_swrm_port_config { | |
134 | u8 si; | |
135 | u8 off1; | |
136 | u8 off2; | |
5ffba1fb | 137 | u8 bp_mode; |
128eaf93 SK |
138 | u8 hstart; |
139 | u8 hstop; | |
140 | u8 word_length; | |
141 | u8 blk_group_count; | |
142 | u8 lane_control; | |
02efb49a SK |
143 | }; |
144 | ||
145 | struct qcom_swrm_ctrl { | |
146 | struct sdw_bus bus; | |
147 | struct device *dev; | |
148 | struct regmap *regmap; | |
82f5c70c | 149 | void __iomem *mmio; |
33ba0178 | 150 | struct reset_control *audio_cgcr; |
abd9a604 SK |
151 | #ifdef CONFIG_DEBUG_FS |
152 | struct dentry *debugfs; | |
153 | #endif | |
ddea6cf7 | 154 | struct completion broadcast; |
06dd9673 | 155 | struct completion enumeration; |
02efb49a | 156 | struct work_struct slave_work; |
02efb49a SK |
157 | /* Port alloc/free lock */ |
158 | struct mutex port_lock; | |
159 | struct clk *hclk; | |
160 | u8 wr_cmd_id; | |
161 | u8 rd_cmd_id; | |
162 | int irq; | |
163 | unsigned int version; | |
04d46a7b | 164 | int wake_irq; |
02efb49a SK |
165 | int num_din_ports; |
166 | int num_dout_ports; | |
8cb3b4e7 SK |
167 | int cols_index; |
168 | int rows_index; | |
02efb49a SK |
169 | unsigned long dout_port_mask; |
170 | unsigned long din_port_mask; | |
c7d49c76 | 171 | u32 intr_mask; |
ddea6cf7 SK |
172 | u8 rcmd_id; |
173 | u8 wcmd_id; | |
02efb49a SK |
174 | struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS]; |
175 | struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS]; | |
4ef3f2af | 176 | enum sdw_slave_status status[SDW_MAX_DEVICES + 1]; |
02efb49a SK |
177 | int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val); |
178 | int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val); | |
a6e65819 | 179 | u32 slave_status; |
a661308c SK |
180 | u32 wr_fifo_depth; |
181 | u32 rd_fifo_depth; | |
74e79da9 | 182 | bool clock_stop_not_supported; |
02efb49a SK |
183 | }; |
184 | ||
8cb3b4e7 SK |
185 | struct qcom_swrm_data { |
186 | u32 default_cols; | |
187 | u32 default_rows; | |
1fd0d85a | 188 | bool sw_clk_gate_required; |
8cb3b4e7 SK |
189 | }; |
190 | ||
35732a06 | 191 | static const struct qcom_swrm_data swrm_v1_3_data = { |
8cb3b4e7 SK |
192 | .default_rows = 48, |
193 | .default_cols = 16, | |
194 | }; | |
195 | ||
35732a06 | 196 | static const struct qcom_swrm_data swrm_v1_5_data = { |
8cb3b4e7 SK |
197 | .default_rows = 50, |
198 | .default_cols = 16, | |
199 | }; | |
200 | ||
3f4a7026 SRM |
201 | static const struct qcom_swrm_data swrm_v1_6_data = { |
202 | .default_rows = 50, | |
203 | .default_cols = 16, | |
204 | .sw_clk_gate_required = true, | |
205 | }; | |
206 | ||
02efb49a SK |
207 | #define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus) |
208 | ||
d1df23fe | 209 | static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, |
02efb49a SK |
210 | u32 *val) |
211 | { | |
212 | struct regmap *wcd_regmap = ctrl->regmap; | |
213 | int ret; | |
214 | ||
215 | /* pg register + offset */ | |
216 | ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0, | |
217 | (u8 *)®, 4); | |
218 | if (ret < 0) | |
219 | return SDW_CMD_FAIL; | |
220 | ||
221 | ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0, | |
222 | val, 4); | |
223 | if (ret < 0) | |
224 | return SDW_CMD_FAIL; | |
225 | ||
226 | return SDW_CMD_OK; | |
227 | } | |
228 | ||
229 | static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl, | |
230 | int reg, int val) | |
231 | { | |
232 | struct regmap *wcd_regmap = ctrl->regmap; | |
233 | int ret; | |
234 | /* pg register + offset */ | |
235 | ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0, | |
236 | (u8 *)&val, 4); | |
237 | if (ret) | |
238 | return SDW_CMD_FAIL; | |
239 | ||
240 | /* write address register */ | |
241 | ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0, | |
242 | (u8 *)®, 4); | |
243 | if (ret) | |
244 | return SDW_CMD_FAIL; | |
245 | ||
246 | return SDW_CMD_OK; | |
247 | } | |
248 | ||
82f5c70c JM |
249 | static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, |
250 | u32 *val) | |
251 | { | |
252 | *val = readl(ctrl->mmio + reg); | |
253 | return SDW_CMD_OK; | |
254 | } | |
255 | ||
256 | static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg, | |
257 | int val) | |
258 | { | |
259 | writel(val, ctrl->mmio + reg); | |
260 | return SDW_CMD_OK; | |
261 | } | |
262 | ||
ddea6cf7 SK |
263 | static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data, |
264 | u8 dev_addr, u16 reg_addr) | |
02efb49a | 265 | { |
02efb49a | 266 | u32 val; |
ddea6cf7 | 267 | u8 id = *cmd_id; |
02efb49a | 268 | |
ddea6cf7 SK |
269 | if (id != SWR_BROADCAST_CMD_ID) { |
270 | if (id < SWR_MAX_CMD_ID) | |
271 | id += 1; | |
272 | else | |
273 | id = 0; | |
274 | *cmd_id = id; | |
275 | } | |
276 | val = SWRM_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr); | |
02efb49a | 277 | |
ddea6cf7 | 278 | return val; |
02efb49a SK |
279 | } |
280 | ||
a661308c SK |
281 | static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *swrm) |
282 | { | |
283 | u32 fifo_outstanding_data, value; | |
284 | int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT; | |
285 | ||
286 | do { | |
287 | /* Check for fifo underflow during read */ | |
288 | swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); | |
289 | fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value); | |
290 | ||
291 | /* Check if read data is available in read fifo */ | |
292 | if (fifo_outstanding_data > 0) | |
293 | return 0; | |
294 | ||
295 | usleep_range(500, 510); | |
296 | } while (fifo_retry_count--); | |
297 | ||
298 | if (fifo_outstanding_data == 0) { | |
299 | dev_err_ratelimited(swrm->dev, "%s err read underflow\n", __func__); | |
300 | return -EIO; | |
301 | } | |
302 | ||
303 | return 0; | |
304 | } | |
305 | ||
306 | static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *swrm) | |
307 | { | |
308 | u32 fifo_outstanding_cmds, value; | |
309 | int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT; | |
310 | ||
311 | do { | |
312 | /* Check for fifo overflow during write */ | |
313 | swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); | |
314 | fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value); | |
315 | ||
316 | /* Check for space in write fifo before writing */ | |
317 | if (fifo_outstanding_cmds < swrm->wr_fifo_depth) | |
318 | return 0; | |
319 | ||
320 | usleep_range(500, 510); | |
321 | } while (fifo_retry_count--); | |
322 | ||
323 | if (fifo_outstanding_cmds == swrm->wr_fifo_depth) { | |
324 | dev_err_ratelimited(swrm->dev, "%s err write overflow\n", __func__); | |
325 | return -EIO; | |
326 | } | |
327 | ||
328 | return 0; | |
329 | } | |
ddea6cf7 SK |
330 | |
331 | static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data, | |
332 | u8 dev_addr, u16 reg_addr) | |
02efb49a | 333 | { |
02efb49a | 334 | |
ddea6cf7 SK |
335 | u32 val; |
336 | int ret = 0; | |
337 | u8 cmd_id = 0x0; | |
02efb49a | 338 | |
ddea6cf7 SK |
339 | if (dev_addr == SDW_BROADCAST_DEV_NUM) { |
340 | cmd_id = SWR_BROADCAST_CMD_ID; | |
341 | val = swrm_get_packed_reg_val(&cmd_id, cmd_data, | |
342 | dev_addr, reg_addr); | |
343 | } else { | |
344 | val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data, | |
345 | dev_addr, reg_addr); | |
346 | } | |
02efb49a | 347 | |
a661308c SK |
348 | if (swrm_wait_for_wr_fifo_avail(swrm)) |
349 | return SDW_CMD_FAIL_OTHER; | |
350 | ||
f936fa7a SK |
351 | if (cmd_id == SWR_BROADCAST_CMD_ID) |
352 | reinit_completion(&swrm->broadcast); | |
353 | ||
ddea6cf7 SK |
354 | /* Its assumed that write is okay as we do not get any status back */ |
355 | swrm->reg_write(swrm, SWRM_CMD_FIFO_WR_CMD, val); | |
356 | ||
208a03ee | 357 | if (swrm->version <= SWRM_VERSION_1_3_0) |
ddea6cf7 SK |
358 | usleep_range(150, 155); |
359 | ||
360 | if (cmd_id == SWR_BROADCAST_CMD_ID) { | |
361 | /* | |
362 | * sleep for 10ms for MSM soundwire variant to allow broadcast | |
363 | * command to complete. | |
364 | */ | |
365 | ret = wait_for_completion_timeout(&swrm->broadcast, | |
366 | msecs_to_jiffies(TIMEOUT_MS)); | |
367 | if (!ret) | |
368 | ret = SDW_CMD_IGNORED; | |
369 | else | |
370 | ret = SDW_CMD_OK; | |
02efb49a | 371 | |
02efb49a SK |
372 | } else { |
373 | ret = SDW_CMD_OK; | |
374 | } | |
ddea6cf7 SK |
375 | return ret; |
376 | } | |
02efb49a | 377 | |
ddea6cf7 SK |
378 | static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *swrm, |
379 | u8 dev_addr, u16 reg_addr, | |
380 | u32 len, u8 *rval) | |
381 | { | |
382 | u32 cmd_data, cmd_id, val, retry_attempt = 0; | |
383 | ||
384 | val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr); | |
385 | ||
49a46731 SK |
386 | /* |
387 | * Check for outstanding cmd wrt. write fifo depth to avoid | |
388 | * overflow as read will also increase write fifo cnt. | |
389 | */ | |
390 | swrm_wait_for_wr_fifo_avail(swrm); | |
391 | ||
ddea6cf7 SK |
392 | /* wait for FIFO RD to complete to avoid overflow */ |
393 | usleep_range(100, 105); | |
394 | swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val); | |
395 | /* wait for FIFO RD CMD complete to avoid overflow */ | |
396 | usleep_range(250, 255); | |
397 | ||
a661308c SK |
398 | if (swrm_wait_for_rd_fifo_avail(swrm)) |
399 | return SDW_CMD_FAIL_OTHER; | |
400 | ||
ddea6cf7 SK |
401 | do { |
402 | swrm->reg_read(swrm, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data); | |
403 | rval[0] = cmd_data & 0xFF; | |
404 | cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data); | |
405 | ||
406 | if (cmd_id != swrm->rcmd_id) { | |
407 | if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) { | |
408 | /* wait 500 us before retry on fifo read failure */ | |
409 | usleep_range(500, 505); | |
410 | swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, | |
411 | SWRM_CMD_FIFO_FLUSH); | |
412 | swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val); | |
413 | } | |
414 | retry_attempt++; | |
415 | } else { | |
416 | return SDW_CMD_OK; | |
417 | } | |
02efb49a | 418 | |
ddea6cf7 | 419 | } while (retry_attempt < MAX_FIFO_RD_RETRY); |
02efb49a | 420 | |
ddea6cf7 SK |
421 | dev_err(swrm->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\ |
422 | dev_num: 0x%x, cmd_data: 0x%x\n", | |
423 | reg_addr, swrm->rcmd_id, dev_addr, cmd_data); | |
424 | ||
425 | return SDW_CMD_IGNORED; | |
02efb49a SK |
426 | } |
427 | ||
c7d49c76 SK |
428 | static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl) |
429 | { | |
430 | u32 val, status; | |
431 | int dev_num; | |
432 | ||
433 | ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); | |
434 | ||
ed8d07ac | 435 | for (dev_num = 1; dev_num <= SDW_MAX_DEVICES; dev_num++) { |
c7d49c76 SK |
436 | status = (val >> (dev_num * SWRM_MCP_SLV_STATUS_SZ)); |
437 | ||
438 | if ((status & SWRM_MCP_SLV_STATUS_MASK) == SDW_SLAVE_ALERT) { | |
439 | ctrl->status[dev_num] = status; | |
440 | return dev_num; | |
441 | } | |
442 | } | |
443 | ||
444 | return -EINVAL; | |
445 | } | |
446 | ||
02efb49a SK |
447 | static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl) |
448 | { | |
449 | u32 val; | |
450 | int i; | |
451 | ||
452 | ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); | |
a6e65819 | 453 | ctrl->slave_status = val; |
02efb49a | 454 | |
8039b6f3 | 455 | for (i = 1; i <= SDW_MAX_DEVICES; i++) { |
02efb49a SK |
456 | u32 s; |
457 | ||
458 | s = (val >> (i * 2)); | |
459 | s &= SWRM_MCP_SLV_STATUS_MASK; | |
460 | ctrl->status[i] = s; | |
461 | } | |
462 | } | |
463 | ||
a6e65819 SK |
464 | static void qcom_swrm_set_slave_dev_num(struct sdw_bus *bus, |
465 | struct sdw_slave *slave, int devnum) | |
466 | { | |
467 | struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); | |
468 | u32 status; | |
469 | ||
470 | ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status); | |
471 | status = (status >> (devnum * SWRM_MCP_SLV_STATUS_SZ)); | |
472 | status &= SWRM_MCP_SLV_STATUS_MASK; | |
473 | ||
474 | if (status == SDW_SLAVE_ATTACHED) { | |
475 | if (slave) | |
476 | slave->dev_num = devnum; | |
477 | mutex_lock(&bus->bus_lock); | |
478 | set_bit(devnum, bus->assigned); | |
479 | mutex_unlock(&bus->bus_lock); | |
480 | } | |
481 | } | |
482 | ||
483 | static int qcom_swrm_enumerate(struct sdw_bus *bus) | |
484 | { | |
485 | struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); | |
486 | struct sdw_slave *slave, *_s; | |
487 | struct sdw_slave_id id; | |
488 | u32 val1, val2; | |
489 | bool found; | |
490 | u64 addr; | |
491 | int i; | |
492 | char *buf1 = (char *)&val1, *buf2 = (char *)&val2; | |
493 | ||
494 | for (i = 1; i <= SDW_MAX_DEVICES; i++) { | |
aa1262ca SK |
495 | /* do not continue if the status is Not Present */ |
496 | if (!ctrl->status[i]) | |
497 | continue; | |
498 | ||
a6e65819 SK |
499 | /*SCP_Devid5 - Devid 4*/ |
500 | ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1); | |
501 | ||
502 | /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/ | |
503 | ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2); | |
504 | ||
505 | if (!val1 && !val2) | |
506 | break; | |
507 | ||
508 | addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) | | |
509 | ((u64)buf1[2] << 24) | ((u64)buf1[1] << 32) | | |
510 | ((u64)buf1[0] << 40); | |
511 | ||
512 | sdw_extract_slave_id(bus, addr, &id); | |
513 | found = false; | |
514 | /* Now compare with entries */ | |
515 | list_for_each_entry_safe(slave, _s, &bus->slaves, node) { | |
516 | if (sdw_compare_devid(slave, id) == 0) { | |
517 | qcom_swrm_set_slave_dev_num(bus, slave, i); | |
518 | found = true; | |
519 | break; | |
520 | } | |
521 | } | |
522 | ||
523 | if (!found) { | |
524 | qcom_swrm_set_slave_dev_num(bus, NULL, i); | |
525 | sdw_slave_add(bus, &id, NULL); | |
526 | } | |
527 | } | |
528 | ||
06dd9673 | 529 | complete(&ctrl->enumeration); |
a6e65819 SK |
530 | return 0; |
531 | } | |
532 | ||
04d46a7b SK |
533 | static irqreturn_t qcom_swrm_wake_irq_handler(int irq, void *dev_id) |
534 | { | |
535 | struct qcom_swrm_ctrl *swrm = dev_id; | |
536 | int ret; | |
537 | ||
57ed510b | 538 | ret = pm_runtime_resume_and_get(swrm->dev); |
04d46a7b SK |
539 | if (ret < 0 && ret != -EACCES) { |
540 | dev_err_ratelimited(swrm->dev, | |
57ed510b | 541 | "pm_runtime_resume_and_get failed in %s, ret %d\n", |
04d46a7b | 542 | __func__, ret); |
f6ee6c84 | 543 | return ret; |
04d46a7b SK |
544 | } |
545 | ||
546 | if (swrm->wake_irq > 0) { | |
547 | if (!irqd_irq_disabled(irq_get_irq_data(swrm->wake_irq))) | |
548 | disable_irq_nosync(swrm->wake_irq); | |
549 | } | |
550 | ||
551 | pm_runtime_mark_last_busy(swrm->dev); | |
552 | pm_runtime_put_autosuspend(swrm->dev); | |
553 | ||
554 | return IRQ_HANDLED; | |
555 | } | |
556 | ||
02efb49a SK |
557 | static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) |
558 | { | |
c7d49c76 | 559 | struct qcom_swrm_ctrl *swrm = dev_id; |
a6e65819 | 560 | u32 value, intr_sts, intr_sts_masked, slave_status; |
c7d49c76 | 561 | u32 i; |
b26b4874 | 562 | int devnum; |
c7d49c76 | 563 | int ret = IRQ_HANDLED; |
74e79da9 | 564 | clk_prepare_enable(swrm->hclk); |
02efb49a | 565 | |
c7d49c76 SK |
566 | swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts); |
567 | intr_sts_masked = intr_sts & swrm->intr_mask; | |
02efb49a | 568 | |
c7d49c76 SK |
569 | do { |
570 | for (i = 0; i < SWRM_INTERRUPT_MAX; i++) { | |
571 | value = intr_sts_masked & BIT(i); | |
572 | if (!value) | |
573 | continue; | |
574 | ||
575 | switch (value) { | |
576 | case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ: | |
577 | devnum = qcom_swrm_get_alert_slave_dev_num(swrm); | |
578 | if (devnum < 0) { | |
579 | dev_err_ratelimited(swrm->dev, | |
580 | "no slave alert found.spurious interrupt\n"); | |
581 | } else { | |
582 | sdw_handle_slave_status(&swrm->bus, swrm->status); | |
583 | } | |
584 | ||
585 | break; | |
586 | case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED: | |
587 | case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS: | |
ba8ec0f6 | 588 | dev_dbg_ratelimited(swrm->dev, "SWR new slave attached\n"); |
a6e65819 SK |
589 | swrm->reg_read(swrm, SWRM_MCP_SLV_STATUS, &slave_status); |
590 | if (swrm->slave_status == slave_status) { | |
ba8ec0f6 | 591 | dev_dbg(swrm->dev, "Slave status not changed %x\n", |
a6e65819 SK |
592 | slave_status); |
593 | } else { | |
594 | qcom_swrm_get_device_status(swrm); | |
595 | qcom_swrm_enumerate(&swrm->bus); | |
596 | sdw_handle_slave_status(&swrm->bus, swrm->status); | |
597 | } | |
c7d49c76 SK |
598 | break; |
599 | case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET: | |
600 | dev_err_ratelimited(swrm->dev, | |
601 | "%s: SWR bus clsh detected\n", | |
602 | __func__); | |
603 | swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; | |
604 | swrm->reg_write(swrm, SWRM_INTERRUPT_CPU_EN, swrm->intr_mask); | |
605 | break; | |
606 | case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW: | |
607 | swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); | |
608 | dev_err_ratelimited(swrm->dev, | |
609 | "%s: SWR read FIFO overflow fifo status 0x%x\n", | |
610 | __func__, value); | |
611 | break; | |
612 | case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW: | |
613 | swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); | |
614 | dev_err_ratelimited(swrm->dev, | |
615 | "%s: SWR read FIFO underflow fifo status 0x%x\n", | |
616 | __func__, value); | |
617 | break; | |
618 | case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW: | |
619 | swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); | |
620 | dev_err(swrm->dev, | |
621 | "%s: SWR write FIFO overflow fifo status %x\n", | |
622 | __func__, value); | |
623 | swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1); | |
624 | break; | |
625 | case SWRM_INTERRUPT_STATUS_CMD_ERROR: | |
626 | swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); | |
627 | dev_err_ratelimited(swrm->dev, | |
628 | "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n", | |
629 | __func__, value); | |
630 | swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1); | |
631 | break; | |
632 | case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION: | |
633 | dev_err_ratelimited(swrm->dev, | |
634 | "%s: SWR Port collision detected\n", | |
635 | __func__); | |
636 | swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION; | |
637 | swrm->reg_write(swrm, | |
638 | SWRM_INTERRUPT_CPU_EN, swrm->intr_mask); | |
639 | break; | |
640 | case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH: | |
641 | dev_err_ratelimited(swrm->dev, | |
642 | "%s: SWR read enable valid mismatch\n", | |
643 | __func__); | |
644 | swrm->intr_mask &= | |
645 | ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH; | |
646 | swrm->reg_write(swrm, | |
647 | SWRM_INTERRUPT_CPU_EN, swrm->intr_mask); | |
648 | break; | |
649 | case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED: | |
650 | complete(&swrm->broadcast); | |
651 | break; | |
652 | case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2: | |
653 | break; | |
654 | case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2: | |
655 | break; | |
656 | case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP: | |
657 | break; | |
658 | default: | |
659 | dev_err_ratelimited(swrm->dev, | |
660 | "%s: SWR unknown interrupt value: %d\n", | |
661 | __func__, value); | |
662 | ret = IRQ_NONE; | |
663 | break; | |
664 | } | |
665 | } | |
666 | swrm->reg_write(swrm, SWRM_INTERRUPT_CLEAR, intr_sts); | |
667 | swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts); | |
668 | intr_sts_masked = intr_sts & swrm->intr_mask; | |
669 | } while (intr_sts_masked); | |
02efb49a | 670 | |
74e79da9 | 671 | clk_disable_unprepare(swrm->hclk); |
c7d49c76 | 672 | return ret; |
02efb49a | 673 | } |
ddea6cf7 | 674 | |
02efb49a SK |
675 | static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl) |
676 | { | |
677 | u32 val; | |
678 | ||
679 | /* Clear Rows and Cols */ | |
8cb3b4e7 SK |
680 | val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index); |
681 | val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index); | |
02efb49a | 682 | |
33ba0178 SRM |
683 | reset_control_reset(ctrl->audio_cgcr); |
684 | ||
02efb49a SK |
685 | ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val); |
686 | ||
a6e65819 SK |
687 | /* Enable Auto enumeration */ |
688 | ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1); | |
02efb49a | 689 | |
c7d49c76 | 690 | ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK; |
02efb49a SK |
691 | /* Mask soundwire interrupts */ |
692 | ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, | |
693 | SWRM_INTERRUPT_STATUS_RMSK); | |
694 | ||
695 | /* Configure No pings */ | |
696 | ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val); | |
578ddced | 697 | u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK); |
02efb49a SK |
698 | ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val); |
699 | ||
208a03ee | 700 | if (ctrl->version >= SWRM_VERSION_1_7_0) { |
cf43cd33 SK |
701 | ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); |
702 | ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, | |
703 | SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU); | |
704 | } else { | |
705 | ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); | |
706 | } | |
707 | ||
02efb49a | 708 | /* Configure number of retries of a read/write cmd */ |
208a03ee | 709 | if (ctrl->version >= SWRM_VERSION_1_5_1) { |
542d3491 SK |
710 | ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, |
711 | SWRM_RD_WR_CMD_RETRIES | | |
712 | SWRM_CONTINUE_EXEC_ON_CMD_IGNORE); | |
713 | } else { | |
714 | ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, | |
715 | SWRM_RD_WR_CMD_RETRIES); | |
716 | } | |
02efb49a SK |
717 | |
718 | /* Set IRQ to PULSE */ | |
719 | ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, | |
720 | SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK | | |
721 | SWRM_COMP_CFG_ENABLE_MSK); | |
82f5c70c JM |
722 | |
723 | /* enable CPU IRQs */ | |
724 | if (ctrl->mmio) { | |
725 | ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, | |
726 | SWRM_INTERRUPT_STATUS_RMSK); | |
727 | } | |
a6e65819 | 728 | ctrl->slave_status = 0; |
a661308c SK |
729 | ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); |
730 | ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val); | |
731 | ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val); | |
732 | ||
02efb49a SK |
733 | return 0; |
734 | } | |
735 | ||
736 | static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus, | |
737 | struct sdw_msg *msg) | |
738 | { | |
739 | struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); | |
740 | int ret, i, len; | |
741 | ||
742 | if (msg->flags == SDW_MSG_FLAG_READ) { | |
743 | for (i = 0; i < msg->len;) { | |
744 | if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN) | |
745 | len = msg->len - i; | |
746 | else | |
747 | len = QCOM_SWRM_MAX_RD_LEN; | |
748 | ||
749 | ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num, | |
750 | msg->addr + i, len, | |
751 | &msg->buf[i]); | |
752 | if (ret) | |
753 | return ret; | |
754 | ||
755 | i = i + len; | |
756 | } | |
757 | } else if (msg->flags == SDW_MSG_FLAG_WRITE) { | |
758 | for (i = 0; i < msg->len; i++) { | |
759 | ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i], | |
760 | msg->dev_num, | |
761 | msg->addr + i); | |
762 | if (ret) | |
763 | return SDW_CMD_IGNORED; | |
764 | } | |
765 | } | |
766 | ||
767 | return SDW_CMD_OK; | |
768 | } | |
769 | ||
770 | static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus) | |
771 | { | |
772 | u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank); | |
773 | struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); | |
774 | u32 val; | |
775 | ||
776 | ctrl->reg_read(ctrl, reg, &val); | |
777 | ||
8cb3b4e7 SK |
778 | u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK); |
779 | u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK); | |
02efb49a SK |
780 | |
781 | return ctrl->reg_write(ctrl, reg, val); | |
782 | } | |
783 | ||
784 | static int qcom_swrm_port_params(struct sdw_bus *bus, | |
785 | struct sdw_port_params *p_params, | |
786 | unsigned int bank) | |
787 | { | |
128eaf93 SK |
788 | struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); |
789 | ||
790 | return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num), | |
791 | p_params->bps - 1); | |
792 | ||
02efb49a SK |
793 | } |
794 | ||
795 | static int qcom_swrm_transport_params(struct sdw_bus *bus, | |
796 | struct sdw_transport_params *params, | |
797 | enum sdw_reg_bank bank) | |
798 | { | |
799 | struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); | |
128eaf93 | 800 | struct qcom_swrm_port_config *pcfg; |
02efb49a | 801 | u32 value; |
5ffba1fb SK |
802 | int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank); |
803 | int ret; | |
02efb49a | 804 | |
9916c02c | 805 | pcfg = &ctrl->pconfig[params->port_num]; |
128eaf93 SK |
806 | |
807 | value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT; | |
808 | value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT; | |
809 | value |= pcfg->si; | |
02efb49a | 810 | |
5ffba1fb | 811 | ret = ctrl->reg_write(ctrl, reg, value); |
e729e0fd SK |
812 | if (ret) |
813 | goto err; | |
5ffba1fb | 814 | |
128eaf93 SK |
815 | if (pcfg->lane_control != SWR_INVALID_PARAM) { |
816 | reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank); | |
817 | value = pcfg->lane_control; | |
818 | ret = ctrl->reg_write(ctrl, reg, value); | |
e729e0fd SK |
819 | if (ret) |
820 | goto err; | |
128eaf93 | 821 | } |
5ffba1fb | 822 | |
128eaf93 SK |
823 | if (pcfg->blk_group_count != SWR_INVALID_PARAM) { |
824 | reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank); | |
825 | value = pcfg->blk_group_count; | |
826 | ret = ctrl->reg_write(ctrl, reg, value); | |
e729e0fd SK |
827 | if (ret) |
828 | goto err; | |
128eaf93 SK |
829 | } |
830 | ||
831 | if (pcfg->hstart != SWR_INVALID_PARAM | |
832 | && pcfg->hstop != SWR_INVALID_PARAM) { | |
833 | reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank); | |
834 | value = (pcfg->hstop << 4) | pcfg->hstart; | |
835 | ret = ctrl->reg_write(ctrl, reg, value); | |
836 | } else { | |
837 | reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank); | |
838 | value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL; | |
839 | ret = ctrl->reg_write(ctrl, reg, value); | |
840 | } | |
841 | ||
e729e0fd SK |
842 | if (ret) |
843 | goto err; | |
844 | ||
128eaf93 SK |
845 | if (pcfg->bp_mode != SWR_INVALID_PARAM) { |
846 | reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank); | |
847 | ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode); | |
5ffba1fb SK |
848 | } |
849 | ||
e729e0fd | 850 | err: |
5ffba1fb | 851 | return ret; |
02efb49a SK |
852 | } |
853 | ||
854 | static int qcom_swrm_port_enable(struct sdw_bus *bus, | |
855 | struct sdw_enable_ch *enable_ch, | |
856 | unsigned int bank) | |
857 | { | |
858 | u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank); | |
859 | struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); | |
860 | u32 val; | |
861 | ||
862 | ctrl->reg_read(ctrl, reg, &val); | |
863 | ||
864 | if (enable_ch->enable) | |
865 | val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT); | |
866 | else | |
867 | val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT); | |
868 | ||
869 | return ctrl->reg_write(ctrl, reg, val); | |
870 | } | |
871 | ||
51fe3881 | 872 | static const struct sdw_master_port_ops qcom_swrm_port_ops = { |
02efb49a SK |
873 | .dpn_set_port_params = qcom_swrm_port_params, |
874 | .dpn_set_port_transport_params = qcom_swrm_transport_params, | |
875 | .dpn_port_enable_ch = qcom_swrm_port_enable, | |
876 | }; | |
877 | ||
51fe3881 | 878 | static const struct sdw_master_ops qcom_swrm_ops = { |
02efb49a SK |
879 | .xfer_msg = qcom_swrm_xfer_msg, |
880 | .pre_bank_switch = qcom_swrm_pre_bank_switch, | |
881 | }; | |
882 | ||
883 | static int qcom_swrm_compute_params(struct sdw_bus *bus) | |
884 | { | |
885 | struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); | |
886 | struct sdw_master_runtime *m_rt; | |
887 | struct sdw_slave_runtime *s_rt; | |
888 | struct sdw_port_runtime *p_rt; | |
889 | struct qcom_swrm_port_config *pcfg; | |
eb5a9094 SK |
890 | struct sdw_slave *slave; |
891 | unsigned int m_port; | |
9916c02c | 892 | int i = 1; |
02efb49a SK |
893 | |
894 | list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) { | |
895 | list_for_each_entry(p_rt, &m_rt->port_list, port_node) { | |
9916c02c | 896 | pcfg = &ctrl->pconfig[p_rt->num]; |
02efb49a | 897 | p_rt->transport_params.port_num = p_rt->num; |
128eaf93 SK |
898 | if (pcfg->word_length != SWR_INVALID_PARAM) { |
899 | sdw_fill_port_params(&p_rt->port_params, | |
900 | p_rt->num, pcfg->word_length + 1, | |
901 | SDW_PORT_FLOW_MODE_ISOCH, | |
902 | SDW_PORT_DATA_MODE_NORMAL); | |
903 | } | |
904 | ||
02efb49a SK |
905 | } |
906 | ||
907 | list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { | |
eb5a9094 | 908 | slave = s_rt->slave; |
02efb49a | 909 | list_for_each_entry(p_rt, &s_rt->port_list, port_node) { |
eb5a9094 SK |
910 | m_port = slave->m_port_map[p_rt->num]; |
911 | /* port config starts at offset 0 so -1 from actual port number */ | |
912 | if (m_port) | |
9916c02c | 913 | pcfg = &ctrl->pconfig[m_port]; |
eb5a9094 SK |
914 | else |
915 | pcfg = &ctrl->pconfig[i]; | |
02efb49a SK |
916 | p_rt->transport_params.port_num = p_rt->num; |
917 | p_rt->transport_params.sample_interval = | |
918 | pcfg->si + 1; | |
919 | p_rt->transport_params.offset1 = pcfg->off1; | |
920 | p_rt->transport_params.offset2 = pcfg->off2; | |
5ffba1fb | 921 | p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode; |
128eaf93 SK |
922 | p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count; |
923 | ||
924 | p_rt->transport_params.hstart = pcfg->hstart; | |
925 | p_rt->transport_params.hstop = pcfg->hstop; | |
926 | p_rt->transport_params.lane_ctrl = pcfg->lane_control; | |
927 | if (pcfg->word_length != SWR_INVALID_PARAM) { | |
928 | sdw_fill_port_params(&p_rt->port_params, | |
929 | p_rt->num, | |
930 | pcfg->word_length + 1, | |
931 | SDW_PORT_FLOW_MODE_ISOCH, | |
932 | SDW_PORT_DATA_MODE_NORMAL); | |
933 | } | |
02efb49a SK |
934 | i++; |
935 | } | |
936 | } | |
937 | } | |
938 | ||
939 | return 0; | |
940 | } | |
941 | ||
942 | static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = { | |
943 | DEFAULT_CLK_FREQ, | |
944 | }; | |
945 | ||
02efb49a SK |
946 | static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl, |
947 | struct sdw_stream_runtime *stream) | |
948 | { | |
949 | struct sdw_master_runtime *m_rt; | |
950 | struct sdw_port_runtime *p_rt; | |
951 | unsigned long *port_mask; | |
952 | ||
953 | mutex_lock(&ctrl->port_lock); | |
954 | ||
955 | list_for_each_entry(m_rt, &stream->master_list, stream_node) { | |
956 | if (m_rt->direction == SDW_DATA_DIR_RX) | |
957 | port_mask = &ctrl->dout_port_mask; | |
958 | else | |
959 | port_mask = &ctrl->din_port_mask; | |
960 | ||
961 | list_for_each_entry(p_rt, &m_rt->port_list, port_node) | |
650dfdb8 | 962 | clear_bit(p_rt->num, port_mask); |
02efb49a SK |
963 | } |
964 | ||
965 | mutex_unlock(&ctrl->port_lock); | |
966 | } | |
967 | ||
968 | static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl, | |
969 | struct sdw_stream_runtime *stream, | |
970 | struct snd_pcm_hw_params *params, | |
971 | int direction) | |
972 | { | |
973 | struct sdw_port_config pconfig[QCOM_SDW_MAX_PORTS]; | |
974 | struct sdw_stream_config sconfig; | |
975 | struct sdw_master_runtime *m_rt; | |
976 | struct sdw_slave_runtime *s_rt; | |
977 | struct sdw_port_runtime *p_rt; | |
eb5a9094 | 978 | struct sdw_slave *slave; |
02efb49a SK |
979 | unsigned long *port_mask; |
980 | int i, maxport, pn, nports = 0, ret = 0; | |
eb5a9094 | 981 | unsigned int m_port; |
02efb49a SK |
982 | |
983 | mutex_lock(&ctrl->port_lock); | |
984 | list_for_each_entry(m_rt, &stream->master_list, stream_node) { | |
985 | if (m_rt->direction == SDW_DATA_DIR_RX) { | |
986 | maxport = ctrl->num_dout_ports; | |
987 | port_mask = &ctrl->dout_port_mask; | |
988 | } else { | |
989 | maxport = ctrl->num_din_ports; | |
990 | port_mask = &ctrl->din_port_mask; | |
991 | } | |
992 | ||
993 | list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { | |
eb5a9094 | 994 | slave = s_rt->slave; |
02efb49a | 995 | list_for_each_entry(p_rt, &s_rt->port_list, port_node) { |
eb5a9094 | 996 | m_port = slave->m_port_map[p_rt->num]; |
02efb49a | 997 | /* Port numbers start from 1 - 14*/ |
eb5a9094 SK |
998 | if (m_port) |
999 | pn = m_port; | |
1000 | else | |
1001 | pn = find_first_zero_bit(port_mask, maxport); | |
1002 | ||
650dfdb8 | 1003 | if (pn > maxport) { |
02efb49a SK |
1004 | dev_err(ctrl->dev, "All ports busy\n"); |
1005 | ret = -EBUSY; | |
1006 | goto err; | |
1007 | } | |
1008 | set_bit(pn, port_mask); | |
650dfdb8 | 1009 | pconfig[nports].num = pn; |
02efb49a SK |
1010 | pconfig[nports].ch_mask = p_rt->ch_mask; |
1011 | nports++; | |
1012 | } | |
1013 | } | |
1014 | } | |
1015 | ||
1016 | if (direction == SNDRV_PCM_STREAM_CAPTURE) | |
1017 | sconfig.direction = SDW_DATA_DIR_TX; | |
1018 | else | |
1019 | sconfig.direction = SDW_DATA_DIR_RX; | |
1020 | ||
1021 | /* hw parameters wil be ignored as we only support PDM */ | |
1022 | sconfig.ch_count = 1; | |
1023 | sconfig.frame_rate = params_rate(params); | |
1024 | sconfig.type = stream->type; | |
1025 | sconfig.bps = 1; | |
1026 | sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig, | |
1027 | nports, stream); | |
1028 | err: | |
1029 | if (ret) { | |
1030 | for (i = 0; i < nports; i++) | |
650dfdb8 | 1031 | clear_bit(pconfig[i].num, port_mask); |
02efb49a SK |
1032 | } |
1033 | ||
1034 | mutex_unlock(&ctrl->port_lock); | |
1035 | ||
1036 | return ret; | |
1037 | } | |
1038 | ||
1039 | static int qcom_swrm_hw_params(struct snd_pcm_substream *substream, | |
1040 | struct snd_pcm_hw_params *params, | |
1041 | struct snd_soc_dai *dai) | |
1042 | { | |
1043 | struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); | |
1044 | struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; | |
1045 | int ret; | |
1046 | ||
1047 | ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params, | |
1048 | substream->stream); | |
1049 | if (ret) | |
1050 | qcom_swrm_stream_free_ports(ctrl, sruntime); | |
1051 | ||
1052 | return ret; | |
1053 | } | |
1054 | ||
1055 | static int qcom_swrm_hw_free(struct snd_pcm_substream *substream, | |
1056 | struct snd_soc_dai *dai) | |
1057 | { | |
1058 | struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); | |
1059 | struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; | |
1060 | ||
1061 | qcom_swrm_stream_free_ports(ctrl, sruntime); | |
1062 | sdw_stream_remove_master(&ctrl->bus, sruntime); | |
1063 | ||
1064 | return 0; | |
1065 | } | |
1066 | ||
1067 | static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai, | |
1068 | void *stream, int direction) | |
1069 | { | |
1070 | struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); | |
1071 | ||
1072 | ctrl->sruntime[dai->id] = stream; | |
1073 | ||
1074 | return 0; | |
1075 | } | |
1076 | ||
39ec6f99 SK |
1077 | static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction) |
1078 | { | |
1079 | struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); | |
1080 | ||
1081 | return ctrl->sruntime[dai->id]; | |
1082 | } | |
1083 | ||
02efb49a SK |
1084 | static int qcom_swrm_startup(struct snd_pcm_substream *substream, |
1085 | struct snd_soc_dai *dai) | |
1086 | { | |
1087 | struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); | |
1088 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1089 | struct sdw_stream_runtime *sruntime; | |
ce83baca | 1090 | struct snd_soc_dai *codec_dai; |
02efb49a SK |
1091 | int ret, i; |
1092 | ||
57ed510b | 1093 | ret = pm_runtime_resume_and_get(ctrl->dev); |
74e79da9 SK |
1094 | if (ret < 0 && ret != -EACCES) { |
1095 | dev_err_ratelimited(ctrl->dev, | |
57ed510b | 1096 | "pm_runtime_resume_and_get failed in %s, ret %d\n", |
74e79da9 | 1097 | __func__, ret); |
74e79da9 SK |
1098 | return ret; |
1099 | } | |
1100 | ||
02efb49a SK |
1101 | sruntime = sdw_alloc_stream(dai->name); |
1102 | if (!sruntime) | |
1103 | return -ENOMEM; | |
1104 | ||
1105 | ctrl->sruntime[dai->id] = sruntime; | |
1106 | ||
c998ee30 | 1107 | for_each_rtd_codec_dais(rtd, i, codec_dai) { |
e8444560 PLB |
1108 | ret = snd_soc_dai_set_stream(codec_dai, sruntime, |
1109 | substream->stream); | |
02efb49a | 1110 | if (ret < 0 && ret != -ENOTSUPP) { |
e6cb15b5 | 1111 | dev_err(dai->dev, "Failed to set sdw stream on %s\n", |
ce83baca | 1112 | codec_dai->name); |
02efb49a SK |
1113 | sdw_release_stream(sruntime); |
1114 | return ret; | |
1115 | } | |
1116 | } | |
1117 | ||
1118 | return 0; | |
1119 | } | |
1120 | ||
1121 | static void qcom_swrm_shutdown(struct snd_pcm_substream *substream, | |
1122 | struct snd_soc_dai *dai) | |
1123 | { | |
1124 | struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); | |
1125 | ||
1126 | sdw_release_stream(ctrl->sruntime[dai->id]); | |
1127 | ctrl->sruntime[dai->id] = NULL; | |
74e79da9 SK |
1128 | pm_runtime_mark_last_busy(ctrl->dev); |
1129 | pm_runtime_put_autosuspend(ctrl->dev); | |
1130 | ||
02efb49a SK |
1131 | } |
1132 | ||
1133 | static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = { | |
1134 | .hw_params = qcom_swrm_hw_params, | |
1135 | .hw_free = qcom_swrm_hw_free, | |
1136 | .startup = qcom_swrm_startup, | |
1137 | .shutdown = qcom_swrm_shutdown, | |
e8444560 PLB |
1138 | .set_stream = qcom_swrm_set_sdw_stream, |
1139 | .get_stream = qcom_swrm_get_sdw_stream, | |
02efb49a SK |
1140 | }; |
1141 | ||
1142 | static const struct snd_soc_component_driver qcom_swrm_dai_component = { | |
1143 | .name = "soundwire", | |
1144 | }; | |
1145 | ||
1146 | static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl) | |
1147 | { | |
1148 | int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports; | |
1149 | struct snd_soc_dai_driver *dais; | |
1150 | struct snd_soc_pcm_stream *stream; | |
1151 | struct device *dev = ctrl->dev; | |
1152 | int i; | |
1153 | ||
1154 | /* PDM dais are only tested for now */ | |
1155 | dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL); | |
1156 | if (!dais) | |
1157 | return -ENOMEM; | |
1158 | ||
1159 | for (i = 0; i < num_dais; i++) { | |
1160 | dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i); | |
1161 | if (!dais[i].name) | |
1162 | return -ENOMEM; | |
1163 | ||
1164 | if (i < ctrl->num_dout_ports) | |
1165 | stream = &dais[i].playback; | |
1166 | else | |
1167 | stream = &dais[i].capture; | |
1168 | ||
1169 | stream->channels_min = 1; | |
1170 | stream->channels_max = 1; | |
1171 | stream->rates = SNDRV_PCM_RATE_48000; | |
1172 | stream->formats = SNDRV_PCM_FMTBIT_S16_LE; | |
1173 | ||
1174 | dais[i].ops = &qcom_swrm_pdm_dai_ops; | |
1175 | dais[i].id = i; | |
1176 | } | |
1177 | ||
1178 | return devm_snd_soc_register_component(ctrl->dev, | |
1179 | &qcom_swrm_dai_component, | |
1180 | dais, num_dais); | |
1181 | } | |
1182 | ||
1183 | static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl) | |
1184 | { | |
1185 | struct device_node *np = ctrl->dev->of_node; | |
1186 | u8 off1[QCOM_SDW_MAX_PORTS]; | |
1187 | u8 off2[QCOM_SDW_MAX_PORTS]; | |
1188 | u8 si[QCOM_SDW_MAX_PORTS]; | |
5ffba1fb | 1189 | u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, }; |
128eaf93 SK |
1190 | u8 hstart[QCOM_SDW_MAX_PORTS]; |
1191 | u8 hstop[QCOM_SDW_MAX_PORTS]; | |
1192 | u8 word_length[QCOM_SDW_MAX_PORTS]; | |
1193 | u8 blk_group_count[QCOM_SDW_MAX_PORTS]; | |
1194 | u8 lane_control[QCOM_SDW_MAX_PORTS]; | |
02efb49a SK |
1195 | int i, ret, nports, val; |
1196 | ||
1197 | ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); | |
1198 | ||
9972b90a VK |
1199 | ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val); |
1200 | ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val); | |
02efb49a SK |
1201 | |
1202 | ret = of_property_read_u32(np, "qcom,din-ports", &val); | |
1203 | if (ret) | |
1204 | return ret; | |
1205 | ||
1206 | if (val > ctrl->num_din_ports) | |
1207 | return -EINVAL; | |
1208 | ||
1209 | ctrl->num_din_ports = val; | |
1210 | ||
1211 | ret = of_property_read_u32(np, "qcom,dout-ports", &val); | |
1212 | if (ret) | |
1213 | return ret; | |
1214 | ||
1215 | if (val > ctrl->num_dout_ports) | |
1216 | return -EINVAL; | |
1217 | ||
1218 | ctrl->num_dout_ports = val; | |
1219 | ||
1220 | nports = ctrl->num_dout_ports + ctrl->num_din_ports; | |
2367e0ec KK |
1221 | if (nports > QCOM_SDW_MAX_PORTS) |
1222 | return -EINVAL; | |
1223 | ||
650dfdb8 SK |
1224 | /* Valid port numbers are from 1-14, so mask out port 0 explicitly */ |
1225 | set_bit(0, &ctrl->dout_port_mask); | |
1226 | set_bit(0, &ctrl->din_port_mask); | |
02efb49a SK |
1227 | |
1228 | ret = of_property_read_u8_array(np, "qcom,ports-offset1", | |
1229 | off1, nports); | |
1230 | if (ret) | |
1231 | return ret; | |
1232 | ||
1233 | ret = of_property_read_u8_array(np, "qcom,ports-offset2", | |
1234 | off2, nports); | |
1235 | if (ret) | |
1236 | return ret; | |
1237 | ||
1238 | ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low", | |
1239 | si, nports); | |
1240 | if (ret) | |
1241 | return ret; | |
1242 | ||
5ffba1fb SK |
1243 | ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode", |
1244 | bp_mode, nports); | |
da096fbc | 1245 | if (ret) { |
208a03ee | 1246 | if (ctrl->version <= SWRM_VERSION_1_3_0) |
da096fbc SK |
1247 | memset(bp_mode, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); |
1248 | else | |
1249 | return ret; | |
1250 | } | |
a5943e4f | 1251 | |
128eaf93 SK |
1252 | memset(hstart, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); |
1253 | of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports); | |
1254 | ||
1255 | memset(hstop, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); | |
1256 | of_property_read_u8_array(np, "qcom,ports-hstop", hstop, nports); | |
1257 | ||
1258 | memset(word_length, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); | |
1259 | of_property_read_u8_array(np, "qcom,ports-word-length", word_length, nports); | |
1260 | ||
1261 | memset(blk_group_count, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); | |
1262 | of_property_read_u8_array(np, "qcom,ports-block-group-count", blk_group_count, nports); | |
1263 | ||
1264 | memset(lane_control, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); | |
1265 | of_property_read_u8_array(np, "qcom,ports-lane-control", lane_control, nports); | |
1266 | ||
02efb49a | 1267 | for (i = 0; i < nports; i++) { |
9916c02c SK |
1268 | /* Valid port number range is from 1-14 */ |
1269 | ctrl->pconfig[i + 1].si = si[i]; | |
1270 | ctrl->pconfig[i + 1].off1 = off1[i]; | |
1271 | ctrl->pconfig[i + 1].off2 = off2[i]; | |
1272 | ctrl->pconfig[i + 1].bp_mode = bp_mode[i]; | |
1273 | ctrl->pconfig[i + 1].hstart = hstart[i]; | |
1274 | ctrl->pconfig[i + 1].hstop = hstop[i]; | |
1275 | ctrl->pconfig[i + 1].word_length = word_length[i]; | |
1276 | ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i]; | |
1277 | ctrl->pconfig[i + 1].lane_control = lane_control[i]; | |
02efb49a SK |
1278 | } |
1279 | ||
1280 | return 0; | |
1281 | } | |
1282 | ||
abd9a604 SK |
1283 | #ifdef CONFIG_DEBUG_FS |
1284 | static int swrm_reg_show(struct seq_file *s_file, void *data) | |
1285 | { | |
1286 | struct qcom_swrm_ctrl *swrm = s_file->private; | |
74e79da9 SK |
1287 | int reg, reg_val, ret; |
1288 | ||
57ed510b | 1289 | ret = pm_runtime_resume_and_get(swrm->dev); |
74e79da9 SK |
1290 | if (ret < 0 && ret != -EACCES) { |
1291 | dev_err_ratelimited(swrm->dev, | |
57ed510b | 1292 | "pm_runtime_resume_and_get failed in %s, ret %d\n", |
74e79da9 | 1293 | __func__, ret); |
f6ee6c84 | 1294 | return ret; |
74e79da9 | 1295 | } |
abd9a604 SK |
1296 | |
1297 | for (reg = 0; reg <= SWR_MSTR_MAX_REG_ADDR; reg += 4) { | |
1298 | swrm->reg_read(swrm, reg, ®_val); | |
1299 | seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val); | |
1300 | } | |
74e79da9 SK |
1301 | pm_runtime_mark_last_busy(swrm->dev); |
1302 | pm_runtime_put_autosuspend(swrm->dev); | |
1303 | ||
abd9a604 SK |
1304 | |
1305 | return 0; | |
1306 | } | |
1307 | DEFINE_SHOW_ATTRIBUTE(swrm_reg); | |
1308 | #endif | |
1309 | ||
02efb49a SK |
1310 | static int qcom_swrm_probe(struct platform_device *pdev) |
1311 | { | |
1312 | struct device *dev = &pdev->dev; | |
1313 | struct sdw_master_prop *prop; | |
1314 | struct sdw_bus_params *params; | |
1315 | struct qcom_swrm_ctrl *ctrl; | |
8cb3b4e7 | 1316 | const struct qcom_swrm_data *data; |
02efb49a SK |
1317 | int ret; |
1318 | u32 val; | |
1319 | ||
1320 | ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); | |
1321 | if (!ctrl) | |
1322 | return -ENOMEM; | |
1323 | ||
8cb3b4e7 SK |
1324 | data = of_device_get_match_data(dev); |
1325 | ctrl->rows_index = sdw_find_row_index(data->default_rows); | |
1326 | ctrl->cols_index = sdw_find_col_index(data->default_cols); | |
47edc010 | 1327 | #if IS_REACHABLE(CONFIG_SLIMBUS) |
02efb49a | 1328 | if (dev->parent->bus == &slimbus_bus) { |
5bd77324 JM |
1329 | #else |
1330 | if (false) { | |
1331 | #endif | |
d1df23fe | 1332 | ctrl->reg_read = qcom_swrm_ahb_reg_read; |
02efb49a SK |
1333 | ctrl->reg_write = qcom_swrm_ahb_reg_write; |
1334 | ctrl->regmap = dev_get_regmap(dev->parent, NULL); | |
1335 | if (!ctrl->regmap) | |
1336 | return -EINVAL; | |
1337 | } else { | |
82f5c70c JM |
1338 | ctrl->reg_read = qcom_swrm_cpu_reg_read; |
1339 | ctrl->reg_write = qcom_swrm_cpu_reg_write; | |
1340 | ctrl->mmio = devm_platform_ioremap_resource(pdev, 0); | |
1341 | if (IS_ERR(ctrl->mmio)) | |
1342 | return PTR_ERR(ctrl->mmio); | |
02efb49a SK |
1343 | } |
1344 | ||
1fd0d85a | 1345 | if (data->sw_clk_gate_required) { |
1cdbfd4c SK |
1346 | ctrl->audio_cgcr = devm_reset_control_get_optional_exclusive(dev, "swr_audio_cgcr"); |
1347 | if (IS_ERR(ctrl->audio_cgcr)) { | |
1fd0d85a SRM |
1348 | dev_err(dev, "Failed to get cgcr reset ctrl required for SW gating\n"); |
1349 | ret = PTR_ERR(ctrl->audio_cgcr); | |
1350 | goto err_init; | |
1351 | } | |
1352 | } | |
1353 | ||
02efb49a | 1354 | ctrl->irq = of_irq_get(dev->of_node, 0); |
91b5cfc0 PLB |
1355 | if (ctrl->irq < 0) { |
1356 | ret = ctrl->irq; | |
1357 | goto err_init; | |
1358 | } | |
02efb49a SK |
1359 | |
1360 | ctrl->hclk = devm_clk_get(dev, "iface"); | |
91b5cfc0 PLB |
1361 | if (IS_ERR(ctrl->hclk)) { |
1362 | ret = PTR_ERR(ctrl->hclk); | |
1363 | goto err_init; | |
1364 | } | |
02efb49a SK |
1365 | |
1366 | clk_prepare_enable(ctrl->hclk); | |
1367 | ||
1368 | ctrl->dev = dev; | |
1369 | dev_set_drvdata(&pdev->dev, ctrl); | |
02efb49a | 1370 | mutex_init(&ctrl->port_lock); |
ddea6cf7 | 1371 | init_completion(&ctrl->broadcast); |
06dd9673 | 1372 | init_completion(&ctrl->enumeration); |
02efb49a | 1373 | |
02efb49a SK |
1374 | ctrl->bus.ops = &qcom_swrm_ops; |
1375 | ctrl->bus.port_ops = &qcom_swrm_port_ops; | |
1376 | ctrl->bus.compute_params = &qcom_swrm_compute_params; | |
74e79da9 | 1377 | ctrl->bus.clk_stop_timeout = 300; |
02efb49a SK |
1378 | |
1379 | ret = qcom_swrm_get_port_config(ctrl); | |
1380 | if (ret) | |
91b5cfc0 | 1381 | goto err_clk; |
02efb49a SK |
1382 | |
1383 | params = &ctrl->bus.params; | |
1384 | params->max_dr_freq = DEFAULT_CLK_FREQ; | |
1385 | params->curr_dr_freq = DEFAULT_CLK_FREQ; | |
8cb3b4e7 SK |
1386 | params->col = data->default_cols; |
1387 | params->row = data->default_rows; | |
02efb49a SK |
1388 | ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val); |
1389 | params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK; | |
1390 | params->next_bank = !params->curr_bank; | |
1391 | ||
1392 | prop = &ctrl->bus.prop; | |
1393 | prop->max_clk_freq = DEFAULT_CLK_FREQ; | |
1394 | prop->num_clk_gears = 0; | |
1395 | prop->num_clk_freq = MAX_FREQ_NUM; | |
1396 | prop->clk_freq = &qcom_swrm_freq_tbl[0]; | |
8cb3b4e7 SK |
1397 | prop->default_col = data->default_cols; |
1398 | prop->default_row = data->default_rows; | |
02efb49a SK |
1399 | |
1400 | ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version); | |
1401 | ||
1402 | ret = devm_request_threaded_irq(dev, ctrl->irq, NULL, | |
1403 | qcom_swrm_irq_handler, | |
4f1738f4 SZ |
1404 | IRQF_TRIGGER_RISING | |
1405 | IRQF_ONESHOT, | |
02efb49a SK |
1406 | "soundwire", ctrl); |
1407 | if (ret) { | |
1408 | dev_err(dev, "Failed to request soundwire irq\n"); | |
91b5cfc0 | 1409 | goto err_clk; |
02efb49a SK |
1410 | } |
1411 | ||
04d46a7b SK |
1412 | ctrl->wake_irq = of_irq_get(dev->of_node, 1); |
1413 | if (ctrl->wake_irq > 0) { | |
1414 | ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL, | |
1415 | qcom_swrm_wake_irq_handler, | |
1416 | IRQF_TRIGGER_HIGH | IRQF_ONESHOT, | |
1417 | "swr_wake_irq", ctrl); | |
1418 | if (ret) { | |
1419 | dev_err(dev, "Failed to request soundwire wake irq\n"); | |
1420 | goto err_init; | |
1421 | } | |
1422 | } | |
1423 | ||
5cab3ff2 | 1424 | ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode); |
02efb49a SK |
1425 | if (ret) { |
1426 | dev_err(dev, "Failed to register Soundwire controller (%d)\n", | |
1427 | ret); | |
91b5cfc0 | 1428 | goto err_clk; |
02efb49a SK |
1429 | } |
1430 | ||
1431 | qcom_swrm_init(ctrl); | |
06dd9673 SK |
1432 | wait_for_completion_timeout(&ctrl->enumeration, |
1433 | msecs_to_jiffies(TIMEOUT_MS)); | |
02efb49a SK |
1434 | ret = qcom_swrm_register_dais(ctrl); |
1435 | if (ret) | |
91b5cfc0 | 1436 | goto err_master_add; |
02efb49a SK |
1437 | |
1438 | dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n", | |
1439 | (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff, | |
1440 | ctrl->version & 0xffff); | |
1441 | ||
74e79da9 SK |
1442 | pm_runtime_set_autosuspend_delay(dev, 3000); |
1443 | pm_runtime_use_autosuspend(dev); | |
1444 | pm_runtime_mark_last_busy(dev); | |
1445 | pm_runtime_set_active(dev); | |
1446 | pm_runtime_enable(dev); | |
1447 | ||
1448 | /* Clk stop is not supported on WSA Soundwire masters */ | |
208a03ee | 1449 | if (ctrl->version <= SWRM_VERSION_1_3_0) { |
74e79da9 SK |
1450 | ctrl->clock_stop_not_supported = true; |
1451 | } else { | |
1452 | ctrl->reg_read(ctrl, SWRM_COMP_MASTER_ID, &val); | |
1453 | if (val == MASTER_ID_WSA) | |
1454 | ctrl->clock_stop_not_supported = true; | |
1455 | } | |
1456 | ||
abd9a604 SK |
1457 | #ifdef CONFIG_DEBUG_FS |
1458 | ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs); | |
1459 | debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl, | |
1460 | &swrm_reg_fops); | |
1461 | #endif | |
1462 | ||
02efb49a | 1463 | return 0; |
91b5cfc0 PLB |
1464 | |
1465 | err_master_add: | |
5cab3ff2 | 1466 | sdw_bus_master_delete(&ctrl->bus); |
91b5cfc0 | 1467 | err_clk: |
02efb49a | 1468 | clk_disable_unprepare(ctrl->hclk); |
91b5cfc0 | 1469 | err_init: |
02efb49a SK |
1470 | return ret; |
1471 | } | |
1472 | ||
1473 | static int qcom_swrm_remove(struct platform_device *pdev) | |
1474 | { | |
1475 | struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev); | |
1476 | ||
5cab3ff2 | 1477 | sdw_bus_master_delete(&ctrl->bus); |
02efb49a SK |
1478 | clk_disable_unprepare(ctrl->hclk); |
1479 | ||
1480 | return 0; | |
1481 | } | |
1482 | ||
74e79da9 SK |
1483 | static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *swrm) |
1484 | { | |
1485 | int retry = SWRM_LINK_STATUS_RETRY_CNT; | |
1486 | int comp_sts; | |
1487 | ||
1488 | do { | |
1489 | swrm->reg_read(swrm, SWRM_COMP_STATUS, &comp_sts); | |
1490 | ||
1491 | if (comp_sts & SWRM_FRM_GEN_ENABLED) | |
1492 | return true; | |
1493 | ||
1494 | usleep_range(500, 510); | |
1495 | } while (retry--); | |
1496 | ||
1497 | dev_err(swrm->dev, "%s: link status not %s\n", __func__, | |
d146de34 | 1498 | comp_sts & SWRM_FRM_GEN_ENABLED ? "connected" : "disconnected"); |
74e79da9 SK |
1499 | |
1500 | return false; | |
1501 | } | |
1502 | ||
266fa946 | 1503 | static int __maybe_unused swrm_runtime_resume(struct device *dev) |
74e79da9 SK |
1504 | { |
1505 | struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev); | |
1506 | int ret; | |
1507 | ||
04d46a7b SK |
1508 | if (ctrl->wake_irq > 0) { |
1509 | if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq))) | |
1510 | disable_irq_nosync(ctrl->wake_irq); | |
1511 | } | |
1512 | ||
74e79da9 SK |
1513 | clk_prepare_enable(ctrl->hclk); |
1514 | ||
1515 | if (ctrl->clock_stop_not_supported) { | |
1516 | reinit_completion(&ctrl->enumeration); | |
1517 | ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01); | |
1518 | usleep_range(100, 105); | |
1519 | ||
1520 | qcom_swrm_init(ctrl); | |
1521 | ||
1522 | usleep_range(100, 105); | |
1523 | if (!swrm_wait_for_frame_gen_enabled(ctrl)) | |
1524 | dev_err(ctrl->dev, "link failed to connect\n"); | |
1525 | ||
1526 | /* wait for hw enumeration to complete */ | |
1527 | wait_for_completion_timeout(&ctrl->enumeration, | |
1528 | msecs_to_jiffies(TIMEOUT_MS)); | |
1529 | qcom_swrm_get_device_status(ctrl); | |
1530 | sdw_handle_slave_status(&ctrl->bus, ctrl->status); | |
1531 | } else { | |
33ba0178 SRM |
1532 | reset_control_reset(ctrl->audio_cgcr); |
1533 | ||
208a03ee | 1534 | if (ctrl->version >= SWRM_VERSION_1_7_0) { |
cf43cd33 SK |
1535 | ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); |
1536 | ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, | |
1537 | SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU); | |
1538 | } else { | |
1539 | ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); | |
1540 | } | |
74e79da9 SK |
1541 | ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR, |
1542 | SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET); | |
1543 | ||
1544 | ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; | |
1545 | ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask); | |
1546 | ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask); | |
1547 | ||
1548 | usleep_range(100, 105); | |
1549 | if (!swrm_wait_for_frame_gen_enabled(ctrl)) | |
1550 | dev_err(ctrl->dev, "link failed to connect\n"); | |
1551 | ||
1552 | ret = sdw_bus_exit_clk_stop(&ctrl->bus); | |
1553 | if (ret < 0) | |
1554 | dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret); | |
1555 | } | |
1556 | ||
1557 | return 0; | |
1558 | } | |
1559 | ||
1560 | static int __maybe_unused swrm_runtime_suspend(struct device *dev) | |
1561 | { | |
1562 | struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev); | |
1563 | int ret; | |
1564 | ||
1565 | if (!ctrl->clock_stop_not_supported) { | |
1566 | /* Mask bus clash interrupt */ | |
1567 | ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; | |
1568 | ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask); | |
1569 | ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask); | |
1570 | /* Prepare slaves for clock stop */ | |
1571 | ret = sdw_bus_prep_clk_stop(&ctrl->bus); | |
1572 | if (ret < 0 && ret != -ENODATA) { | |
1573 | dev_err(dev, "prepare clock stop failed %d", ret); | |
1574 | return ret; | |
1575 | } | |
1576 | ||
1577 | ret = sdw_bus_clk_stop(&ctrl->bus); | |
1578 | if (ret < 0 && ret != -ENODATA) { | |
1579 | dev_err(dev, "bus clock stop failed %d", ret); | |
1580 | return ret; | |
1581 | } | |
1582 | } | |
1583 | ||
1584 | clk_disable_unprepare(ctrl->hclk); | |
1585 | ||
1586 | usleep_range(300, 305); | |
1587 | ||
04d46a7b SK |
1588 | if (ctrl->wake_irq > 0) { |
1589 | if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq))) | |
1590 | enable_irq(ctrl->wake_irq); | |
1591 | } | |
1592 | ||
74e79da9 SK |
1593 | return 0; |
1594 | } | |
1595 | ||
1596 | static const struct dev_pm_ops swrm_dev_pm_ops = { | |
1597 | SET_RUNTIME_PM_OPS(swrm_runtime_suspend, swrm_runtime_resume, NULL) | |
1598 | }; | |
1599 | ||
02efb49a | 1600 | static const struct of_device_id qcom_swrm_of_match[] = { |
8cb3b4e7 SK |
1601 | { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data }, |
1602 | { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data }, | |
3f4a7026 | 1603 | { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data }, |
cf43cd33 | 1604 | { .compatible = "qcom,soundwire-v1.7.0", .data = &swrm_v1_5_data }, |
02efb49a SK |
1605 | {/* sentinel */}, |
1606 | }; | |
1607 | ||
1608 | MODULE_DEVICE_TABLE(of, qcom_swrm_of_match); | |
1609 | ||
1610 | static struct platform_driver qcom_swrm_driver = { | |
1611 | .probe = &qcom_swrm_probe, | |
1612 | .remove = &qcom_swrm_remove, | |
1613 | .driver = { | |
1614 | .name = "qcom-soundwire", | |
1615 | .of_match_table = qcom_swrm_of_match, | |
74e79da9 | 1616 | .pm = &swrm_dev_pm_ops, |
02efb49a SK |
1617 | } |
1618 | }; | |
1619 | module_platform_driver(qcom_swrm_driver); | |
1620 | ||
1621 | MODULE_DESCRIPTION("Qualcomm soundwire driver"); | |
1622 | MODULE_LICENSE("GPL v2"); |