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6f23f4e2 PLB |
1 | // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) |
2 | // Copyright(c) 2023 Intel Corporation. All rights reserved. | |
3 | ||
4 | /* | |
5 | * Soundwire Intel ops for LunarLake | |
6 | */ | |
7 | ||
8 | #include <linux/acpi.h> | |
9 | #include <linux/device.h> | |
10 | #include <linux/soundwire/sdw_registers.h> | |
11 | #include <linux/soundwire/sdw.h> | |
12 | #include <linux/soundwire/sdw_intel.h> | |
8c4c9a9a | 13 | #include <sound/pcm_params.h> |
806f5abd | 14 | #include <sound/hda-mlink.h> |
6f23f4e2 PLB |
15 | #include "cadence_master.h" |
16 | #include "bus.h" | |
17 | #include "intel.h" | |
18 | ||
f40bb244 PLB |
19 | /* |
20 | * shim vendor-specific (vs) ops | |
21 | */ | |
22 | ||
23 | static void intel_shim_vs_init(struct sdw_intel *sdw) | |
24 | { | |
25 | void __iomem *shim_vs = sdw->link_res->shim_vs; | |
26 | u16 act = 0; | |
27 | ||
28 | u16p_replace_bits(&act, 0x1, SDW_SHIM2_INTEL_VS_ACTMCTL_DOAIS); | |
29 | act |= SDW_SHIM2_INTEL_VS_ACTMCTL_DACTQE; | |
30 | act |= SDW_SHIM2_INTEL_VS_ACTMCTL_DODS; | |
31 | intel_writew(shim_vs, SDW_SHIM2_INTEL_VS_ACTMCTL, act); | |
32 | usleep_range(10, 15); | |
33 | } | |
34 | ||
b8e39bc4 PLB |
35 | static int intel_shim_check_wake(struct sdw_intel *sdw) |
36 | { | |
37 | void __iomem *shim_vs; | |
38 | u16 wake_sts; | |
39 | ||
40 | shim_vs = sdw->link_res->shim_vs; | |
41 | wake_sts = intel_readw(shim_vs, SDW_SHIM2_INTEL_VS_WAKESTS); | |
42 | ||
43 | return wake_sts & SDW_SHIM2_INTEL_VS_WAKEEN_PWS; | |
44 | } | |
45 | ||
46 | static void intel_shim_wake(struct sdw_intel *sdw, bool wake_enable) | |
47 | { | |
48 | void __iomem *shim_vs = sdw->link_res->shim_vs; | |
49 | u16 wake_en; | |
50 | u16 wake_sts; | |
51 | ||
52 | wake_en = intel_readw(shim_vs, SDW_SHIM2_INTEL_VS_WAKEEN); | |
53 | ||
54 | if (wake_enable) { | |
55 | /* Enable the wakeup */ | |
56 | wake_en |= SDW_SHIM2_INTEL_VS_WAKEEN_PWE; | |
57 | intel_writew(shim_vs, SDW_SHIM2_INTEL_VS_WAKEEN, wake_en); | |
58 | } else { | |
59 | /* Disable the wake up interrupt */ | |
60 | wake_en &= ~SDW_SHIM2_INTEL_VS_WAKEEN_PWE; | |
61 | intel_writew(shim_vs, SDW_SHIM2_INTEL_VS_WAKEEN, wake_en); | |
62 | ||
63 | /* Clear wake status (W1C) */ | |
64 | wake_sts = intel_readw(shim_vs, SDW_SHIM2_INTEL_VS_WAKESTS); | |
65 | wake_sts |= SDW_SHIM2_INTEL_VS_WAKEEN_PWS; | |
66 | intel_writew(shim_vs, SDW_SHIM2_INTEL_VS_WAKESTS, wake_sts); | |
67 | } | |
68 | } | |
69 | ||
806f5abd PLB |
70 | static int intel_link_power_up(struct sdw_intel *sdw) |
71 | { | |
d3565643 PLB |
72 | struct sdw_bus *bus = &sdw->cdns.bus; |
73 | struct sdw_master_prop *prop = &bus->prop; | |
74 | u32 *shim_mask = sdw->link_res->shim_mask; | |
75 | unsigned int link_id = sdw->instance; | |
76 | u32 syncprd; | |
806f5abd PLB |
77 | int ret; |
78 | ||
79 | mutex_lock(sdw->link_res->shim_lock); | |
80 | ||
d3565643 PLB |
81 | if (!*shim_mask) { |
82 | /* we first need to program the SyncPRD/CPU registers */ | |
83 | dev_dbg(sdw->cdns.dev, "first link up, programming SYNCPRD\n"); | |
84 | ||
85 | if (prop->mclk_freq % 6000000) | |
86 | syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4; | |
87 | else | |
88 | syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24; | |
89 | ||
90 | ret = hdac_bus_eml_sdw_set_syncprd_unlocked(sdw->link_res->hbus, syncprd); | |
91 | if (ret < 0) { | |
92 | dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_set_syncprd failed: %d\n", | |
93 | __func__, ret); | |
94 | goto out; | |
95 | } | |
96 | } | |
97 | ||
98 | ret = hdac_bus_eml_sdw_power_up_unlocked(sdw->link_res->hbus, link_id); | |
806f5abd PLB |
99 | if (ret < 0) { |
100 | dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_power_up failed: %d\n", | |
101 | __func__, ret); | |
102 | goto out; | |
103 | } | |
104 | ||
d3565643 PLB |
105 | if (!*shim_mask) { |
106 | /* SYNCPU will change once link is active */ | |
107 | ret = hdac_bus_eml_sdw_wait_syncpu_unlocked(sdw->link_res->hbus); | |
108 | if (ret < 0) { | |
109 | dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_wait_syncpu failed: %d\n", | |
110 | __func__, ret); | |
111 | goto out; | |
112 | } | |
113 | } | |
114 | ||
115 | *shim_mask |= BIT(link_id); | |
116 | ||
806f5abd | 117 | sdw->cdns.link_up = true; |
f40bb244 PLB |
118 | |
119 | intel_shim_vs_init(sdw); | |
120 | ||
806f5abd PLB |
121 | out: |
122 | mutex_unlock(sdw->link_res->shim_lock); | |
123 | ||
124 | return ret; | |
125 | } | |
126 | ||
127 | static int intel_link_power_down(struct sdw_intel *sdw) | |
128 | { | |
d3565643 PLB |
129 | u32 *shim_mask = sdw->link_res->shim_mask; |
130 | unsigned int link_id = sdw->instance; | |
806f5abd PLB |
131 | int ret; |
132 | ||
133 | mutex_lock(sdw->link_res->shim_lock); | |
134 | ||
135 | sdw->cdns.link_up = false; | |
136 | ||
d3565643 PLB |
137 | *shim_mask &= ~BIT(link_id); |
138 | ||
139 | ret = hdac_bus_eml_sdw_power_down_unlocked(sdw->link_res->hbus, link_id); | |
806f5abd PLB |
140 | if (ret < 0) { |
141 | dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_power_down failed: %d\n", | |
142 | __func__, ret); | |
143 | ||
144 | /* | |
145 | * we leave the sdw->cdns.link_up flag as false since we've disabled | |
146 | * the link at this point and cannot handle interrupts any longer. | |
147 | */ | |
148 | } | |
149 | ||
150 | mutex_unlock(sdw->link_res->shim_lock); | |
151 | ||
152 | return ret; | |
153 | } | |
154 | ||
4d1e2464 PLB |
155 | static void intel_sync_arm(struct sdw_intel *sdw) |
156 | { | |
157 | unsigned int link_id = sdw->instance; | |
158 | ||
159 | mutex_lock(sdw->link_res->shim_lock); | |
160 | ||
161 | hdac_bus_eml_sdw_sync_arm_unlocked(sdw->link_res->hbus, link_id); | |
162 | ||
163 | mutex_unlock(sdw->link_res->shim_lock); | |
164 | } | |
165 | ||
166 | static int intel_sync_go_unlocked(struct sdw_intel *sdw) | |
167 | { | |
168 | int ret; | |
169 | ||
170 | ret = hdac_bus_eml_sdw_sync_go_unlocked(sdw->link_res->hbus); | |
171 | if (ret < 0) | |
172 | dev_err(sdw->cdns.dev, "%s: SyncGO clear failed: %d\n", __func__, ret); | |
173 | ||
174 | return ret; | |
175 | } | |
176 | ||
177 | static int intel_sync_go(struct sdw_intel *sdw) | |
178 | { | |
179 | int ret; | |
180 | ||
181 | mutex_lock(sdw->link_res->shim_lock); | |
182 | ||
183 | ret = intel_sync_go_unlocked(sdw); | |
184 | ||
185 | mutex_unlock(sdw->link_res->shim_lock); | |
186 | ||
187 | return ret; | |
188 | } | |
189 | ||
7ba18639 PLB |
190 | static bool intel_check_cmdsync_unlocked(struct sdw_intel *sdw) |
191 | { | |
192 | return hdac_bus_eml_sdw_check_cmdsync_unlocked(sdw->link_res->hbus); | |
193 | } | |
194 | ||
8c4c9a9a PLB |
195 | /* DAI callbacks */ |
196 | static int intel_params_stream(struct sdw_intel *sdw, | |
197 | struct snd_pcm_substream *substream, | |
198 | struct snd_soc_dai *dai, | |
199 | struct snd_pcm_hw_params *hw_params, | |
200 | int link_id, int alh_stream_id) | |
201 | { | |
202 | struct sdw_intel_link_res *res = sdw->link_res; | |
203 | struct sdw_intel_stream_params_data params_data; | |
204 | ||
205 | params_data.substream = substream; | |
206 | params_data.dai = dai; | |
207 | params_data.hw_params = hw_params; | |
208 | params_data.link_id = link_id; | |
209 | params_data.alh_stream_id = alh_stream_id; | |
210 | ||
211 | if (res->ops && res->ops->params_stream && res->dev) | |
212 | return res->ops->params_stream(res->dev, | |
213 | ¶ms_data); | |
214 | return -EIO; | |
215 | } | |
216 | ||
217 | static int intel_free_stream(struct sdw_intel *sdw, | |
218 | struct snd_pcm_substream *substream, | |
219 | struct snd_soc_dai *dai, | |
220 | int link_id) | |
221 | ||
222 | { | |
223 | struct sdw_intel_link_res *res = sdw->link_res; | |
224 | struct sdw_intel_stream_free_data free_data; | |
225 | ||
226 | free_data.substream = substream; | |
227 | free_data.dai = dai; | |
228 | free_data.link_id = link_id; | |
229 | ||
230 | if (res->ops && res->ops->free_stream && res->dev) | |
231 | return res->ops->free_stream(res->dev, | |
232 | &free_data); | |
233 | ||
234 | return 0; | |
235 | } | |
236 | ||
d2f0daf6 PLB |
237 | /* |
238 | * DAI operations | |
239 | */ | |
8c4c9a9a PLB |
240 | static int intel_hw_params(struct snd_pcm_substream *substream, |
241 | struct snd_pcm_hw_params *params, | |
242 | struct snd_soc_dai *dai) | |
243 | { | |
244 | struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); | |
245 | struct sdw_intel *sdw = cdns_to_intel(cdns); | |
246 | struct sdw_cdns_dai_runtime *dai_runtime; | |
247 | struct sdw_cdns_pdi *pdi; | |
248 | struct sdw_stream_config sconfig; | |
249 | struct sdw_port_config *pconfig; | |
250 | int ch, dir; | |
251 | int ret; | |
252 | ||
253 | dai_runtime = cdns->dai_runtime_array[dai->id]; | |
254 | if (!dai_runtime) | |
255 | return -EIO; | |
256 | ||
257 | ch = params_channels(params); | |
258 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
259 | dir = SDW_DATA_DIR_RX; | |
260 | else | |
261 | dir = SDW_DATA_DIR_TX; | |
262 | ||
263 | pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, ch, dir, dai->id); | |
264 | ||
265 | if (!pdi) { | |
266 | ret = -EINVAL; | |
267 | goto error; | |
268 | } | |
269 | ||
270 | /* the SHIM will be configured in the callback functions */ | |
271 | ||
272 | sdw_cdns_config_stream(cdns, ch, dir, pdi); | |
273 | ||
274 | /* store pdi and state, may be needed in prepare step */ | |
275 | dai_runtime->paused = false; | |
276 | dai_runtime->suspended = false; | |
277 | dai_runtime->pdi = pdi; | |
278 | ||
279 | /* Inform DSP about PDI stream number */ | |
280 | ret = intel_params_stream(sdw, substream, dai, params, | |
281 | sdw->instance, | |
282 | pdi->intel_alh_id); | |
283 | if (ret) | |
284 | goto error; | |
285 | ||
286 | sconfig.direction = dir; | |
287 | sconfig.ch_count = ch; | |
288 | sconfig.frame_rate = params_rate(params); | |
289 | sconfig.type = dai_runtime->stream_type; | |
290 | ||
291 | sconfig.bps = snd_pcm_format_width(params_format(params)); | |
292 | ||
293 | /* Port configuration */ | |
294 | pconfig = kzalloc(sizeof(*pconfig), GFP_KERNEL); | |
295 | if (!pconfig) { | |
296 | ret = -ENOMEM; | |
297 | goto error; | |
298 | } | |
299 | ||
300 | pconfig->num = pdi->num; | |
301 | pconfig->ch_mask = (1 << ch) - 1; | |
302 | ||
303 | ret = sdw_stream_add_master(&cdns->bus, &sconfig, | |
304 | pconfig, 1, dai_runtime->stream); | |
305 | if (ret) | |
306 | dev_err(cdns->dev, "add master to stream failed:%d\n", ret); | |
307 | ||
308 | kfree(pconfig); | |
309 | error: | |
310 | return ret; | |
311 | } | |
312 | ||
313 | static int intel_prepare(struct snd_pcm_substream *substream, | |
314 | struct snd_soc_dai *dai) | |
315 | { | |
316 | struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); | |
317 | struct sdw_intel *sdw = cdns_to_intel(cdns); | |
318 | struct sdw_cdns_dai_runtime *dai_runtime; | |
319 | int ch, dir; | |
320 | int ret = 0; | |
321 | ||
322 | dai_runtime = cdns->dai_runtime_array[dai->id]; | |
323 | if (!dai_runtime) { | |
324 | dev_err(dai->dev, "failed to get dai runtime in %s\n", | |
325 | __func__); | |
326 | return -EIO; | |
327 | } | |
328 | ||
329 | if (dai_runtime->suspended) { | |
330 | struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); | |
331 | struct snd_pcm_hw_params *hw_params; | |
332 | ||
333 | hw_params = &rtd->dpcm[substream->stream].hw_params; | |
334 | ||
335 | dai_runtime->suspended = false; | |
336 | ||
337 | /* | |
338 | * .prepare() is called after system resume, where we | |
339 | * need to reinitialize the SHIM/ALH/Cadence IP. | |
340 | * .prepare() is also called to deal with underflows, | |
341 | * but in those cases we cannot touch ALH/SHIM | |
342 | * registers | |
343 | */ | |
344 | ||
345 | /* configure stream */ | |
346 | ch = params_channels(hw_params); | |
347 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
348 | dir = SDW_DATA_DIR_RX; | |
349 | else | |
350 | dir = SDW_DATA_DIR_TX; | |
351 | ||
352 | /* the SHIM will be configured in the callback functions */ | |
353 | ||
354 | sdw_cdns_config_stream(cdns, ch, dir, dai_runtime->pdi); | |
355 | ||
356 | /* Inform DSP about PDI stream number */ | |
357 | ret = intel_params_stream(sdw, substream, dai, | |
358 | hw_params, | |
359 | sdw->instance, | |
360 | dai_runtime->pdi->intel_alh_id); | |
361 | } | |
362 | ||
363 | return ret; | |
364 | } | |
365 | ||
366 | static int | |
367 | intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) | |
368 | { | |
369 | struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); | |
370 | struct sdw_intel *sdw = cdns_to_intel(cdns); | |
371 | struct sdw_cdns_dai_runtime *dai_runtime; | |
372 | int ret; | |
373 | ||
374 | dai_runtime = cdns->dai_runtime_array[dai->id]; | |
375 | if (!dai_runtime) | |
376 | return -EIO; | |
377 | ||
378 | /* | |
379 | * The sdw stream state will transition to RELEASED when stream-> | |
380 | * master_list is empty. So the stream state will transition to | |
381 | * DEPREPARED for the first cpu-dai and to RELEASED for the last | |
382 | * cpu-dai. | |
383 | */ | |
384 | ret = sdw_stream_remove_master(&cdns->bus, dai_runtime->stream); | |
385 | if (ret < 0) { | |
386 | dev_err(dai->dev, "remove master from stream %s failed: %d\n", | |
387 | dai_runtime->stream->name, ret); | |
388 | return ret; | |
389 | } | |
390 | ||
391 | ret = intel_free_stream(sdw, substream, dai, sdw->instance); | |
392 | if (ret < 0) { | |
393 | dev_err(dai->dev, "intel_free_stream: failed %d\n", ret); | |
394 | return ret; | |
395 | } | |
396 | ||
397 | dai_runtime->pdi = NULL; | |
398 | ||
399 | return 0; | |
400 | } | |
401 | ||
402 | static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai, | |
403 | void *stream, int direction) | |
404 | { | |
405 | return cdns_set_sdw_stream(dai, stream, direction); | |
406 | } | |
407 | ||
408 | static void *intel_get_sdw_stream(struct snd_soc_dai *dai, | |
409 | int direction) | |
410 | { | |
411 | struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); | |
412 | struct sdw_cdns_dai_runtime *dai_runtime; | |
413 | ||
414 | dai_runtime = cdns->dai_runtime_array[dai->id]; | |
415 | if (!dai_runtime) | |
416 | return ERR_PTR(-EINVAL); | |
417 | ||
418 | return dai_runtime->stream; | |
419 | } | |
420 | ||
421 | static int intel_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai) | |
422 | { | |
423 | struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); | |
424 | struct sdw_intel *sdw = cdns_to_intel(cdns); | |
425 | struct sdw_intel_link_res *res = sdw->link_res; | |
426 | struct sdw_cdns_dai_runtime *dai_runtime; | |
427 | int ret = 0; | |
428 | ||
429 | /* | |
430 | * The .trigger callback is used to program HDaudio DMA and send required IPC to audio | |
431 | * firmware. | |
432 | */ | |
433 | if (res->ops && res->ops->trigger) { | |
434 | ret = res->ops->trigger(substream, cmd, dai); | |
435 | if (ret < 0) | |
436 | return ret; | |
437 | } | |
438 | ||
439 | dai_runtime = cdns->dai_runtime_array[dai->id]; | |
440 | if (!dai_runtime) { | |
441 | dev_err(dai->dev, "failed to get dai runtime in %s\n", | |
442 | __func__); | |
443 | return -EIO; | |
444 | } | |
445 | ||
446 | switch (cmd) { | |
447 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
448 | ||
449 | /* | |
450 | * The .prepare callback is used to deal with xruns and resume operations. | |
451 | * In the case of xruns, the DMAs and SHIM registers cannot be touched, | |
452 | * but for resume operations the DMAs and SHIM registers need to be initialized. | |
453 | * the .trigger callback is used to track the suspend case only. | |
454 | */ | |
455 | ||
456 | dai_runtime->suspended = true; | |
457 | ||
458 | break; | |
459 | ||
460 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
461 | dai_runtime->paused = true; | |
462 | break; | |
463 | case SNDRV_PCM_TRIGGER_STOP: | |
464 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
465 | dai_runtime->paused = false; | |
466 | break; | |
467 | default: | |
468 | break; | |
469 | } | |
470 | ||
471 | return ret; | |
472 | } | |
473 | ||
d2f0daf6 | 474 | static const struct snd_soc_dai_ops intel_pcm_dai_ops = { |
8c4c9a9a PLB |
475 | .hw_params = intel_hw_params, |
476 | .prepare = intel_prepare, | |
477 | .hw_free = intel_hw_free, | |
478 | .trigger = intel_trigger, | |
479 | .set_stream = intel_pcm_set_sdw_stream, | |
480 | .get_stream = intel_get_sdw_stream, | |
d2f0daf6 PLB |
481 | }; |
482 | ||
483 | static const struct snd_soc_component_driver dai_component = { | |
484 | .name = "soundwire", | |
485 | }; | |
486 | ||
487 | /* | |
488 | * PDI routines | |
489 | */ | |
490 | static void intel_pdi_init(struct sdw_intel *sdw, | |
491 | struct sdw_cdns_stream_config *config) | |
492 | { | |
493 | void __iomem *shim = sdw->link_res->shim; | |
494 | int pcm_cap; | |
495 | ||
496 | /* PCM Stream Capability */ | |
497 | pcm_cap = intel_readw(shim, SDW_SHIM2_PCMSCAP); | |
498 | ||
499 | config->pcm_bd = FIELD_GET(SDW_SHIM2_PCMSCAP_BSS, pcm_cap); | |
500 | config->pcm_in = FIELD_GET(SDW_SHIM2_PCMSCAP_ISS, pcm_cap); | |
501 | config->pcm_out = FIELD_GET(SDW_SHIM2_PCMSCAP_ISS, pcm_cap); | |
502 | ||
503 | dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n", | |
504 | config->pcm_bd, config->pcm_in, config->pcm_out); | |
505 | } | |
506 | ||
507 | static int | |
508 | intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num) | |
509 | { | |
510 | void __iomem *shim = sdw->link_res->shim; | |
511 | ||
512 | /* zero based values for channel count in register */ | |
513 | return intel_readw(shim, SDW_SHIM2_PCMSYCHC(pdi_num)) + 1; | |
514 | } | |
515 | ||
516 | static void intel_pdi_get_ch_update(struct sdw_intel *sdw, | |
517 | struct sdw_cdns_pdi *pdi, | |
518 | unsigned int num_pdi, | |
519 | unsigned int *num_ch) | |
520 | { | |
521 | int ch_count = 0; | |
522 | int i; | |
523 | ||
524 | for (i = 0; i < num_pdi; i++) { | |
525 | pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num); | |
526 | ch_count += pdi->ch_count; | |
527 | pdi++; | |
528 | } | |
529 | ||
530 | *num_ch = ch_count; | |
531 | } | |
532 | ||
533 | static void intel_pdi_stream_ch_update(struct sdw_intel *sdw, | |
534 | struct sdw_cdns_streams *stream) | |
535 | { | |
536 | intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd, | |
537 | &stream->num_ch_bd); | |
538 | ||
539 | intel_pdi_get_ch_update(sdw, stream->in, stream->num_in, | |
540 | &stream->num_ch_in); | |
541 | ||
542 | intel_pdi_get_ch_update(sdw, stream->out, stream->num_out, | |
543 | &stream->num_ch_out); | |
544 | } | |
545 | ||
546 | static int intel_create_dai(struct sdw_cdns *cdns, | |
547 | struct snd_soc_dai_driver *dais, | |
548 | enum intel_pdi_type type, | |
549 | u32 num, u32 off, u32 max_ch) | |
550 | { | |
551 | int i; | |
552 | ||
553 | if (!num) | |
554 | return 0; | |
555 | ||
556 | for (i = off; i < (off + num); i++) { | |
557 | dais[i].name = devm_kasprintf(cdns->dev, GFP_KERNEL, | |
558 | "SDW%d Pin%d", | |
559 | cdns->instance, i); | |
560 | if (!dais[i].name) | |
561 | return -ENOMEM; | |
562 | ||
563 | if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) { | |
564 | dais[i].playback.channels_min = 1; | |
565 | dais[i].playback.channels_max = max_ch; | |
566 | } | |
567 | ||
568 | if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) { | |
569 | dais[i].capture.channels_min = 1; | |
570 | dais[i].capture.channels_max = max_ch; | |
571 | } | |
572 | ||
573 | dais[i].ops = &intel_pcm_dai_ops; | |
574 | } | |
575 | ||
576 | return 0; | |
577 | } | |
578 | ||
579 | static int intel_register_dai(struct sdw_intel *sdw) | |
580 | { | |
581 | struct sdw_cdns_dai_runtime **dai_runtime_array; | |
582 | struct sdw_cdns_stream_config config; | |
583 | struct sdw_cdns *cdns = &sdw->cdns; | |
584 | struct sdw_cdns_streams *stream; | |
585 | struct snd_soc_dai_driver *dais; | |
586 | int num_dai; | |
587 | int ret; | |
588 | int off = 0; | |
589 | ||
590 | /* Read the PDI config and initialize cadence PDI */ | |
591 | intel_pdi_init(sdw, &config); | |
592 | ret = sdw_cdns_pdi_init(cdns, config); | |
593 | if (ret) | |
594 | return ret; | |
595 | ||
596 | intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm); | |
597 | ||
598 | /* DAIs are created based on total number of PDIs supported */ | |
599 | num_dai = cdns->pcm.num_pdi; | |
600 | ||
601 | dai_runtime_array = devm_kcalloc(cdns->dev, num_dai, | |
602 | sizeof(struct sdw_cdns_dai_runtime *), | |
603 | GFP_KERNEL); | |
604 | if (!dai_runtime_array) | |
605 | return -ENOMEM; | |
606 | cdns->dai_runtime_array = dai_runtime_array; | |
607 | ||
608 | dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL); | |
609 | if (!dais) | |
610 | return -ENOMEM; | |
611 | ||
612 | /* Create PCM DAIs */ | |
613 | stream = &cdns->pcm; | |
614 | ||
615 | ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pcm.num_in, | |
616 | off, stream->num_ch_in); | |
617 | if (ret) | |
618 | return ret; | |
619 | ||
620 | off += cdns->pcm.num_in; | |
621 | ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out, | |
622 | off, stream->num_ch_out); | |
623 | if (ret) | |
624 | return ret; | |
625 | ||
626 | off += cdns->pcm.num_out; | |
627 | ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd, | |
628 | off, stream->num_ch_bd); | |
629 | if (ret) | |
630 | return ret; | |
631 | ||
632 | return devm_snd_soc_register_component(cdns->dev, &dai_component, | |
633 | dais, num_dai); | |
634 | } | |
635 | ||
bcf71917 PLB |
636 | static void intel_program_sdi(struct sdw_intel *sdw, int dev_num) |
637 | { | |
638 | int ret; | |
639 | ||
640 | ret = hdac_bus_eml_sdw_set_lsdiid(sdw->link_res->hbus, sdw->instance, dev_num); | |
641 | if (ret < 0) | |
642 | dev_err(sdw->cdns.dev, "%s: could not set lsdiid for link %d %d\n", | |
643 | __func__, sdw->instance, dev_num); | |
644 | } | |
645 | ||
6f23f4e2 | 646 | const struct sdw_intel_hw_ops sdw_intel_lnl_hw_ops = { |
312316d5 PLB |
647 | .debugfs_init = intel_ace2x_debugfs_init, |
648 | .debugfs_exit = intel_ace2x_debugfs_exit, | |
806f5abd | 649 | |
d2f0daf6 PLB |
650 | .register_dai = intel_register_dai, |
651 | ||
f90ba301 PLB |
652 | .check_clock_stop = intel_check_clock_stop, |
653 | .start_bus = intel_start_bus, | |
654 | .start_bus_after_reset = intel_start_bus_after_reset, | |
655 | .start_bus_after_clock_stop = intel_start_bus_after_clock_stop, | |
656 | .stop_bus = intel_stop_bus, | |
657 | ||
806f5abd PLB |
658 | .link_power_up = intel_link_power_up, |
659 | .link_power_down = intel_link_power_down, | |
4d1e2464 | 660 | |
b8e39bc4 PLB |
661 | .shim_check_wake = intel_shim_check_wake, |
662 | .shim_wake = intel_shim_wake, | |
663 | ||
32c3aa85 PLB |
664 | .pre_bank_switch = intel_pre_bank_switch, |
665 | .post_bank_switch = intel_post_bank_switch, | |
666 | ||
4d1e2464 PLB |
667 | .sync_arm = intel_sync_arm, |
668 | .sync_go_unlocked = intel_sync_go_unlocked, | |
669 | .sync_go = intel_sync_go, | |
7ba18639 | 670 | .sync_check_cmdsync_unlocked = intel_check_cmdsync_unlocked, |
bcf71917 PLB |
671 | |
672 | .program_sdi = intel_program_sdi, | |
6f23f4e2 PLB |
673 | }; |
674 | EXPORT_SYMBOL_NS(sdw_intel_lnl_hw_ops, SOUNDWIRE_INTEL); | |
806f5abd PLB |
675 | |
676 | MODULE_IMPORT_NS(SND_SOC_SOF_HDA_MLINK); |