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23859465 PLB |
1 | /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ |
2 | /* Copyright(c) 2015-17 Intel Corporation. */ | |
71bb8a1b VK |
3 | |
4 | #ifndef __SDW_INTEL_LOCAL_H | |
5 | #define __SDW_INTEL_LOCAL_H | |
6 | ||
7 | /** | |
f98f690f PLB |
8 | * struct sdw_intel_link_res - Soundwire Intel link resource structure, |
9 | * typically populated by the controller driver. | |
b3ad31f3 | 10 | * @hw_ops: platform-specific ops |
f98f690f | 11 | * @mmio_base: mmio base of SoundWire registers |
71bb8a1b VK |
12 | * @registers: Link IO registers base |
13 | * @shim: Audio shim pointer | |
14 | * @alh: ALH (Audio Link Hub) pointer | |
15 | * @irq: Interrupt line | |
c46302ec | 16 | * @ops: Shim callback ops |
4b206d34 | 17 | * @dev: device implementing hw_params and free callbacks |
4a17c441 PLB |
18 | * @shim_lock: mutex to handle access to shared SHIM registers |
19 | * @shim_mask: global pointer to check SHIM register initialization | |
a320f41e | 20 | * @clock_stop_quirks: mask defining requested behavior on pm_suspend |
de763fa8 | 21 | * @link_mask: global mask needed for power-up/down sequences |
4a98a6b2 BL |
22 | * @cdns: Cadence master descriptor |
23 | * @list: used to walk-through all masters exposed by the same controller | |
71bb8a1b VK |
24 | */ |
25 | struct sdw_intel_link_res { | |
b3ad31f3 PLB |
26 | const struct sdw_intel_hw_ops *hw_ops; |
27 | ||
f98f690f | 28 | void __iomem *mmio_base; /* not strictly needed, useful for debug */ |
71bb8a1b VK |
29 | void __iomem *registers; |
30 | void __iomem *shim; | |
31 | void __iomem *alh; | |
32 | int irq; | |
c46302ec | 33 | const struct sdw_intel_ops *ops; |
4b206d34 | 34 | struct device *dev; |
4a17c441 PLB |
35 | struct mutex *shim_lock; /* protect shared registers */ |
36 | u32 *shim_mask; | |
a320f41e | 37 | u32 clock_stop_quirks; |
de763fa8 | 38 | u32 link_mask; |
4a98a6b2 BL |
39 | struct sdw_cdns *cdns; |
40 | struct list_head list; | |
71bb8a1b VK |
41 | }; |
42 | ||
b6109dd6 PLB |
43 | struct sdw_intel { |
44 | struct sdw_cdns cdns; | |
45 | int instance; | |
46 | struct sdw_intel_link_res *link_res; | |
e4401abb | 47 | bool startup_done; |
b6109dd6 PLB |
48 | #ifdef CONFIG_DEBUG_FS |
49 | struct dentry *debugfs; | |
50 | #endif | |
51 | }; | |
52 | ||
7cbf00bd | 53 | #define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns) |
29a269c6 | 54 | |
7cbf00bd | 55 | #define INTEL_MASTER_RESET_ITERATIONS 10 |
6d2c6669 | 56 | |
fb2dc6a0 PLB |
57 | #define SDW_INTEL_CHECK_OPS(sdw, cb) ((sdw) && (sdw)->link_res && (sdw)->link_res->hw_ops && \ |
58 | (sdw)->link_res->hw_ops->cb) | |
59 | #define SDW_INTEL_OPS(sdw, cb) ((sdw)->link_res->hw_ops->cb) | |
60 | ||
61 | static inline void sdw_intel_debugfs_init(struct sdw_intel *sdw) | |
62 | { | |
63 | if (SDW_INTEL_CHECK_OPS(sdw, debugfs_init)) | |
64 | SDW_INTEL_OPS(sdw, debugfs_init)(sdw); | |
65 | } | |
66 | ||
67 | static inline void sdw_intel_debugfs_exit(struct sdw_intel *sdw) | |
68 | { | |
69 | if (SDW_INTEL_CHECK_OPS(sdw, debugfs_exit)) | |
70 | SDW_INTEL_OPS(sdw, debugfs_exit)(sdw); | |
71 | } | |
72 | ||
b6234bcc PLB |
73 | static inline int sdw_intel_register_dai(struct sdw_intel *sdw) |
74 | { | |
75 | if (SDW_INTEL_CHECK_OPS(sdw, register_dai)) | |
76 | return SDW_INTEL_OPS(sdw, register_dai)(sdw); | |
77 | return -ENOTSUPP; | |
78 | } | |
79 | ||
3db0c5a6 PLB |
80 | static inline void sdw_intel_check_clock_stop(struct sdw_intel *sdw) |
81 | { | |
82 | if (SDW_INTEL_CHECK_OPS(sdw, check_clock_stop)) | |
83 | SDW_INTEL_OPS(sdw, check_clock_stop)(sdw); | |
84 | } | |
85 | ||
86 | static inline int sdw_intel_start_bus(struct sdw_intel *sdw) | |
87 | { | |
88 | if (SDW_INTEL_CHECK_OPS(sdw, start_bus)) | |
89 | return SDW_INTEL_OPS(sdw, start_bus)(sdw); | |
90 | return -ENOTSUPP; | |
91 | } | |
92 | ||
93 | static inline int sdw_intel_start_bus_after_reset(struct sdw_intel *sdw) | |
94 | { | |
95 | if (SDW_INTEL_CHECK_OPS(sdw, start_bus_after_reset)) | |
96 | return SDW_INTEL_OPS(sdw, start_bus_after_reset)(sdw); | |
97 | return -ENOTSUPP; | |
98 | } | |
99 | ||
100 | static inline int sdw_intel_start_bus_after_clock_stop(struct sdw_intel *sdw) | |
101 | { | |
102 | if (SDW_INTEL_CHECK_OPS(sdw, start_bus_after_clock_stop)) | |
103 | return SDW_INTEL_OPS(sdw, start_bus_after_clock_stop)(sdw); | |
104 | return -ENOTSUPP; | |
105 | } | |
106 | ||
107 | static inline int sdw_intel_stop_bus(struct sdw_intel *sdw, bool clock_stop) | |
108 | { | |
109 | if (SDW_INTEL_CHECK_OPS(sdw, stop_bus)) | |
110 | return SDW_INTEL_OPS(sdw, stop_bus)(sdw, clock_stop); | |
111 | return -ENOTSUPP; | |
112 | } | |
113 | ||
49c9ff45 PLB |
114 | static inline int sdw_intel_link_power_up(struct sdw_intel *sdw) |
115 | { | |
116 | if (SDW_INTEL_CHECK_OPS(sdw, link_power_up)) | |
117 | return SDW_INTEL_OPS(sdw, link_power_up)(sdw); | |
118 | return -ENOTSUPP; | |
119 | } | |
120 | ||
121 | static inline int sdw_intel_link_power_down(struct sdw_intel *sdw) | |
122 | { | |
123 | if (SDW_INTEL_CHECK_OPS(sdw, link_power_down)) | |
124 | return SDW_INTEL_OPS(sdw, link_power_down)(sdw); | |
125 | return -ENOTSUPP; | |
126 | } | |
127 | ||
36e3b385 PLB |
128 | static inline int sdw_intel_shim_check_wake(struct sdw_intel *sdw) |
129 | { | |
130 | if (SDW_INTEL_CHECK_OPS(sdw, shim_check_wake)) | |
131 | return SDW_INTEL_OPS(sdw, shim_check_wake)(sdw); | |
132 | return -ENOTSUPP; | |
133 | } | |
134 | ||
135 | static inline void sdw_intel_shim_wake(struct sdw_intel *sdw, bool wake_enable) | |
136 | { | |
137 | if (SDW_INTEL_CHECK_OPS(sdw, shim_wake)) | |
138 | SDW_INTEL_OPS(sdw, shim_wake)(sdw, wake_enable); | |
139 | } | |
140 | ||
71bb8a1b | 141 | #endif /* __SDW_INTEL_LOCAL_H */ |