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23859465 PLB |
1 | /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ |
2 | /* Copyright(c) 2015-17 Intel Corporation. */ | |
71bb8a1b VK |
3 | |
4 | #ifndef __SDW_INTEL_LOCAL_H | |
5 | #define __SDW_INTEL_LOCAL_H | |
6 | ||
881cf1e9 PLB |
7 | struct hdac_bus; |
8 | ||
71bb8a1b | 9 | /** |
f98f690f PLB |
10 | * struct sdw_intel_link_res - Soundwire Intel link resource structure, |
11 | * typically populated by the controller driver. | |
b3ad31f3 | 12 | * @hw_ops: platform-specific ops |
f98f690f | 13 | * @mmio_base: mmio base of SoundWire registers |
71bb8a1b | 14 | * @registers: Link IO registers base |
e40e0e11 | 15 | * @ip_offset: offset for MCP_IP registers |
71bb8a1b | 16 | * @shim: Audio shim pointer |
6ab915b9 | 17 | * @shim_vs: Audio vendor-specific shim pointer |
71bb8a1b VK |
18 | * @alh: ALH (Audio Link Hub) pointer |
19 | * @irq: Interrupt line | |
c46302ec | 20 | * @ops: Shim callback ops |
4b206d34 | 21 | * @dev: device implementing hw_params and free callbacks |
4a17c441 PLB |
22 | * @shim_lock: mutex to handle access to shared SHIM registers |
23 | * @shim_mask: global pointer to check SHIM register initialization | |
a320f41e | 24 | * @clock_stop_quirks: mask defining requested behavior on pm_suspend |
de763fa8 | 25 | * @link_mask: global mask needed for power-up/down sequences |
4a98a6b2 BL |
26 | * @cdns: Cadence master descriptor |
27 | * @list: used to walk-through all masters exposed by the same controller | |
881cf1e9 | 28 | * @hbus: hdac_bus pointer, needed for power management |
71bb8a1b VK |
29 | */ |
30 | struct sdw_intel_link_res { | |
b3ad31f3 PLB |
31 | const struct sdw_intel_hw_ops *hw_ops; |
32 | ||
f98f690f | 33 | void __iomem *mmio_base; /* not strictly needed, useful for debug */ |
71bb8a1b | 34 | void __iomem *registers; |
e40e0e11 | 35 | u32 ip_offset; |
71bb8a1b | 36 | void __iomem *shim; |
6ab915b9 | 37 | void __iomem *shim_vs; |
71bb8a1b VK |
38 | void __iomem *alh; |
39 | int irq; | |
c46302ec | 40 | const struct sdw_intel_ops *ops; |
4b206d34 | 41 | struct device *dev; |
4a17c441 PLB |
42 | struct mutex *shim_lock; /* protect shared registers */ |
43 | u32 *shim_mask; | |
a320f41e | 44 | u32 clock_stop_quirks; |
de763fa8 | 45 | u32 link_mask; |
4a98a6b2 BL |
46 | struct sdw_cdns *cdns; |
47 | struct list_head list; | |
881cf1e9 | 48 | struct hdac_bus *hbus; |
71bb8a1b VK |
49 | }; |
50 | ||
b6109dd6 PLB |
51 | struct sdw_intel { |
52 | struct sdw_cdns cdns; | |
53 | int instance; | |
54 | struct sdw_intel_link_res *link_res; | |
e4401abb | 55 | bool startup_done; |
b6109dd6 PLB |
56 | #ifdef CONFIG_DEBUG_FS |
57 | struct dentry *debugfs; | |
58 | #endif | |
59 | }; | |
60 | ||
4dd50aff PLB |
61 | enum intel_pdi_type { |
62 | INTEL_PDI_IN = 0, | |
63 | INTEL_PDI_OUT = 1, | |
64 | INTEL_PDI_BD = 2, | |
65 | }; | |
66 | ||
67 | /* | |
68 | * Read, write helpers for HW registers | |
69 | */ | |
70 | static inline int intel_readl(void __iomem *base, int offset) | |
71 | { | |
72 | return readl(base + offset); | |
73 | } | |
74 | ||
75 | static inline void intel_writel(void __iomem *base, int offset, int value) | |
76 | { | |
77 | writel(value, base + offset); | |
78 | } | |
79 | ||
80 | static inline u16 intel_readw(void __iomem *base, int offset) | |
81 | { | |
82 | return readw(base + offset); | |
83 | } | |
84 | ||
85 | static inline void intel_writew(void __iomem *base, int offset, u16 value) | |
86 | { | |
87 | writew(value, base + offset); | |
88 | } | |
89 | ||
7cbf00bd | 90 | #define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns) |
29a269c6 | 91 | |
7cbf00bd | 92 | #define INTEL_MASTER_RESET_ITERATIONS 10 |
6d2c6669 | 93 | |
fb2dc6a0 PLB |
94 | #define SDW_INTEL_CHECK_OPS(sdw, cb) ((sdw) && (sdw)->link_res && (sdw)->link_res->hw_ops && \ |
95 | (sdw)->link_res->hw_ops->cb) | |
96 | #define SDW_INTEL_OPS(sdw, cb) ((sdw)->link_res->hw_ops->cb) | |
97 | ||
312316d5 PLB |
98 | #ifdef CONFIG_DEBUG_FS |
99 | void intel_ace2x_debugfs_init(struct sdw_intel *sdw); | |
100 | void intel_ace2x_debugfs_exit(struct sdw_intel *sdw); | |
101 | #else | |
102 | static inline void intel_ace2x_debugfs_init(struct sdw_intel *sdw) {} | |
103 | static inline void intel_ace2x_debugfs_exit(struct sdw_intel *sdw) {} | |
104 | #endif | |
105 | ||
fb2dc6a0 PLB |
106 | static inline void sdw_intel_debugfs_init(struct sdw_intel *sdw) |
107 | { | |
108 | if (SDW_INTEL_CHECK_OPS(sdw, debugfs_init)) | |
109 | SDW_INTEL_OPS(sdw, debugfs_init)(sdw); | |
110 | } | |
111 | ||
112 | static inline void sdw_intel_debugfs_exit(struct sdw_intel *sdw) | |
113 | { | |
114 | if (SDW_INTEL_CHECK_OPS(sdw, debugfs_exit)) | |
115 | SDW_INTEL_OPS(sdw, debugfs_exit)(sdw); | |
116 | } | |
117 | ||
b6234bcc PLB |
118 | static inline int sdw_intel_register_dai(struct sdw_intel *sdw) |
119 | { | |
120 | if (SDW_INTEL_CHECK_OPS(sdw, register_dai)) | |
121 | return SDW_INTEL_OPS(sdw, register_dai)(sdw); | |
122 | return -ENOTSUPP; | |
123 | } | |
124 | ||
3db0c5a6 PLB |
125 | static inline void sdw_intel_check_clock_stop(struct sdw_intel *sdw) |
126 | { | |
127 | if (SDW_INTEL_CHECK_OPS(sdw, check_clock_stop)) | |
128 | SDW_INTEL_OPS(sdw, check_clock_stop)(sdw); | |
129 | } | |
130 | ||
131 | static inline int sdw_intel_start_bus(struct sdw_intel *sdw) | |
132 | { | |
133 | if (SDW_INTEL_CHECK_OPS(sdw, start_bus)) | |
134 | return SDW_INTEL_OPS(sdw, start_bus)(sdw); | |
135 | return -ENOTSUPP; | |
136 | } | |
137 | ||
138 | static inline int sdw_intel_start_bus_after_reset(struct sdw_intel *sdw) | |
139 | { | |
140 | if (SDW_INTEL_CHECK_OPS(sdw, start_bus_after_reset)) | |
141 | return SDW_INTEL_OPS(sdw, start_bus_after_reset)(sdw); | |
142 | return -ENOTSUPP; | |
143 | } | |
144 | ||
145 | static inline int sdw_intel_start_bus_after_clock_stop(struct sdw_intel *sdw) | |
146 | { | |
147 | if (SDW_INTEL_CHECK_OPS(sdw, start_bus_after_clock_stop)) | |
148 | return SDW_INTEL_OPS(sdw, start_bus_after_clock_stop)(sdw); | |
149 | return -ENOTSUPP; | |
150 | } | |
151 | ||
152 | static inline int sdw_intel_stop_bus(struct sdw_intel *sdw, bool clock_stop) | |
153 | { | |
154 | if (SDW_INTEL_CHECK_OPS(sdw, stop_bus)) | |
155 | return SDW_INTEL_OPS(sdw, stop_bus)(sdw, clock_stop); | |
156 | return -ENOTSUPP; | |
157 | } | |
158 | ||
49c9ff45 PLB |
159 | static inline int sdw_intel_link_power_up(struct sdw_intel *sdw) |
160 | { | |
161 | if (SDW_INTEL_CHECK_OPS(sdw, link_power_up)) | |
162 | return SDW_INTEL_OPS(sdw, link_power_up)(sdw); | |
163 | return -ENOTSUPP; | |
164 | } | |
165 | ||
166 | static inline int sdw_intel_link_power_down(struct sdw_intel *sdw) | |
167 | { | |
168 | if (SDW_INTEL_CHECK_OPS(sdw, link_power_down)) | |
169 | return SDW_INTEL_OPS(sdw, link_power_down)(sdw); | |
170 | return -ENOTSUPP; | |
171 | } | |
172 | ||
36e3b385 PLB |
173 | static inline int sdw_intel_shim_check_wake(struct sdw_intel *sdw) |
174 | { | |
175 | if (SDW_INTEL_CHECK_OPS(sdw, shim_check_wake)) | |
176 | return SDW_INTEL_OPS(sdw, shim_check_wake)(sdw); | |
177 | return -ENOTSUPP; | |
178 | } | |
179 | ||
180 | static inline void sdw_intel_shim_wake(struct sdw_intel *sdw, bool wake_enable) | |
181 | { | |
182 | if (SDW_INTEL_CHECK_OPS(sdw, shim_wake)) | |
183 | SDW_INTEL_OPS(sdw, shim_wake)(sdw, wake_enable); | |
184 | } | |
185 | ||
84706e9a PLB |
186 | static inline void sdw_intel_sync_arm(struct sdw_intel *sdw) |
187 | { | |
188 | if (SDW_INTEL_CHECK_OPS(sdw, sync_arm)) | |
189 | SDW_INTEL_OPS(sdw, sync_arm)(sdw); | |
190 | } | |
191 | ||
192 | static inline int sdw_intel_sync_go_unlocked(struct sdw_intel *sdw) | |
193 | { | |
194 | if (SDW_INTEL_CHECK_OPS(sdw, sync_go_unlocked)) | |
195 | return SDW_INTEL_OPS(sdw, sync_go_unlocked)(sdw); | |
196 | return -ENOTSUPP; | |
197 | } | |
198 | ||
199 | static inline int sdw_intel_sync_go(struct sdw_intel *sdw) | |
200 | { | |
201 | if (SDW_INTEL_CHECK_OPS(sdw, sync_go)) | |
202 | return SDW_INTEL_OPS(sdw, sync_go)(sdw); | |
203 | return -ENOTSUPP; | |
204 | } | |
205 | ||
1e76de2e PLB |
206 | static inline bool sdw_intel_sync_check_cmdsync_unlocked(struct sdw_intel *sdw) |
207 | { | |
208 | if (SDW_INTEL_CHECK_OPS(sdw, sync_check_cmdsync_unlocked)) | |
209 | return SDW_INTEL_OPS(sdw, sync_check_cmdsync_unlocked)(sdw); | |
210 | return false; | |
211 | } | |
212 | ||
1a1a6a69 PLB |
213 | /* common bus management */ |
214 | int intel_start_bus(struct sdw_intel *sdw); | |
215 | int intel_start_bus_after_reset(struct sdw_intel *sdw); | |
216 | void intel_check_clock_stop(struct sdw_intel *sdw); | |
217 | int intel_start_bus_after_clock_stop(struct sdw_intel *sdw); | |
218 | int intel_stop_bus(struct sdw_intel *sdw, bool clock_stop); | |
219 | ||
fb43d62e PLB |
220 | /* common bank switch routines */ |
221 | int intel_pre_bank_switch(struct sdw_intel *sdw); | |
222 | int intel_post_bank_switch(struct sdw_intel *sdw); | |
223 | ||
71bb8a1b | 224 | #endif /* __SDW_INTEL_LOCAL_H */ |