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soundwire: intel: remove unused variables
[linux-2.6-block.git] / drivers / soundwire / intel.c
CommitLineData
71bb8a1b
VK		 1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2// Copyright(c) 2015-17 Intel Corporation.
3
4/*
5 * Soundwire Intel Master Driver
6 */
7
8#include <linux/acpi.h>
9#include <linux/delay.h>
4abbd783 10#include <linux/module.h>
71bb8a1b
VK		 11#include <linux/interrupt.h>
12#include <linux/platform_device.h>
37a2d22b
VK		 13#include <sound/pcm_params.h>
14#include <sound/soc.h>
71bb8a1b
VK		 15#include <linux/soundwire/sdw_registers.h>
16#include <linux/soundwire/sdw.h>
17#include <linux/soundwire/sdw_intel.h>
18#include "cadence_master.h"
19#include "intel.h"
20
21/* Intel SHIM Registers Definition */
22#define SDW_SHIM_LCAP 0x0
23#define SDW_SHIM_LCTL 0x4
24#define SDW_SHIM_IPPTR 0x8
25#define SDW_SHIM_SYNC 0xC
26
7cc6e315
PLB		 27#define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x))
28#define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x))
29#define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x))
30#define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x))
31#define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x))
32#define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x))
33
34#define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y)))
35#define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y)))
36#define SDW_SHIM_PDMSCAP(x) (0x062 + 0x60 * (x))
37#define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x))
38#define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x))
71bb8a1b
VK		 39
40#define SDW_SHIM_WAKEEN 0x190
41#define SDW_SHIM_WAKESTS 0x192
42
43#define SDW_SHIM_LCTL_SPA BIT(0)
44#define SDW_SHIM_LCTL_CPA BIT(8)
45
46#define SDW_SHIM_SYNC_SYNCPRD_VAL 0x176F
47#define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0)
48#define SDW_SHIM_SYNC_SYNCCPU BIT(15)
49#define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16)
50#define SDW_SHIM_SYNC_CMDSYNC BIT(16)
51#define SDW_SHIM_SYNC_SYNCGO BIT(24)
52
53#define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0)
54#define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4)
55#define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8)
56
57#define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0)
58#define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4)
59#define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8)
60#define SDW_SHIM_PCMSYCM_DIR BIT(15)
61
62#define SDW_SHIM_PDMSCAP_ISS GENMASK(3, 0)
63#define SDW_SHIM_PDMSCAP_OSS GENMASK(7, 4)
64#define SDW_SHIM_PDMSCAP_BSS GENMASK(12, 8)
65#define SDW_SHIM_PDMSCAP_CPSS GENMASK(15, 13)
66
67#define SDW_SHIM_IOCTL_MIF BIT(0)
68#define SDW_SHIM_IOCTL_CO BIT(1)
69#define SDW_SHIM_IOCTL_COE BIT(2)
70#define SDW_SHIM_IOCTL_DO BIT(3)
71#define SDW_SHIM_IOCTL_DOE BIT(4)
72#define SDW_SHIM_IOCTL_BKE BIT(5)
73#define SDW_SHIM_IOCTL_WPDD BIT(6)
74#define SDW_SHIM_IOCTL_CIBD BIT(8)
75#define SDW_SHIM_IOCTL_DIBD BIT(9)
76
77#define SDW_SHIM_CTMCTL_DACTQE BIT(0)
78#define SDW_SHIM_CTMCTL_DODS BIT(1)
79#define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3)
80
81#define SDW_SHIM_WAKEEN_ENABLE BIT(0)
82#define SDW_SHIM_WAKESTS_STATUS BIT(0)
83
84/* Intel ALH Register definitions */
7cc6e315 85#define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x)))
71bb8a1b
VK		 86
87#define SDW_ALH_STRMZCFG_DMAT_VAL 0x3
88#define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0)
89#define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16)
90
c46302ec
VK		 91enum intel_pdi_type {
92 INTEL_PDI_IN = 0,
93 INTEL_PDI_OUT = 1,
94 INTEL_PDI_BD = 2,
95};
96
71bb8a1b
VK		 97struct sdw_intel {
98 struct sdw_cdns cdns;
99 int instance;
100 struct sdw_intel_link_res *res;
101};
102
103#define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns)
104
105/*
106 * Read, write helpers for HW registers
107 */
108static inline int intel_readl(void __iomem *base, int offset)
109{
110 return readl(base + offset);
111}
112
113static inline void intel_writel(void __iomem *base, int offset, int value)
114{
115 writel(value, base + offset);
116}
117
118static inline u16 intel_readw(void __iomem *base, int offset)
119{
120 return readw(base + offset);
121}
122
123static inline void intel_writew(void __iomem *base, int offset, u16 value)
124{
125 writew(value, base + offset);
126}
127
128static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask)
129{
130 int timeout = 10;
131 u32 reg_read;
132
133 writel(value, base + offset);
134 do {
135 reg_read = readl(base + offset);
136 if (!(reg_read & mask))
137 return 0;
138
139 timeout--;
140 udelay(50);
141 } while (timeout != 0);
142
143 return -EAGAIN;
144}
145
146static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask)
147{
148 int timeout = 10;
149 u32 reg_read;
150
151 writel(value, base + offset);
152 do {
153 reg_read = readl(base + offset);
154 if (reg_read & mask)
155 return 0;
156
157 timeout--;
158 udelay(50);
159 } while (timeout != 0);
160
161 return -EAGAIN;
162}
163
164/*
165 * shim ops
166 */
167
168static int intel_link_power_up(struct sdw_intel *sdw)
169{
170 unsigned int link_id = sdw->instance;
171 void __iomem *shim = sdw->res->shim;
172 int spa_mask, cpa_mask;
173 int link_control, ret;
174
175 /* Link power up sequence */
176 link_control = intel_readl(shim, SDW_SHIM_LCTL);
177 spa_mask = (SDW_SHIM_LCTL_SPA << link_id);
178 cpa_mask = (SDW_SHIM_LCTL_CPA << link_id);
179 link_control |= spa_mask;
180
181 ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);
182 if (ret < 0)
183 return ret;
184
185 sdw->cdns.link_up = true;
186 return 0;
187}
188
189static int intel_shim_init(struct sdw_intel *sdw)
190{
191 void __iomem *shim = sdw->res->shim;
192 unsigned int link_id = sdw->instance;
193 int sync_reg, ret;
194 u16 ioctl = 0, act = 0;
195
196 /* Initialize Shim */
197 ioctl |= SDW_SHIM_IOCTL_BKE;
198 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
199
200 ioctl |= SDW_SHIM_IOCTL_WPDD;
201 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
202
203 ioctl |= SDW_SHIM_IOCTL_DO;
204 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
205
206 ioctl |= SDW_SHIM_IOCTL_DOE;
207 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
208
209 /* Switch to MIP from Glue logic */
210 ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id));
211
212 ioctl &= ~(SDW_SHIM_IOCTL_DOE);
213 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
214
215 ioctl &= ~(SDW_SHIM_IOCTL_DO);
216 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
217
218 ioctl |= (SDW_SHIM_IOCTL_MIF);
219 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
220
221 ioctl &= ~(SDW_SHIM_IOCTL_BKE);
222 ioctl &= ~(SDW_SHIM_IOCTL_COE);
223
224 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
225
226 act |= 0x1 << SDW_REG_SHIFT(SDW_SHIM_CTMCTL_DOAIS);
227 act |= SDW_SHIM_CTMCTL_DACTQE;
228 act |= SDW_SHIM_CTMCTL_DODS;
229 intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act);
230
231 /* Now set SyncPRD period */
232 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
233 sync_reg |= (SDW_SHIM_SYNC_SYNCPRD_VAL <<
234 SDW_REG_SHIFT(SDW_SHIM_SYNC_SYNCPRD));
235
236 /* Set SyncCPU bit */
237 sync_reg |= SDW_SHIM_SYNC_SYNCCPU;
238 ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg,
d542bc9e 239 SDW_SHIM_SYNC_SYNCCPU);
71bb8a1b 240 if (ret < 0)
17ed5bef 241 dev_err(sdw->cdns.dev, "Failed to set sync period: %d\n", ret);
71bb8a1b
VK		 242
243 return ret;
244}
245
37a2d22b
VK		 246/*
247 * PDI routines
248 */
249static void intel_pdi_init(struct sdw_intel *sdw,
d542bc9e 250 struct sdw_cdns_stream_config *config)
37a2d22b
VK		 251{
252 void __iomem *shim = sdw->res->shim;
253 unsigned int link_id = sdw->instance;
254 int pcm_cap, pdm_cap;
255
256 /* PCM Stream Capability */
257 pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id));
258
259 config->pcm_bd = (pcm_cap & SDW_SHIM_PCMSCAP_BSS) >>
260 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_BSS);
261 config->pcm_in = (pcm_cap & SDW_SHIM_PCMSCAP_ISS) >>
262 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_ISS);
263 config->pcm_out = (pcm_cap & SDW_SHIM_PCMSCAP_OSS) >>
264 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_OSS);
265
121f4361
PLB		 266 dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n",
267 config->pcm_bd, config->pcm_in, config->pcm_out);
268
37a2d22b
VK		 269 /* PDM Stream Capability */
270 pdm_cap = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
271
272 config->pdm_bd = (pdm_cap & SDW_SHIM_PDMSCAP_BSS) >>
273 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_BSS);
274 config->pdm_in = (pdm_cap & SDW_SHIM_PDMSCAP_ISS) >>
275 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_ISS);
276 config->pdm_out = (pdm_cap & SDW_SHIM_PDMSCAP_OSS) >>
277 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_OSS);
121f4361
PLB		 278
279 dev_dbg(sdw->cdns.dev, "PDM cap bd:%d in:%d out:%d\n",
280 config->pdm_bd, config->pdm_in, config->pdm_out);
37a2d22b
VK		 281}
282
283static int
284intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num, bool pcm)
285{
286 void __iomem *shim = sdw->res->shim;
287 unsigned int link_id = sdw->instance;
288 int count;
289
290 if (pcm) {
291 count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num));
18046335
PLB		 292
293 /*
294 * WORKAROUND: on all existing Intel controllers, pdi
295 * number 2 reports channel count as 1 even though it
296 * supports 8 channels. Performing hardcoding for pdi
297 * number 2.
298 */
299 if (pdi_num == 2)
300 count = 7;
301
37a2d22b
VK		 302 } else {
303 count = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
304 count = ((count & SDW_SHIM_PDMSCAP_CPSS) >>
305 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_CPSS));
306 }
307
308 /* zero based values for channel count in register */
309 count++;
310
311 return count;
312}
313
314static int intel_pdi_get_ch_update(struct sdw_intel *sdw,
d542bc9e
PLB		 315 struct sdw_cdns_pdi *pdi,
316 unsigned int num_pdi,
317 unsigned int *num_ch, bool pcm)
37a2d22b
VK		 318{
319 int i, ch_count = 0;
320
321 for (i = 0; i < num_pdi; i++) {
322 pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num, pcm);
323 ch_count += pdi->ch_count;
324 pdi++;
325 }
326
327 *num_ch = ch_count;
328 return 0;
329}
330
331static int intel_pdi_stream_ch_update(struct sdw_intel *sdw,
d542bc9e 332 struct sdw_cdns_streams *stream, bool pcm)
37a2d22b
VK		 333{
334 intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd,
d542bc9e 335 &stream->num_ch_bd, pcm);
37a2d22b
VK		 336
337 intel_pdi_get_ch_update(sdw, stream->in, stream->num_in,
d542bc9e 338 &stream->num_ch_in, pcm);
37a2d22b
VK		 339
340 intel_pdi_get_ch_update(sdw, stream->out, stream->num_out,
d542bc9e 341 &stream->num_ch_out, pcm);
37a2d22b
VK		 342
343 return 0;
344}
345
346static int intel_pdi_ch_update(struct sdw_intel *sdw)
347{
348 /* First update PCM streams followed by PDM streams */
349 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm, true);
350 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pdm, false);
351
352 return 0;
353}
354
355static void
356intel_pdi_shim_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
357{
358 void __iomem *shim = sdw->res->shim;
359 unsigned int link_id = sdw->instance;
360 int pdi_conf = 0;
361
362 pdi->intel_alh_id = (link_id * 16) + pdi->num + 5;
363
364 /*
365 * Program stream parameters to stream SHIM register
366 * This is applicable for PCM stream only.
367 */
368 if (pdi->type != SDW_STREAM_PCM)
369 return;
370
371 if (pdi->dir == SDW_DATA_DIR_RX)
372 pdi_conf |= SDW_SHIM_PCMSYCM_DIR;
373 else
374 pdi_conf &= ~(SDW_SHIM_PCMSYCM_DIR);
375
376 pdi_conf |= (pdi->intel_alh_id <<
377 SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_STREAM));
378 pdi_conf |= (pdi->l_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_LCHN));
379 pdi_conf |= (pdi->h_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_HCHN));
380
381 intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf);
382}
383
384static void
385intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
386{
387 void __iomem *alh = sdw->res->alh;
388 unsigned int link_id = sdw->instance;
389 unsigned int conf;
390
391 pdi->intel_alh_id = (link_id * 16) + pdi->num + 5;
392
393 /* Program Stream config ALH register */
394 conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id));
395
396 conf |= (SDW_ALH_STRMZCFG_DMAT_VAL <<
397 SDW_REG_SHIFT(SDW_ALH_STRMZCFG_DMAT));
398
399 conf |= ((pdi->ch_count - 1) <<
400 SDW_REG_SHIFT(SDW_ALH_STRMZCFG_CHN));
401
402 intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf);
403}
404
c46302ec 405static int intel_config_stream(struct sdw_intel *sdw,
d542bc9e
PLB		 406 struct snd_pcm_substream *substream,
407 struct snd_soc_dai *dai,
408 struct snd_pcm_hw_params *hw_params, int link_id)
c46302ec 409{
05c8afe4
PLB		 410 struct sdw_intel_link_res *res = sdw->res;
411
412 if (res->ops && res->ops->config_stream && res->arg)
413 return res->ops->config_stream(res->arg,
c46302ec
VK		 414 substream, dai, hw_params, link_id);
415
416 return -EIO;
417}
418
30246e2d
SN		 419/*
420 * bank switch routines
421 */
422
423static int intel_pre_bank_switch(struct sdw_bus *bus)
424{
425 struct sdw_cdns *cdns = bus_to_cdns(bus);
426 struct sdw_intel *sdw = cdns_to_intel(cdns);
427 void __iomem *shim = sdw->res->shim;
428 int sync_reg;
429
430 /* Write to register only for multi-link */
431 if (!bus->multi_link)
432 return 0;
433
434 /* Read SYNC register */
435 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
436 sync_reg |= SDW_SHIM_SYNC_CMDSYNC << sdw->instance;
437 intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
438
439 return 0;
440}
441
442static int intel_post_bank_switch(struct sdw_bus *bus)
443{
444 struct sdw_cdns *cdns = bus_to_cdns(bus);
445 struct sdw_intel *sdw = cdns_to_intel(cdns);
446 void __iomem *shim = sdw->res->shim;
447 int sync_reg, ret;
448
449 /* Write to register only for multi-link */
450 if (!bus->multi_link)
451 return 0;
452
453 /* Read SYNC register */
454 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
455
456 /*
457 * post_bank_switch() ops is called from the bus in loop for
458 * all the Masters in the steam with the expectation that
459 * we trigger the bankswitch for the only first Master in the list
460 * and do nothing for the other Masters
461 *
462 * So, set the SYNCGO bit only if CMDSYNC bit is set for any Master.
463 */
464 if (!(sync_reg & SDW_SHIM_SYNC_CMDSYNC_MASK))
465 return 0;
466
467 /*
468 * Set SyncGO bit to synchronously trigger a bank switch for
469 * all the masters. A write to SYNCGO bit clears CMDSYNC bit for all
470 * the Masters.
471 */
472 sync_reg |= SDW_SHIM_SYNC_SYNCGO;
473
474 ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg,
d542bc9e 475 SDW_SHIM_SYNC_SYNCGO);
30246e2d 476 if (ret < 0)
17ed5bef 477 dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret);
30246e2d
SN		 478
479 return ret;
480}
481
c46302ec
VK		 482/*
483 * DAI routines
484 */
485
486static struct sdw_cdns_port *intel_alloc_port(struct sdw_intel *sdw,
d542bc9e 487 u32 ch, u32 dir, bool pcm)
c46302ec
VK		 488{
489 struct sdw_cdns *cdns = &sdw->cdns;
490 struct sdw_cdns_port *port = NULL;
491 int i, ret = 0;
492
493 for (i = 0; i < cdns->num_ports; i++) {
2890a636 494 if (cdns->ports[i].assigned)
c46302ec
VK		 495 continue;
496
497 port = &cdns->ports[i];
498 port->assigned = true;
499 port->direction = dir;
500 port->ch = ch;
501 break;
502 }
503
504 if (!port) {
505 dev_err(cdns->dev, "Unable to find a free port\n");
506 return NULL;
507 }
508
509 if (pcm) {
510 ret = sdw_cdns_alloc_stream(cdns, &cdns->pcm, port, ch, dir);
511 if (ret)
512 goto out;
513
514 intel_pdi_shim_configure(sdw, port->pdi);
515 sdw_cdns_config_stream(cdns, port, ch, dir, port->pdi);
516
517 intel_pdi_alh_configure(sdw, port->pdi);
518
519 } else {
520 ret = sdw_cdns_alloc_stream(cdns, &cdns->pdm, port, ch, dir);
521 }
522
523out:
524 if (ret) {
525 port->assigned = false;
526 port = NULL;
527 }
528
529 return port;
530}
531
532static void intel_port_cleanup(struct sdw_cdns_dma_data *dma)
533{
534 int i;
535
536 for (i = 0; i < dma->nr_ports; i++) {
537 if (dma->port[i]) {
538 dma->port[i]->pdi->assigned = false;
539 dma->port[i]->pdi = NULL;
540 dma->port[i]->assigned = false;
541 dma->port[i] = NULL;
542 }
543 }
544}
545
546static int intel_hw_params(struct snd_pcm_substream *substream,
d542bc9e
PLB		 547 struct snd_pcm_hw_params *params,
548 struct snd_soc_dai *dai)
c46302ec
VK		 549{
550 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
551 struct sdw_intel *sdw = cdns_to_intel(cdns);
552 struct sdw_cdns_dma_data *dma;
553 struct sdw_stream_config sconfig;
554 struct sdw_port_config *pconfig;
555 int ret, i, ch, dir;
556 bool pcm = true;
557
558 dma = snd_soc_dai_get_dma_data(dai, substream);
559 if (!dma)
560 return -EIO;
561
562 ch = params_channels(params);
563 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
564 dir = SDW_DATA_DIR_RX;
565 else
566 dir = SDW_DATA_DIR_TX;
567
568 if (dma->stream_type == SDW_STREAM_PDM) {
569 /* TODO: Check whether PDM decimator is already in use */
570 dma->nr_ports = sdw_cdns_get_stream(cdns, &cdns->pdm, ch, dir);
571 pcm = false;
572 } else {
573 dma->nr_ports = sdw_cdns_get_stream(cdns, &cdns->pcm, ch, dir);
574 }
575
576 if (!dma->nr_ports) {
17ed5bef 577 dev_err(dai->dev, "ports/resources not available\n");
c46302ec
VK		 578 return -EINVAL;
579 }
580
581 dma->port = kcalloc(dma->nr_ports, sizeof(*dma->port), GFP_KERNEL);
582 if (!dma->port)
583 return -ENOMEM;
584
585 for (i = 0; i < dma->nr_ports; i++) {
586 dma->port[i] = intel_alloc_port(sdw, ch, dir, pcm);
587 if (!dma->port[i]) {
588 ret = -EINVAL;
589 goto port_error;
590 }
591 }
592
593 /* Inform DSP about PDI stream number */
594 for (i = 0; i < dma->nr_ports; i++) {
595 ret = intel_config_stream(sdw, substream, dai, params,
d542bc9e 596 dma->port[i]->pdi->intel_alh_id);
c46302ec
VK		 597 if (ret)
598 goto port_error;
599 }
600
601 sconfig.direction = dir;
602 sconfig.ch_count = ch;
603 sconfig.frame_rate = params_rate(params);
604 sconfig.type = dma->stream_type;
605
606 if (dma->stream_type == SDW_STREAM_PDM) {
607 sconfig.frame_rate *= 50;
608 sconfig.bps = 1;
609 } else {
610 sconfig.bps = snd_pcm_format_width(params_format(params));
611 }
612
613 /* Port configuration */
614 pconfig = kcalloc(dma->nr_ports, sizeof(*pconfig), GFP_KERNEL);
615 if (!pconfig) {
616 ret = -ENOMEM;
617 goto port_error;
618 }
619
620 for (i = 0; i < dma->nr_ports; i++) {
621 pconfig[i].num = dma->port[i]->num;
622 pconfig[i].ch_mask = (1 << ch) - 1;
623 }
624
625 ret = sdw_stream_add_master(&cdns->bus, &sconfig,
d542bc9e 626 pconfig, dma->nr_ports, dma->stream);
c46302ec 627 if (ret) {
17ed5bef 628 dev_err(cdns->dev, "add master to stream failed:%d\n", ret);
c46302ec
VK		 629 goto stream_error;
630 }
631
632 kfree(pconfig);
633 return ret;
634
635stream_error:
636 kfree(pconfig);
637port_error:
638 intel_port_cleanup(dma);
639 kfree(dma->port);
640 return ret;
641}
642
643static int
644intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
645{
646 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
647 struct sdw_cdns_dma_data *dma;
648 int ret;
649
650 dma = snd_soc_dai_get_dma_data(dai, substream);
651 if (!dma)
652 return -EIO;
653
654 ret = sdw_stream_remove_master(&cdns->bus, dma->stream);
655 if (ret < 0)
17ed5bef 656 dev_err(dai->dev, "remove master from stream %s failed: %d\n",
d542bc9e 657 dma->stream->name, ret);
c46302ec
VK		 658
659 intel_port_cleanup(dma);
660 kfree(dma->port);
661 return ret;
662}
663
183c7687
PLB		 664static void intel_shutdown(struct snd_pcm_substream *substream,
665 struct snd_soc_dai *dai)
666{
667 struct sdw_cdns_dma_data *dma;
668
669 dma = snd_soc_dai_get_dma_data(dai, substream);
670 if (!dma)
671 return;
672
673 snd_soc_dai_set_dma_data(dai, substream, NULL);
674 kfree(dma);
675}
676
c46302ec 677static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai,
d542bc9e 678 void *stream, int direction)
c46302ec
VK		 679{
680 return cdns_set_sdw_stream(dai, stream, true, direction);
681}
682
683static int intel_pdm_set_sdw_stream(struct snd_soc_dai *dai,
d542bc9e 684 void *stream, int direction)
c46302ec
VK		 685{
686 return cdns_set_sdw_stream(dai, stream, false, direction);
687}
688
b1635596 689static const struct snd_soc_dai_ops intel_pcm_dai_ops = {
c46302ec
VK		 690 .hw_params = intel_hw_params,
691 .hw_free = intel_hw_free,
183c7687 692 .shutdown = intel_shutdown,
c46302ec
VK		 693 .set_sdw_stream = intel_pcm_set_sdw_stream,
694};
695
b1635596 696static const struct snd_soc_dai_ops intel_pdm_dai_ops = {
c46302ec
VK		 697 .hw_params = intel_hw_params,
698 .hw_free = intel_hw_free,
183c7687 699 .shutdown = intel_shutdown,
c46302ec
VK		 700 .set_sdw_stream = intel_pdm_set_sdw_stream,
701};
702
703static const struct snd_soc_component_driver dai_component = {
704 .name = "soundwire",
705};
706
707static int intel_create_dai(struct sdw_cdns *cdns,
d542bc9e
PLB		 708 struct snd_soc_dai_driver *dais,
709 enum intel_pdi_type type,
710 u32 num, u32 off, u32 max_ch, bool pcm)
c46302ec
VK		 711{
712 int i;
713
714 if (num == 0)
715 return 0;
716
717 /* TODO: Read supported rates/formats from hardware */
718 for (i = off; i < (off + num); i++) {
719 dais[i].name = kasprintf(GFP_KERNEL, "SDW%d Pin%d",
d542bc9e 720 cdns->instance, i);
c46302ec
VK		 721 if (!dais[i].name)
722 return -ENOMEM;
723
724 if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) {
1215daee
VK		 725 dais[i].playback.stream_name =
726 kasprintf(GFP_KERNEL, "SDW%d Tx%d",
727 cdns->instance, i);
c46302ec
VK		 728 if (!dais[i].playback.stream_name) {
729 kfree(dais[i].name);
730 return -ENOMEM;
731 }
732
733 dais[i].playback.channels_min = 1;
734 dais[i].playback.channels_max = max_ch;
735 dais[i].playback.rates = SNDRV_PCM_RATE_48000;
736 dais[i].playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
737 }
738
739 if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) {
1215daee
VK		 740 dais[i].capture.stream_name =
741 kasprintf(GFP_KERNEL, "SDW%d Rx%d",
742 cdns->instance, i);
c46302ec
VK		 743 if (!dais[i].capture.stream_name) {
744 kfree(dais[i].name);
745 kfree(dais[i].playback.stream_name);
746 return -ENOMEM;
747 }
748
39194128
SK		 749 dais[i].capture.channels_min = 1;
750 dais[i].capture.channels_max = max_ch;
c46302ec
VK		 751 dais[i].capture.rates = SNDRV_PCM_RATE_48000;
752 dais[i].capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
753 }
754
755 dais[i].id = SDW_DAI_ID_RANGE_START + i;
756
757 if (pcm)
758 dais[i].ops = &intel_pcm_dai_ops;
759 else
760 dais[i].ops = &intel_pdm_dai_ops;
761 }
762
763 return 0;
764}
765
766static int intel_register_dai(struct sdw_intel *sdw)
767{
768 struct sdw_cdns *cdns = &sdw->cdns;
769 struct sdw_cdns_streams *stream;
770 struct snd_soc_dai_driver *dais;
771 int num_dai, ret, off = 0;
772
773 /* DAIs are created based on total number of PDIs supported */
774 num_dai = cdns->pcm.num_pdi + cdns->pdm.num_pdi;
775
776 dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL);
777 if (!dais)
778 return -ENOMEM;
779
780 /* Create PCM DAIs */
781 stream = &cdns->pcm;
782
1215daee
VK		 783 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, stream->num_in,
784 off, stream->num_ch_in, true);
c46302ec
VK		 785 if (ret)
786 return ret;
787
788 off += cdns->pcm.num_in;
1215daee
VK		 789 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out,
790 off, stream->num_ch_out, true);
c46302ec
VK		 791 if (ret)
792 return ret;
793
794 off += cdns->pcm.num_out;
1215daee
VK		 795 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd,
796 off, stream->num_ch_bd, true);
c46302ec
VK		 797 if (ret)
798 return ret;
799
800 /* Create PDM DAIs */
801 stream = &cdns->pdm;
802 off += cdns->pcm.num_bd;
1215daee
VK		 803 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pdm.num_in,
804 off, stream->num_ch_in, false);
c46302ec
VK		 805 if (ret)
806 return ret;
807
808 off += cdns->pdm.num_in;
1215daee
VK		 809 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pdm.num_out,
810 off, stream->num_ch_out, false);
c46302ec
VK		 811 if (ret)
812 return ret;
813
814 off += cdns->pdm.num_bd;
1215daee
VK		 815 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pdm.num_bd,
816 off, stream->num_ch_bd, false);
c46302ec
VK		 817 if (ret)
818 return ret;
819
820 return snd_soc_register_component(cdns->dev, &dai_component,
d542bc9e 821 dais, num_dai);
c46302ec
VK		 822}
823
085f4ace
PLB		 824static int sdw_master_read_intel_prop(struct sdw_bus *bus)
825{
826 struct sdw_master_prop *prop = &bus->prop;
827 struct fwnode_handle *link;
828 char name[32];
085f4ace
PLB		 829
830 /* Find master handle */
831 snprintf(name, sizeof(name),
832 "mipi-sdw-link-%d-subproperties", bus->link_id);
833
834 link = device_get_named_child_node(bus->dev, name);
835 if (!link) {
836 dev_err(bus->dev, "Master node %s not found\n", name);
837 return -EIO;
838 }
839
840 fwnode_property_read_u32(link,
841 "intel-sdw-ip-clock",
842 &prop->mclk_freq);
843 return 0;
844}
845
71bb8a1b
VK		 846static int intel_prop_read(struct sdw_bus *bus)
847{
848 /* Initialize with default handler to read all DisCo properties */
849 sdw_master_read_prop(bus);
850
085f4ace
PLB		 851 /* read Intel-specific properties */
852 sdw_master_read_intel_prop(bus);
853
71bb8a1b
VK		 854 return 0;
855}
856
c91605f4
SN		 857static struct sdw_master_ops sdw_intel_ops = {
858 .read_prop = sdw_master_read_prop,
859 .xfer_msg = cdns_xfer_msg,
860 .xfer_msg_defer = cdns_xfer_msg_defer,
861 .reset_page_addr = cdns_reset_page_addr,
07abeff1 862 .set_bus_conf = cdns_bus_conf,
30246e2d
SN		 863 .pre_bank_switch = intel_pre_bank_switch,
864 .post_bank_switch = intel_post_bank_switch,
c91605f4
SN		 865};
866
71bb8a1b
VK		 867/*
868 * probe and init
869 */
870static int intel_probe(struct platform_device *pdev)
871{
37a2d22b 872 struct sdw_cdns_stream_config config;
71bb8a1b
VK		 873 struct sdw_intel *sdw;
874 int ret;
875
876 sdw = devm_kzalloc(&pdev->dev, sizeof(*sdw), GFP_KERNEL);
877 if (!sdw)
878 return -ENOMEM;
879
880 sdw->instance = pdev->id;
881 sdw->res = dev_get_platdata(&pdev->dev);
882 sdw->cdns.dev = &pdev->dev;
883 sdw->cdns.registers = sdw->res->registers;
884 sdw->cdns.instance = sdw->instance;
885 sdw->cdns.msg_count = 0;
886 sdw->cdns.bus.dev = &pdev->dev;
887 sdw->cdns.bus.link_id = pdev->id;
888
889 sdw_cdns_probe(&sdw->cdns);
890
891 /* Set property read ops */
c91605f4
SN		 892 sdw_intel_ops.read_prop = intel_prop_read;
893 sdw->cdns.bus.ops = &sdw_intel_ops;
71bb8a1b
VK		 894
895 platform_set_drvdata(pdev, sdw);
896
897 ret = sdw_add_bus_master(&sdw->cdns.bus);
898 if (ret) {
899 dev_err(&pdev->dev, "sdw_add_bus_master fail: %d\n", ret);
900 goto err_master_reg;
901 }
902
903 /* Initialize shim and controller */
904 intel_link_power_up(sdw);
905 intel_shim_init(sdw);
906
907 ret = sdw_cdns_init(&sdw->cdns);
908 if (ret)
909 goto err_init;
910
7094dc2b 911 ret = sdw_cdns_enable_interrupt(&sdw->cdns);
37a2d22b
VK		 912
913 /* Read the PDI config and initialize cadence PDI */
914 intel_pdi_init(sdw, &config);
915 ret = sdw_cdns_pdi_init(&sdw->cdns, config);
71bb8a1b
VK		 916 if (ret)
917 goto err_init;
918
37a2d22b
VK		 919 intel_pdi_ch_update(sdw);
920
71bb8a1b 921 /* Acquire IRQ */
d542bc9e
PLB		 922 ret = request_threaded_irq(sdw->res->irq, sdw_cdns_irq, sdw_cdns_thread,
923 IRQF_SHARED, KBUILD_MODNAME, &sdw->cdns);
71bb8a1b
VK		 924 if (ret < 0) {
925 dev_err(sdw->cdns.dev, "unable to grab IRQ %d, disabling device\n",
d542bc9e 926 sdw->res->irq);
71bb8a1b
VK		 927 goto err_init;
928 }
929
c46302ec
VK		 930 /* Register DAIs */
931 ret = intel_register_dai(sdw);
932 if (ret) {
17ed5bef 933 dev_err(sdw->cdns.dev, "DAI registration failed: %d\n", ret);
c46302ec
VK		 934 snd_soc_unregister_component(sdw->cdns.dev);
935 goto err_dai;
936 }
937
71bb8a1b
VK		 938 return 0;
939
c46302ec
VK		 940err_dai:
941 free_irq(sdw->res->irq, sdw);
71bb8a1b
VK		 942err_init:
943 sdw_delete_bus_master(&sdw->cdns.bus);
944err_master_reg:
945 return ret;
946}
947
948static int intel_remove(struct platform_device *pdev)
949{
950 struct sdw_intel *sdw;
951
952 sdw = platform_get_drvdata(pdev);
953
954 free_irq(sdw->res->irq, sdw);
c46302ec 955 snd_soc_unregister_component(sdw->cdns.dev);
71bb8a1b
VK		 956 sdw_delete_bus_master(&sdw->cdns.bus);
957
958 return 0;
959}
960
961static struct platform_driver sdw_intel_drv = {
962 .probe = intel_probe,
963 .remove = intel_remove,
964 .driver = {
965 .name = "int-sdw",
966
967 },
968};
969
970module_platform_driver(sdw_intel_drv);
971
972MODULE_LICENSE("Dual BSD/GPL");
973MODULE_ALIAS("platform:int-sdw");
974MODULE_DESCRIPTION("Intel Soundwire Master Driver");
Linux 6.x block layer and io_uring tree(s)