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soundwire: intel: ignore software command retries
[linux-block.git] / drivers / soundwire / intel.c
CommitLineData
71bb8a1b
VK		 1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2// Copyright(c) 2015-17 Intel Corporation.
3
4/*
5 * Soundwire Intel Master Driver
6 */
7
8#include <linux/acpi.h>
79ee6631 9#include <linux/debugfs.h>
71bb8a1b 10#include <linux/delay.h>
4abbd783 11#include <linux/module.h>
71bb8a1b 12#include <linux/interrupt.h>
df72b719 13#include <linux/io.h>
71bb8a1b 14#include <linux/platform_device.h>
37a2d22b 15#include <sound/pcm_params.h>
ab2c9132 16#include <linux/pm_runtime.h>
37a2d22b 17#include <sound/soc.h>
71bb8a1b
VK		 18#include <linux/soundwire/sdw_registers.h>
19#include <linux/soundwire/sdw.h>
20#include <linux/soundwire/sdw_intel.h>
21#include "cadence_master.h"
79ee6631 22#include "bus.h"
71bb8a1b
VK		 23#include "intel.h"
24
ebf878ed
PLB		 25#define INTEL_MASTER_SUSPEND_DELAY_MS 3000
26
27/*
28 * debug/config flags for the Intel SoundWire Master.
29 *
30 * Since we may have multiple masters active, we can have up to 8
31 * flags reused in each byte, with master0 using the ls-byte, etc.
32 */
33
a2d9c161
PLB		 34#define SDW_INTEL_MASTER_DISABLE_PM_RUNTIME BIT(0)
35#define SDW_INTEL_MASTER_DISABLE_CLOCK_STOP BIT(1)
36#define SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE BIT(2)
ebf878ed
PLB		 37
38static int md_flags;
39module_param_named(sdw_md_flags, md_flags, int, 0444);
40MODULE_PARM_DESC(sdw_md_flags, "SoundWire Intel Master device flags (0x0 all off)");
41
71bb8a1b
VK		 42/* Intel SHIM Registers Definition */
43#define SDW_SHIM_LCAP 0x0
44#define SDW_SHIM_LCTL 0x4
45#define SDW_SHIM_IPPTR 0x8
46#define SDW_SHIM_SYNC 0xC
47
7cc6e315
PLB		 48#define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x))
49#define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x))
50#define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x))
51#define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x))
52#define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x))
53#define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x))
54
55#define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y)))
56#define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y)))
57#define SDW_SHIM_PDMSCAP(x) (0x062 + 0x60 * (x))
58#define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x))
59#define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x))
71bb8a1b
VK		 60
61#define SDW_SHIM_WAKEEN 0x190
62#define SDW_SHIM_WAKESTS 0x192
63
64#define SDW_SHIM_LCTL_SPA BIT(0)
65#define SDW_SHIM_LCTL_CPA BIT(8)
66
4a17c441
PLB		 67#define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1)
68#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1)
71bb8a1b
VK		 69#define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0)
70#define SDW_SHIM_SYNC_SYNCCPU BIT(15)
71#define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16)
72#define SDW_SHIM_SYNC_CMDSYNC BIT(16)
73#define SDW_SHIM_SYNC_SYNCGO BIT(24)
74
75#define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0)
76#define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4)
77#define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8)
78
79#define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0)
80#define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4)
81#define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8)
82#define SDW_SHIM_PCMSYCM_DIR BIT(15)
83
84#define SDW_SHIM_PDMSCAP_ISS GENMASK(3, 0)
85#define SDW_SHIM_PDMSCAP_OSS GENMASK(7, 4)
86#define SDW_SHIM_PDMSCAP_BSS GENMASK(12, 8)
87#define SDW_SHIM_PDMSCAP_CPSS GENMASK(15, 13)
88
89#define SDW_SHIM_IOCTL_MIF BIT(0)
90#define SDW_SHIM_IOCTL_CO BIT(1)
91#define SDW_SHIM_IOCTL_COE BIT(2)
92#define SDW_SHIM_IOCTL_DO BIT(3)
93#define SDW_SHIM_IOCTL_DOE BIT(4)
94#define SDW_SHIM_IOCTL_BKE BIT(5)
95#define SDW_SHIM_IOCTL_WPDD BIT(6)
96#define SDW_SHIM_IOCTL_CIBD BIT(8)
97#define SDW_SHIM_IOCTL_DIBD BIT(9)
98
99#define SDW_SHIM_CTMCTL_DACTQE BIT(0)
100#define SDW_SHIM_CTMCTL_DODS BIT(1)
101#define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3)
102
103#define SDW_SHIM_WAKEEN_ENABLE BIT(0)
104#define SDW_SHIM_WAKESTS_STATUS BIT(0)
105
106/* Intel ALH Register definitions */
7cc6e315 107#define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x)))
79ee6631 108#define SDW_ALH_NUM_STREAMS 64
71bb8a1b
VK		 109
110#define SDW_ALH_STRMZCFG_DMAT_VAL 0x3
111#define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0)
112#define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16)
113
c46302ec
VK		 114enum intel_pdi_type {
115 INTEL_PDI_IN = 0,
116 INTEL_PDI_OUT = 1,
117 INTEL_PDI_BD = 2,
118};
119
71bb8a1b
VK		 120#define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns)
121
122/*
123 * Read, write helpers for HW registers
124 */
125static inline int intel_readl(void __iomem *base, int offset)
126{
127 return readl(base + offset);
128}
129
130static inline void intel_writel(void __iomem *base, int offset, int value)
131{
132 writel(value, base + offset);
133}
134
135static inline u16 intel_readw(void __iomem *base, int offset)
136{
137 return readw(base + offset);
138}
139
140static inline void intel_writew(void __iomem *base, int offset, u16 value)
141{
142 writew(value, base + offset);
143}
144
7d2845d5 145static int intel_wait_bit(void __iomem *base, int offset, u32 mask, u32 target)
71bb8a1b
VK		 146{
147 int timeout = 10;
148 u32 reg_read;
149
71bb8a1b
VK		 150 do {
151 reg_read = readl(base + offset);
7d2845d5 152 if ((reg_read & mask) == target)
71bb8a1b
VK		 153 return 0;
154
155 timeout--;
7d2845d5 156 usleep_range(50, 100);
71bb8a1b
VK		 157 } while (timeout != 0);
158
159 return -EAGAIN;
160}
161
7d2845d5 162static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask)
71bb8a1b 163{
71bb8a1b 164 writel(value, base + offset);
7d2845d5
PLB		 165 return intel_wait_bit(base, offset, mask, 0);
166}
71bb8a1b 167
7d2845d5
PLB		 168static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask)
169{
170 writel(value, base + offset);
171 return intel_wait_bit(base, offset, mask, mask);
71bb8a1b
VK		 172}
173
79ee6631
PLB		 174/*
175 * debugfs
176 */
177#ifdef CONFIG_DEBUG_FS
178
179#define RD_BUF (2 * PAGE_SIZE)
180
181static ssize_t intel_sprintf(void __iomem *mem, bool l,
182 char *buf, size_t pos, unsigned int reg)
183{
184 int value;
185
186 if (l)
187 value = intel_readl(mem, reg);
188 else
189 value = intel_readw(mem, reg);
190
191 return scnprintf(buf + pos, RD_BUF - pos, "%4x\t%4x\n", reg, value);
192}
193
194static int intel_reg_show(struct seq_file *s_file, void *data)
195{
196 struct sdw_intel *sdw = s_file->private;
2523486b
PLB		 197 void __iomem *s = sdw->link_res->shim;
198 void __iomem *a = sdw->link_res->alh;
79ee6631
PLB		 199 char *buf;
200 ssize_t ret;
201 int i, j;
202 unsigned int links, reg;
203
204 buf = kzalloc(RD_BUF, GFP_KERNEL);
205 if (!buf)
206 return -ENOMEM;
207
208 links = intel_readl(s, SDW_SHIM_LCAP) & GENMASK(2, 0);
209
210 ret = scnprintf(buf, RD_BUF, "Register Value\n");
211 ret += scnprintf(buf + ret, RD_BUF - ret, "\nShim\n");
212
213 for (i = 0; i < links; i++) {
214 reg = SDW_SHIM_LCAP + i * 4;
215 ret += intel_sprintf(s, true, buf, ret, reg);
216 }
217
218 for (i = 0; i < links; i++) {
219 ret += scnprintf(buf + ret, RD_BUF - ret, "\nLink%d\n", i);
220 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLSCAP(i));
221 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS0CM(i));
222 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS1CM(i));
223 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS2CM(i));
224 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS3CM(i));
225 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PCMSCAP(i));
226
227 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PCMSyCH registers\n");
228
229 /*
230 * the value 10 is the number of PDIs. We will need a
231 * cleanup to remove hard-coded Intel configurations
232 * from cadence_master.c
233 */
234 for (j = 0; j < 10; j++) {
235 ret += intel_sprintf(s, false, buf, ret,
236 SDW_SHIM_PCMSYCHM(i, j));
237 ret += intel_sprintf(s, false, buf, ret,
238 SDW_SHIM_PCMSYCHC(i, j));
239 }
240 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PDMSCAP, IOCTL, CTMCTL\n");
241
242 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PDMSCAP(i));
243 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_IOCTL(i));
244 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTMCTL(i));
245 }
246
247 ret += scnprintf(buf + ret, RD_BUF - ret, "\nWake registers\n");
248 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKEEN);
249 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKESTS);
250
251 ret += scnprintf(buf + ret, RD_BUF - ret, "\nALH STRMzCFG\n");
252 for (i = 0; i < SDW_ALH_NUM_STREAMS; i++)
253 ret += intel_sprintf(a, true, buf, ret, SDW_ALH_STRMZCFG(i));
254
255 seq_printf(s_file, "%s", buf);
256 kfree(buf);
257
258 return 0;
259}
260DEFINE_SHOW_ATTRIBUTE(intel_reg);
261
262static void intel_debugfs_init(struct sdw_intel *sdw)
263{
264 struct dentry *root = sdw->cdns.bus.debugfs;
265
266 if (!root)
267 return;
268
269 sdw->debugfs = debugfs_create_dir("intel-sdw", root);
270
271 debugfs_create_file("intel-registers", 0400, sdw->debugfs, sdw,
272 &intel_reg_fops);
273
274 sdw_cdns_debugfs_init(&sdw->cdns, sdw->debugfs);
275}
276
277static void intel_debugfs_exit(struct sdw_intel *sdw)
278{
279 debugfs_remove_recursive(sdw->debugfs);
280}
281#else
282static void intel_debugfs_init(struct sdw_intel *sdw) {}
283static void intel_debugfs_exit(struct sdw_intel *sdw) {}
284#endif /* CONFIG_DEBUG_FS */
285
71bb8a1b
VK		 286/*
287 * shim ops
288 */
289
290static int intel_link_power_up(struct sdw_intel *sdw)
291{
292 unsigned int link_id = sdw->instance;
2523486b 293 void __iomem *shim = sdw->link_res->shim;
4a17c441
PLB		 294 u32 *shim_mask = sdw->link_res->shim_mask;
295 struct sdw_bus *bus = &sdw->cdns.bus;
296 struct sdw_master_prop *prop = &bus->prop;
71bb8a1b 297 int spa_mask, cpa_mask;
4a17c441
PLB		 298 int link_control;
299 int ret = 0;
300 u32 syncprd;
301 u32 sync_reg;
302
303 mutex_lock(sdw->link_res->shim_lock);
304
305 /*
306 * The hardware relies on an internal counter, typically 4kHz,
307 * to generate the SoundWire SSP - which defines a 'safe'
308 * synchronization point between commands and audio transport
309 * and allows for multi link synchronization. The SYNCPRD value
310 * is only dependent on the oscillator clock provided to
311 * the IP, so adjust based on _DSD properties reported in DSDT
312 * tables. The values reported are based on either 24MHz
313 * (CNL/CML) or 38.4 MHz (ICL/TGL+).
314 */
315 if (prop->mclk_freq % 6000000)
316 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4;
317 else
318 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24;
319
320 if (!*shim_mask) {
321 /* we first need to program the SyncPRD/CPU registers */
322 dev_dbg(sdw->cdns.dev,
323 "%s: first link up, programming SYNCPRD\n", __func__);
324
325 /* set SyncPRD period */
326 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
327 sync_reg |= (syncprd <<
328 SDW_REG_SHIFT(SDW_SHIM_SYNC_SYNCPRD));
329
330 /* Set SyncCPU bit */
331 sync_reg |= SDW_SHIM_SYNC_SYNCCPU;
332 intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
333 }
71bb8a1b
VK		 334
335 /* Link power up sequence */
336 link_control = intel_readl(shim, SDW_SHIM_LCTL);
337 spa_mask = (SDW_SHIM_LCTL_SPA << link_id);
338 cpa_mask = (SDW_SHIM_LCTL_CPA << link_id);
339 link_control |= spa_mask;
340
341 ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);
4a17c441
PLB		 342 if (ret < 0) {
343 dev_err(sdw->cdns.dev, "Failed to power up link: %d\n", ret);
344 goto out;
345 }
346
347 if (!*shim_mask) {
348 /* SyncCPU will change once link is active */
349 ret = intel_wait_bit(shim, SDW_SHIM_SYNC,
350 SDW_SHIM_SYNC_SYNCCPU, 0);
351 if (ret < 0) {
352 dev_err(sdw->cdns.dev,
353 "Failed to set SHIM_SYNC: %d\n", ret);
354 goto out;
355 }
356 }
357
358 *shim_mask |= BIT(link_id);
71bb8a1b
VK		 359
360 sdw->cdns.link_up = true;
4a17c441
PLB		 361out:
362 mutex_unlock(sdw->link_res->shim_lock);
363
364 return ret;
71bb8a1b
VK		 365}
366
4a17c441
PLB		 367/* this needs to be called with shim_lock */
368static void intel_shim_glue_to_master_ip(struct sdw_intel *sdw)
71bb8a1b 369{
2523486b 370 void __iomem *shim = sdw->link_res->shim;
71bb8a1b 371 unsigned int link_id = sdw->instance;
4a17c441 372 u16 ioctl;
71bb8a1b 373
4a17c441
PLB		 374 /* Switch to MIP from Glue logic */
375 ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id));
376
377 ioctl &= ~(SDW_SHIM_IOCTL_DOE);
71bb8a1b 378 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
4a17c441 379 usleep_range(10, 15);
71bb8a1b 380
4a17c441 381 ioctl &= ~(SDW_SHIM_IOCTL_DO);
71bb8a1b 382 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
4a17c441 383 usleep_range(10, 15);
71bb8a1b 384
4a17c441 385 ioctl |= (SDW_SHIM_IOCTL_MIF);
71bb8a1b 386 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
4a17c441 387 usleep_range(10, 15);
71bb8a1b 388
4a17c441
PLB		 389 ioctl &= ~(SDW_SHIM_IOCTL_BKE);
390 ioctl &= ~(SDW_SHIM_IOCTL_COE);
71bb8a1b 391 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
4a17c441 392 usleep_range(10, 15);
71bb8a1b 393
4a17c441
PLB		 394 /* at this point Master IP has full control of the I/Os */
395}
71bb8a1b 396
4a17c441
PLB		 397/* this needs to be called with shim_lock */
398static void intel_shim_master_ip_to_glue(struct sdw_intel *sdw)
399{
400 unsigned int link_id = sdw->instance;
401 void __iomem *shim = sdw->link_res->shim;
402 u16 ioctl;
403
404 /* Glue logic */
405 ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id));
406 ioctl |= SDW_SHIM_IOCTL_BKE;
407 ioctl |= SDW_SHIM_IOCTL_COE;
71bb8a1b 408 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
4a17c441 409 usleep_range(10, 15);
71bb8a1b 410
4a17c441 411 ioctl &= ~(SDW_SHIM_IOCTL_MIF);
71bb8a1b 412 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
4a17c441 413 usleep_range(10, 15);
71bb8a1b 414
4a17c441
PLB		 415 /* at this point Integration Glue has full control of the I/Os */
416}
417
418static int intel_shim_init(struct sdw_intel *sdw, bool clock_stop)
419{
420 void __iomem *shim = sdw->link_res->shim;
421 unsigned int link_id = sdw->instance;
422 int ret = 0;
423 u16 ioctl = 0, act = 0;
424
425 mutex_lock(sdw->link_res->shim_lock);
426
427 /* Initialize Shim */
428 ioctl |= SDW_SHIM_IOCTL_BKE;
71bb8a1b 429 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
4a17c441 430 usleep_range(10, 15);
71bb8a1b 431
4a17c441
PLB		 432 ioctl |= SDW_SHIM_IOCTL_WPDD;
433 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
434 usleep_range(10, 15);
71bb8a1b 435
4a17c441 436 ioctl |= SDW_SHIM_IOCTL_DO;
71bb8a1b 437 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
4a17c441
PLB		 438 usleep_range(10, 15);
439
440 ioctl |= SDW_SHIM_IOCTL_DOE;
71bb8a1b 441 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
4a17c441
PLB		 442 usleep_range(10, 15);
443
444 intel_shim_glue_to_master_ip(sdw);
71bb8a1b
VK		 445
446 act |= 0x1 << SDW_REG_SHIFT(SDW_SHIM_CTMCTL_DOAIS);
447 act |= SDW_SHIM_CTMCTL_DACTQE;
448 act |= SDW_SHIM_CTMCTL_DODS;
449 intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act);
4a17c441 450 usleep_range(10, 15);
71bb8a1b 451
4a17c441
PLB		 452 mutex_unlock(sdw->link_res->shim_lock);
453
454 return ret;
455}
456
ab2c9132 457static void intel_shim_wake(struct sdw_intel *sdw, bool wake_enable)
4a17c441
PLB		 458{
459 void __iomem *shim = sdw->link_res->shim;
460 unsigned int link_id = sdw->instance;
461 u16 wake_en, wake_sts;
462
463 mutex_lock(sdw->link_res->shim_lock);
464 wake_en = intel_readw(shim, SDW_SHIM_WAKEEN);
465
466 if (wake_enable) {
467 /* Enable the wakeup */
468 wake_en |= (SDW_SHIM_WAKEEN_ENABLE << link_id);
469 intel_writew(shim, SDW_SHIM_WAKEEN, wake_en);
470 } else {
471 /* Disable the wake up interrupt */
472 wake_en &= ~(SDW_SHIM_WAKEEN_ENABLE << link_id);
473 intel_writew(shim, SDW_SHIM_WAKEEN, wake_en);
474
475 /* Clear wake status */
476 wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS);
477 wake_sts |= (SDW_SHIM_WAKEEN_ENABLE << link_id);
478 intel_writew(shim, SDW_SHIM_WAKESTS_STATUS, wake_sts);
479 }
480 mutex_unlock(sdw->link_res->shim_lock);
481}
482
9b3b4b3f 483static int intel_link_power_down(struct sdw_intel *sdw)
4a17c441
PLB		 484{
485 int link_control, spa_mask, cpa_mask;
486 unsigned int link_id = sdw->instance;
487 void __iomem *shim = sdw->link_res->shim;
488 u32 *shim_mask = sdw->link_res->shim_mask;
489 int ret = 0;
490
491 mutex_lock(sdw->link_res->shim_lock);
492
493 intel_shim_master_ip_to_glue(sdw);
494
495 /* Link power down sequence */
496 link_control = intel_readl(shim, SDW_SHIM_LCTL);
497 spa_mask = ~(SDW_SHIM_LCTL_SPA << link_id);
498 cpa_mask = (SDW_SHIM_LCTL_CPA << link_id);
499 link_control &= spa_mask;
500
501 ret = intel_clear_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);
502
503 if (!(*shim_mask & BIT(link_id)))
504 dev_err(sdw->cdns.dev,
505 "%s: Unbalanced power-up/down calls\n", __func__);
506
507 *shim_mask &= ~BIT(link_id);
508
509 mutex_unlock(sdw->link_res->shim_lock);
71bb8a1b 510
71bb8a1b 511 if (ret < 0)
4a17c441 512 return ret;
71bb8a1b 513
4a17c441
PLB		 514 sdw->cdns.link_up = false;
515 return 0;
71bb8a1b
VK		 516}
517
02629e45
PLB		 518static void intel_shim_sync_arm(struct sdw_intel *sdw)
519{
520 void __iomem *shim = sdw->link_res->shim;
521 u32 sync_reg;
522
523 mutex_lock(sdw->link_res->shim_lock);
524
525 /* update SYNC register */
526 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
527 sync_reg |= (SDW_SHIM_SYNC_CMDSYNC << sdw->instance);
528 intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
529
530 mutex_unlock(sdw->link_res->shim_lock);
531}
532
437e3289
PLB		 533static int intel_shim_sync_go_unlocked(struct sdw_intel *sdw)
534{
535 void __iomem *shim = sdw->link_res->shim;
536 u32 sync_reg;
537 int ret;
71bb8a1b 538
437e3289 539 /* Read SYNC register */
71bb8a1b 540 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
71bb8a1b 541
437e3289
PLB		 542 /*
543 * Set SyncGO bit to synchronously trigger a bank switch for
544 * all the masters. A write to SYNCGO bit clears CMDSYNC bit for all
545 * the Masters.
546 */
547 sync_reg |= SDW_SHIM_SYNC_SYNCGO;
548
71bb8a1b 549 ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg,
437e3289
PLB		 550 SDW_SHIM_SYNC_SYNCGO);
551
71bb8a1b 552 if (ret < 0)
437e3289 553 dev_err(sdw->cdns.dev, "SyncGO clear failed: %d\n", ret);
71bb8a1b
VK		 554
555 return ret;
556}
557
37a2d22b
VK		 558/*
559 * PDI routines
560 */
561static void intel_pdi_init(struct sdw_intel *sdw,
d542bc9e 562 struct sdw_cdns_stream_config *config)
37a2d22b 563{
2523486b 564 void __iomem *shim = sdw->link_res->shim;
37a2d22b
VK		 565 unsigned int link_id = sdw->instance;
566 int pcm_cap, pdm_cap;
567
568 /* PCM Stream Capability */
569 pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id));
570
571 config->pcm_bd = (pcm_cap & SDW_SHIM_PCMSCAP_BSS) >>
572 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_BSS);
573 config->pcm_in = (pcm_cap & SDW_SHIM_PCMSCAP_ISS) >>
574 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_ISS);
575 config->pcm_out = (pcm_cap & SDW_SHIM_PCMSCAP_OSS) >>
576 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_OSS);
577
121f4361
PLB		 578 dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n",
579 config->pcm_bd, config->pcm_in, config->pcm_out);
580
37a2d22b
VK		 581 /* PDM Stream Capability */
582 pdm_cap = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
583
584 config->pdm_bd = (pdm_cap & SDW_SHIM_PDMSCAP_BSS) >>
585 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_BSS);
586 config->pdm_in = (pdm_cap & SDW_SHIM_PDMSCAP_ISS) >>
587 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_ISS);
588 config->pdm_out = (pdm_cap & SDW_SHIM_PDMSCAP_OSS) >>
589 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_OSS);
121f4361
PLB		 590
591 dev_dbg(sdw->cdns.dev, "PDM cap bd:%d in:%d out:%d\n",
592 config->pdm_bd, config->pdm_in, config->pdm_out);
37a2d22b
VK		 593}
594
595static int
596intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num, bool pcm)
597{
2523486b 598 void __iomem *shim = sdw->link_res->shim;
37a2d22b
VK		 599 unsigned int link_id = sdw->instance;
600 int count;
601
602 if (pcm) {
603 count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num));
18046335
PLB		 604
605 /*
606 * WORKAROUND: on all existing Intel controllers, pdi
607 * number 2 reports channel count as 1 even though it
608 * supports 8 channels. Performing hardcoding for pdi
609 * number 2.
610 */
611 if (pdi_num == 2)
612 count = 7;
613
37a2d22b
VK		 614 } else {
615 count = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
616 count = ((count & SDW_SHIM_PDMSCAP_CPSS) >>
617 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_CPSS));
618 }
619
620 /* zero based values for channel count in register */
621 count++;
622
623 return count;
624}
625
626static int intel_pdi_get_ch_update(struct sdw_intel *sdw,
d542bc9e
PLB		 627 struct sdw_cdns_pdi *pdi,
628 unsigned int num_pdi,
629 unsigned int *num_ch, bool pcm)
37a2d22b
VK		 630{
631 int i, ch_count = 0;
632
633 for (i = 0; i < num_pdi; i++) {
634 pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num, pcm);
635 ch_count += pdi->ch_count;
636 pdi++;
637 }
638
639 *num_ch = ch_count;
640 return 0;
641}
642
643static int intel_pdi_stream_ch_update(struct sdw_intel *sdw,
d542bc9e 644 struct sdw_cdns_streams *stream, bool pcm)
37a2d22b
VK		 645{
646 intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd,
d542bc9e 647 &stream->num_ch_bd, pcm);
37a2d22b
VK		 648
649 intel_pdi_get_ch_update(sdw, stream->in, stream->num_in,
d542bc9e 650 &stream->num_ch_in, pcm);
37a2d22b
VK		 651
652 intel_pdi_get_ch_update(sdw, stream->out, stream->num_out,
d542bc9e 653 &stream->num_ch_out, pcm);
37a2d22b
VK		 654
655 return 0;
656}
657
658static int intel_pdi_ch_update(struct sdw_intel *sdw)
659{
660 /* First update PCM streams followed by PDM streams */
661 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm, true);
662 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pdm, false);
663
664 return 0;
665}
666
667static void
668intel_pdi_shim_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
669{
2523486b 670 void __iomem *shim = sdw->link_res->shim;
37a2d22b
VK		 671 unsigned int link_id = sdw->instance;
672 int pdi_conf = 0;
673
c134f914
PLB		 674 /* the Bulk and PCM streams are not contiguous */
675 pdi->intel_alh_id = (link_id * 16) + pdi->num + 3;
676 if (pdi->num >= 2)
677 pdi->intel_alh_id += 2;
37a2d22b
VK		 678
679 /*
680 * Program stream parameters to stream SHIM register
681 * This is applicable for PCM stream only.
682 */
683 if (pdi->type != SDW_STREAM_PCM)
684 return;
685
686 if (pdi->dir == SDW_DATA_DIR_RX)
687 pdi_conf |= SDW_SHIM_PCMSYCM_DIR;
688 else
689 pdi_conf &= ~(SDW_SHIM_PCMSYCM_DIR);
690
691 pdi_conf |= (pdi->intel_alh_id <<
692 SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_STREAM));
693 pdi_conf |= (pdi->l_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_LCHN));
694 pdi_conf |= (pdi->h_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_HCHN));
695
696 intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf);
697}
698
699static void
700intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
701{
2523486b 702 void __iomem *alh = sdw->link_res->alh;
37a2d22b
VK		 703 unsigned int link_id = sdw->instance;
704 unsigned int conf;
705
c134f914
PLB		 706 /* the Bulk and PCM streams are not contiguous */
707 pdi->intel_alh_id = (link_id * 16) + pdi->num + 3;
708 if (pdi->num >= 2)
709 pdi->intel_alh_id += 2;
37a2d22b
VK		 710
711 /* Program Stream config ALH register */
712 conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id));
713
714 conf |= (SDW_ALH_STRMZCFG_DMAT_VAL <<
715 SDW_REG_SHIFT(SDW_ALH_STRMZCFG_DMAT));
716
717 conf |= ((pdi->ch_count - 1) <<
718 SDW_REG_SHIFT(SDW_ALH_STRMZCFG_CHN));
719
720 intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf);
721}
722
4b206d34 723static int intel_params_stream(struct sdw_intel *sdw,
d542bc9e
PLB		 724 struct snd_pcm_substream *substream,
725 struct snd_soc_dai *dai,
4b206d34
RW		 726 struct snd_pcm_hw_params *hw_params,
727 int link_id, int alh_stream_id)
c46302ec 728{
2523486b 729 struct sdw_intel_link_res *res = sdw->link_res;
4b206d34 730 struct sdw_intel_stream_params_data params_data;
05c8afe4 731
4b206d34
RW		 732 params_data.substream = substream;
733 params_data.dai = dai;
734 params_data.hw_params = hw_params;
735 params_data.link_id = link_id;
736 params_data.alh_stream_id = alh_stream_id;
c46302ec 737
4b206d34
RW		 738 if (res->ops && res->ops->params_stream && res->dev)
739 return res->ops->params_stream(res->dev,
740 &params_data);
c46302ec
VK		 741 return -EIO;
742}
743
eff346f2
PLB		 744static int intel_free_stream(struct sdw_intel *sdw,
745 struct snd_pcm_substream *substream,
746 struct snd_soc_dai *dai,
747 int link_id)
748{
749 struct sdw_intel_link_res *res = sdw->link_res;
750 struct sdw_intel_stream_free_data free_data;
751
752 free_data.substream = substream;
753 free_data.dai = dai;
754 free_data.link_id = link_id;
755
756 if (res->ops && res->ops->free_stream && res->dev)
757 return res->ops->free_stream(res->dev,
758 &free_data);
759
760 return 0;
761}
762
30246e2d
SN		 763/*
764 * bank switch routines
765 */
766
767static int intel_pre_bank_switch(struct sdw_bus *bus)
768{
769 struct sdw_cdns *cdns = bus_to_cdns(bus);
770 struct sdw_intel *sdw = cdns_to_intel(cdns);
30246e2d
SN		 771
772 /* Write to register only for multi-link */
773 if (!bus->multi_link)
774 return 0;
775
02629e45 776 intel_shim_sync_arm(sdw);
30246e2d
SN		 777
778 return 0;
779}
780
781static int intel_post_bank_switch(struct sdw_bus *bus)
782{
783 struct sdw_cdns *cdns = bus_to_cdns(bus);
784 struct sdw_intel *sdw = cdns_to_intel(cdns);
2523486b 785 void __iomem *shim = sdw->link_res->shim;
30246e2d
SN		 786 int sync_reg, ret;
787
788 /* Write to register only for multi-link */
789 if (!bus->multi_link)
790 return 0;
791
4a17c441
PLB		 792 mutex_lock(sdw->link_res->shim_lock);
793
30246e2d
SN		 794 /* Read SYNC register */
795 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
796
797 /*
798 * post_bank_switch() ops is called from the bus in loop for
799 * all the Masters in the steam with the expectation that
800 * we trigger the bankswitch for the only first Master in the list
801 * and do nothing for the other Masters
802 *
803 * So, set the SYNCGO bit only if CMDSYNC bit is set for any Master.
804 */
4a17c441
PLB		 805 if (!(sync_reg & SDW_SHIM_SYNC_CMDSYNC_MASK)) {
806 ret = 0;
807 goto unlock;
808 }
30246e2d 809
437e3289 810 ret = intel_shim_sync_go_unlocked(sdw);
4a17c441
PLB		 811unlock:
812 mutex_unlock(sdw->link_res->shim_lock);
30246e2d 813
30246e2d 814 if (ret < 0)
17ed5bef 815 dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret);
30246e2d
SN		 816
817 return ret;
818}
819
c46302ec
VK		 820/*
821 * DAI routines
822 */
823
5e7484d0
RW		 824static int intel_startup(struct snd_pcm_substream *substream,
825 struct snd_soc_dai *dai)
826{
ebf878ed
PLB		 827 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
828 int ret;
829
830 ret = pm_runtime_get_sync(cdns->dev);
831 if (ret < 0 && ret != -EACCES) {
832 dev_err_ratelimited(cdns->dev,
833 "pm_runtime_get_sync failed in %s, ret %d\n",
834 __func__, ret);
835 pm_runtime_put_noidle(cdns->dev);
836 return ret;
837 }
ff16d1e5 838 return 0;
5e7484d0
RW		 839}
840
c46302ec 841static int intel_hw_params(struct snd_pcm_substream *substream,
d542bc9e
PLB		 842 struct snd_pcm_hw_params *params,
843 struct snd_soc_dai *dai)
c46302ec
VK		 844{
845 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
846 struct sdw_intel *sdw = cdns_to_intel(cdns);
847 struct sdw_cdns_dma_data *dma;
57a34790 848 struct sdw_cdns_pdi *pdi;
c46302ec
VK		 849 struct sdw_stream_config sconfig;
850 struct sdw_port_config *pconfig;
57a34790
PLB		 851 int ch, dir;
852 int ret;
c46302ec
VK		 853 bool pcm = true;
854
855 dma = snd_soc_dai_get_dma_data(dai, substream);
856 if (!dma)
857 return -EIO;
858
859 ch = params_channels(params);
860 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
861 dir = SDW_DATA_DIR_RX;
862 else
863 dir = SDW_DATA_DIR_TX;
864
57a34790 865 if (dma->stream_type == SDW_STREAM_PDM)
c46302ec 866 pcm = false;
c46302ec 867
57a34790 868 if (pcm)
1b53385e 869 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, ch, dir, dai->id);
57a34790 870 else
1b53385e 871 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pdm, ch, dir, dai->id);
57a34790
PLB		 872
873 if (!pdi) {
874 ret = -EINVAL;
875 goto error;
c46302ec
VK		 876 }
877
57a34790
PLB		 878 /* do run-time configurations for SHIM, ALH and PDI/PORT */
879 intel_pdi_shim_configure(sdw, pdi);
880 intel_pdi_alh_configure(sdw, pdi);
881 sdw_cdns_config_stream(cdns, ch, dir, pdi);
c46302ec 882
a5a0239c
BL		 883 /* store pdi and hw_params, may be needed in prepare step */
884 dma->suspended = false;
885 dma->pdi = pdi;
886 dma->hw_params = params;
c46302ec
VK		 887
888 /* Inform DSP about PDI stream number */
4b206d34
RW		 889 ret = intel_params_stream(sdw, substream, dai, params,
890 sdw->instance,
57a34790
PLB		 891 pdi->intel_alh_id);
892 if (ret)
893 goto error;
c46302ec
VK		 894
895 sconfig.direction = dir;
896 sconfig.ch_count = ch;
897 sconfig.frame_rate = params_rate(params);
898 sconfig.type = dma->stream_type;
899
900 if (dma->stream_type == SDW_STREAM_PDM) {
901 sconfig.frame_rate *= 50;
902 sconfig.bps = 1;
903 } else {
904 sconfig.bps = snd_pcm_format_width(params_format(params));
905 }
906
907 /* Port configuration */
57a34790 908 pconfig = kcalloc(1, sizeof(*pconfig), GFP_KERNEL);
c46302ec
VK		 909 if (!pconfig) {
910 ret = -ENOMEM;
57a34790 911 goto error;
c46302ec
VK		 912 }
913
57a34790
PLB		 914 pconfig->num = pdi->num;
915 pconfig->ch_mask = (1 << ch) - 1;
c46302ec
VK		 916
917 ret = sdw_stream_add_master(&cdns->bus, &sconfig,
57a34790
PLB		 918 pconfig, 1, dma->stream);
919 if (ret)
17ed5bef 920 dev_err(cdns->dev, "add master to stream failed:%d\n", ret);
c46302ec 921
c46302ec 922 kfree(pconfig);
57a34790 923error:
c46302ec
VK		 924 return ret;
925}
926
27b198f4
RW		 927static int intel_prepare(struct snd_pcm_substream *substream,
928 struct snd_soc_dai *dai)
929{
a5a0239c
BL		 930 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
931 struct sdw_intel *sdw = cdns_to_intel(cdns);
27b198f4 932 struct sdw_cdns_dma_data *dma;
a5a0239c
BL		 933 int ch, dir;
934 int ret;
27b198f4
RW		 935
936 dma = snd_soc_dai_get_dma_data(dai, substream);
937 if (!dma) {
938 dev_err(dai->dev, "failed to get dma data in %s",
939 __func__);
940 return -EIO;
941 }
942
a5a0239c
BL		 943 if (dma->suspended) {
944 dma->suspended = false;
945
946 /*
947 * .prepare() is called after system resume, where we
948 * need to reinitialize the SHIM/ALH/Cadence IP.
949 * .prepare() is also called to deal with underflows,
950 * but in those cases we cannot touch ALH/SHIM
951 * registers
952 */
953
954 /* configure stream */
955 ch = params_channels(dma->hw_params);
956 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
957 dir = SDW_DATA_DIR_RX;
958 else
959 dir = SDW_DATA_DIR_TX;
960
961 intel_pdi_shim_configure(sdw, dma->pdi);
962 intel_pdi_alh_configure(sdw, dma->pdi);
963 sdw_cdns_config_stream(cdns, ch, dir, dma->pdi);
964
965 /* Inform DSP about PDI stream number */
966 ret = intel_params_stream(sdw, substream, dai,
967 dma->hw_params,
968 sdw->instance,
969 dma->pdi->intel_alh_id);
970 if (ret)
971 goto err;
972 }
973
974 ret = sdw_prepare_stream(dma->stream);
975
976err:
977 return ret;
27b198f4
RW		 978}
979
973a8429
RW		 980static int intel_trigger(struct snd_pcm_substream *substream, int cmd,
981 struct snd_soc_dai *dai)
982{
983 struct sdw_cdns_dma_data *dma;
984 int ret;
985
986 dma = snd_soc_dai_get_dma_data(dai, substream);
987 if (!dma) {
988 dev_err(dai->dev, "failed to get dma data in %s", __func__);
989 return -EIO;
990 }
991
992 switch (cmd) {
993 case SNDRV_PCM_TRIGGER_START:
994 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
995 case SNDRV_PCM_TRIGGER_RESUME:
996 ret = sdw_enable_stream(dma->stream);
997 break;
998
999 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1000 case SNDRV_PCM_TRIGGER_SUSPEND:
1001 case SNDRV_PCM_TRIGGER_STOP:
1002 ret = sdw_disable_stream(dma->stream);
1003 break;
1004
1005 default:
1006 ret = -EINVAL;
1007 break;
1008 }
1009
1010 if (ret)
1011 dev_err(dai->dev,
1012 "%s trigger %d failed: %d",
1013 __func__, cmd, ret);
1014 return ret;
1015}
1016
c46302ec
VK		 1017static int
1018intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
1019{
1020 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
eff346f2 1021 struct sdw_intel *sdw = cdns_to_intel(cdns);
c46302ec
VK		 1022 struct sdw_cdns_dma_data *dma;
1023 int ret;
1024
1025 dma = snd_soc_dai_get_dma_data(dai, substream);
1026 if (!dma)
1027 return -EIO;
1028
eff346f2
PLB		 1029 ret = sdw_deprepare_stream(dma->stream);
1030 if (ret) {
1031 dev_err(dai->dev, "sdw_deprepare_stream: failed %d", ret);
1032 return ret;
1033 }
1034
c46302ec 1035 ret = sdw_stream_remove_master(&cdns->bus, dma->stream);
eff346f2 1036 if (ret < 0) {
17ed5bef 1037 dev_err(dai->dev, "remove master from stream %s failed: %d\n",
d542bc9e 1038 dma->stream->name, ret);
eff346f2
PLB		 1039 return ret;
1040 }
c46302ec 1041
eff346f2
PLB		 1042 ret = intel_free_stream(sdw, substream, dai, sdw->instance);
1043 if (ret < 0) {
1044 dev_err(dai->dev, "intel_free_stream: failed %d", ret);
1045 return ret;
1046 }
1047
a5a0239c
BL		 1048 dma->hw_params = NULL;
1049 dma->pdi = NULL;
1050
eff346f2 1051 return 0;
c46302ec
VK		 1052}
1053
183c7687
PLB		 1054static void intel_shutdown(struct snd_pcm_substream *substream,
1055 struct snd_soc_dai *dai)
1056{
ebf878ed 1057 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
183c7687 1058
ebf878ed
PLB		 1059 pm_runtime_mark_last_busy(cdns->dev);
1060 pm_runtime_put_autosuspend(cdns->dev);
183c7687
PLB		 1061}
1062
a5a0239c
BL		 1063static int intel_component_dais_suspend(struct snd_soc_component *component)
1064{
1065 struct sdw_cdns_dma_data *dma;
1066 struct snd_soc_dai *dai;
1067
1068 for_each_component_dais(component, dai) {
1069 /*
1070 * we don't have a .suspend dai_ops, and we don't have access
1071 * to the substream, so let's mark both capture and playback
1072 * DMA contexts as suspended
1073 */
1074 dma = dai->playback_dma_data;
1075 if (dma)
1076 dma->suspended = true;
1077
1078 dma = dai->capture_dma_data;
1079 if (dma)
1080 dma->suspended = true;
1081 }
1082
1083 return 0;
1084}
1085
c46302ec 1086static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai,
d542bc9e 1087 void *stream, int direction)
c46302ec
VK		 1088{
1089 return cdns_set_sdw_stream(dai, stream, true, direction);
1090}
1091
1092static int intel_pdm_set_sdw_stream(struct snd_soc_dai *dai,
d542bc9e 1093 void *stream, int direction)
c46302ec
VK		 1094{
1095 return cdns_set_sdw_stream(dai, stream, false, direction);
1096}
1097
09553140
PLB		 1098static void *intel_get_sdw_stream(struct snd_soc_dai *dai,
1099 int direction)
1100{
1101 struct sdw_cdns_dma_data *dma;
1102
1103 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1104 dma = dai->playback_dma_data;
1105 else
1106 dma = dai->capture_dma_data;
1107
1108 if (!dma)
1109 return NULL;
1110
1111 return dma->stream;
1112}
1113
b1635596 1114static const struct snd_soc_dai_ops intel_pcm_dai_ops = {
5e7484d0 1115 .startup = intel_startup,
c46302ec 1116 .hw_params = intel_hw_params,
27b198f4 1117 .prepare = intel_prepare,
973a8429 1118 .trigger = intel_trigger,
c46302ec 1119 .hw_free = intel_hw_free,
183c7687 1120 .shutdown = intel_shutdown,
c46302ec 1121 .set_sdw_stream = intel_pcm_set_sdw_stream,
09553140 1122 .get_sdw_stream = intel_get_sdw_stream,
c46302ec
VK		 1123};
1124
b1635596 1125static const struct snd_soc_dai_ops intel_pdm_dai_ops = {
5e7484d0 1126 .startup = intel_startup,
c46302ec 1127 .hw_params = intel_hw_params,
27b198f4 1128 .prepare = intel_prepare,
973a8429 1129 .trigger = intel_trigger,
c46302ec 1130 .hw_free = intel_hw_free,
183c7687 1131 .shutdown = intel_shutdown,
c46302ec 1132 .set_sdw_stream = intel_pdm_set_sdw_stream,
09553140 1133 .get_sdw_stream = intel_get_sdw_stream,
c46302ec
VK		 1134};
1135
1136static const struct snd_soc_component_driver dai_component = {
1137 .name = "soundwire",
a5a0239c 1138 .suspend = intel_component_dais_suspend
c46302ec
VK		 1139};
1140
1141static int intel_create_dai(struct sdw_cdns *cdns,
d542bc9e
PLB		 1142 struct snd_soc_dai_driver *dais,
1143 enum intel_pdi_type type,
1144 u32 num, u32 off, u32 max_ch, bool pcm)
c46302ec
VK		 1145{
1146 int i;
1147
1148 if (num == 0)
1149 return 0;
1150
1151 /* TODO: Read supported rates/formats from hardware */
1152 for (i = off; i < (off + num); i++) {
bf6d6e68
PLB		 1153 dais[i].name = devm_kasprintf(cdns->dev, GFP_KERNEL,
1154 "SDW%d Pin%d",
1155 cdns->instance, i);
c46302ec
VK		 1156 if (!dais[i].name)
1157 return -ENOMEM;
1158
1159 if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) {
c46302ec
VK		 1160 dais[i].playback.channels_min = 1;
1161 dais[i].playback.channels_max = max_ch;
1162 dais[i].playback.rates = SNDRV_PCM_RATE_48000;
1163 dais[i].playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
1164 }
1165
1166 if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) {
39194128
SK		 1167 dais[i].capture.channels_min = 1;
1168 dais[i].capture.channels_max = max_ch;
c46302ec
VK		 1169 dais[i].capture.rates = SNDRV_PCM_RATE_48000;
1170 dais[i].capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
1171 }
1172
c46302ec
VK		 1173 if (pcm)
1174 dais[i].ops = &intel_pcm_dai_ops;
1175 else
1176 dais[i].ops = &intel_pdm_dai_ops;
1177 }
1178
1179 return 0;
1180}
1181
1182static int intel_register_dai(struct sdw_intel *sdw)
1183{
1184 struct sdw_cdns *cdns = &sdw->cdns;
1185 struct sdw_cdns_streams *stream;
1186 struct snd_soc_dai_driver *dais;
1187 int num_dai, ret, off = 0;
1188
1189 /* DAIs are created based on total number of PDIs supported */
1190 num_dai = cdns->pcm.num_pdi + cdns->pdm.num_pdi;
1191
1192 dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL);
1193 if (!dais)
1194 return -ENOMEM;
1195
1196 /* Create PCM DAIs */
1197 stream = &cdns->pcm;
1198
cf924962 1199 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pcm.num_in,
1215daee 1200 off, stream->num_ch_in, true);
c46302ec
VK		 1201 if (ret)
1202 return ret;
1203
1204 off += cdns->pcm.num_in;
1215daee
VK		 1205 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out,
1206 off, stream->num_ch_out, true);
c46302ec
VK		 1207 if (ret)
1208 return ret;
1209
1210 off += cdns->pcm.num_out;
1215daee
VK		 1211 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd,
1212 off, stream->num_ch_bd, true);
c46302ec
VK		 1213 if (ret)
1214 return ret;
1215
1216 /* Create PDM DAIs */
1217 stream = &cdns->pdm;
1218 off += cdns->pcm.num_bd;
1215daee
VK		 1219 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pdm.num_in,
1220 off, stream->num_ch_in, false);
c46302ec
VK		 1221 if (ret)
1222 return ret;
1223
1224 off += cdns->pdm.num_in;
1215daee
VK		 1225 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pdm.num_out,
1226 off, stream->num_ch_out, false);
c46302ec
VK		 1227 if (ret)
1228 return ret;
1229
cf924962 1230 off += cdns->pdm.num_out;
1215daee
VK		 1231 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pdm.num_bd,
1232 off, stream->num_ch_bd, false);
c46302ec
VK		 1233 if (ret)
1234 return ret;
1235
1236 return snd_soc_register_component(cdns->dev, &dai_component,
d542bc9e 1237 dais, num_dai);
c46302ec
VK		 1238}
1239
085f4ace
PLB		 1240static int sdw_master_read_intel_prop(struct sdw_bus *bus)
1241{
1242 struct sdw_master_prop *prop = &bus->prop;
1243 struct fwnode_handle *link;
1244 char name[32];
395713d8 1245 u32 quirk_mask;
085f4ace
PLB		 1246
1247 /* Find master handle */
1248 snprintf(name, sizeof(name),
1249 "mipi-sdw-link-%d-subproperties", bus->link_id);
1250
1251 link = device_get_named_child_node(bus->dev, name);
1252 if (!link) {
1253 dev_err(bus->dev, "Master node %s not found\n", name);
1254 return -EIO;
1255 }
1256
1257 fwnode_property_read_u32(link,
1258 "intel-sdw-ip-clock",
1259 &prop->mclk_freq);
395713d8 1260
a19efb52
BL		 1261 /* the values reported by BIOS are the 2x clock, not the bus clock */
1262 prop->mclk_freq /= 2;
1263
395713d8
PLB		 1264 fwnode_property_read_u32(link,
1265 "intel-quirk-mask",
1266 &quirk_mask);
1267
1268 if (quirk_mask & SDW_INTEL_QUIRK_MASK_BUS_DISABLE)
1269 prop->hw_disabled = true;
1270
085f4ace
PLB		 1271 return 0;
1272}
1273
71bb8a1b
VK		 1274static int intel_prop_read(struct sdw_bus *bus)
1275{
1276 /* Initialize with default handler to read all DisCo properties */
1277 sdw_master_read_prop(bus);
1278
085f4ace
PLB		 1279 /* read Intel-specific properties */
1280 sdw_master_read_intel_prop(bus);
1281
71bb8a1b
VK		 1282 return 0;
1283}
1284
c91605f4
SN		 1285static struct sdw_master_ops sdw_intel_ops = {
1286 .read_prop = sdw_master_read_prop,
1287 .xfer_msg = cdns_xfer_msg,
1288 .xfer_msg_defer = cdns_xfer_msg_defer,
1289 .reset_page_addr = cdns_reset_page_addr,
07abeff1 1290 .set_bus_conf = cdns_bus_conf,
30246e2d
SN		 1291 .pre_bank_switch = intel_pre_bank_switch,
1292 .post_bank_switch = intel_post_bank_switch,
c91605f4
SN		 1293};
1294
dfbe642d
PLB		 1295static int intel_init(struct sdw_intel *sdw)
1296{
4a17c441
PLB		 1297 bool clock_stop;
1298
dfbe642d
PLB		 1299 /* Initialize shim and controller */
1300 intel_link_power_up(sdw);
4a17c441
PLB		 1301
1302 clock_stop = sdw_cdns_is_clock_stop(&sdw->cdns);
1303
1304 intel_shim_init(sdw, clock_stop);
1305
1306 if (clock_stop)
1307 return 0;
dfbe642d 1308
7b174f24 1309 return sdw_cdns_init(&sdw->cdns);
dfbe642d
PLB		 1310}
1311
71bb8a1b
VK		 1312/*
1313 * probe and init
1314 */
b6109dd6 1315static int intel_master_probe(struct platform_device *pdev)
71bb8a1b 1316{
b6109dd6 1317 struct device *dev = &pdev->dev;
71bb8a1b 1318 struct sdw_intel *sdw;
83e129af 1319 struct sdw_cdns *cdns;
b6109dd6 1320 struct sdw_bus *bus;
71bb8a1b
VK		 1321 int ret;
1322
b6109dd6 1323 sdw = devm_kzalloc(dev, sizeof(*sdw), GFP_KERNEL);
71bb8a1b
VK		 1324 if (!sdw)
1325 return -ENOMEM;
1326
83e129af
PLB		 1327 cdns = &sdw->cdns;
1328 bus = &cdns->bus;
b6109dd6 1329
71bb8a1b 1330 sdw->instance = pdev->id;
b6109dd6 1331 sdw->link_res = dev_get_platdata(dev);
83e129af
PLB		 1332 cdns->dev = dev;
1333 cdns->registers = sdw->link_res->registers;
1334 cdns->instance = sdw->instance;
1335 cdns->msg_count = 0;
1336
b6109dd6 1337 bus->link_id = pdev->id;
71bb8a1b 1338
83e129af 1339 sdw_cdns_probe(cdns);
71bb8a1b
VK		 1340
1341 /* Set property read ops */
c91605f4 1342 sdw_intel_ops.read_prop = intel_prop_read;
b6109dd6 1343 bus->ops = &sdw_intel_ops;
71bb8a1b 1344
b6109dd6 1345 /* set driver data, accessed by snd_soc_dai_get_drvdata() */
83e129af 1346 dev_set_drvdata(dev, cdns);
71bb8a1b 1347
b6109dd6 1348 ret = sdw_bus_master_add(bus, dev, dev->fwnode);
71bb8a1b 1349 if (ret) {
b6109dd6 1350 dev_err(dev, "sdw_bus_master_add fail: %d\n", ret);
9e3d47fb 1351 return ret;
71bb8a1b
VK		 1352 }
1353
6d2c6669 1354 if (bus->prop.hw_disabled)
b6109dd6
PLB		 1355 dev_info(dev,
1356 "SoundWire master %d is disabled, will be ignored\n",
1357 bus->link_id);
0ef2986e
PLB		 1358 /*
1359 * Ignore BIOS err_threshold, it's a really bad idea when dealing
1360 * with multiple hardware synchronized links
1361 */
1362 bus->prop.err_threshold = 0;
6d2c6669 1363
6d2c6669 1364 return 0;
6d2c6669
PLB		 1365}
1366
1367int intel_master_startup(struct platform_device *pdev)
1368{
1369 struct sdw_cdns_stream_config config;
1370 struct device *dev = &pdev->dev;
1371 struct sdw_cdns *cdns = dev_get_drvdata(dev);
1372 struct sdw_intel *sdw = cdns_to_intel(cdns);
1373 struct sdw_bus *bus = &cdns->bus;
ebf878ed 1374 int link_flags;
caf68819 1375 u32 clock_stop_quirks;
6d2c6669
PLB		 1376 int ret;
1377
1378 if (bus->prop.hw_disabled) {
1379 dev_info(dev,
1380 "SoundWire master %d is disabled, ignoring\n",
1381 sdw->instance);
395713d8
PLB		 1382 return 0;
1383 }
1384
dfbe642d
PLB		 1385 /* Initialize shim, controller and Cadence IP */
1386 ret = intel_init(sdw);
71bb8a1b
VK		 1387 if (ret)
1388 goto err_init;
1389
37a2d22b
VK		 1390 /* Read the PDI config and initialize cadence PDI */
1391 intel_pdi_init(sdw, &config);
83e129af 1392 ret = sdw_cdns_pdi_init(cdns, config);
71bb8a1b
VK		 1393 if (ret)
1394 goto err_init;
1395
37a2d22b
VK		 1396 intel_pdi_ch_update(sdw);
1397
83e129af 1398 ret = sdw_cdns_enable_interrupt(cdns, true);
71bb8a1b 1399 if (ret < 0) {
b6109dd6 1400 dev_err(dev, "cannot enable interrupts\n");
71bb8a1b
VK		 1401 goto err_init;
1402 }
1403
83e129af 1404 ret = sdw_cdns_exit_reset(cdns);
49ea07d3 1405 if (ret < 0) {
b6109dd6 1406 dev_err(dev, "unable to exit bus reset sequence\n");
9e3d47fb 1407 goto err_interrupt;
49ea07d3
PLB		 1408 }
1409
c46302ec
VK		 1410 /* Register DAIs */
1411 ret = intel_register_dai(sdw);
1412 if (ret) {
b6109dd6
PLB		 1413 dev_err(dev, "DAI registration failed: %d\n", ret);
1414 snd_soc_unregister_component(dev);
9e3d47fb 1415 goto err_interrupt;
c46302ec
VK		 1416 }
1417
79ee6631
PLB		 1418 intel_debugfs_init(sdw);
1419
ebf878ed
PLB		 1420 /* Enable runtime PM */
1421 link_flags = md_flags >> (bus->link_id * 8);
1422 if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME)) {
1423 pm_runtime_set_autosuspend_delay(dev,
1424 INTEL_MASTER_SUSPEND_DELAY_MS);
1425 pm_runtime_use_autosuspend(dev);
1426 pm_runtime_mark_last_busy(dev);
1427
1428 pm_runtime_set_active(dev);
1429 pm_runtime_enable(dev);
1430 }
1431
caf68819
PLB		 1432 clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1433 if (clock_stop_quirks & SDW_INTEL_CLK_STOP_NOT_ALLOWED) {
1434 /*
1435 * To keep the clock running we need to prevent
1436 * pm_runtime suspend from happening by increasing the
1437 * reference count.
1438 * This quirk is specified by the parent PCI device in
1439 * case of specific latency requirements. It will have
1440 * no effect if pm_runtime is disabled by the user via
1441 * a module parameter for testing purposes.
1442 */
1443 pm_runtime_get_noresume(dev);
1444 }
1445
a2d9c161
PLB		 1446 /*
1447 * The runtime PM status of Slave devices is "Unsupported"
1448 * until they report as ATTACHED. If they don't, e.g. because
1449 * there are no Slave devices populated or if the power-on is
1450 * delayed or dependent on a power switch, the Master will
1451 * remain active and prevent its parent from suspending.
1452 *
1453 * Conditionally force the pm_runtime core to re-evaluate the
1454 * Master status in the absence of any Slave activity. A quirk
1455 * is provided to e.g. deal with Slaves that may be powered on
1456 * with a delay. A more complete solution would require the
1457 * definition of Master properties.
1458 */
1459 if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE))
1460 pm_runtime_idle(dev);
1461
71bb8a1b
VK		 1462 return 0;
1463
9e3d47fb 1464err_interrupt:
83e129af 1465 sdw_cdns_enable_interrupt(cdns, false);
71bb8a1b 1466err_init:
71bb8a1b
VK		 1467 return ret;
1468}
1469
b6109dd6 1470static int intel_master_remove(struct platform_device *pdev)
71bb8a1b 1471{
b6109dd6 1472 struct device *dev = &pdev->dev;
83e129af
PLB		 1473 struct sdw_cdns *cdns = dev_get_drvdata(dev);
1474 struct sdw_intel *sdw = cdns_to_intel(cdns);
1475 struct sdw_bus *bus = &cdns->bus;
b6109dd6 1476
caf68819
PLB		 1477 /*
1478 * Since pm_runtime is already disabled, we don't decrease
1479 * the refcount when the clock_stop_quirk is
1480 * SDW_INTEL_CLK_STOP_NOT_ALLOWED
1481 */
b6109dd6 1482 if (!bus->prop.hw_disabled) {
395713d8 1483 intel_debugfs_exit(sdw);
83e129af 1484 sdw_cdns_enable_interrupt(cdns, false);
b6109dd6 1485 snd_soc_unregister_component(dev);
395713d8 1486 }
b6109dd6 1487 sdw_bus_master_delete(bus);
71bb8a1b
VK		 1488
1489 return 0;
1490}
1491
ab2c9132
RW		 1492int intel_master_process_wakeen_event(struct platform_device *pdev)
1493{
1494 struct device *dev = &pdev->dev;
71bb8a1b 1495 struct sdw_intel *sdw;
ab2c9132
RW		 1496 struct sdw_bus *bus;
1497 void __iomem *shim;
1498 u16 wake_sts;
71bb8a1b
VK		 1499
1500 sdw = platform_get_drvdata(pdev);
ab2c9132 1501 bus = &sdw->cdns.bus;
71bb8a1b 1502
ab2c9132
RW		 1503 if (bus->prop.hw_disabled) {
1504 dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n", bus->link_id);
1505 return 0;
395713d8 1506 }
ab2c9132
RW		 1507
1508 shim = sdw->link_res->shim;
1509 wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS);
1510
1511 if (!(wake_sts & BIT(sdw->instance)))
1512 return 0;
1513
1514 /* disable WAKEEN interrupt ASAP to prevent interrupt flood */
1515 intel_shim_wake(sdw, false);
1516
1517 /*
1518 * resume the Master, which will generate a bus reset and result in
1519 * Slaves re-attaching and be re-enumerated. The SoundWire physical
1520 * device which generated the wake will trigger an interrupt, which
1521 * will in turn cause the corresponding Linux Slave device to be
1522 * resumed and the Slave codec driver to check the status.
1523 */
1524 pm_request_resume(dev);
71bb8a1b
VK		 1525
1526 return 0;
1527}
1528
9b3b4b3f
PLB		 1529/*
1530 * PM calls
1531 */
1532
1533#ifdef CONFIG_PM
1534
f046b233 1535static int __maybe_unused intel_suspend(struct device *dev)
9b3b4b3f
PLB		 1536{
1537 struct sdw_cdns *cdns = dev_get_drvdata(dev);
1538 struct sdw_intel *sdw = cdns_to_intel(cdns);
1539 struct sdw_bus *bus = &cdns->bus;
e4be9fac 1540 u32 clock_stop_quirks;
9b3b4b3f
PLB		 1541 int ret;
1542
1543 if (bus->prop.hw_disabled) {
1544 dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n",
1545 bus->link_id);
1546 return 0;
1547 }
1548
b61b8b37
PLB		 1549 if (pm_runtime_suspended(dev)) {
1550 dev_dbg(dev, "%s: pm_runtime status: suspended\n", __func__);
1551
e4be9fac
PLB		 1552 clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1553
1554 if ((clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET ||
1555 !clock_stop_quirks) &&
1556 !pm_runtime_suspended(dev->parent)) {
1557
1558 /*
1559 * if we've enabled clock stop, and the parent
1560 * is still active, disable shim wake. The
1561 * SHIM registers are not accessible if the
1562 * parent is already pm_runtime suspended so
1563 * it's too late to change that configuration
1564 */
1565
1566 intel_shim_wake(sdw, false);
1567 }
1568
b61b8b37
PLB		 1569 return 0;
1570 }
1571
9b3b4b3f
PLB		 1572 ret = sdw_cdns_enable_interrupt(cdns, false);
1573 if (ret < 0) {
1574 dev_err(dev, "cannot disable interrupts on suspend\n");
1575 return ret;
1576 }
1577
1578 ret = intel_link_power_down(sdw);
1579 if (ret) {
1580 dev_err(dev, "Link power down failed: %d", ret);
1581 return ret;
1582 }
1583
1584 intel_shim_wake(sdw, false);
1585
1586 return 0;
1587}
1588
ebf878ed
PLB		 1589static int intel_suspend_runtime(struct device *dev)
1590{
1591 struct sdw_cdns *cdns = dev_get_drvdata(dev);
1592 struct sdw_intel *sdw = cdns_to_intel(cdns);
1593 struct sdw_bus *bus = &cdns->bus;
a320f41e 1594 u32 clock_stop_quirks;
ebf878ed
PLB		 1595 int ret;
1596
1597 if (bus->prop.hw_disabled) {
1598 dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n",
1599 bus->link_id);
1600 return 0;
1601 }
1602
a320f41e 1603 clock_stop_quirks = sdw->link_res->clock_stop_quirks;
ebf878ed 1604
a320f41e 1605 if (clock_stop_quirks & SDW_INTEL_CLK_STOP_TEARDOWN) {
ebf878ed 1606
a320f41e
PLB		 1607 ret = sdw_cdns_enable_interrupt(cdns, false);
1608 if (ret < 0) {
1609 dev_err(dev, "cannot disable interrupts on suspend\n");
1610 return ret;
1611 }
ebf878ed 1612
a320f41e
PLB		 1613 ret = intel_link_power_down(sdw);
1614 if (ret) {
1615 dev_err(dev, "Link power down failed: %d", ret);
1616 return ret;
1617 }
1618
1619 intel_shim_wake(sdw, false);
1620
61fb830b
PLB		 1621 } else if (clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET ||
1622 !clock_stop_quirks) {
6626a616
RW		 1623 ret = sdw_cdns_clock_stop(cdns, true);
1624 if (ret < 0) {
1625 dev_err(dev, "cannot enable clock stop on suspend\n");
1626 return ret;
1627 }
1628
1629 ret = sdw_cdns_enable_interrupt(cdns, false);
1630 if (ret < 0) {
1631 dev_err(dev, "cannot disable interrupts on suspend\n");
1632 return ret;
1633 }
1634
1635 ret = intel_link_power_down(sdw);
1636 if (ret) {
1637 dev_err(dev, "Link power down failed: %d", ret);
1638 return ret;
1639 }
1640
1641 intel_shim_wake(sdw, true);
a320f41e
PLB		 1642 } else {
1643 dev_err(dev, "%s clock_stop_quirks %x unsupported\n",
1644 __func__, clock_stop_quirks);
1645 ret = -EINVAL;
1646 }
1647
1648 return ret;
ebf878ed
PLB		 1649}
1650
f046b233 1651static int __maybe_unused intel_resume(struct device *dev)
9b3b4b3f
PLB		 1652{
1653 struct sdw_cdns *cdns = dev_get_drvdata(dev);
1654 struct sdw_intel *sdw = cdns_to_intel(cdns);
1655 struct sdw_bus *bus = &cdns->bus;
a2d9c161 1656 int link_flags;
9b3b4b3f
PLB		 1657 int ret;
1658
1659 if (bus->prop.hw_disabled) {
1660 dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n",
1661 bus->link_id);
1662 return 0;
1663 }
1664
b61b8b37
PLB		 1665 if (pm_runtime_suspended(dev)) {
1666 dev_dbg(dev, "%s: pm_runtime status was suspended, forcing active\n", __func__);
1667
1668 /* follow required sequence from runtime_pm.rst */
1669 pm_runtime_disable(dev);
1670 pm_runtime_set_active(dev);
1671 pm_runtime_mark_last_busy(dev);
1672 pm_runtime_enable(dev);
a2d9c161
PLB		 1673
1674 link_flags = md_flags >> (bus->link_id * 8);
1675 if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE))
1676 pm_runtime_idle(dev);
b61b8b37
PLB		 1677 }
1678
9b3b4b3f
PLB		 1679 ret = intel_init(sdw);
1680 if (ret) {
1681 dev_err(dev, "%s failed: %d", __func__, ret);
1682 return ret;
1683 }
1684
99b6a30f
PLB		 1685 /*
1686 * make sure all Slaves are tagged as UNATTACHED and provide
1687 * reason for reinitialization
1688 */
1689 sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET);
1690
9b3b4b3f
PLB		 1691 ret = sdw_cdns_enable_interrupt(cdns, true);
1692 if (ret < 0) {
1693 dev_err(dev, "cannot enable interrupts during resume\n");
1694 return ret;
1695 }
1696
1697 ret = sdw_cdns_exit_reset(cdns);
1698 if (ret < 0) {
1699 dev_err(dev, "unable to exit bus reset sequence during resume\n");
1700 return ret;
1701 }
1702
cb1e6d59
PLB		 1703 /*
1704 * after system resume, the pm_runtime suspend() may kick in
1705 * during the enumeration, before any children device force the
1706 * master device to remain active. Using pm_runtime_get()
1707 * routines is not really possible, since it'd prevent the
1708 * master from suspending.
1709 * A reasonable compromise is to update the pm_runtime
1710 * counters and delay the pm_runtime suspend by several
1711 * seconds, by when all enumeration should be complete.
1712 */
1713 pm_runtime_mark_last_busy(dev);
1714
9b3b4b3f
PLB		 1715 return ret;
1716}
1717
ebf878ed
PLB		 1718static int intel_resume_runtime(struct device *dev)
1719{
1720 struct sdw_cdns *cdns = dev_get_drvdata(dev);
1721 struct sdw_intel *sdw = cdns_to_intel(cdns);
1722 struct sdw_bus *bus = &cdns->bus;
a320f41e 1723 u32 clock_stop_quirks;
08abad9f
RW		 1724 bool clock_stop0;
1725 int status;
ebf878ed
PLB		 1726 int ret;
1727
1728 if (bus->prop.hw_disabled) {
1729 dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n",
1730 bus->link_id);
1731 return 0;
1732 }
1733
a320f41e 1734 clock_stop_quirks = sdw->link_res->clock_stop_quirks;
ebf878ed 1735
a320f41e
PLB		 1736 if (clock_stop_quirks & SDW_INTEL_CLK_STOP_TEARDOWN) {
1737 ret = intel_init(sdw);
1738 if (ret) {
1739 dev_err(dev, "%s failed: %d", __func__, ret);
1740 return ret;
1741 }
99b6a30f 1742
a320f41e
PLB		 1743 /*
1744 * make sure all Slaves are tagged as UNATTACHED and provide
1745 * reason for reinitialization
1746 */
1747 sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET);
ebf878ed 1748
a320f41e
PLB		 1749 ret = sdw_cdns_enable_interrupt(cdns, true);
1750 if (ret < 0) {
1751 dev_err(dev, "cannot enable interrupts during resume\n");
1752 return ret;
1753 }
1754
1755 ret = sdw_cdns_exit_reset(cdns);
1756 if (ret < 0) {
1757 dev_err(dev, "unable to exit bus reset sequence during resume\n");
1758 return ret;
1759 }
6626a616
RW		 1760 } else if (clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET) {
1761 ret = intel_init(sdw);
1762 if (ret) {
1763 dev_err(dev, "%s failed: %d", __func__, ret);
1764 return ret;
1765 }
1766
08abad9f
RW		 1767 /*
1768 * An exception condition occurs for the CLK_STOP_BUS_RESET
1769 * case if one or more masters remain active. In this condition,
1770 * all the masters are powered on for they are in the same power
1771 * domain. Master can preserve its context for clock stop0, so
1772 * there is no need to clear slave status and reset bus.
1773 */
1774 clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns);
1775
6626a616
RW		 1776 /*
1777 * make sure all Slaves are tagged as UNATTACHED and
1778 * provide reason for reinitialization
1779 */
08abad9f
RW		 1780 if (!clock_stop0) {
1781 status = SDW_UNATTACH_REQUEST_MASTER_RESET;
1782 sdw_clear_slave_status(bus, status);
1783 }
1784
6626a616
RW		 1785
1786 ret = sdw_cdns_enable_interrupt(cdns, true);
1787 if (ret < 0) {
1788 dev_err(dev, "cannot enable interrupts during resume\n");
1789 return ret;
1790 }
1791
08abad9f 1792 ret = sdw_cdns_clock_restart(cdns, !clock_stop0);
6626a616
RW		 1793 if (ret < 0) {
1794 dev_err(dev, "unable to restart clock during resume\n");
1795 return ret;
1796 }
61fb830b
PLB		 1797 } else if (!clock_stop_quirks) {
1798 ret = intel_init(sdw);
1799 if (ret) {
1800 dev_err(dev, "%s failed: %d", __func__, ret);
1801 return ret;
1802 }
1803
1804 ret = sdw_cdns_enable_interrupt(cdns, true);
1805 if (ret < 0) {
1806 dev_err(dev, "cannot enable interrupts during resume\n");
1807 return ret;
1808 }
1809
1810 ret = sdw_cdns_clock_restart(cdns, false);
1811 if (ret < 0) {
1812 dev_err(dev, "unable to resume master during resume\n");
1813 return ret;
1814 }
a320f41e
PLB		 1815 } else {
1816 dev_err(dev, "%s clock_stop_quirks %x unsupported\n",
1817 __func__, clock_stop_quirks);
1818 ret = -EINVAL;
ebf878ed
PLB		 1819 }
1820
1821 return ret;
1822}
1823
9b3b4b3f
PLB		 1824#endif
1825
1826static const struct dev_pm_ops intel_pm = {
1827 SET_SYSTEM_SLEEP_PM_OPS(intel_suspend, intel_resume)
ebf878ed 1828 SET_RUNTIME_PM_OPS(intel_suspend_runtime, intel_resume_runtime, NULL)
9b3b4b3f
PLB		 1829};
1830
71bb8a1b 1831static struct platform_driver sdw_intel_drv = {
b6109dd6
PLB		 1832 .probe = intel_master_probe,
1833 .remove = intel_master_remove,
71bb8a1b 1834 .driver = {
6d2c6669 1835 .name = "intel-sdw",
9b3b4b3f
PLB		 1836 .pm = &intel_pm,
1837 }
71bb8a1b
VK		 1838};
1839
1840module_platform_driver(sdw_intel_drv);
1841
1842MODULE_LICENSE("Dual BSD/GPL");
6d2c6669 1843MODULE_ALIAS("platform:intel-sdw");
71bb8a1b 1844MODULE_DESCRIPTION("Intel Soundwire Master Driver");
Linux 6.x block layer and io_uring tree(s)