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7c3cd189 VK |
1 | // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) |
2 | // Copyright(c) 2015-17 Intel Corporation. | |
3 | ||
4 | #include <linux/acpi.h> | |
0231453b | 5 | #include <linux/delay.h> |
7c3cd189 | 6 | #include <linux/mod_devicetable.h> |
9d715fa0 VK |
7 | #include <linux/pm_runtime.h> |
8 | #include <linux/soundwire/sdw_registers.h> | |
7c3cd189 VK |
9 | #include <linux/soundwire/sdw.h> |
10 | #include "bus.h" | |
bcac5902 | 11 | #include "sysfs_local.h" |
7c3cd189 | 12 | |
dbb50c7a BL |
13 | static DEFINE_IDA(sdw_ida); |
14 | ||
15 | static int sdw_get_id(struct sdw_bus *bus) | |
16 | { | |
17 | int rc = ida_alloc(&sdw_ida, GFP_KERNEL); | |
18 | ||
19 | if (rc < 0) | |
20 | return rc; | |
21 | ||
22 | bus->id = rc; | |
23 | return 0; | |
24 | } | |
25 | ||
7c3cd189 | 26 | /** |
5cab3ff2 | 27 | * sdw_bus_master_add() - add a bus Master instance |
7c3cd189 | 28 | * @bus: bus instance |
5cab3ff2 PLB |
29 | * @parent: parent device |
30 | * @fwnode: firmware node handle | |
7c3cd189 VK |
31 | * |
32 | * Initializes the bus instance, read properties and create child | |
33 | * devices. | |
34 | */ | |
5cab3ff2 PLB |
35 | int sdw_bus_master_add(struct sdw_bus *bus, struct device *parent, |
36 | struct fwnode_handle *fwnode) | |
7c3cd189 | 37 | { |
5c3eb9f7 | 38 | struct sdw_master_prop *prop = NULL; |
7c3cd189 VK |
39 | int ret; |
40 | ||
7ceaa40b PLB |
41 | if (!parent) { |
42 | pr_err("SoundWire parent device is not set\n"); | |
7c3cd189 VK |
43 | return -ENODEV; |
44 | } | |
45 | ||
dbb50c7a | 46 | ret = sdw_get_id(bus); |
a5759f19 | 47 | if (ret < 0) { |
7ceaa40b PLB |
48 | dev_err(parent, "Failed to get bus id\n"); |
49 | return ret; | |
50 | } | |
51 | ||
52 | ret = sdw_master_device_add(bus, parent, fwnode); | |
a5759f19 | 53 | if (ret < 0) { |
7ceaa40b PLB |
54 | dev_err(parent, "Failed to add master device at link %d\n", |
55 | bus->link_id); | |
dbb50c7a BL |
56 | return ret; |
57 | } | |
58 | ||
9d715fa0 | 59 | if (!bus->ops) { |
17ed5bef | 60 | dev_err(bus->dev, "SoundWire Bus ops are not set\n"); |
9d715fa0 VK |
61 | return -EINVAL; |
62 | } | |
63 | ||
9026118f BL |
64 | if (!bus->compute_params) { |
65 | dev_err(bus->dev, | |
66 | "Bandwidth allocation not configured, compute_params no set\n"); | |
67 | return -EINVAL; | |
68 | } | |
69 | ||
9d715fa0 | 70 | mutex_init(&bus->msg_lock); |
7c3cd189 VK |
71 | mutex_init(&bus->bus_lock); |
72 | INIT_LIST_HEAD(&bus->slaves); | |
89e59053 | 73 | INIT_LIST_HEAD(&bus->m_rt_list); |
7c3cd189 | 74 | |
ce6e74d0 SN |
75 | /* |
76 | * Initialize multi_link flag | |
77 | * TODO: populate this flag by reading property from FW node | |
78 | */ | |
79 | bus->multi_link = false; | |
56d4fe31 VK |
80 | if (bus->ops->read_prop) { |
81 | ret = bus->ops->read_prop(bus); | |
82 | if (ret < 0) { | |
62f0cec3 VK |
83 | dev_err(bus->dev, |
84 | "Bus read properties failed:%d\n", ret); | |
56d4fe31 VK |
85 | return ret; |
86 | } | |
87 | } | |
88 | ||
bf03473d PLB |
89 | sdw_bus_debugfs_init(bus); |
90 | ||
7c3cd189 | 91 | /* |
21c2de29 | 92 | * Device numbers in SoundWire are 0 through 15. Enumeration device |
7c3cd189 VK |
93 | * number (0), Broadcast device number (15), Group numbers (12 and |
94 | * 13) and Master device number (14) are not used for assignment so | |
95 | * mask these and other higher bits. | |
96 | */ | |
97 | ||
98 | /* Set higher order bits */ | |
99 | *bus->assigned = ~GENMASK(SDW_BROADCAST_DEV_NUM, SDW_ENUM_DEV_NUM); | |
100 | ||
101 | /* Set enumuration device number and broadcast device number */ | |
102 | set_bit(SDW_ENUM_DEV_NUM, bus->assigned); | |
103 | set_bit(SDW_BROADCAST_DEV_NUM, bus->assigned); | |
104 | ||
105 | /* Set group device numbers and master device number */ | |
106 | set_bit(SDW_GROUP12_DEV_NUM, bus->assigned); | |
107 | set_bit(SDW_GROUP13_DEV_NUM, bus->assigned); | |
108 | set_bit(SDW_MASTER_DEV_NUM, bus->assigned); | |
109 | ||
110 | /* | |
111 | * SDW is an enumerable bus, but devices can be powered off. So, | |
112 | * they won't be able to report as present. | |
113 | * | |
114 | * Create Slave devices based on Slaves described in | |
115 | * the respective firmware (ACPI/DT) | |
116 | */ | |
117 | if (IS_ENABLED(CONFIG_ACPI) && ACPI_HANDLE(bus->dev)) | |
118 | ret = sdw_acpi_find_slaves(bus); | |
a2e48458 SK |
119 | else if (IS_ENABLED(CONFIG_OF) && bus->dev->of_node) |
120 | ret = sdw_of_find_slaves(bus); | |
7c3cd189 VK |
121 | else |
122 | ret = -ENOTSUPP; /* No ACPI/DT so error out */ | |
123 | ||
a5759f19 | 124 | if (ret < 0) { |
7c3cd189 VK |
125 | dev_err(bus->dev, "Finding slaves failed:%d\n", ret); |
126 | return ret; | |
127 | } | |
128 | ||
99b8a5d6 | 129 | /* |
5c3eb9f7 | 130 | * Initialize clock values based on Master properties. The max |
3424305b | 131 | * frequency is read from max_clk_freq property. Current assumption |
5c3eb9f7 SK |
132 | * is that the bus will start at highest clock frequency when |
133 | * powered on. | |
134 | * | |
99b8a5d6 SK |
135 | * Default active bank will be 0 as out of reset the Slaves have |
136 | * to start with bank 0 (Table 40 of Spec) | |
137 | */ | |
5c3eb9f7 | 138 | prop = &bus->prop; |
3424305b | 139 | bus->params.max_dr_freq = prop->max_clk_freq * SDW_DOUBLE_RATE_FACTOR; |
5c3eb9f7 | 140 | bus->params.curr_dr_freq = bus->params.max_dr_freq; |
99b8a5d6 SK |
141 | bus->params.curr_bank = SDW_BANK0; |
142 | bus->params.next_bank = SDW_BANK1; | |
143 | ||
7c3cd189 VK |
144 | return 0; |
145 | } | |
5cab3ff2 | 146 | EXPORT_SYMBOL(sdw_bus_master_add); |
7c3cd189 VK |
147 | |
148 | static int sdw_delete_slave(struct device *dev, void *data) | |
149 | { | |
150 | struct sdw_slave *slave = dev_to_sdw_dev(dev); | |
151 | struct sdw_bus *bus = slave->bus; | |
152 | ||
dff70572 PLB |
153 | pm_runtime_disable(dev); |
154 | ||
bf03473d PLB |
155 | sdw_slave_debugfs_exit(slave); |
156 | ||
7c3cd189 VK |
157 | mutex_lock(&bus->bus_lock); |
158 | ||
159 | if (slave->dev_num) /* clear dev_num if assigned */ | |
160 | clear_bit(slave->dev_num, bus->assigned); | |
161 | ||
162 | list_del_init(&slave->node); | |
163 | mutex_unlock(&bus->bus_lock); | |
164 | ||
165 | device_unregister(dev); | |
166 | return 0; | |
167 | } | |
168 | ||
169 | /** | |
5cab3ff2 | 170 | * sdw_bus_master_delete() - delete the bus master instance |
7c3cd189 VK |
171 | * @bus: bus to be deleted |
172 | * | |
173 | * Remove the instance, delete the child devices. | |
174 | */ | |
5cab3ff2 | 175 | void sdw_bus_master_delete(struct sdw_bus *bus) |
7c3cd189 VK |
176 | { |
177 | device_for_each_child(bus->dev, NULL, sdw_delete_slave); | |
7ceaa40b | 178 | sdw_master_device_del(bus); |
bf03473d PLB |
179 | |
180 | sdw_bus_debugfs_exit(bus); | |
dbb50c7a | 181 | ida_free(&sdw_ida, bus->id); |
7c3cd189 | 182 | } |
5cab3ff2 | 183 | EXPORT_SYMBOL(sdw_bus_master_delete); |
7c3cd189 | 184 | |
9d715fa0 VK |
185 | /* |
186 | * SDW IO Calls | |
187 | */ | |
188 | ||
189 | static inline int find_response_code(enum sdw_command_response resp) | |
190 | { | |
191 | switch (resp) { | |
192 | case SDW_CMD_OK: | |
193 | return 0; | |
194 | ||
195 | case SDW_CMD_IGNORED: | |
196 | return -ENODATA; | |
197 | ||
198 | case SDW_CMD_TIMEOUT: | |
199 | return -ETIMEDOUT; | |
200 | ||
201 | default: | |
202 | return -EIO; | |
203 | } | |
204 | } | |
205 | ||
206 | static inline int do_transfer(struct sdw_bus *bus, struct sdw_msg *msg) | |
207 | { | |
208 | int retry = bus->prop.err_threshold; | |
209 | enum sdw_command_response resp; | |
210 | int ret = 0, i; | |
211 | ||
212 | for (i = 0; i <= retry; i++) { | |
213 | resp = bus->ops->xfer_msg(bus, msg); | |
214 | ret = find_response_code(resp); | |
215 | ||
216 | /* if cmd is ok or ignored return */ | |
217 | if (ret == 0 || ret == -ENODATA) | |
218 | return ret; | |
219 | } | |
220 | ||
221 | return ret; | |
222 | } | |
223 | ||
224 | static inline int do_transfer_defer(struct sdw_bus *bus, | |
73ede046 PLB |
225 | struct sdw_msg *msg, |
226 | struct sdw_defer *defer) | |
9d715fa0 VK |
227 | { |
228 | int retry = bus->prop.err_threshold; | |
229 | enum sdw_command_response resp; | |
230 | int ret = 0, i; | |
231 | ||
232 | defer->msg = msg; | |
233 | defer->length = msg->len; | |
a306a0e4 | 234 | init_completion(&defer->complete); |
9d715fa0 VK |
235 | |
236 | for (i = 0; i <= retry; i++) { | |
237 | resp = bus->ops->xfer_msg_defer(bus, msg, defer); | |
238 | ret = find_response_code(resp); | |
239 | /* if cmd is ok or ignored return */ | |
240 | if (ret == 0 || ret == -ENODATA) | |
241 | return ret; | |
242 | } | |
243 | ||
244 | return ret; | |
245 | } | |
246 | ||
247 | static int sdw_reset_page(struct sdw_bus *bus, u16 dev_num) | |
248 | { | |
249 | int retry = bus->prop.err_threshold; | |
250 | enum sdw_command_response resp; | |
251 | int ret = 0, i; | |
252 | ||
253 | for (i = 0; i <= retry; i++) { | |
254 | resp = bus->ops->reset_page_addr(bus, dev_num); | |
255 | ret = find_response_code(resp); | |
256 | /* if cmd is ok or ignored return */ | |
257 | if (ret == 0 || ret == -ENODATA) | |
258 | return ret; | |
259 | } | |
260 | ||
261 | return ret; | |
262 | } | |
263 | ||
a350aff4 PLB |
264 | static int sdw_transfer_unlocked(struct sdw_bus *bus, struct sdw_msg *msg) |
265 | { | |
266 | int ret; | |
267 | ||
268 | ret = do_transfer(bus, msg); | |
269 | if (ret != 0 && ret != -ENODATA) | |
ec475187 BL |
270 | dev_err(bus->dev, "trf on Slave %d failed:%d %s addr %x count %d\n", |
271 | msg->dev_num, ret, | |
272 | (msg->flags & SDW_MSG_FLAG_WRITE) ? "write" : "read", | |
273 | msg->addr, msg->len); | |
a350aff4 PLB |
274 | |
275 | if (msg->page) | |
276 | sdw_reset_page(bus, msg->dev_num); | |
277 | ||
278 | return ret; | |
279 | } | |
280 | ||
9d715fa0 VK |
281 | /** |
282 | * sdw_transfer() - Synchronous transfer message to a SDW Slave device | |
283 | * @bus: SDW bus | |
284 | * @msg: SDW message to be xfered | |
285 | */ | |
286 | int sdw_transfer(struct sdw_bus *bus, struct sdw_msg *msg) | |
287 | { | |
288 | int ret; | |
289 | ||
290 | mutex_lock(&bus->msg_lock); | |
291 | ||
a350aff4 | 292 | ret = sdw_transfer_unlocked(bus, msg); |
9d715fa0 VK |
293 | |
294 | mutex_unlock(&bus->msg_lock); | |
295 | ||
296 | return ret; | |
297 | } | |
298 | ||
299 | /** | |
300 | * sdw_transfer_defer() - Asynchronously transfer message to a SDW Slave device | |
301 | * @bus: SDW bus | |
302 | * @msg: SDW message to be xfered | |
303 | * @defer: Defer block for signal completion | |
304 | * | |
305 | * Caller needs to hold the msg_lock lock while calling this | |
306 | */ | |
307 | int sdw_transfer_defer(struct sdw_bus *bus, struct sdw_msg *msg, | |
73ede046 | 308 | struct sdw_defer *defer) |
9d715fa0 VK |
309 | { |
310 | int ret; | |
311 | ||
312 | if (!bus->ops->xfer_msg_defer) | |
313 | return -ENOTSUPP; | |
314 | ||
315 | ret = do_transfer_defer(bus, msg, defer); | |
316 | if (ret != 0 && ret != -ENODATA) | |
317 | dev_err(bus->dev, "Defer trf on Slave %d failed:%d\n", | |
73ede046 | 318 | msg->dev_num, ret); |
9d715fa0 VK |
319 | |
320 | if (msg->page) | |
321 | sdw_reset_page(bus, msg->dev_num); | |
322 | ||
323 | return ret; | |
324 | } | |
325 | ||
9d715fa0 | 326 | int sdw_fill_msg(struct sdw_msg *msg, struct sdw_slave *slave, |
73ede046 | 327 | u32 addr, size_t count, u16 dev_num, u8 flags, u8 *buf) |
9d715fa0 VK |
328 | { |
329 | memset(msg, 0, sizeof(*msg)); | |
330 | msg->addr = addr; /* addr is 16 bit and truncated here */ | |
331 | msg->len = count; | |
332 | msg->dev_num = dev_num; | |
333 | msg->flags = flags; | |
334 | msg->buf = buf; | |
9d715fa0 | 335 | |
f779ad09 | 336 | if (addr < SDW_REG_NO_PAGE) /* no paging area */ |
9d715fa0 | 337 | return 0; |
f779ad09 GL |
338 | |
339 | if (addr >= SDW_REG_MAX) { /* illegal addr */ | |
9d715fa0 VK |
340 | pr_err("SDW: Invalid address %x passed\n", addr); |
341 | return -EINVAL; | |
342 | } | |
343 | ||
344 | if (addr < SDW_REG_OPTIONAL_PAGE) { /* 32k but no page */ | |
345 | if (slave && !slave->prop.paging_support) | |
346 | return 0; | |
21c2de29 | 347 | /* no need for else as that will fall-through to paging */ |
9d715fa0 VK |
348 | } |
349 | ||
350 | /* paging mandatory */ | |
351 | if (dev_num == SDW_ENUM_DEV_NUM || dev_num == SDW_BROADCAST_DEV_NUM) { | |
352 | pr_err("SDW: Invalid device for paging :%d\n", dev_num); | |
353 | return -EINVAL; | |
354 | } | |
355 | ||
356 | if (!slave) { | |
357 | pr_err("SDW: No slave for paging addr\n"); | |
358 | return -EINVAL; | |
f779ad09 GL |
359 | } |
360 | ||
361 | if (!slave->prop.paging_support) { | |
9d715fa0 | 362 | dev_err(&slave->dev, |
17ed5bef | 363 | "address %x needs paging but no support\n", addr); |
9d715fa0 VK |
364 | return -EINVAL; |
365 | } | |
366 | ||
d5826a4b VK |
367 | msg->addr_page1 = FIELD_GET(SDW_SCP_ADDRPAGE1_MASK, addr); |
368 | msg->addr_page2 = FIELD_GET(SDW_SCP_ADDRPAGE2_MASK, addr); | |
9d715fa0 VK |
369 | msg->addr |= BIT(15); |
370 | msg->page = true; | |
371 | ||
372 | return 0; | |
373 | } | |
374 | ||
60ee9be2 PLB |
375 | /* |
376 | * Read/Write IO functions. | |
377 | * no_pm versions can only be called by the bus, e.g. while enumerating or | |
378 | * handling suspend-resume sequences. | |
379 | * all clients need to use the pm versions | |
380 | */ | |
381 | ||
382 | static int | |
383 | sdw_nread_no_pm(struct sdw_slave *slave, u32 addr, size_t count, u8 *val) | |
384 | { | |
385 | struct sdw_msg msg; | |
386 | int ret; | |
387 | ||
388 | ret = sdw_fill_msg(&msg, slave, addr, count, | |
389 | slave->dev_num, SDW_MSG_FLAG_READ, val); | |
390 | if (ret < 0) | |
391 | return ret; | |
392 | ||
393 | return sdw_transfer(slave->bus, &msg); | |
394 | } | |
395 | ||
396 | static int | |
397 | sdw_nwrite_no_pm(struct sdw_slave *slave, u32 addr, size_t count, u8 *val) | |
398 | { | |
399 | struct sdw_msg msg; | |
400 | int ret; | |
401 | ||
402 | ret = sdw_fill_msg(&msg, slave, addr, count, | |
403 | slave->dev_num, SDW_MSG_FLAG_WRITE, val); | |
404 | if (ret < 0) | |
405 | return ret; | |
406 | ||
407 | return sdw_transfer(slave->bus, &msg); | |
408 | } | |
409 | ||
167790ab | 410 | int sdw_write_no_pm(struct sdw_slave *slave, u32 addr, u8 value) |
60ee9be2 PLB |
411 | { |
412 | return sdw_nwrite_no_pm(slave, addr, 1, &value); | |
413 | } | |
167790ab | 414 | EXPORT_SYMBOL(sdw_write_no_pm); |
60ee9be2 | 415 | |
0231453b RW |
416 | static int |
417 | sdw_bread_no_pm(struct sdw_bus *bus, u16 dev_num, u32 addr) | |
418 | { | |
419 | struct sdw_msg msg; | |
420 | u8 buf; | |
421 | int ret; | |
422 | ||
423 | ret = sdw_fill_msg(&msg, NULL, addr, 1, dev_num, | |
424 | SDW_MSG_FLAG_READ, &buf); | |
a5759f19 | 425 | if (ret < 0) |
0231453b RW |
426 | return ret; |
427 | ||
428 | ret = sdw_transfer(bus, &msg); | |
429 | if (ret < 0) | |
430 | return ret; | |
f779ad09 GL |
431 | |
432 | return buf; | |
0231453b RW |
433 | } |
434 | ||
435 | static int | |
436 | sdw_bwrite_no_pm(struct sdw_bus *bus, u16 dev_num, u32 addr, u8 value) | |
437 | { | |
438 | struct sdw_msg msg; | |
439 | int ret; | |
440 | ||
441 | ret = sdw_fill_msg(&msg, NULL, addr, 1, dev_num, | |
442 | SDW_MSG_FLAG_WRITE, &value); | |
a5759f19 | 443 | if (ret < 0) |
0231453b RW |
444 | return ret; |
445 | ||
446 | return sdw_transfer(bus, &msg); | |
447 | } | |
448 | ||
a350aff4 PLB |
449 | int sdw_bread_no_pm_unlocked(struct sdw_bus *bus, u16 dev_num, u32 addr) |
450 | { | |
451 | struct sdw_msg msg; | |
452 | u8 buf; | |
453 | int ret; | |
454 | ||
455 | ret = sdw_fill_msg(&msg, NULL, addr, 1, dev_num, | |
456 | SDW_MSG_FLAG_READ, &buf); | |
a5759f19 | 457 | if (ret < 0) |
a350aff4 PLB |
458 | return ret; |
459 | ||
460 | ret = sdw_transfer_unlocked(bus, &msg); | |
461 | if (ret < 0) | |
462 | return ret; | |
463 | ||
464 | return buf; | |
465 | } | |
466 | EXPORT_SYMBOL(sdw_bread_no_pm_unlocked); | |
467 | ||
468 | int sdw_bwrite_no_pm_unlocked(struct sdw_bus *bus, u16 dev_num, u32 addr, u8 value) | |
469 | { | |
470 | struct sdw_msg msg; | |
471 | int ret; | |
472 | ||
473 | ret = sdw_fill_msg(&msg, NULL, addr, 1, dev_num, | |
474 | SDW_MSG_FLAG_WRITE, &value); | |
a5759f19 | 475 | if (ret < 0) |
a350aff4 PLB |
476 | return ret; |
477 | ||
478 | return sdw_transfer_unlocked(bus, &msg); | |
479 | } | |
480 | EXPORT_SYMBOL(sdw_bwrite_no_pm_unlocked); | |
481 | ||
167790ab | 482 | int sdw_read_no_pm(struct sdw_slave *slave, u32 addr) |
0231453b RW |
483 | { |
484 | u8 buf; | |
485 | int ret; | |
486 | ||
487 | ret = sdw_nread_no_pm(slave, addr, 1, &buf); | |
488 | if (ret < 0) | |
489 | return ret; | |
490 | else | |
491 | return buf; | |
492 | } | |
167790ab | 493 | EXPORT_SYMBOL(sdw_read_no_pm); |
0231453b | 494 | |
b04c975e PLB |
495 | static int sdw_update_no_pm(struct sdw_slave *slave, u32 addr, u8 mask, u8 val) |
496 | { | |
497 | int tmp; | |
498 | ||
499 | tmp = sdw_read_no_pm(slave, addr); | |
500 | if (tmp < 0) | |
501 | return tmp; | |
502 | ||
503 | tmp = (tmp & ~mask) | val; | |
504 | return sdw_write_no_pm(slave, addr, tmp); | |
505 | } | |
506 | ||
9d715fa0 VK |
507 | /** |
508 | * sdw_nread() - Read "n" contiguous SDW Slave registers | |
509 | * @slave: SDW Slave | |
510 | * @addr: Register address | |
511 | * @count: length | |
512 | * @val: Buffer for values to be read | |
513 | */ | |
514 | int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val) | |
515 | { | |
9d715fa0 VK |
516 | int ret; |
517 | ||
973794e8 | 518 | ret = pm_runtime_get_sync(&slave->dev); |
60ee9be2 | 519 | if (ret < 0 && ret != -EACCES) { |
973794e8 | 520 | pm_runtime_put_noidle(&slave->dev); |
9d715fa0 | 521 | return ret; |
60ee9be2 PLB |
522 | } |
523 | ||
524 | ret = sdw_nread_no_pm(slave, addr, count, val); | |
9d715fa0 | 525 | |
973794e8 PLB |
526 | pm_runtime_mark_last_busy(&slave->dev); |
527 | pm_runtime_put(&slave->dev); | |
9d715fa0 VK |
528 | |
529 | return ret; | |
530 | } | |
531 | EXPORT_SYMBOL(sdw_nread); | |
532 | ||
533 | /** | |
534 | * sdw_nwrite() - Write "n" contiguous SDW Slave registers | |
535 | * @slave: SDW Slave | |
536 | * @addr: Register address | |
537 | * @count: length | |
538 | * @val: Buffer for values to be read | |
539 | */ | |
540 | int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, u8 *val) | |
541 | { | |
9d715fa0 VK |
542 | int ret; |
543 | ||
973794e8 | 544 | ret = pm_runtime_get_sync(&slave->dev); |
60ee9be2 | 545 | if (ret < 0 && ret != -EACCES) { |
973794e8 | 546 | pm_runtime_put_noidle(&slave->dev); |
9d715fa0 | 547 | return ret; |
60ee9be2 PLB |
548 | } |
549 | ||
550 | ret = sdw_nwrite_no_pm(slave, addr, count, val); | |
9d715fa0 | 551 | |
973794e8 PLB |
552 | pm_runtime_mark_last_busy(&slave->dev); |
553 | pm_runtime_put(&slave->dev); | |
9d715fa0 VK |
554 | |
555 | return ret; | |
556 | } | |
557 | EXPORT_SYMBOL(sdw_nwrite); | |
558 | ||
559 | /** | |
560 | * sdw_read() - Read a SDW Slave register | |
561 | * @slave: SDW Slave | |
562 | * @addr: Register address | |
563 | */ | |
564 | int sdw_read(struct sdw_slave *slave, u32 addr) | |
565 | { | |
566 | u8 buf; | |
567 | int ret; | |
568 | ||
569 | ret = sdw_nread(slave, addr, 1, &buf); | |
570 | if (ret < 0) | |
571 | return ret; | |
f779ad09 GL |
572 | |
573 | return buf; | |
9d715fa0 VK |
574 | } |
575 | EXPORT_SYMBOL(sdw_read); | |
576 | ||
577 | /** | |
578 | * sdw_write() - Write a SDW Slave register | |
579 | * @slave: SDW Slave | |
580 | * @addr: Register address | |
581 | * @value: Register value | |
582 | */ | |
583 | int sdw_write(struct sdw_slave *slave, u32 addr, u8 value) | |
584 | { | |
585 | return sdw_nwrite(slave, addr, 1, &value); | |
9d715fa0 VK |
586 | } |
587 | EXPORT_SYMBOL(sdw_write); | |
588 | ||
d52d7a1b SK |
589 | /* |
590 | * SDW alert handling | |
591 | */ | |
592 | ||
593 | /* called with bus_lock held */ | |
594 | static struct sdw_slave *sdw_get_slave(struct sdw_bus *bus, int i) | |
595 | { | |
1429cc26 | 596 | struct sdw_slave *slave; |
d52d7a1b SK |
597 | |
598 | list_for_each_entry(slave, &bus->slaves, node) { | |
599 | if (slave->dev_num == i) | |
600 | return slave; | |
601 | } | |
602 | ||
603 | return NULL; | |
604 | } | |
605 | ||
606 | static int sdw_compare_devid(struct sdw_slave *slave, struct sdw_slave_id id) | |
607 | { | |
2e8c4ad1 | 608 | if (slave->id.mfg_id != id.mfg_id || |
09830d5e | 609 | slave->id.part_id != id.part_id || |
2e8c4ad1 PLB |
610 | slave->id.class_id != id.class_id || |
611 | (slave->id.unique_id != SDW_IGNORED_UNIQUE_ID && | |
612 | slave->id.unique_id != id.unique_id)) | |
d52d7a1b SK |
613 | return -ENODEV; |
614 | ||
615 | return 0; | |
616 | } | |
617 | ||
618 | /* called with bus_lock held */ | |
619 | static int sdw_get_device_num(struct sdw_slave *slave) | |
620 | { | |
621 | int bit; | |
622 | ||
623 | bit = find_first_zero_bit(slave->bus->assigned, SDW_MAX_DEVICES); | |
624 | if (bit == SDW_MAX_DEVICES) { | |
625 | bit = -ENODEV; | |
626 | goto err; | |
627 | } | |
628 | ||
629 | /* | |
630 | * Do not update dev_num in Slave data structure here, | |
631 | * Update once program dev_num is successful | |
632 | */ | |
633 | set_bit(bit, slave->bus->assigned); | |
634 | ||
635 | err: | |
636 | return bit; | |
637 | } | |
638 | ||
639 | static int sdw_assign_device_num(struct sdw_slave *slave) | |
640 | { | |
6d7a1ff7 | 641 | struct sdw_bus *bus = slave->bus; |
d52d7a1b | 642 | int ret, dev_num; |
fd6a3ac8 | 643 | bool new_device = false; |
d52d7a1b SK |
644 | |
645 | /* check first if device number is assigned, if so reuse that */ | |
646 | if (!slave->dev_num) { | |
fd6a3ac8 PLB |
647 | if (!slave->dev_num_sticky) { |
648 | mutex_lock(&slave->bus->bus_lock); | |
649 | dev_num = sdw_get_device_num(slave); | |
650 | mutex_unlock(&slave->bus->bus_lock); | |
651 | if (dev_num < 0) { | |
6d7a1ff7 | 652 | dev_err(bus->dev, "Get dev_num failed: %d\n", |
fd6a3ac8 PLB |
653 | dev_num); |
654 | return dev_num; | |
655 | } | |
656 | slave->dev_num = dev_num; | |
657 | slave->dev_num_sticky = dev_num; | |
658 | new_device = true; | |
659 | } else { | |
660 | slave->dev_num = slave->dev_num_sticky; | |
d52d7a1b | 661 | } |
fd6a3ac8 PLB |
662 | } |
663 | ||
664 | if (!new_device) | |
6d7a1ff7 | 665 | dev_dbg(bus->dev, |
f48f4fd9 PLB |
666 | "Slave already registered, reusing dev_num:%d\n", |
667 | slave->dev_num); | |
d52d7a1b | 668 | |
fd6a3ac8 PLB |
669 | /* Clear the slave->dev_num to transfer message on device 0 */ |
670 | dev_num = slave->dev_num; | |
671 | slave->dev_num = 0; | |
d52d7a1b | 672 | |
d300de4f | 673 | ret = sdw_write_no_pm(slave, SDW_SCP_DEVNUMBER, dev_num); |
d52d7a1b | 674 | if (ret < 0) { |
6d7a1ff7 | 675 | dev_err(bus->dev, "Program device_num %d failed: %d\n", |
6e0ac6a6 | 676 | dev_num, ret); |
d52d7a1b SK |
677 | return ret; |
678 | } | |
679 | ||
680 | /* After xfer of msg, restore dev_num */ | |
fd6a3ac8 | 681 | slave->dev_num = slave->dev_num_sticky; |
d52d7a1b SK |
682 | |
683 | return 0; | |
684 | } | |
685 | ||
7c3cd189 | 686 | void sdw_extract_slave_id(struct sdw_bus *bus, |
73ede046 | 687 | u64 addr, struct sdw_slave_id *id) |
7c3cd189 | 688 | { |
17ed5bef | 689 | dev_dbg(bus->dev, "SDW Slave Addr: %llx\n", addr); |
7c3cd189 | 690 | |
2c6cff68 PLB |
691 | id->sdw_version = SDW_VERSION(addr); |
692 | id->unique_id = SDW_UNIQUE_ID(addr); | |
693 | id->mfg_id = SDW_MFG_ID(addr); | |
694 | id->part_id = SDW_PART_ID(addr); | |
695 | id->class_id = SDW_CLASS_ID(addr); | |
7c3cd189 VK |
696 | |
697 | dev_dbg(bus->dev, | |
c397efb7 PLB |
698 | "SDW Slave class_id 0x%02x, mfg_id 0x%04x, part_id 0x%04x, unique_id 0x%x, version 0x%x\n", |
699 | id->class_id, id->mfg_id, id->part_id, id->unique_id, id->sdw_version); | |
7c3cd189 | 700 | } |
d52d7a1b SK |
701 | |
702 | static int sdw_program_device_num(struct sdw_bus *bus) | |
703 | { | |
704 | u8 buf[SDW_NUM_DEV_ID_REGISTERS] = {0}; | |
705 | struct sdw_slave *slave, *_s; | |
706 | struct sdw_slave_id id; | |
707 | struct sdw_msg msg; | |
708 | bool found = false; | |
709 | int count = 0, ret; | |
710 | u64 addr; | |
711 | ||
712 | /* No Slave, so use raw xfer api */ | |
713 | ret = sdw_fill_msg(&msg, NULL, SDW_SCP_DEVID_0, | |
73ede046 | 714 | SDW_NUM_DEV_ID_REGISTERS, 0, SDW_MSG_FLAG_READ, buf); |
d52d7a1b SK |
715 | if (ret < 0) |
716 | return ret; | |
717 | ||
718 | do { | |
719 | ret = sdw_transfer(bus, &msg); | |
720 | if (ret == -ENODATA) { /* end of device id reads */ | |
6e0ac6a6 | 721 | dev_dbg(bus->dev, "No more devices to enumerate\n"); |
d52d7a1b SK |
722 | ret = 0; |
723 | break; | |
724 | } | |
725 | if (ret < 0) { | |
726 | dev_err(bus->dev, "DEVID read fail:%d\n", ret); | |
727 | break; | |
728 | } | |
729 | ||
730 | /* | |
731 | * Construct the addr and extract. Cast the higher shift | |
732 | * bits to avoid truncation due to size limit. | |
733 | */ | |
734 | addr = buf[5] | (buf[4] << 8) | (buf[3] << 16) | | |
0132af05 CIK |
735 | ((u64)buf[2] << 24) | ((u64)buf[1] << 32) | |
736 | ((u64)buf[0] << 40); | |
d52d7a1b SK |
737 | |
738 | sdw_extract_slave_id(bus, addr, &id); | |
739 | ||
740 | /* Now compare with entries */ | |
741 | list_for_each_entry_safe(slave, _s, &bus->slaves, node) { | |
742 | if (sdw_compare_devid(slave, id) == 0) { | |
743 | found = true; | |
744 | ||
745 | /* | |
746 | * Assign a new dev_num to this Slave and | |
747 | * not mark it present. It will be marked | |
748 | * present after it reports ATTACHED on new | |
749 | * dev_num | |
750 | */ | |
751 | ret = sdw_assign_device_num(slave); | |
a5759f19 | 752 | if (ret < 0) { |
6d7a1ff7 | 753 | dev_err(bus->dev, |
17ed5bef | 754 | "Assign dev_num failed:%d\n", |
d52d7a1b SK |
755 | ret); |
756 | return ret; | |
757 | } | |
758 | ||
759 | break; | |
760 | } | |
761 | } | |
762 | ||
d7b956b6 | 763 | if (!found) { |
d52d7a1b | 764 | /* TODO: Park this device in Group 13 */ |
fcb9d730 SK |
765 | |
766 | /* | |
767 | * add Slave device even if there is no platform | |
768 | * firmware description. There will be no driver probe | |
769 | * but the user/integration will be able to see the | |
770 | * device, enumeration status and device number in sysfs | |
771 | */ | |
772 | sdw_slave_add(bus, &id, NULL); | |
773 | ||
17ed5bef | 774 | dev_err(bus->dev, "Slave Entry not found\n"); |
d52d7a1b SK |
775 | } |
776 | ||
777 | count++; | |
778 | ||
779 | /* | |
780 | * Check till error out or retry (count) exhausts. | |
781 | * Device can drop off and rejoin during enumeration | |
782 | * so count till twice the bound. | |
783 | */ | |
784 | ||
785 | } while (ret == 0 && count < (SDW_MAX_DEVICES * 2)); | |
786 | ||
787 | return ret; | |
788 | } | |
789 | ||
790 | static void sdw_modify_slave_status(struct sdw_slave *slave, | |
73ede046 | 791 | enum sdw_slave_status status) |
d52d7a1b | 792 | { |
6d7a1ff7 PLB |
793 | struct sdw_bus *bus = slave->bus; |
794 | ||
795 | mutex_lock(&bus->bus_lock); | |
fb9469e5 | 796 | |
6d7a1ff7 | 797 | dev_vdbg(bus->dev, |
fb9469e5 PLB |
798 | "%s: changing status slave %d status %d new status %d\n", |
799 | __func__, slave->dev_num, slave->status, status); | |
800 | ||
801 | if (status == SDW_SLAVE_UNATTACHED) { | |
802 | dev_dbg(&slave->dev, | |
f1b69026 | 803 | "%s: initializing enumeration and init completion for Slave %d\n", |
fb9469e5 PLB |
804 | __func__, slave->dev_num); |
805 | ||
806 | init_completion(&slave->enumeration_complete); | |
a90def06 | 807 | init_completion(&slave->initialization_complete); |
fb9469e5 PLB |
808 | |
809 | } else if ((status == SDW_SLAVE_ATTACHED) && | |
810 | (slave->status == SDW_SLAVE_UNATTACHED)) { | |
811 | dev_dbg(&slave->dev, | |
f1b69026 | 812 | "%s: signaling enumeration completion for Slave %d\n", |
fb9469e5 PLB |
813 | __func__, slave->dev_num); |
814 | ||
815 | complete(&slave->enumeration_complete); | |
816 | } | |
d52d7a1b | 817 | slave->status = status; |
6d7a1ff7 | 818 | mutex_unlock(&bus->bus_lock); |
d52d7a1b SK |
819 | } |
820 | ||
0231453b RW |
821 | static enum sdw_clk_stop_mode sdw_get_clk_stop_mode(struct sdw_slave *slave) |
822 | { | |
823 | enum sdw_clk_stop_mode mode; | |
824 | ||
825 | /* | |
826 | * Query for clock stop mode if Slave implements | |
827 | * ops->get_clk_stop_mode, else read from property. | |
828 | */ | |
829 | if (slave->ops && slave->ops->get_clk_stop_mode) { | |
830 | mode = slave->ops->get_clk_stop_mode(slave); | |
831 | } else { | |
832 | if (slave->prop.clk_stop_mode1) | |
833 | mode = SDW_CLK_STOP_MODE1; | |
834 | else | |
835 | mode = SDW_CLK_STOP_MODE0; | |
836 | } | |
837 | ||
838 | return mode; | |
839 | } | |
840 | ||
841 | static int sdw_slave_clk_stop_callback(struct sdw_slave *slave, | |
842 | enum sdw_clk_stop_mode mode, | |
843 | enum sdw_clk_stop_type type) | |
844 | { | |
845 | int ret; | |
846 | ||
847 | if (slave->ops && slave->ops->clk_stop) { | |
848 | ret = slave->ops->clk_stop(slave, mode, type); | |
849 | if (ret < 0) { | |
850 | dev_err(&slave->dev, | |
851 | "Clk Stop type =%d failed: %d\n", type, ret); | |
852 | return ret; | |
853 | } | |
854 | } | |
855 | ||
856 | return 0; | |
857 | } | |
858 | ||
859 | static int sdw_slave_clk_stop_prepare(struct sdw_slave *slave, | |
860 | enum sdw_clk_stop_mode mode, | |
861 | bool prepare) | |
862 | { | |
863 | bool wake_en; | |
864 | u32 val = 0; | |
865 | int ret; | |
866 | ||
867 | wake_en = slave->prop.wake_capable; | |
868 | ||
869 | if (prepare) { | |
870 | val = SDW_SCP_SYSTEMCTRL_CLK_STP_PREP; | |
871 | ||
872 | if (mode == SDW_CLK_STOP_MODE1) | |
873 | val |= SDW_SCP_SYSTEMCTRL_CLK_STP_MODE1; | |
874 | ||
875 | if (wake_en) | |
876 | val |= SDW_SCP_SYSTEMCTRL_WAKE_UP_EN; | |
877 | } else { | |
665cf215 PLB |
878 | ret = sdw_read_no_pm(slave, SDW_SCP_SYSTEMCTRL); |
879 | if (ret < 0) { | |
880 | dev_err(&slave->dev, "SDW_SCP_SYSTEMCTRL read failed:%d\n", ret); | |
881 | return ret; | |
882 | } | |
883 | val = ret; | |
0231453b RW |
884 | val &= ~(SDW_SCP_SYSTEMCTRL_CLK_STP_PREP); |
885 | } | |
886 | ||
887 | ret = sdw_write_no_pm(slave, SDW_SCP_SYSTEMCTRL, val); | |
888 | ||
a5759f19 | 889 | if (ret < 0) |
0231453b RW |
890 | dev_err(&slave->dev, |
891 | "Clock Stop prepare failed for slave: %d", ret); | |
892 | ||
893 | return ret; | |
894 | } | |
895 | ||
896 | static int sdw_bus_wait_for_clk_prep_deprep(struct sdw_bus *bus, u16 dev_num) | |
897 | { | |
898 | int retry = bus->clk_stop_timeout; | |
899 | int val; | |
900 | ||
901 | do { | |
665cf215 PLB |
902 | val = sdw_bread_no_pm(bus, dev_num, SDW_SCP_STAT); |
903 | if (val < 0) { | |
904 | dev_err(bus->dev, "SDW_SCP_STAT bread failed:%d\n", val); | |
905 | return val; | |
906 | } | |
907 | val &= SDW_SCP_STAT_CLK_STP_NF; | |
0231453b | 908 | if (!val) { |
af7254b4 PLB |
909 | dev_dbg(bus->dev, "clock stop prep/de-prep done slave:%d", |
910 | dev_num); | |
0231453b RW |
911 | return 0; |
912 | } | |
913 | ||
914 | usleep_range(1000, 1500); | |
915 | retry--; | |
916 | } while (retry); | |
917 | ||
918 | dev_err(bus->dev, "clock stop prep/de-prep failed slave:%d", | |
919 | dev_num); | |
920 | ||
921 | return -ETIMEDOUT; | |
922 | } | |
923 | ||
924 | /** | |
925 | * sdw_bus_prep_clk_stop: prepare Slave(s) for clock stop | |
926 | * | |
927 | * @bus: SDW bus instance | |
928 | * | |
929 | * Query Slave for clock stop mode and prepare for that mode. | |
930 | */ | |
931 | int sdw_bus_prep_clk_stop(struct sdw_bus *bus) | |
932 | { | |
933 | enum sdw_clk_stop_mode slave_mode; | |
934 | bool simple_clk_stop = true; | |
935 | struct sdw_slave *slave; | |
936 | bool is_slave = false; | |
937 | int ret = 0; | |
938 | ||
939 | /* | |
940 | * In order to save on transition time, prepare | |
941 | * each Slave and then wait for all Slave(s) to be | |
942 | * prepared for clock stop. | |
943 | */ | |
944 | list_for_each_entry(slave, &bus->slaves, node) { | |
945 | if (!slave->dev_num) | |
946 | continue; | |
947 | ||
0231453b RW |
948 | if (slave->status != SDW_SLAVE_ATTACHED && |
949 | slave->status != SDW_SLAVE_ALERT) | |
950 | continue; | |
951 | ||
929cfee3 BL |
952 | /* Identify if Slave(s) are available on Bus */ |
953 | is_slave = true; | |
954 | ||
0231453b RW |
955 | slave_mode = sdw_get_clk_stop_mode(slave); |
956 | slave->curr_clk_stop_mode = slave_mode; | |
957 | ||
958 | ret = sdw_slave_clk_stop_callback(slave, slave_mode, | |
959 | SDW_CLK_PRE_PREPARE); | |
960 | if (ret < 0) { | |
961 | dev_err(&slave->dev, | |
962 | "pre-prepare failed:%d", ret); | |
963 | return ret; | |
964 | } | |
965 | ||
966 | ret = sdw_slave_clk_stop_prepare(slave, | |
967 | slave_mode, true); | |
968 | if (ret < 0) { | |
969 | dev_err(&slave->dev, | |
970 | "pre-prepare failed:%d", ret); | |
971 | return ret; | |
972 | } | |
973 | ||
974 | if (slave_mode == SDW_CLK_STOP_MODE1) | |
975 | simple_clk_stop = false; | |
976 | } | |
977 | ||
18de2f72 CS |
978 | /* Skip remaining clock stop preparation if no Slave is attached */ |
979 | if (!is_slave) | |
980 | return ret; | |
981 | ||
982 | if (!simple_clk_stop) { | |
0231453b RW |
983 | ret = sdw_bus_wait_for_clk_prep_deprep(bus, |
984 | SDW_BROADCAST_DEV_NUM); | |
985 | if (ret < 0) | |
986 | return ret; | |
987 | } | |
988 | ||
989 | /* Inform slaves that prep is done */ | |
990 | list_for_each_entry(slave, &bus->slaves, node) { | |
991 | if (!slave->dev_num) | |
992 | continue; | |
993 | ||
994 | if (slave->status != SDW_SLAVE_ATTACHED && | |
995 | slave->status != SDW_SLAVE_ALERT) | |
996 | continue; | |
997 | ||
998 | slave_mode = slave->curr_clk_stop_mode; | |
999 | ||
1000 | if (slave_mode == SDW_CLK_STOP_MODE1) { | |
1001 | ret = sdw_slave_clk_stop_callback(slave, | |
1002 | slave_mode, | |
1003 | SDW_CLK_POST_PREPARE); | |
1004 | ||
1005 | if (ret < 0) { | |
1006 | dev_err(&slave->dev, | |
1007 | "post-prepare failed:%d", ret); | |
1008 | } | |
1009 | } | |
1010 | } | |
1011 | ||
1012 | return ret; | |
1013 | } | |
1014 | EXPORT_SYMBOL(sdw_bus_prep_clk_stop); | |
1015 | ||
1016 | /** | |
1017 | * sdw_bus_clk_stop: stop bus clock | |
1018 | * | |
1019 | * @bus: SDW bus instance | |
1020 | * | |
1021 | * After preparing the Slaves for clock stop, stop the clock by broadcasting | |
1022 | * write to SCP_CTRL register. | |
1023 | */ | |
1024 | int sdw_bus_clk_stop(struct sdw_bus *bus) | |
1025 | { | |
1026 | int ret; | |
1027 | ||
1028 | /* | |
1029 | * broadcast clock stop now, attached Slaves will ACK this, | |
1030 | * unattached will ignore | |
1031 | */ | |
1032 | ret = sdw_bwrite_no_pm(bus, SDW_BROADCAST_DEV_NUM, | |
1033 | SDW_SCP_CTRL, SDW_SCP_CTRL_CLK_STP_NOW); | |
1034 | if (ret < 0) { | |
dde73538 PLB |
1035 | if (ret == -ENODATA) |
1036 | dev_dbg(bus->dev, | |
1037 | "ClockStopNow Broadcast msg ignored %d", ret); | |
1038 | else | |
1039 | dev_err(bus->dev, | |
1040 | "ClockStopNow Broadcast msg failed %d", ret); | |
0231453b RW |
1041 | return ret; |
1042 | } | |
1043 | ||
1044 | return 0; | |
1045 | } | |
1046 | EXPORT_SYMBOL(sdw_bus_clk_stop); | |
1047 | ||
1048 | /** | |
1049 | * sdw_bus_exit_clk_stop: Exit clock stop mode | |
1050 | * | |
1051 | * @bus: SDW bus instance | |
1052 | * | |
1053 | * This De-prepares the Slaves by exiting Clock Stop Mode 0. For the Slaves | |
1054 | * exiting Clock Stop Mode 1, they will be de-prepared after they enumerate | |
1055 | * back. | |
1056 | */ | |
1057 | int sdw_bus_exit_clk_stop(struct sdw_bus *bus) | |
1058 | { | |
1059 | enum sdw_clk_stop_mode mode; | |
1060 | bool simple_clk_stop = true; | |
1061 | struct sdw_slave *slave; | |
1062 | bool is_slave = false; | |
1063 | int ret; | |
1064 | ||
1065 | /* | |
1066 | * In order to save on transition time, de-prepare | |
1067 | * each Slave and then wait for all Slave(s) to be | |
1068 | * de-prepared after clock resume. | |
1069 | */ | |
1070 | list_for_each_entry(slave, &bus->slaves, node) { | |
1071 | if (!slave->dev_num) | |
1072 | continue; | |
1073 | ||
0231453b RW |
1074 | if (slave->status != SDW_SLAVE_ATTACHED && |
1075 | slave->status != SDW_SLAVE_ALERT) | |
1076 | continue; | |
1077 | ||
929cfee3 BL |
1078 | /* Identify if Slave(s) are available on Bus */ |
1079 | is_slave = true; | |
1080 | ||
0231453b RW |
1081 | mode = slave->curr_clk_stop_mode; |
1082 | ||
1083 | if (mode == SDW_CLK_STOP_MODE1) { | |
1084 | simple_clk_stop = false; | |
1085 | continue; | |
1086 | } | |
1087 | ||
1088 | ret = sdw_slave_clk_stop_callback(slave, mode, | |
1089 | SDW_CLK_PRE_DEPREPARE); | |
1090 | if (ret < 0) | |
1091 | dev_warn(&slave->dev, | |
1092 | "clk stop deprep failed:%d", ret); | |
1093 | ||
1094 | ret = sdw_slave_clk_stop_prepare(slave, mode, | |
1095 | false); | |
1096 | ||
1097 | if (ret < 0) | |
1098 | dev_warn(&slave->dev, | |
1099 | "clk stop deprep failed:%d", ret); | |
1100 | } | |
1101 | ||
18de2f72 | 1102 | /* Skip remaining clock stop de-preparation if no Slave is attached */ |
929cfee3 BL |
1103 | if (!is_slave) |
1104 | return 0; | |
1105 | ||
18de2f72 CS |
1106 | if (!simple_clk_stop) |
1107 | sdw_bus_wait_for_clk_prep_deprep(bus, SDW_BROADCAST_DEV_NUM); | |
1108 | ||
0231453b RW |
1109 | list_for_each_entry(slave, &bus->slaves, node) { |
1110 | if (!slave->dev_num) | |
1111 | continue; | |
1112 | ||
1113 | if (slave->status != SDW_SLAVE_ATTACHED && | |
1114 | slave->status != SDW_SLAVE_ALERT) | |
1115 | continue; | |
1116 | ||
1117 | mode = slave->curr_clk_stop_mode; | |
1118 | sdw_slave_clk_stop_callback(slave, mode, | |
1119 | SDW_CLK_POST_DEPREPARE); | |
1120 | } | |
1121 | ||
1122 | return 0; | |
1123 | } | |
1124 | EXPORT_SYMBOL(sdw_bus_exit_clk_stop); | |
1125 | ||
79df15b7 | 1126 | int sdw_configure_dpn_intr(struct sdw_slave *slave, |
73ede046 | 1127 | int port, bool enable, int mask) |
79df15b7 SK |
1128 | { |
1129 | u32 addr; | |
1130 | int ret; | |
1131 | u8 val = 0; | |
1132 | ||
dd87a72a PLB |
1133 | if (slave->bus->params.s_data_mode != SDW_PORT_DATA_MODE_NORMAL) { |
1134 | dev_dbg(&slave->dev, "TEST FAIL interrupt %s\n", | |
1135 | enable ? "on" : "off"); | |
1136 | mask |= SDW_DPN_INT_TEST_FAIL; | |
1137 | } | |
1138 | ||
79df15b7 SK |
1139 | addr = SDW_DPN_INTMASK(port); |
1140 | ||
1141 | /* Set/Clear port ready interrupt mask */ | |
1142 | if (enable) { | |
1143 | val |= mask; | |
1144 | val |= SDW_DPN_INT_PORT_READY; | |
1145 | } else { | |
1146 | val &= ~(mask); | |
1147 | val &= ~SDW_DPN_INT_PORT_READY; | |
1148 | } | |
1149 | ||
1150 | ret = sdw_update(slave, addr, (mask | SDW_DPN_INT_PORT_READY), val); | |
1151 | if (ret < 0) | |
6d7a1ff7 | 1152 | dev_err(&slave->dev, |
17ed5bef | 1153 | "SDW_DPN_INTMASK write failed:%d\n", val); |
79df15b7 SK |
1154 | |
1155 | return ret; | |
1156 | } | |
1157 | ||
29d158f9 PLB |
1158 | static int sdw_slave_set_frequency(struct sdw_slave *slave) |
1159 | { | |
1160 | u32 mclk_freq = slave->bus->prop.mclk_freq; | |
1161 | u32 curr_freq = slave->bus->params.curr_dr_freq >> 1; | |
1162 | unsigned int scale; | |
1163 | u8 scale_index; | |
1164 | u8 base; | |
1165 | int ret; | |
1166 | ||
1167 | /* | |
1168 | * frequency base and scale registers are required for SDCA | |
1169 | * devices. They may also be used for 1.2+/non-SDCA devices, | |
1170 | * but we will need a DisCo property to cover this case | |
1171 | */ | |
1172 | if (!slave->id.class_id) | |
1173 | return 0; | |
1174 | ||
1175 | if (!mclk_freq) { | |
1176 | dev_err(&slave->dev, | |
1177 | "no bus MCLK, cannot set SDW_SCP_BUS_CLOCK_BASE\n"); | |
1178 | return -EINVAL; | |
1179 | } | |
1180 | ||
1181 | /* | |
1182 | * map base frequency using Table 89 of SoundWire 1.2 spec. | |
1183 | * The order of the tests just follows the specification, this | |
1184 | * is not a selection between possible values or a search for | |
1185 | * the best value but just a mapping. Only one case per platform | |
1186 | * is relevant. | |
1187 | * Some BIOS have inconsistent values for mclk_freq but a | |
1188 | * correct root so we force the mclk_freq to avoid variations. | |
1189 | */ | |
1190 | if (!(19200000 % mclk_freq)) { | |
1191 | mclk_freq = 19200000; | |
1192 | base = SDW_SCP_BASE_CLOCK_19200000_HZ; | |
1193 | } else if (!(24000000 % mclk_freq)) { | |
1194 | mclk_freq = 24000000; | |
1195 | base = SDW_SCP_BASE_CLOCK_24000000_HZ; | |
1196 | } else if (!(24576000 % mclk_freq)) { | |
1197 | mclk_freq = 24576000; | |
1198 | base = SDW_SCP_BASE_CLOCK_24576000_HZ; | |
1199 | } else if (!(22579200 % mclk_freq)) { | |
1200 | mclk_freq = 22579200; | |
1201 | base = SDW_SCP_BASE_CLOCK_22579200_HZ; | |
1202 | } else if (!(32000000 % mclk_freq)) { | |
1203 | mclk_freq = 32000000; | |
1204 | base = SDW_SCP_BASE_CLOCK_32000000_HZ; | |
1205 | } else { | |
1206 | dev_err(&slave->dev, | |
1207 | "Unsupported clock base, mclk %d\n", | |
1208 | mclk_freq); | |
1209 | return -EINVAL; | |
1210 | } | |
1211 | ||
1212 | if (mclk_freq % curr_freq) { | |
1213 | dev_err(&slave->dev, | |
1214 | "mclk %d is not multiple of bus curr_freq %d\n", | |
1215 | mclk_freq, curr_freq); | |
1216 | return -EINVAL; | |
1217 | } | |
1218 | ||
1219 | scale = mclk_freq / curr_freq; | |
1220 | ||
1221 | /* | |
1222 | * map scale to Table 90 of SoundWire 1.2 spec - and check | |
1223 | * that the scale is a power of two and maximum 64 | |
1224 | */ | |
1225 | scale_index = ilog2(scale); | |
1226 | ||
1227 | if (BIT(scale_index) != scale || scale_index > 6) { | |
1228 | dev_err(&slave->dev, | |
1229 | "No match found for scale %d, bus mclk %d curr_freq %d\n", | |
1230 | scale, mclk_freq, curr_freq); | |
1231 | return -EINVAL; | |
1232 | } | |
1233 | scale_index++; | |
1234 | ||
299e9780 | 1235 | ret = sdw_write_no_pm(slave, SDW_SCP_BUS_CLOCK_BASE, base); |
29d158f9 PLB |
1236 | if (ret < 0) { |
1237 | dev_err(&slave->dev, | |
1238 | "SDW_SCP_BUS_CLOCK_BASE write failed:%d\n", ret); | |
1239 | return ret; | |
1240 | } | |
1241 | ||
1242 | /* initialize scale for both banks */ | |
299e9780 | 1243 | ret = sdw_write_no_pm(slave, SDW_SCP_BUSCLOCK_SCALE_B0, scale_index); |
29d158f9 PLB |
1244 | if (ret < 0) { |
1245 | dev_err(&slave->dev, | |
1246 | "SDW_SCP_BUSCLOCK_SCALE_B0 write failed:%d\n", ret); | |
1247 | return ret; | |
1248 | } | |
299e9780 | 1249 | ret = sdw_write_no_pm(slave, SDW_SCP_BUSCLOCK_SCALE_B1, scale_index); |
29d158f9 PLB |
1250 | if (ret < 0) |
1251 | dev_err(&slave->dev, | |
1252 | "SDW_SCP_BUSCLOCK_SCALE_B1 write failed:%d\n", ret); | |
1253 | ||
1254 | dev_dbg(&slave->dev, | |
1255 | "Configured bus base %d, scale %d, mclk %d, curr_freq %d\n", | |
1256 | base, scale_index, mclk_freq, curr_freq); | |
1257 | ||
1258 | return ret; | |
1259 | } | |
1260 | ||
d52d7a1b SK |
1261 | static int sdw_initialize_slave(struct sdw_slave *slave) |
1262 | { | |
1263 | struct sdw_slave_prop *prop = &slave->prop; | |
6b8caa6f | 1264 | int status; |
d52d7a1b SK |
1265 | int ret; |
1266 | u8 val; | |
1267 | ||
29d158f9 PLB |
1268 | ret = sdw_slave_set_frequency(slave); |
1269 | if (ret < 0) | |
1270 | return ret; | |
1271 | ||
6b8caa6f BL |
1272 | if (slave->bus->prop.quirks & SDW_MASTER_QUIRKS_CLEAR_INITIAL_CLASH) { |
1273 | /* Clear bus clash interrupt before enabling interrupt mask */ | |
1274 | status = sdw_read_no_pm(slave, SDW_SCP_INT1); | |
1275 | if (status < 0) { | |
1276 | dev_err(&slave->dev, | |
1277 | "SDW_SCP_INT1 (BUS_CLASH) read failed:%d\n", status); | |
1278 | return status; | |
1279 | } | |
1280 | if (status & SDW_SCP_INT1_BUS_CLASH) { | |
1281 | dev_warn(&slave->dev, "Bus clash detected before INT mask is enabled\n"); | |
1282 | ret = sdw_write_no_pm(slave, SDW_SCP_INT1, SDW_SCP_INT1_BUS_CLASH); | |
1283 | if (ret < 0) { | |
1284 | dev_err(&slave->dev, | |
1285 | "SDW_SCP_INT1 (BUS_CLASH) write failed:%d\n", ret); | |
1286 | return ret; | |
1287 | } | |
1288 | } | |
1289 | } | |
1290 | if ((slave->bus->prop.quirks & SDW_MASTER_QUIRKS_CLEAR_INITIAL_PARITY) && | |
1291 | !(slave->prop.quirks & SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY)) { | |
1292 | /* Clear parity interrupt before enabling interrupt mask */ | |
1293 | status = sdw_read_no_pm(slave, SDW_SCP_INT1); | |
1294 | if (status < 0) { | |
1295 | dev_err(&slave->dev, | |
1296 | "SDW_SCP_INT1 (PARITY) read failed:%d\n", status); | |
1297 | return status; | |
1298 | } | |
1299 | if (status & SDW_SCP_INT1_PARITY) { | |
1300 | dev_warn(&slave->dev, "PARITY error detected before INT mask is enabled\n"); | |
1301 | ret = sdw_write_no_pm(slave, SDW_SCP_INT1, SDW_SCP_INT1_PARITY); | |
1302 | if (ret < 0) { | |
1303 | dev_err(&slave->dev, | |
1304 | "SDW_SCP_INT1 (PARITY) write failed:%d\n", ret); | |
1305 | return ret; | |
1306 | } | |
1307 | } | |
1308 | } | |
1309 | ||
d52d7a1b | 1310 | /* |
2acd30b9 PLB |
1311 | * Set SCP_INT1_MASK register, typically bus clash and |
1312 | * implementation-defined interrupt mask. The Parity detection | |
1313 | * may not always be correct on startup so its use is | |
1314 | * device-dependent, it might e.g. only be enabled in | |
1315 | * steady-state after a couple of frames. | |
d52d7a1b | 1316 | */ |
2acd30b9 | 1317 | val = slave->prop.scp_int1_mask; |
d52d7a1b SK |
1318 | |
1319 | /* Enable SCP interrupts */ | |
b04c975e | 1320 | ret = sdw_update_no_pm(slave, SDW_SCP_INTMASK1, val, val); |
d52d7a1b | 1321 | if (ret < 0) { |
6d7a1ff7 | 1322 | dev_err(&slave->dev, |
17ed5bef | 1323 | "SDW_SCP_INTMASK1 write failed:%d\n", ret); |
d52d7a1b SK |
1324 | return ret; |
1325 | } | |
1326 | ||
1327 | /* No need to continue if DP0 is not present */ | |
1328 | if (!slave->prop.dp0_prop) | |
1329 | return 0; | |
1330 | ||
1331 | /* Enable DP0 interrupts */ | |
8acbbfec | 1332 | val = prop->dp0_prop->imp_def_interrupts; |
d52d7a1b SK |
1333 | val |= SDW_DP0_INT_PORT_READY | SDW_DP0_INT_BRA_FAILURE; |
1334 | ||
b04c975e | 1335 | ret = sdw_update_no_pm(slave, SDW_DP0_INTMASK, val, val); |
5de79ba8 | 1336 | if (ret < 0) |
6d7a1ff7 | 1337 | dev_err(&slave->dev, |
17ed5bef | 1338 | "SDW_DP0_INTMASK read failed:%d\n", ret); |
5de79ba8 | 1339 | return ret; |
d52d7a1b | 1340 | } |
b0a9c37b VK |
1341 | |
1342 | static int sdw_handle_dp0_interrupt(struct sdw_slave *slave, u8 *slave_status) | |
1343 | { | |
b35991de | 1344 | u8 clear, impl_int_mask; |
b0a9c37b VK |
1345 | int status, status2, ret, count = 0; |
1346 | ||
c30b63ef | 1347 | status = sdw_read_no_pm(slave, SDW_DP0_INT); |
b0a9c37b | 1348 | if (status < 0) { |
6d7a1ff7 | 1349 | dev_err(&slave->dev, |
17ed5bef | 1350 | "SDW_DP0_INT read failed:%d\n", status); |
b0a9c37b VK |
1351 | return status; |
1352 | } | |
1353 | ||
1354 | do { | |
b35991de PLB |
1355 | clear = status & ~SDW_DP0_INTERRUPTS; |
1356 | ||
b0a9c37b | 1357 | if (status & SDW_DP0_INT_TEST_FAIL) { |
17ed5bef | 1358 | dev_err(&slave->dev, "Test fail for port 0\n"); |
b0a9c37b VK |
1359 | clear |= SDW_DP0_INT_TEST_FAIL; |
1360 | } | |
1361 | ||
1362 | /* | |
1363 | * Assumption: PORT_READY interrupt will be received only for | |
1364 | * ports implementing Channel Prepare state machine (CP_SM) | |
1365 | */ | |
1366 | ||
1367 | if (status & SDW_DP0_INT_PORT_READY) { | |
1368 | complete(&slave->port_ready[0]); | |
1369 | clear |= SDW_DP0_INT_PORT_READY; | |
1370 | } | |
1371 | ||
1372 | if (status & SDW_DP0_INT_BRA_FAILURE) { | |
17ed5bef | 1373 | dev_err(&slave->dev, "BRA failed\n"); |
b0a9c37b VK |
1374 | clear |= SDW_DP0_INT_BRA_FAILURE; |
1375 | } | |
1376 | ||
1377 | impl_int_mask = SDW_DP0_INT_IMPDEF1 | | |
1378 | SDW_DP0_INT_IMPDEF2 | SDW_DP0_INT_IMPDEF3; | |
1379 | ||
1380 | if (status & impl_int_mask) { | |
1381 | clear |= impl_int_mask; | |
1382 | *slave_status = clear; | |
1383 | } | |
1384 | ||
b35991de | 1385 | /* clear the interrupts but don't touch reserved and SDCA_CASCADE fields */ |
c30b63ef | 1386 | ret = sdw_write_no_pm(slave, SDW_DP0_INT, clear); |
b0a9c37b | 1387 | if (ret < 0) { |
6d7a1ff7 | 1388 | dev_err(&slave->dev, |
17ed5bef | 1389 | "SDW_DP0_INT write failed:%d\n", ret); |
b0a9c37b VK |
1390 | return ret; |
1391 | } | |
1392 | ||
1393 | /* Read DP0 interrupt again */ | |
c30b63ef | 1394 | status2 = sdw_read_no_pm(slave, SDW_DP0_INT); |
b0a9c37b | 1395 | if (status2 < 0) { |
6d7a1ff7 | 1396 | dev_err(&slave->dev, |
17ed5bef | 1397 | "SDW_DP0_INT read failed:%d\n", status2); |
80cd8f01 | 1398 | return status2; |
b0a9c37b | 1399 | } |
6e06a855 | 1400 | /* filter to limit loop to interrupts identified in the first status read */ |
b0a9c37b VK |
1401 | status &= status2; |
1402 | ||
1403 | count++; | |
1404 | ||
1405 | /* we can get alerts while processing so keep retrying */ | |
b35991de | 1406 | } while ((status & SDW_DP0_INTERRUPTS) && (count < SDW_READ_INTR_CLEAR_RETRY)); |
b0a9c37b VK |
1407 | |
1408 | if (count == SDW_READ_INTR_CLEAR_RETRY) | |
6d7a1ff7 | 1409 | dev_warn(&slave->dev, "Reached MAX_RETRY on DP0 read\n"); |
b0a9c37b VK |
1410 | |
1411 | return ret; | |
1412 | } | |
1413 | ||
1414 | static int sdw_handle_port_interrupt(struct sdw_slave *slave, | |
73ede046 | 1415 | int port, u8 *slave_status) |
b0a9c37b | 1416 | { |
47b85209 | 1417 | u8 clear, impl_int_mask; |
b0a9c37b VK |
1418 | int status, status2, ret, count = 0; |
1419 | u32 addr; | |
1420 | ||
1421 | if (port == 0) | |
1422 | return sdw_handle_dp0_interrupt(slave, slave_status); | |
1423 | ||
1424 | addr = SDW_DPN_INT(port); | |
c30b63ef | 1425 | status = sdw_read_no_pm(slave, addr); |
b0a9c37b | 1426 | if (status < 0) { |
6d7a1ff7 | 1427 | dev_err(&slave->dev, |
17ed5bef | 1428 | "SDW_DPN_INT read failed:%d\n", status); |
b0a9c37b VK |
1429 | |
1430 | return status; | |
1431 | } | |
1432 | ||
1433 | do { | |
47b85209 PLB |
1434 | clear = status & ~SDW_DPN_INTERRUPTS; |
1435 | ||
b0a9c37b | 1436 | if (status & SDW_DPN_INT_TEST_FAIL) { |
17ed5bef | 1437 | dev_err(&slave->dev, "Test fail for port:%d\n", port); |
b0a9c37b VK |
1438 | clear |= SDW_DPN_INT_TEST_FAIL; |
1439 | } | |
1440 | ||
1441 | /* | |
1442 | * Assumption: PORT_READY interrupt will be received only | |
1443 | * for ports implementing CP_SM. | |
1444 | */ | |
1445 | if (status & SDW_DPN_INT_PORT_READY) { | |
1446 | complete(&slave->port_ready[port]); | |
1447 | clear |= SDW_DPN_INT_PORT_READY; | |
1448 | } | |
1449 | ||
1450 | impl_int_mask = SDW_DPN_INT_IMPDEF1 | | |
1451 | SDW_DPN_INT_IMPDEF2 | SDW_DPN_INT_IMPDEF3; | |
1452 | ||
b0a9c37b VK |
1453 | if (status & impl_int_mask) { |
1454 | clear |= impl_int_mask; | |
1455 | *slave_status = clear; | |
1456 | } | |
1457 | ||
47b85209 | 1458 | /* clear the interrupt but don't touch reserved fields */ |
c30b63ef | 1459 | ret = sdw_write_no_pm(slave, addr, clear); |
b0a9c37b | 1460 | if (ret < 0) { |
6d7a1ff7 | 1461 | dev_err(&slave->dev, |
17ed5bef | 1462 | "SDW_DPN_INT write failed:%d\n", ret); |
b0a9c37b VK |
1463 | return ret; |
1464 | } | |
1465 | ||
1466 | /* Read DPN interrupt again */ | |
c30b63ef | 1467 | status2 = sdw_read_no_pm(slave, addr); |
80cd8f01 | 1468 | if (status2 < 0) { |
6d7a1ff7 | 1469 | dev_err(&slave->dev, |
17ed5bef | 1470 | "SDW_DPN_INT read failed:%d\n", status2); |
80cd8f01 | 1471 | return status2; |
b0a9c37b | 1472 | } |
6e06a855 | 1473 | /* filter to limit loop to interrupts identified in the first status read */ |
b0a9c37b VK |
1474 | status &= status2; |
1475 | ||
1476 | count++; | |
1477 | ||
1478 | /* we can get alerts while processing so keep retrying */ | |
47b85209 | 1479 | } while ((status & SDW_DPN_INTERRUPTS) && (count < SDW_READ_INTR_CLEAR_RETRY)); |
b0a9c37b VK |
1480 | |
1481 | if (count == SDW_READ_INTR_CLEAR_RETRY) | |
6d7a1ff7 | 1482 | dev_warn(&slave->dev, "Reached MAX_RETRY on port read"); |
b0a9c37b VK |
1483 | |
1484 | return ret; | |
1485 | } | |
1486 | ||
1487 | static int sdw_handle_slave_alerts(struct sdw_slave *slave) | |
1488 | { | |
1489 | struct sdw_slave_intr_status slave_intr; | |
f1fac63a | 1490 | u8 clear = 0, bit, port_status[15] = {0}; |
b0a9c37b VK |
1491 | int port_num, stat, ret, count = 0; |
1492 | unsigned long port; | |
7ffaba04 | 1493 | bool slave_notify; |
b7cab9be | 1494 | u8 sdca_cascade = 0; |
b0a9c37b | 1495 | u8 buf, buf2[2], _buf, _buf2[2]; |
4724f12c PLB |
1496 | bool parity_check; |
1497 | bool parity_quirk; | |
b0a9c37b VK |
1498 | |
1499 | sdw_modify_slave_status(slave, SDW_SLAVE_ALERT); | |
1500 | ||
aa792935 RW |
1501 | ret = pm_runtime_get_sync(&slave->dev); |
1502 | if (ret < 0 && ret != -EACCES) { | |
1503 | dev_err(&slave->dev, "Failed to resume device: %d\n", ret); | |
973794e8 | 1504 | pm_runtime_put_noidle(&slave->dev); |
aa792935 RW |
1505 | return ret; |
1506 | } | |
1507 | ||
f8d0168e | 1508 | /* Read Intstat 1, Intstat 2 and Intstat 3 registers */ |
c30b63ef | 1509 | ret = sdw_read_no_pm(slave, SDW_SCP_INT1); |
b0a9c37b | 1510 | if (ret < 0) { |
6d7a1ff7 | 1511 | dev_err(&slave->dev, |
17ed5bef | 1512 | "SDW_SCP_INT1 read failed:%d\n", ret); |
aa792935 | 1513 | goto io_err; |
b0a9c37b | 1514 | } |
72b16d4a | 1515 | buf = ret; |
b0a9c37b | 1516 | |
c30b63ef | 1517 | ret = sdw_nread_no_pm(slave, SDW_SCP_INTSTAT2, 2, buf2); |
b0a9c37b | 1518 | if (ret < 0) { |
6d7a1ff7 | 1519 | dev_err(&slave->dev, |
17ed5bef | 1520 | "SDW_SCP_INT2/3 read failed:%d\n", ret); |
aa792935 | 1521 | goto io_err; |
b0a9c37b VK |
1522 | } |
1523 | ||
b7cab9be | 1524 | if (slave->prop.is_sdca) { |
c30b63ef | 1525 | ret = sdw_read_no_pm(slave, SDW_DP0_INT); |
b7cab9be | 1526 | if (ret < 0) { |
6d7a1ff7 | 1527 | dev_err(&slave->dev, |
b7cab9be PLB |
1528 | "SDW_DP0_INT read failed:%d\n", ret); |
1529 | goto io_err; | |
1530 | } | |
1531 | sdca_cascade = ret & SDW_DP0_SDCA_CASCADE; | |
1532 | } | |
1533 | ||
b0a9c37b | 1534 | do { |
7ffaba04 PLB |
1535 | slave_notify = false; |
1536 | ||
b0a9c37b VK |
1537 | /* |
1538 | * Check parity, bus clash and Slave (impl defined) | |
1539 | * interrupt | |
1540 | */ | |
1541 | if (buf & SDW_SCP_INT1_PARITY) { | |
4724f12c PLB |
1542 | parity_check = slave->prop.scp_int1_mask & SDW_SCP_INT1_PARITY; |
1543 | parity_quirk = !slave->first_interrupt_done && | |
1544 | (slave->prop.quirks & SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY); | |
1545 | ||
1546 | if (parity_check && !parity_quirk) | |
310f6dc6 | 1547 | dev_err(&slave->dev, "Parity error detected\n"); |
b0a9c37b VK |
1548 | clear |= SDW_SCP_INT1_PARITY; |
1549 | } | |
1550 | ||
1551 | if (buf & SDW_SCP_INT1_BUS_CLASH) { | |
310f6dc6 PLB |
1552 | if (slave->prop.scp_int1_mask & SDW_SCP_INT1_BUS_CLASH) |
1553 | dev_err(&slave->dev, "Bus clash detected\n"); | |
b0a9c37b VK |
1554 | clear |= SDW_SCP_INT1_BUS_CLASH; |
1555 | } | |
1556 | ||
1557 | /* | |
1558 | * When bus clash or parity errors are detected, such errors | |
1559 | * are unlikely to be recoverable errors. | |
1560 | * TODO: In such scenario, reset bus. Make this configurable | |
1561 | * via sysfs property with bus reset being the default. | |
1562 | */ | |
1563 | ||
1564 | if (buf & SDW_SCP_INT1_IMPL_DEF) { | |
310f6dc6 PLB |
1565 | if (slave->prop.scp_int1_mask & SDW_SCP_INT1_IMPL_DEF) { |
1566 | dev_dbg(&slave->dev, "Slave impl defined interrupt\n"); | |
1567 | slave_notify = true; | |
1568 | } | |
b0a9c37b | 1569 | clear |= SDW_SCP_INT1_IMPL_DEF; |
b0a9c37b VK |
1570 | } |
1571 | ||
b7cab9be PLB |
1572 | /* the SDCA interrupts are cleared in the codec driver .interrupt_callback() */ |
1573 | if (sdca_cascade) | |
1574 | slave_notify = true; | |
1575 | ||
b0a9c37b VK |
1576 | /* Check port 0 - 3 interrupts */ |
1577 | port = buf & SDW_SCP_INT1_PORT0_3; | |
1578 | ||
1579 | /* To get port number corresponding to bits, shift it */ | |
d5826a4b | 1580 | port = FIELD_GET(SDW_SCP_INT1_PORT0_3, port); |
b0a9c37b VK |
1581 | for_each_set_bit(bit, &port, 8) { |
1582 | sdw_handle_port_interrupt(slave, bit, | |
73ede046 | 1583 | &port_status[bit]); |
b0a9c37b VK |
1584 | } |
1585 | ||
1586 | /* Check if cascade 2 interrupt is present */ | |
1587 | if (buf & SDW_SCP_INT1_SCP2_CASCADE) { | |
1588 | port = buf2[0] & SDW_SCP_INTSTAT2_PORT4_10; | |
1589 | for_each_set_bit(bit, &port, 8) { | |
1590 | /* scp2 ports start from 4 */ | |
1591 | port_num = bit + 3; | |
1592 | sdw_handle_port_interrupt(slave, | |
1593 | port_num, | |
1594 | &port_status[port_num]); | |
1595 | } | |
1596 | } | |
1597 | ||
1598 | /* now check last cascade */ | |
1599 | if (buf2[0] & SDW_SCP_INTSTAT2_SCP3_CASCADE) { | |
1600 | port = buf2[1] & SDW_SCP_INTSTAT3_PORT11_14; | |
1601 | for_each_set_bit(bit, &port, 8) { | |
1602 | /* scp3 ports start from 11 */ | |
1603 | port_num = bit + 10; | |
1604 | sdw_handle_port_interrupt(slave, | |
1605 | port_num, | |
1606 | &port_status[port_num]); | |
1607 | } | |
1608 | } | |
1609 | ||
1610 | /* Update the Slave driver */ | |
09830d5e PLB |
1611 | if (slave_notify && slave->ops && |
1612 | slave->ops->interrupt_callback) { | |
b7cab9be | 1613 | slave_intr.sdca_cascade = sdca_cascade; |
b0a9c37b VK |
1614 | slave_intr.control_port = clear; |
1615 | memcpy(slave_intr.port, &port_status, | |
73ede046 | 1616 | sizeof(slave_intr.port)); |
b0a9c37b VK |
1617 | |
1618 | slave->ops->interrupt_callback(slave, &slave_intr); | |
1619 | } | |
1620 | ||
1621 | /* Ack interrupt */ | |
c30b63ef | 1622 | ret = sdw_write_no_pm(slave, SDW_SCP_INT1, clear); |
b0a9c37b | 1623 | if (ret < 0) { |
6d7a1ff7 | 1624 | dev_err(&slave->dev, |
17ed5bef | 1625 | "SDW_SCP_INT1 write failed:%d\n", ret); |
aa792935 | 1626 | goto io_err; |
b0a9c37b VK |
1627 | } |
1628 | ||
c2819e19 PLB |
1629 | /* at this point all initial interrupt sources were handled */ |
1630 | slave->first_interrupt_done = true; | |
1631 | ||
b0a9c37b VK |
1632 | /* |
1633 | * Read status again to ensure no new interrupts arrived | |
1634 | * while servicing interrupts. | |
1635 | */ | |
c30b63ef | 1636 | ret = sdw_read_no_pm(slave, SDW_SCP_INT1); |
b0a9c37b | 1637 | if (ret < 0) { |
6d7a1ff7 | 1638 | dev_err(&slave->dev, |
b500127e | 1639 | "SDW_SCP_INT1 recheck read failed:%d\n", ret); |
aa792935 | 1640 | goto io_err; |
b0a9c37b | 1641 | } |
72b16d4a | 1642 | _buf = ret; |
b0a9c37b | 1643 | |
c30b63ef | 1644 | ret = sdw_nread_no_pm(slave, SDW_SCP_INTSTAT2, 2, _buf2); |
b0a9c37b | 1645 | if (ret < 0) { |
6d7a1ff7 | 1646 | dev_err(&slave->dev, |
b500127e | 1647 | "SDW_SCP_INT2/3 recheck read failed:%d\n", ret); |
aa792935 | 1648 | goto io_err; |
b0a9c37b VK |
1649 | } |
1650 | ||
b7cab9be | 1651 | if (slave->prop.is_sdca) { |
c30b63ef | 1652 | ret = sdw_read_no_pm(slave, SDW_DP0_INT); |
b7cab9be | 1653 | if (ret < 0) { |
6d7a1ff7 | 1654 | dev_err(&slave->dev, |
b500127e | 1655 | "SDW_DP0_INT recheck read failed:%d\n", ret); |
b7cab9be PLB |
1656 | goto io_err; |
1657 | } | |
1658 | sdca_cascade = ret & SDW_DP0_SDCA_CASCADE; | |
1659 | } | |
1660 | ||
6e06a855 PLB |
1661 | /* |
1662 | * Make sure no interrupts are pending, but filter to limit loop | |
1663 | * to interrupts identified in the first status read | |
1664 | */ | |
b0a9c37b VK |
1665 | buf &= _buf; |
1666 | buf2[0] &= _buf2[0]; | |
1667 | buf2[1] &= _buf2[1]; | |
b7cab9be | 1668 | stat = buf || buf2[0] || buf2[1] || sdca_cascade; |
b0a9c37b VK |
1669 | |
1670 | /* | |
1671 | * Exit loop if Slave is continuously in ALERT state even | |
1672 | * after servicing the interrupt multiple times. | |
1673 | */ | |
1674 | count++; | |
1675 | ||
1676 | /* we can get alerts while processing so keep retrying */ | |
1677 | } while (stat != 0 && count < SDW_READ_INTR_CLEAR_RETRY); | |
1678 | ||
1679 | if (count == SDW_READ_INTR_CLEAR_RETRY) | |
6d7a1ff7 | 1680 | dev_warn(&slave->dev, "Reached MAX_RETRY on alert read\n"); |
b0a9c37b | 1681 | |
aa792935 RW |
1682 | io_err: |
1683 | pm_runtime_mark_last_busy(&slave->dev); | |
1684 | pm_runtime_put_autosuspend(&slave->dev); | |
1685 | ||
b0a9c37b VK |
1686 | return ret; |
1687 | } | |
1688 | ||
1689 | static int sdw_update_slave_status(struct sdw_slave *slave, | |
73ede046 | 1690 | enum sdw_slave_status status) |
b0a9c37b | 1691 | { |
2140b66b | 1692 | unsigned long time; |
b0a9c37b | 1693 | |
2140b66b PLB |
1694 | if (!slave->probed) { |
1695 | /* | |
1696 | * the slave status update is typically handled in an | |
1697 | * interrupt thread, which can race with the driver | |
1698 | * probe, e.g. when a module needs to be loaded. | |
1699 | * | |
1700 | * make sure the probe is complete before updating | |
1701 | * status. | |
1702 | */ | |
1703 | time = wait_for_completion_timeout(&slave->probe_complete, | |
1704 | msecs_to_jiffies(DEFAULT_PROBE_TIMEOUT)); | |
1705 | if (!time) { | |
1706 | dev_err(&slave->dev, "Probe not complete, timed out\n"); | |
1707 | return -ETIMEDOUT; | |
1708 | } | |
1709 | } | |
1710 | ||
1711 | if (!slave->ops || !slave->ops->update_status) | |
1712 | return 0; | |
1713 | ||
1714 | return slave->ops->update_status(slave, status); | |
b0a9c37b VK |
1715 | } |
1716 | ||
1717 | /** | |
1718 | * sdw_handle_slave_status() - Handle Slave status | |
1719 | * @bus: SDW bus instance | |
1720 | * @status: Status for all Slave(s) | |
1721 | */ | |
1722 | int sdw_handle_slave_status(struct sdw_bus *bus, | |
73ede046 | 1723 | enum sdw_slave_status status[]) |
b0a9c37b VK |
1724 | { |
1725 | enum sdw_slave_status prev_status; | |
1726 | struct sdw_slave *slave; | |
a90def06 | 1727 | bool attached_initializing; |
b0a9c37b VK |
1728 | int i, ret = 0; |
1729 | ||
61061901 PLB |
1730 | /* first check if any Slaves fell off the bus */ |
1731 | for (i = 1; i <= SDW_MAX_DEVICES; i++) { | |
1732 | mutex_lock(&bus->bus_lock); | |
1733 | if (test_bit(i, bus->assigned) == false) { | |
1734 | mutex_unlock(&bus->bus_lock); | |
1735 | continue; | |
1736 | } | |
1737 | mutex_unlock(&bus->bus_lock); | |
1738 | ||
1739 | slave = sdw_get_slave(bus, i); | |
1740 | if (!slave) | |
1741 | continue; | |
1742 | ||
1743 | if (status[i] == SDW_SLAVE_UNATTACHED && | |
1744 | slave->status != SDW_SLAVE_UNATTACHED) | |
1745 | sdw_modify_slave_status(slave, SDW_SLAVE_UNATTACHED); | |
1746 | } | |
1747 | ||
b0a9c37b | 1748 | if (status[0] == SDW_SLAVE_ATTACHED) { |
6e0ac6a6 | 1749 | dev_dbg(bus->dev, "Slave attached, programming device number\n"); |
b0a9c37b | 1750 | ret = sdw_program_device_num(bus); |
a5759f19 | 1751 | if (ret < 0) |
17ed5bef | 1752 | dev_err(bus->dev, "Slave attach failed: %d\n", ret); |
15ed3ea2 PLB |
1753 | /* |
1754 | * programming a device number will have side effects, | |
1755 | * so we deal with other devices at a later time | |
1756 | */ | |
1757 | return ret; | |
b0a9c37b VK |
1758 | } |
1759 | ||
1760 | /* Continue to check other slave statuses */ | |
1761 | for (i = 1; i <= SDW_MAX_DEVICES; i++) { | |
1762 | mutex_lock(&bus->bus_lock); | |
1763 | if (test_bit(i, bus->assigned) == false) { | |
1764 | mutex_unlock(&bus->bus_lock); | |
1765 | continue; | |
1766 | } | |
1767 | mutex_unlock(&bus->bus_lock); | |
1768 | ||
1769 | slave = sdw_get_slave(bus, i); | |
1770 | if (!slave) | |
1771 | continue; | |
1772 | ||
a90def06 PLB |
1773 | attached_initializing = false; |
1774 | ||
b0a9c37b VK |
1775 | switch (status[i]) { |
1776 | case SDW_SLAVE_UNATTACHED: | |
1777 | if (slave->status == SDW_SLAVE_UNATTACHED) | |
1778 | break; | |
1779 | ||
1780 | sdw_modify_slave_status(slave, SDW_SLAVE_UNATTACHED); | |
1781 | break; | |
1782 | ||
1783 | case SDW_SLAVE_ALERT: | |
1784 | ret = sdw_handle_slave_alerts(slave); | |
a5759f19 | 1785 | if (ret < 0) |
6d7a1ff7 | 1786 | dev_err(&slave->dev, |
17ed5bef | 1787 | "Slave %d alert handling failed: %d\n", |
b0a9c37b VK |
1788 | i, ret); |
1789 | break; | |
1790 | ||
1791 | case SDW_SLAVE_ATTACHED: | |
1792 | if (slave->status == SDW_SLAVE_ATTACHED) | |
1793 | break; | |
1794 | ||
1795 | prev_status = slave->status; | |
1796 | sdw_modify_slave_status(slave, SDW_SLAVE_ATTACHED); | |
1797 | ||
1798 | if (prev_status == SDW_SLAVE_ALERT) | |
1799 | break; | |
1800 | ||
a90def06 PLB |
1801 | attached_initializing = true; |
1802 | ||
b0a9c37b | 1803 | ret = sdw_initialize_slave(slave); |
a5759f19 | 1804 | if (ret < 0) |
6d7a1ff7 | 1805 | dev_err(&slave->dev, |
17ed5bef | 1806 | "Slave %d initialization failed: %d\n", |
b0a9c37b VK |
1807 | i, ret); |
1808 | ||
1809 | break; | |
1810 | ||
1811 | default: | |
6d7a1ff7 | 1812 | dev_err(&slave->dev, "Invalid slave %d status:%d\n", |
73ede046 | 1813 | i, status[i]); |
b0a9c37b VK |
1814 | break; |
1815 | } | |
1816 | ||
1817 | ret = sdw_update_slave_status(slave, status[i]); | |
a5759f19 | 1818 | if (ret < 0) |
6d7a1ff7 | 1819 | dev_err(&slave->dev, |
17ed5bef | 1820 | "Update Slave status failed:%d\n", ret); |
f1b69026 PLB |
1821 | if (attached_initializing) { |
1822 | dev_dbg(&slave->dev, | |
1823 | "%s: signaling initialization completion for Slave %d\n", | |
1824 | __func__, slave->dev_num); | |
1825 | ||
a90def06 | 1826 | complete(&slave->initialization_complete); |
f1b69026 | 1827 | } |
b0a9c37b VK |
1828 | } |
1829 | ||
1830 | return ret; | |
1831 | } | |
1832 | EXPORT_SYMBOL(sdw_handle_slave_status); | |
3ab2ca40 PLB |
1833 | |
1834 | void sdw_clear_slave_status(struct sdw_bus *bus, u32 request) | |
1835 | { | |
1836 | struct sdw_slave *slave; | |
1837 | int i; | |
1838 | ||
1839 | /* Check all non-zero devices */ | |
1840 | for (i = 1; i <= SDW_MAX_DEVICES; i++) { | |
1841 | mutex_lock(&bus->bus_lock); | |
1842 | if (test_bit(i, bus->assigned) == false) { | |
1843 | mutex_unlock(&bus->bus_lock); | |
1844 | continue; | |
1845 | } | |
1846 | mutex_unlock(&bus->bus_lock); | |
1847 | ||
1848 | slave = sdw_get_slave(bus, i); | |
1849 | if (!slave) | |
1850 | continue; | |
1851 | ||
c2819e19 | 1852 | if (slave->status != SDW_SLAVE_UNATTACHED) { |
3ab2ca40 | 1853 | sdw_modify_slave_status(slave, SDW_SLAVE_UNATTACHED); |
c2819e19 PLB |
1854 | slave->first_interrupt_done = false; |
1855 | } | |
3ab2ca40 PLB |
1856 | |
1857 | /* keep track of request, used in pm_runtime resume */ | |
1858 | slave->unattach_request = request; | |
1859 | } | |
1860 | } | |
1861 | EXPORT_SYMBOL(sdw_clear_slave_status); |