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Merge tag 'pinctrl-v6.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw...
[linux-block.git] / drivers / soundwire / amd_manager.c
CommitLineData
a4774642 1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
d8f48fbd
VM		 2/*
3 * SoundWire AMD Manager driver
4 *
ed5e8741 5 * Copyright 2023-24 Advanced Micro Devices, Inc.
d8f48fbd
VM		 6 */
7
8#include <linux/completion.h>
9#include <linux/device.h>
10#include <linux/io.h>
11#include <linux/jiffies.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/slab.h>
15#include <linux/soundwire/sdw.h>
16#include <linux/soundwire/sdw_registers.h>
81ff58ff 17#include <linux/pm_runtime.h>
d8f48fbd
VM		 18#include <linux/wait.h>
19#include <sound/pcm_params.h>
20#include <sound/soc.h>
21#include "bus.h"
ed5e8741 22#include "amd_init.h"
d8f48fbd
VM		 23#include "amd_manager.h"
24
25#define DRV_NAME "amd_sdw_manager"
26
27#define to_amd_sdw(b) container_of(b, struct amd_sdw_manager, bus)
28
d8f48fbd
VM		 29static int amd_init_sdw_manager(struct amd_sdw_manager *amd_manager)
30{
31 u32 val;
32 int ret;
33
34 writel(AMD_SDW_ENABLE, amd_manager->mmio + ACP_SW_EN);
35 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, val, ACP_DELAY_US,
36 AMD_SDW_TIMEOUT);
37 if (ret)
38 return ret;
39
40 /* SoundWire manager bus reset */
41 writel(AMD_SDW_BUS_RESET_REQ, amd_manager->mmio + ACP_SW_BUS_RESET_CTRL);
42 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_BUS_RESET_CTRL, val,
43 (val & AMD_SDW_BUS_RESET_DONE), ACP_DELAY_US, AMD_SDW_TIMEOUT);
44 if (ret)
45 return ret;
46
47 writel(AMD_SDW_BUS_RESET_CLEAR_REQ, amd_manager->mmio + ACP_SW_BUS_RESET_CTRL);
48 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_BUS_RESET_CTRL, val, !val,
49 ACP_DELAY_US, AMD_SDW_TIMEOUT);
50 if (ret) {
51 dev_err(amd_manager->dev, "Failed to reset SoundWire manager instance%d\n",
52 amd_manager->instance);
53 return ret;
54 }
55
56 writel(AMD_SDW_DISABLE, amd_manager->mmio + ACP_SW_EN);
57 return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, !val, ACP_DELAY_US,
58 AMD_SDW_TIMEOUT);
59}
60
61static int amd_enable_sdw_manager(struct amd_sdw_manager *amd_manager)
62{
63 u32 val;
64
65 writel(AMD_SDW_ENABLE, amd_manager->mmio + ACP_SW_EN);
66 return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, val, ACP_DELAY_US,
67 AMD_SDW_TIMEOUT);
68}
69
70static int amd_disable_sdw_manager(struct amd_sdw_manager *amd_manager)
71{
72 u32 val;
73
74 writel(AMD_SDW_DISABLE, amd_manager->mmio + ACP_SW_EN);
75 /*
76 * After invoking manager disable sequence, check whether
77 * manager has executed clock stop sequence. In this case,
78 * manager should ignore checking enable status register.
79 */
80 val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);
81 if (val)
82 return 0;
83 return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, !val, ACP_DELAY_US,
84 AMD_SDW_TIMEOUT);
85}
86
87static void amd_enable_sdw_interrupts(struct amd_sdw_manager *amd_manager)
88{
d8f48fbd
VM		 89 u32 val;
90
91 mutex_lock(amd_manager->acp_sdw_lock);
92 val = readl(amd_manager->acp_mmio + ACP_EXTERNAL_INTR_CNTL(amd_manager->instance));
c1263c75 93 val |= sdw_manager_reg_mask_array[amd_manager->instance];
d8f48fbd
VM		 94 writel(val, amd_manager->acp_mmio + ACP_EXTERNAL_INTR_CNTL(amd_manager->instance));
95 mutex_unlock(amd_manager->acp_sdw_lock);
96
97 writel(AMD_SDW_IRQ_MASK_0TO7, amd_manager->mmio +
98 ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7);
99 writel(AMD_SDW_IRQ_MASK_8TO11, amd_manager->mmio +
100 ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);
101 writel(AMD_SDW_IRQ_ERROR_MASK, amd_manager->mmio + ACP_SW_ERROR_INTR_MASK);
102}
103
104static void amd_disable_sdw_interrupts(struct amd_sdw_manager *amd_manager)
105{
d8f48fbd
VM		 106 u32 val;
107
108 mutex_lock(amd_manager->acp_sdw_lock);
109 val = readl(amd_manager->acp_mmio + ACP_EXTERNAL_INTR_CNTL(amd_manager->instance));
c1263c75 110 val &= ~sdw_manager_reg_mask_array[amd_manager->instance];
d8f48fbd
VM		 111 writel(val, amd_manager->acp_mmio + ACP_EXTERNAL_INTR_CNTL(amd_manager->instance));
112 mutex_unlock(amd_manager->acp_sdw_lock);
113
114 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7);
115 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);
116 writel(0x00, amd_manager->mmio + ACP_SW_ERROR_INTR_MASK);
117}
118
81ff58ff
VM		 119static int amd_deinit_sdw_manager(struct amd_sdw_manager *amd_manager)
120{
121 amd_disable_sdw_interrupts(amd_manager);
122 return amd_disable_sdw_manager(amd_manager);
123}
124
d8f48fbd
VM		 125static void amd_sdw_set_frameshape(struct amd_sdw_manager *amd_manager)
126{
127 u32 frame_size;
128
129 frame_size = (amd_manager->rows_index << 3) | amd_manager->cols_index;
130 writel(frame_size, amd_manager->mmio + ACP_SW_FRAMESIZE);
131}
132
63dc588e
VM		 133static void amd_sdw_wake_enable(struct amd_sdw_manager *amd_manager, bool enable)
134{
135 u32 wake_ctrl;
136
137 wake_ctrl = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);
138 if (enable)
139 wake_ctrl |= AMD_SDW_WAKE_INTR_MASK;
140 else
141 wake_ctrl &= ~AMD_SDW_WAKE_INTR_MASK;
142
143 writel(wake_ctrl, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);
144}
145
d8f48fbd
VM		 146static void amd_sdw_ctl_word_prep(u32 *lower_word, u32 *upper_word, struct sdw_msg *msg,
147 int cmd_offset)
148{
149 u32 upper_data;
150 u32 lower_data = 0;
151 u16 addr;
152 u8 upper_addr, lower_addr;
153 u8 data = 0;
154
155 addr = msg->addr + cmd_offset;
156 upper_addr = (addr & 0xFF00) >> 8;
157 lower_addr = addr & 0xFF;
158
159 if (msg->flags == SDW_MSG_FLAG_WRITE)
160 data = msg->buf[cmd_offset];
161
162 upper_data = FIELD_PREP(AMD_SDW_MCP_CMD_DEV_ADDR, msg->dev_num);
163 upper_data |= FIELD_PREP(AMD_SDW_MCP_CMD_COMMAND, msg->flags + 2);
164 upper_data |= FIELD_PREP(AMD_SDW_MCP_CMD_REG_ADDR_HIGH, upper_addr);
165 lower_data |= FIELD_PREP(AMD_SDW_MCP_CMD_REG_ADDR_LOW, lower_addr);
166 lower_data |= FIELD_PREP(AMD_SDW_MCP_CMD_REG_DATA, data);
167
168 *upper_word = upper_data;
169 *lower_word = lower_data;
170}
171
172static u64 amd_sdw_send_cmd_get_resp(struct amd_sdw_manager *amd_manager, u32 lower_data,
173 u32 upper_data)
174{
175 u64 resp;
176 u32 lower_resp, upper_resp;
177 u32 sts;
178 int ret;
179
180 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_IMM_CMD_STS, sts,
181 !(sts & AMD_SDW_IMM_CMD_BUSY), ACP_DELAY_US, AMD_SDW_TIMEOUT);
182 if (ret) {
183 dev_err(amd_manager->dev, "SDW%x previous cmd status clear failed\n",
184 amd_manager->instance);
185 return ret;
186 }
187
188 if (sts & AMD_SDW_IMM_RES_VALID) {
189 dev_err(amd_manager->dev, "SDW%x manager is in bad state\n", amd_manager->instance);
190 writel(0x00, amd_manager->mmio + ACP_SW_IMM_CMD_STS);
191 }
192 writel(upper_data, amd_manager->mmio + ACP_SW_IMM_CMD_UPPER_WORD);
193 writel(lower_data, amd_manager->mmio + ACP_SW_IMM_CMD_LOWER_QWORD);
194
195 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_IMM_CMD_STS, sts,
196 (sts & AMD_SDW_IMM_RES_VALID), ACP_DELAY_US, AMD_SDW_TIMEOUT);
197 if (ret) {
198 dev_err(amd_manager->dev, "SDW%x cmd response timeout occurred\n",
199 amd_manager->instance);
200 return ret;
201 }
202 upper_resp = readl(amd_manager->mmio + ACP_SW_IMM_RESP_UPPER_WORD);
203 lower_resp = readl(amd_manager->mmio + ACP_SW_IMM_RESP_LOWER_QWORD);
204
205 writel(AMD_SDW_IMM_RES_VALID, amd_manager->mmio + ACP_SW_IMM_CMD_STS);
206 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_IMM_CMD_STS, sts,
207 !(sts & AMD_SDW_IMM_RES_VALID), ACP_DELAY_US, AMD_SDW_TIMEOUT);
208 if (ret) {
209 dev_err(amd_manager->dev, "SDW%x cmd status retry failed\n",
210 amd_manager->instance);
211 return ret;
212 }
213 resp = upper_resp;
214 resp = (resp << 32) | lower_resp;
215 return resp;
216}
217
218static enum sdw_command_response
219amd_program_scp_addr(struct amd_sdw_manager *amd_manager, struct sdw_msg *msg)
220{
221 struct sdw_msg scp_msg = {0};
222 u64 response_buf[2] = {0};
223 u32 upper_data = 0, lower_data = 0;
224 int index;
225
226 scp_msg.dev_num = msg->dev_num;
227 scp_msg.addr = SDW_SCP_ADDRPAGE1;
228 scp_msg.buf = &msg->addr_page1;
229 scp_msg.flags = SDW_MSG_FLAG_WRITE;
230 amd_sdw_ctl_word_prep(&lower_data, &upper_data, &scp_msg, 0);
231 response_buf[0] = amd_sdw_send_cmd_get_resp(amd_manager, lower_data, upper_data);
232 scp_msg.addr = SDW_SCP_ADDRPAGE2;
233 scp_msg.buf = &msg->addr_page2;
234 amd_sdw_ctl_word_prep(&lower_data, &upper_data, &scp_msg, 0);
235 response_buf[1] = amd_sdw_send_cmd_get_resp(amd_manager, lower_data, upper_data);
236
237 for (index = 0; index < 2; index++) {
238 if (response_buf[index] == -ETIMEDOUT) {
239 dev_err_ratelimited(amd_manager->dev,
240 "SCP_addrpage command timeout for Slave %d\n",
241 msg->dev_num);
242 return SDW_CMD_TIMEOUT;
243 } else if (!(response_buf[index] & AMD_SDW_MCP_RESP_ACK)) {
244 if (response_buf[index] & AMD_SDW_MCP_RESP_NACK) {
245 dev_err_ratelimited(amd_manager->dev,
246 "SCP_addrpage NACKed for Slave %d\n",
247 msg->dev_num);
248 return SDW_CMD_FAIL;
249 }
250 dev_dbg_ratelimited(amd_manager->dev, "SCP_addrpage ignored for Slave %d\n",
251 msg->dev_num);
252 return SDW_CMD_IGNORED;
253 }
254 }
255 return SDW_CMD_OK;
256}
257
258static int amd_prep_msg(struct amd_sdw_manager *amd_manager, struct sdw_msg *msg)
259{
260 int ret;
261
262 if (msg->page) {
263 ret = amd_program_scp_addr(amd_manager, msg);
264 if (ret) {
265 msg->len = 0;
266 return ret;
267 }
268 }
269 switch (msg->flags) {
270 case SDW_MSG_FLAG_READ:
271 case SDW_MSG_FLAG_WRITE:
272 break;
273 default:
274 dev_err(amd_manager->dev, "Invalid msg cmd: %d\n", msg->flags);
275 return -EINVAL;
276 }
277 return 0;
278}
279
280static enum sdw_command_response amd_sdw_fill_msg_resp(struct amd_sdw_manager *amd_manager,
281 struct sdw_msg *msg, u64 response,
282 int offset)
283{
284 if (response & AMD_SDW_MCP_RESP_ACK) {
285 if (msg->flags == SDW_MSG_FLAG_READ)
286 msg->buf[offset] = FIELD_GET(AMD_SDW_MCP_RESP_RDATA, response);
287 } else {
288 if (response == -ETIMEDOUT) {
289 dev_err_ratelimited(amd_manager->dev, "command timeout for Slave %d\n",
290 msg->dev_num);
291 return SDW_CMD_TIMEOUT;
292 } else if (response & AMD_SDW_MCP_RESP_NACK) {
293 dev_err_ratelimited(amd_manager->dev,
294 "command response NACK received for Slave %d\n",
295 msg->dev_num);
296 return SDW_CMD_FAIL;
297 }
298 dev_err_ratelimited(amd_manager->dev, "command is ignored for Slave %d\n",
299 msg->dev_num);
300 return SDW_CMD_IGNORED;
301 }
302 return SDW_CMD_OK;
303}
304
305static unsigned int _amd_sdw_xfer_msg(struct amd_sdw_manager *amd_manager, struct sdw_msg *msg,
306 int cmd_offset)
307{
308 u64 response;
309 u32 upper_data = 0, lower_data = 0;
310
311 amd_sdw_ctl_word_prep(&lower_data, &upper_data, msg, cmd_offset);
312 response = amd_sdw_send_cmd_get_resp(amd_manager, lower_data, upper_data);
313 return amd_sdw_fill_msg_resp(amd_manager, msg, response, cmd_offset);
314}
315
316static enum sdw_command_response amd_sdw_xfer_msg(struct sdw_bus *bus, struct sdw_msg *msg)
317{
318 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus);
319 int ret, i;
320
321 ret = amd_prep_msg(amd_manager, msg);
322 if (ret)
323 return SDW_CMD_FAIL_OTHER;
324 for (i = 0; i < msg->len; i++) {
325 ret = _amd_sdw_xfer_msg(amd_manager, msg, i);
326 if (ret)
327 return ret;
328 }
329 return SDW_CMD_OK;
330}
331
65f93e40
VM		 332static void amd_sdw_fill_slave_status(struct amd_sdw_manager *amd_manager, u16 index, u32 status)
333{
334 switch (status) {
335 case SDW_SLAVE_ATTACHED:
336 case SDW_SLAVE_UNATTACHED:
337 case SDW_SLAVE_ALERT:
338 amd_manager->status[index] = status;
339 break;
340 default:
341 amd_manager->status[index] = SDW_SLAVE_RESERVED;
342 break;
343 }
344}
345
346static void amd_sdw_process_ping_status(u64 response, struct amd_sdw_manager *amd_manager)
347{
348 u64 slave_stat;
349 u32 val;
350 u16 dev_index;
351
352 /* slave status response */
353 slave_stat = FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_0_3, response);
354 slave_stat |= FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_4_11, response) << 8;
355 dev_dbg(amd_manager->dev, "slave_stat:0x%llx\n", slave_stat);
356 for (dev_index = 0; dev_index <= SDW_MAX_DEVICES; ++dev_index) {
357 val = (slave_stat >> (dev_index * 2)) & AMD_SDW_MCP_SLAVE_STATUS_MASK;
358 dev_dbg(amd_manager->dev, "val:0x%x\n", val);
359 amd_sdw_fill_slave_status(amd_manager, dev_index, val);
360 }
361}
362
363static void amd_sdw_read_and_process_ping_status(struct amd_sdw_manager *amd_manager)
364{
365 u64 response;
366
367 mutex_lock(&amd_manager->bus.msg_lock);
368 response = amd_sdw_send_cmd_get_resp(amd_manager, 0, 0);
369 mutex_unlock(&amd_manager->bus.msg_lock);
370 amd_sdw_process_ping_status(response, amd_manager);
371}
372
d8f48fbd
VM		 373static u32 amd_sdw_read_ping_status(struct sdw_bus *bus)
374{
375 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus);
376 u64 response;
377 u32 slave_stat;
378
379 response = amd_sdw_send_cmd_get_resp(amd_manager, 0, 0);
380 /* slave status from ping response */
381 slave_stat = FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_0_3, response);
382 slave_stat |= FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_4_11, response) << 8;
383 dev_dbg(amd_manager->dev, "slave_stat:0x%x\n", slave_stat);
384 return slave_stat;
385}
386
387static int amd_sdw_compute_params(struct sdw_bus *bus)
388{
389 struct sdw_transport_data t_data = {0};
390 struct sdw_master_runtime *m_rt;
391 struct sdw_port_runtime *p_rt;
392 struct sdw_bus_params *b_params = &bus->params;
393 int port_bo, hstart, hstop, sample_int;
394 unsigned int rate, bps;
395
396 port_bo = 0;
397 hstart = 1;
398 hstop = bus->params.col - 1;
399 t_data.hstop = hstop;
400 t_data.hstart = hstart;
401
402 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
403 rate = m_rt->stream->params.rate;
404 bps = m_rt->stream->params.bps;
405 sample_int = (bus->params.curr_dr_freq / rate);
406 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
407 port_bo = (p_rt->num * 64) + 1;
408 dev_dbg(bus->dev, "p_rt->num=%d hstart=%d hstop=%d port_bo=%d\n",
409 p_rt->num, hstart, hstop, port_bo);
410 sdw_fill_xport_params(&p_rt->transport_params, p_rt->num,
411 false, SDW_BLK_GRP_CNT_1, sample_int,
412 port_bo, port_bo >> 8, hstart, hstop,
413 SDW_BLK_PKG_PER_PORT, 0x0);
414
415 sdw_fill_port_params(&p_rt->port_params,
416 p_rt->num, bps,
417 SDW_PORT_FLOW_MODE_ISOCH,
418 b_params->m_data_mode);
419 t_data.hstart = hstart;
420 t_data.hstop = hstop;
421 t_data.block_offset = port_bo;
422 t_data.sub_block_offset = 0;
423 }
424 sdw_compute_slave_ports(m_rt, &t_data);
425 }
426 return 0;
427}
428
429static int amd_sdw_port_params(struct sdw_bus *bus, struct sdw_port_params *p_params,
430 unsigned int bank)
431{
432 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus);
433 u32 frame_fmt_reg, dpn_frame_fmt;
434
435 dev_dbg(amd_manager->dev, "p_params->num:0x%x\n", p_params->num);
436 switch (amd_manager->instance) {
437 case ACP_SDW0:
438 frame_fmt_reg = sdw0_manager_dp_reg[p_params->num].frame_fmt_reg;
439 break;
440 case ACP_SDW1:
441 frame_fmt_reg = sdw1_manager_dp_reg[p_params->num].frame_fmt_reg;
442 break;
443 default:
444 return -EINVAL;
445 }
446
447 dpn_frame_fmt = readl(amd_manager->mmio + frame_fmt_reg);
448 u32p_replace_bits(&dpn_frame_fmt, p_params->flow_mode, AMD_DPN_FRAME_FMT_PFM);
449 u32p_replace_bits(&dpn_frame_fmt, p_params->data_mode, AMD_DPN_FRAME_FMT_PDM);
450 u32p_replace_bits(&dpn_frame_fmt, p_params->bps - 1, AMD_DPN_FRAME_FMT_WORD_LEN);
451 writel(dpn_frame_fmt, amd_manager->mmio + frame_fmt_reg);
452 return 0;
453}
454
455static int amd_sdw_transport_params(struct sdw_bus *bus,
456 struct sdw_transport_params *params,
457 enum sdw_reg_bank bank)
458{
459 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus);
460 u32 dpn_frame_fmt;
461 u32 dpn_sampleinterval;
462 u32 dpn_hctrl;
463 u32 dpn_offsetctrl;
464 u32 dpn_lanectrl;
465 u32 frame_fmt_reg, sample_int_reg, hctrl_dp0_reg;
466 u32 offset_reg, lane_ctrl_ch_en_reg;
467
468 switch (amd_manager->instance) {
469 case ACP_SDW0:
470 frame_fmt_reg = sdw0_manager_dp_reg[params->port_num].frame_fmt_reg;
471 sample_int_reg = sdw0_manager_dp_reg[params->port_num].sample_int_reg;
472 hctrl_dp0_reg = sdw0_manager_dp_reg[params->port_num].hctrl_dp0_reg;
473 offset_reg = sdw0_manager_dp_reg[params->port_num].offset_reg;
474 lane_ctrl_ch_en_reg = sdw0_manager_dp_reg[params->port_num].lane_ctrl_ch_en_reg;
475 break;
476 case ACP_SDW1:
477 frame_fmt_reg = sdw1_manager_dp_reg[params->port_num].frame_fmt_reg;
478 sample_int_reg = sdw1_manager_dp_reg[params->port_num].sample_int_reg;
479 hctrl_dp0_reg = sdw1_manager_dp_reg[params->port_num].hctrl_dp0_reg;
480 offset_reg = sdw1_manager_dp_reg[params->port_num].offset_reg;
481 lane_ctrl_ch_en_reg = sdw1_manager_dp_reg[params->port_num].lane_ctrl_ch_en_reg;
482 break;
483 default:
484 return -EINVAL;
485 }
486 writel(AMD_SDW_SSP_COUNTER_VAL, amd_manager->mmio + ACP_SW_SSP_COUNTER);
487
488 dpn_frame_fmt = readl(amd_manager->mmio + frame_fmt_reg);
489 u32p_replace_bits(&dpn_frame_fmt, params->blk_pkg_mode, AMD_DPN_FRAME_FMT_BLK_PKG_MODE);
490 u32p_replace_bits(&dpn_frame_fmt, params->blk_grp_ctrl, AMD_DPN_FRAME_FMT_BLK_GRP_CTRL);
491 u32p_replace_bits(&dpn_frame_fmt, SDW_STREAM_PCM, AMD_DPN_FRAME_FMT_PCM_OR_PDM);
492 writel(dpn_frame_fmt, amd_manager->mmio + frame_fmt_reg);
493
494 dpn_sampleinterval = params->sample_interval - 1;
495 writel(dpn_sampleinterval, amd_manager->mmio + sample_int_reg);
496
497 dpn_hctrl = FIELD_PREP(AMD_DPN_HCTRL_HSTOP, params->hstop);
498 dpn_hctrl |= FIELD_PREP(AMD_DPN_HCTRL_HSTART, params->hstart);
499 writel(dpn_hctrl, amd_manager->mmio + hctrl_dp0_reg);
500
501 dpn_offsetctrl = FIELD_PREP(AMD_DPN_OFFSET_CTRL_1, params->offset1);
502 dpn_offsetctrl |= FIELD_PREP(AMD_DPN_OFFSET_CTRL_2, params->offset2);
503 writel(dpn_offsetctrl, amd_manager->mmio + offset_reg);
504
505 /*
506 * lane_ctrl_ch_en_reg will be used to program lane_ctrl and ch_mask
507 * parameters.
508 */
509 dpn_lanectrl = readl(amd_manager->mmio + lane_ctrl_ch_en_reg);
510 u32p_replace_bits(&dpn_lanectrl, params->lane_ctrl, AMD_DPN_CH_EN_LCTRL);
511 writel(dpn_lanectrl, amd_manager->mmio + lane_ctrl_ch_en_reg);
512 return 0;
513}
514
515static int amd_sdw_port_enable(struct sdw_bus *bus,
516 struct sdw_enable_ch *enable_ch,
517 unsigned int bank)
518{
519 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus);
520 u32 dpn_ch_enable;
521 u32 lane_ctrl_ch_en_reg;
522
523 switch (amd_manager->instance) {
524 case ACP_SDW0:
525 lane_ctrl_ch_en_reg = sdw0_manager_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg;
526 break;
527 case ACP_SDW1:
528 lane_ctrl_ch_en_reg = sdw1_manager_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg;
529 break;
530 default:
531 return -EINVAL;
532 }
533
534 /*
535 * lane_ctrl_ch_en_reg will be used to program lane_ctrl and ch_mask
536 * parameters.
537 */
538 dpn_ch_enable = readl(amd_manager->mmio + lane_ctrl_ch_en_reg);
539 u32p_replace_bits(&dpn_ch_enable, enable_ch->ch_mask, AMD_DPN_CH_EN_CHMASK);
540 if (enable_ch->enable)
541 writel(dpn_ch_enable, amd_manager->mmio + lane_ctrl_ch_en_reg);
542 else
543 writel(0, amd_manager->mmio + lane_ctrl_ch_en_reg);
544 return 0;
545}
546
547static int sdw_master_read_amd_prop(struct sdw_bus *bus)
548{
549 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus);
550 struct fwnode_handle *link;
551 struct sdw_master_prop *prop;
552 u32 quirk_mask = 0;
553 u32 wake_en_mask = 0;
554 u32 power_mode_mask = 0;
555 char name[32];
556
557 prop = &bus->prop;
558 /* Find manager handle */
559 snprintf(name, sizeof(name), "mipi-sdw-link-%d-subproperties", bus->link_id);
560 link = device_get_named_child_node(bus->dev, name);
561 if (!link) {
562 dev_err(bus->dev, "Manager node %s not found\n", name);
563 return -EIO;
564 }
565 fwnode_property_read_u32(link, "amd-sdw-enable", &quirk_mask);
566 if (!(quirk_mask & AMD_SDW_QUIRK_MASK_BUS_ENABLE))
567 prop->hw_disabled = true;
568 prop->quirks = SDW_MASTER_QUIRKS_CLEAR_INITIAL_CLASH |
569 SDW_MASTER_QUIRKS_CLEAR_INITIAL_PARITY;
570
571 fwnode_property_read_u32(link, "amd-sdw-wakeup-enable", &wake_en_mask);
572 amd_manager->wake_en_mask = wake_en_mask;
573 fwnode_property_read_u32(link, "amd-sdw-power-mode", &power_mode_mask);
574 amd_manager->power_mode_mask = power_mode_mask;
575 return 0;
576}
577
578static int amd_prop_read(struct sdw_bus *bus)
579{
580 sdw_master_read_prop(bus);
581 sdw_master_read_amd_prop(bus);
582 return 0;
583}
584
585static const struct sdw_master_port_ops amd_sdw_port_ops = {
586 .dpn_set_port_params = amd_sdw_port_params,
587 .dpn_set_port_transport_params = amd_sdw_transport_params,
588 .dpn_port_enable_ch = amd_sdw_port_enable,
589};
590
591static const struct sdw_master_ops amd_sdw_ops = {
592 .read_prop = amd_prop_read,
593 .xfer_msg = amd_sdw_xfer_msg,
594 .read_ping_status = amd_sdw_read_ping_status,
595};
596
2b13596f
VM		 597static int amd_sdw_hw_params(struct snd_pcm_substream *substream,
598 struct snd_pcm_hw_params *params,
599 struct snd_soc_dai *dai)
600{
601 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai);
602 struct sdw_amd_dai_runtime *dai_runtime;
603 struct sdw_stream_config sconfig;
604 struct sdw_port_config *pconfig;
605 int ch, dir;
606 int ret;
607
608 dai_runtime = amd_manager->dai_runtime_array[dai->id];
609 if (!dai_runtime)
610 return -EIO;
611
612 ch = params_channels(params);
613 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
614 dir = SDW_DATA_DIR_RX;
615 else
616 dir = SDW_DATA_DIR_TX;
617 dev_dbg(amd_manager->dev, "dir:%d dai->id:0x%x\n", dir, dai->id);
618
619 sconfig.direction = dir;
620 sconfig.ch_count = ch;
621 sconfig.frame_rate = params_rate(params);
622 sconfig.type = dai_runtime->stream_type;
623
624 sconfig.bps = snd_pcm_format_width(params_format(params));
625
626 /* Port configuration */
627 pconfig = kzalloc(sizeof(*pconfig), GFP_KERNEL);
628 if (!pconfig) {
629 ret = -ENOMEM;
630 goto error;
631 }
632
633 pconfig->num = dai->id;
634 pconfig->ch_mask = (1 << ch) - 1;
635 ret = sdw_stream_add_master(&amd_manager->bus, &sconfig,
636 pconfig, 1, dai_runtime->stream);
637 if (ret)
638 dev_err(amd_manager->dev, "add manager to stream failed:%d\n", ret);
639
640 kfree(pconfig);
641error:
642 return ret;
643}
644
645static int amd_sdw_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
646{
647 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai);
648 struct sdw_amd_dai_runtime *dai_runtime;
649 int ret;
650
651 dai_runtime = amd_manager->dai_runtime_array[dai->id];
652 if (!dai_runtime)
653 return -EIO;
654
655 ret = sdw_stream_remove_master(&amd_manager->bus, dai_runtime->stream);
656 if (ret < 0)
657 dev_err(dai->dev, "remove manager from stream %s failed: %d\n",
658 dai_runtime->stream->name, ret);
659 return ret;
660}
661
662static int amd_set_sdw_stream(struct snd_soc_dai *dai, void *stream, int direction)
663{
664 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai);
665 struct sdw_amd_dai_runtime *dai_runtime;
666
667 dai_runtime = amd_manager->dai_runtime_array[dai->id];
668 if (stream) {
669 /* first paranoia check */
670 if (dai_runtime) {
671 dev_err(dai->dev, "dai_runtime already allocated for dai %s\n", dai->name);
672 return -EINVAL;
673 }
674
675 /* allocate and set dai_runtime info */
676 dai_runtime = kzalloc(sizeof(*dai_runtime), GFP_KERNEL);
677 if (!dai_runtime)
678 return -ENOMEM;
679
680 dai_runtime->stream_type = SDW_STREAM_PCM;
681 dai_runtime->bus = &amd_manager->bus;
682 dai_runtime->stream = stream;
683 amd_manager->dai_runtime_array[dai->id] = dai_runtime;
684 } else {
685 /* second paranoia check */
686 if (!dai_runtime) {
687 dev_err(dai->dev, "dai_runtime not allocated for dai %s\n", dai->name);
688 return -EINVAL;
689 }
690
691 /* for NULL stream we release allocated dai_runtime */
692 kfree(dai_runtime);
693 amd_manager->dai_runtime_array[dai->id] = NULL;
694 }
695 return 0;
696}
697
698static int amd_pcm_set_sdw_stream(struct snd_soc_dai *dai, void *stream, int direction)
699{
700 return amd_set_sdw_stream(dai, stream, direction);
701}
702
703static void *amd_get_sdw_stream(struct snd_soc_dai *dai, int direction)
704{
705 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai);
706 struct sdw_amd_dai_runtime *dai_runtime;
707
708 dai_runtime = amd_manager->dai_runtime_array[dai->id];
709 if (!dai_runtime)
710 return ERR_PTR(-EINVAL);
711
712 return dai_runtime->stream;
713}
714
715static const struct snd_soc_dai_ops amd_sdw_dai_ops = {
716 .hw_params = amd_sdw_hw_params,
717 .hw_free = amd_sdw_hw_free,
718 .set_stream = amd_pcm_set_sdw_stream,
719 .get_stream = amd_get_sdw_stream,
720};
721
722static const struct snd_soc_component_driver amd_sdw_dai_component = {
723 .name = "soundwire",
724};
725
726static int amd_sdw_register_dais(struct amd_sdw_manager *amd_manager)
727{
728 struct sdw_amd_dai_runtime **dai_runtime_array;
729 struct snd_soc_dai_driver *dais;
730 struct snd_soc_pcm_stream *stream;
731 struct device *dev;
732 int i, num_dais;
733
734 dev = amd_manager->dev;
735 num_dais = amd_manager->num_dout_ports + amd_manager->num_din_ports;
736 dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL);
737 if (!dais)
738 return -ENOMEM;
739
740 dai_runtime_array = devm_kcalloc(dev, num_dais,
741 sizeof(struct sdw_amd_dai_runtime *),
742 GFP_KERNEL);
743 if (!dai_runtime_array)
744 return -ENOMEM;
745 amd_manager->dai_runtime_array = dai_runtime_array;
746 for (i = 0; i < num_dais; i++) {
747 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW%d Pin%d", amd_manager->instance,
748 i);
749 if (!dais[i].name)
750 return -ENOMEM;
751 if (i < amd_manager->num_dout_ports)
752 stream = &dais[i].playback;
753 else
754 stream = &dais[i].capture;
755
756 stream->channels_min = 2;
757 stream->channels_max = 2;
758 stream->rates = SNDRV_PCM_RATE_48000;
759 stream->formats = SNDRV_PCM_FMTBIT_S16_LE;
760
761 dais[i].ops = &amd_sdw_dai_ops;
762 dais[i].id = i;
763 }
764
765 return devm_snd_soc_register_component(dev, &amd_sdw_dai_component,
766 dais, num_dais);
767}
768
65f93e40
VM		 769static void amd_sdw_update_slave_status_work(struct work_struct *work)
770{
771 struct amd_sdw_manager *amd_manager =
772 container_of(work, struct amd_sdw_manager, amd_sdw_work);
773 int retry_count = 0;
774
775 if (amd_manager->status[0] == SDW_SLAVE_ATTACHED) {
776 writel(0, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7);
777 writel(0, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);
778 }
779
780update_status:
781 sdw_handle_slave_status(&amd_manager->bus, amd_manager->status);
782 /*
783 * During the peripheral enumeration sequence, the SoundWire manager interrupts
784 * are masked. Once the device number programming is done for all peripherals,
785 * interrupts will be unmasked. Read the peripheral device status from ping command
786 * and process the response. This sequence will ensure all peripheral devices enumerated
787 * and initialized properly.
788 */
789 if (amd_manager->status[0] == SDW_SLAVE_ATTACHED) {
790 if (retry_count++ < SDW_MAX_DEVICES) {
791 writel(AMD_SDW_IRQ_MASK_0TO7, amd_manager->mmio +
792 ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7);
793 writel(AMD_SDW_IRQ_MASK_8TO11, amd_manager->mmio +
794 ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);
795 amd_sdw_read_and_process_ping_status(amd_manager);
796 goto update_status;
797 } else {
798 dev_err_ratelimited(amd_manager->dev,
799 "Device0 detected after %d iterations\n",
800 retry_count);
801 }
802 }
803}
804
805static void amd_sdw_update_slave_status(u32 status_change_0to7, u32 status_change_8to11,
806 struct amd_sdw_manager *amd_manager)
807{
808 u64 slave_stat;
809 u32 val;
810 int dev_index;
811
812 if (status_change_0to7 == AMD_SDW_SLAVE_0_ATTACHED)
813 memset(amd_manager->status, 0, sizeof(amd_manager->status));
814 slave_stat = status_change_0to7;
815 slave_stat |= FIELD_GET(AMD_SDW_MCP_SLAVE_STATUS_8TO_11, status_change_8to11) << 32;
816 dev_dbg(amd_manager->dev, "status_change_0to7:0x%x status_change_8to11:0x%x\n",
817 status_change_0to7, status_change_8to11);
818 if (slave_stat) {
819 for (dev_index = 0; dev_index <= SDW_MAX_DEVICES; ++dev_index) {
820 if (slave_stat & AMD_SDW_MCP_SLAVE_STATUS_VALID_MASK(dev_index)) {
821 val = (slave_stat >> AMD_SDW_MCP_SLAVE_STAT_SHIFT_MASK(dev_index)) &
822 AMD_SDW_MCP_SLAVE_STATUS_MASK;
823 amd_sdw_fill_slave_status(amd_manager, dev_index, val);
824 }
825 }
826 }
827}
828
66c87883
VM		 829static void amd_sdw_process_wake_event(struct amd_sdw_manager *amd_manager)
830{
831 pm_request_resume(amd_manager->dev);
832 writel(0x00, amd_manager->acp_mmio + ACP_SW_WAKE_EN(amd_manager->instance));
833 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11);
834}
835
65f93e40
VM		 836static void amd_sdw_irq_thread(struct work_struct *work)
837{
838 struct amd_sdw_manager *amd_manager =
839 container_of(work, struct amd_sdw_manager, amd_sdw_irq_thread);
840 u32 status_change_8to11;
841 u32 status_change_0to7;
842
843 status_change_8to11 = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11);
844 status_change_0to7 = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_0TO7);
845 dev_dbg(amd_manager->dev, "[SDW%d] SDW INT: 0to7=0x%x, 8to11=0x%x\n",
846 amd_manager->instance, status_change_0to7, status_change_8to11);
66c87883
VM		 847 if (status_change_8to11 & AMD_SDW_WAKE_STAT_MASK)
848 return amd_sdw_process_wake_event(amd_manager);
849
65f93e40
VM		 850 if (status_change_8to11 & AMD_SDW_PREQ_INTR_STAT) {
851 amd_sdw_read_and_process_ping_status(amd_manager);
852 } else {
853 /* Check for the updated status on peripheral device */
854 amd_sdw_update_slave_status(status_change_0to7, status_change_8to11, amd_manager);
855 }
856 if (status_change_8to11 || status_change_0to7)
857 schedule_work(&amd_manager->amd_sdw_work);
858 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11);
859 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_0TO7);
860}
861
ed5e8741 862int amd_sdw_manager_start(struct amd_sdw_manager *amd_manager)
d8f48fbd 863{
d8f48fbd
VM		 864 struct sdw_master_prop *prop;
865 int ret;
866
867 prop = &amd_manager->bus.prop;
868 if (!prop->hw_disabled) {
d8f48fbd
VM		 869 ret = amd_init_sdw_manager(amd_manager);
870 if (ret)
ed5e8741 871 return ret;
d8f48fbd
VM		 872 amd_enable_sdw_interrupts(amd_manager);
873 ret = amd_enable_sdw_manager(amd_manager);
874 if (ret)
ed5e8741 875 return ret;
d8f48fbd
VM		 876 amd_sdw_set_frameshape(amd_manager);
877 }
81ff58ff
VM		 878 /* Enable runtime PM */
879 pm_runtime_set_autosuspend_delay(amd_manager->dev, AMD_SDW_MASTER_SUSPEND_DELAY_MS);
880 pm_runtime_use_autosuspend(amd_manager->dev);
881 pm_runtime_mark_last_busy(amd_manager->dev);
882 pm_runtime_set_active(amd_manager->dev);
883 pm_runtime_enable(amd_manager->dev);
ed5e8741 884 return 0;
d8f48fbd
VM		 885}
886
887static int amd_sdw_manager_probe(struct platform_device *pdev)
888{
889 const struct acp_sdw_pdata *pdata = pdev->dev.platform_data;
890 struct resource *res;
891 struct device *dev = &pdev->dev;
892 struct sdw_master_prop *prop;
893 struct sdw_bus_params *params;
894 struct amd_sdw_manager *amd_manager;
895 int ret;
896
897 amd_manager = devm_kzalloc(dev, sizeof(struct amd_sdw_manager), GFP_KERNEL);
898 if (!amd_manager)
899 return -ENOMEM;
900
901 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
902 if (!res)
903 return -ENOMEM;
904
905 amd_manager->acp_mmio = devm_ioremap(dev, res->start, resource_size(res));
7891d0a5 906 if (!amd_manager->acp_mmio) {
d8f48fbd 907 dev_err(dev, "mmio not found\n");
7891d0a5 908 return -ENOMEM;
d8f48fbd
VM		 909 }
910 amd_manager->instance = pdata->instance;
911 amd_manager->mmio = amd_manager->acp_mmio +
912 (amd_manager->instance * SDW_MANAGER_REG_OFFSET);
913 amd_manager->acp_sdw_lock = pdata->acp_sdw_lock;
914 amd_manager->cols_index = sdw_find_col_index(AMD_SDW_DEFAULT_COLUMNS);
915 amd_manager->rows_index = sdw_find_row_index(AMD_SDW_DEFAULT_ROWS);
916 amd_manager->dev = dev;
917 amd_manager->bus.ops = &amd_sdw_ops;
918 amd_manager->bus.port_ops = &amd_sdw_port_ops;
919 amd_manager->bus.compute_params = &amd_sdw_compute_params;
920 amd_manager->bus.clk_stop_timeout = 200;
921 amd_manager->bus.link_id = amd_manager->instance;
922
6543ac13
PLB		 923 /*
924 * Due to BIOS compatibility, the two links are exposed within
925 * the scope of a single controller. If this changes, the
926 * controller_id will have to be updated with drv_data
927 * information.
928 */
929 amd_manager->bus.controller_id = 0;
930
d8f48fbd
VM		 931 switch (amd_manager->instance) {
932 case ACP_SDW0:
933 amd_manager->num_dout_ports = AMD_SDW0_MAX_TX_PORTS;
934 amd_manager->num_din_ports = AMD_SDW0_MAX_RX_PORTS;
935 break;
936 case ACP_SDW1:
937 amd_manager->num_dout_ports = AMD_SDW1_MAX_TX_PORTS;
938 amd_manager->num_din_ports = AMD_SDW1_MAX_RX_PORTS;
939 break;
940 default:
941 return -EINVAL;
942 }
943
d8f48fbd 944 params = &amd_manager->bus.params;
becfce52 945
d8f48fbd
VM		 946 params->col = AMD_SDW_DEFAULT_COLUMNS;
947 params->row = AMD_SDW_DEFAULT_ROWS;
948 prop = &amd_manager->bus.prop;
949 prop->clk_freq = &amd_sdw_freq_tbl[0];
950 prop->mclk_freq = AMD_SDW_BUS_BASE_FREQ;
becfce52 951 prop->max_clk_freq = AMD_SDW_DEFAULT_CLK_FREQ;
d8f48fbd
VM		 952
953 ret = sdw_bus_master_add(&amd_manager->bus, dev, dev->fwnode);
954 if (ret) {
955 dev_err(dev, "Failed to register SoundWire manager(%d)\n", ret);
956 return ret;
957 }
2b13596f
VM		 958 ret = amd_sdw_register_dais(amd_manager);
959 if (ret) {
960 dev_err(dev, "CPU DAI registration failed\n");
961 sdw_bus_master_delete(&amd_manager->bus);
962 return ret;
963 }
d8f48fbd 964 dev_set_drvdata(dev, amd_manager);
65f93e40
VM		 965 INIT_WORK(&amd_manager->amd_sdw_irq_thread, amd_sdw_irq_thread);
966 INIT_WORK(&amd_manager->amd_sdw_work, amd_sdw_update_slave_status_work);
d8f48fbd
VM		 967 return 0;
968}
969
1ec33e22 970static void amd_sdw_manager_remove(struct platform_device *pdev)
d8f48fbd
VM		 971{
972 struct amd_sdw_manager *amd_manager = dev_get_drvdata(&pdev->dev);
1ec33e22 973 int ret;
d8f48fbd 974
81ff58ff 975 pm_runtime_disable(&pdev->dev);
d8f48fbd
VM		 976 amd_disable_sdw_interrupts(amd_manager);
977 sdw_bus_master_delete(&amd_manager->bus);
1ec33e22
UKK		 978 ret = amd_disable_sdw_manager(amd_manager);
979 if (ret)
980 dev_err(&pdev->dev, "Failed to disable device (%pe)\n", ERR_PTR(ret));
d8f48fbd
VM		 981}
982
81ff58ff
VM		 983static int amd_sdw_clock_stop(struct amd_sdw_manager *amd_manager)
984{
985 u32 val;
986 int ret;
987
988 ret = sdw_bus_prep_clk_stop(&amd_manager->bus);
989 if (ret < 0 && ret != -ENODATA) {
990 dev_err(amd_manager->dev, "prepare clock stop failed %d", ret);
991 return 0;
992 }
993 ret = sdw_bus_clk_stop(&amd_manager->bus);
994 if (ret < 0 && ret != -ENODATA) {
995 dev_err(amd_manager->dev, "bus clock stop failed %d", ret);
996 return 0;
997 }
998
999 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL, val,
1000 (val & AMD_SDW_CLK_STOP_DONE), ACP_DELAY_US, AMD_SDW_TIMEOUT);
1001 if (ret) {
1002 dev_err(amd_manager->dev, "SDW%x clock stop failed\n", amd_manager->instance);
1003 return 0;
1004 }
1005
1006 amd_manager->clk_stopped = true;
1007 if (amd_manager->wake_en_mask)
1008 writel(0x01, amd_manager->acp_mmio + ACP_SW_WAKE_EN(amd_manager->instance));
1009
1010 dev_dbg(amd_manager->dev, "SDW%x clock stop successful\n", amd_manager->instance);
1011 return 0;
1012}
1013
1014static int amd_sdw_clock_stop_exit(struct amd_sdw_manager *amd_manager)
1015{
1016 int ret;
1017 u32 val;
1018
1019 if (amd_manager->clk_stopped) {
1020 val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);
1021 val |= AMD_SDW_CLK_RESUME_REQ;
1022 writel(val, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);
1023 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL, val,
1024 (val & AMD_SDW_CLK_RESUME_DONE), ACP_DELAY_US,
1025 AMD_SDW_TIMEOUT);
1026 if (val & AMD_SDW_CLK_RESUME_DONE) {
1027 writel(0, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);
1028 ret = sdw_bus_exit_clk_stop(&amd_manager->bus);
1029 if (ret < 0)
1030 dev_err(amd_manager->dev, "bus failed to exit clock stop %d\n",
1031 ret);
1032 amd_manager->clk_stopped = false;
1033 }
1034 }
1035 if (amd_manager->clk_stopped) {
1036 dev_err(amd_manager->dev, "SDW%x clock stop exit failed\n", amd_manager->instance);
1037 return 0;
1038 }
1039 dev_dbg(amd_manager->dev, "SDW%x clock stop exit successful\n", amd_manager->instance);
1040 return 0;
1041}
1042
9cf1efc5
VM		 1043static int amd_resume_child_device(struct device *dev, void *data)
1044{
1045 struct sdw_slave *slave = dev_to_sdw_dev(dev);
1046 int ret;
1047
1048 if (!slave->probed) {
1049 dev_dbg(dev, "skipping device, no probed driver\n");
1050 return 0;
1051 }
1052 if (!slave->dev_num_sticky) {
1053 dev_dbg(dev, "skipping device, never detected on bus\n");
1054 return 0;
1055 }
1056 ret = pm_request_resume(dev);
1057 if (ret < 0) {
1058 dev_err(dev, "pm_request_resume failed: %d\n", ret);
1059 return ret;
1060 }
1061 return 0;
1062}
1063
1064static int __maybe_unused amd_pm_prepare(struct device *dev)
1065{
1066 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev);
1067 struct sdw_bus *bus = &amd_manager->bus;
1068 int ret;
1069
1070 if (bus->prop.hw_disabled) {
1071 dev_dbg(bus->dev, "SoundWire manager %d is disabled, ignoring\n",
1072 bus->link_id);
1073 return 0;
1074 }
1075 /*
1076 * When multiple peripheral devices connected over the same link, if SoundWire manager
1077 * device is not in runtime suspend state, observed that device alerts are missing
1078 * without pm_prepare on AMD platforms in clockstop mode0.
1079 */
1080 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) {
1081 ret = pm_request_resume(dev);
1082 if (ret < 0) {
1083 dev_err(bus->dev, "pm_request_resume failed: %d\n", ret);
1084 return 0;
1085 }
1086 }
1087 /* To force peripheral devices to system level suspend state, resume the devices
1088 * from runtime suspend state first. Without that unable to dispatch the alert
1089 * status to peripheral driver during system level resume as they are in runtime
1090 * suspend state.
1091 */
1092 ret = device_for_each_child(bus->dev, NULL, amd_resume_child_device);
1093 if (ret < 0)
1094 dev_err(dev, "amd_resume_child_device failed: %d\n", ret);
1095 return 0;
1096}
1097
1098static int __maybe_unused amd_suspend(struct device *dev)
1099{
1100 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev);
1101 struct sdw_bus *bus = &amd_manager->bus;
1102 int ret;
1103
1104 if (bus->prop.hw_disabled) {
1105 dev_dbg(bus->dev, "SoundWire manager %d is disabled, ignoring\n",
1106 bus->link_id);
1107 return 0;
1108 }
1109
1110 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) {
63dc588e 1111 amd_sdw_wake_enable(amd_manager, false);
9cf1efc5
VM		 1112 return amd_sdw_clock_stop(amd_manager);
1113 } else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) {
1114 /*
1115 * As per hardware programming sequence on AMD platforms,
1116 * clock stop should be invoked first before powering-off
1117 */
1118 ret = amd_sdw_clock_stop(amd_manager);
1119 if (ret)
1120 return ret;
1121 return amd_deinit_sdw_manager(amd_manager);
1122 }
1123 return 0;
1124}
1125
81ff58ff
VM		 1126static int __maybe_unused amd_suspend_runtime(struct device *dev)
1127{
1128 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev);
1129 struct sdw_bus *bus = &amd_manager->bus;
1130 int ret;
1131
1132 if (bus->prop.hw_disabled) {
1133 dev_dbg(bus->dev, "SoundWire manager %d is disabled,\n",
1134 bus->link_id);
1135 return 0;
1136 }
1137 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) {
63dc588e 1138 amd_sdw_wake_enable(amd_manager, true);
81ff58ff
VM		 1139 return amd_sdw_clock_stop(amd_manager);
1140 } else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) {
1141 ret = amd_sdw_clock_stop(amd_manager);
1142 if (ret)
1143 return ret;
1144 return amd_deinit_sdw_manager(amd_manager);
1145 }
1146 return 0;
1147}
1148
1149static int __maybe_unused amd_resume_runtime(struct device *dev)
1150{
1151 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev);
1152 struct sdw_bus *bus = &amd_manager->bus;
1153 int ret;
1154 u32 val;
1155
1156 if (bus->prop.hw_disabled) {
1157 dev_dbg(bus->dev, "SoundWire manager %d is disabled, ignoring\n",
1158 bus->link_id);
1159 return 0;
1160 }
1161
1162 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) {
1163 return amd_sdw_clock_stop_exit(amd_manager);
1164 } else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) {
1165 val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);
1166 if (val) {
1167 val |= AMD_SDW_CLK_RESUME_REQ;
1168 writel(val, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);
1169 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL, val,
1170 (val & AMD_SDW_CLK_RESUME_DONE), ACP_DELAY_US,
1171 AMD_SDW_TIMEOUT);
1172 if (val & AMD_SDW_CLK_RESUME_DONE) {
1173 writel(0, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);
1174 amd_manager->clk_stopped = false;
1175 }
1176 }
1177 sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET);
1178 amd_init_sdw_manager(amd_manager);
1179 amd_enable_sdw_interrupts(amd_manager);
1180 ret = amd_enable_sdw_manager(amd_manager);
1181 if (ret)
1182 return ret;
1183 amd_sdw_set_frameshape(amd_manager);
1184 }
1185 return 0;
1186}
1187
1188static const struct dev_pm_ops amd_pm = {
9cf1efc5
VM		 1189 .prepare = amd_pm_prepare,
1190 SET_SYSTEM_SLEEP_PM_OPS(amd_suspend, amd_resume_runtime)
81ff58ff
VM		 1191 SET_RUNTIME_PM_OPS(amd_suspend_runtime, amd_resume_runtime, NULL)
1192};
1193
d8f48fbd
VM		 1194static struct platform_driver amd_sdw_driver = {
1195 .probe = &amd_sdw_manager_probe,
1ec33e22 1196 .remove_new = &amd_sdw_manager_remove,
d8f48fbd
VM		 1197 .driver = {
1198 .name = "amd_sdw_manager",
81ff58ff 1199 .pm = &amd_pm,
d8f48fbd
VM		 1200 }
1201};
1202module_platform_driver(amd_sdw_driver);
1203
1204MODULE_AUTHOR("Vijendar.Mukunda@amd.com");
1205MODULE_DESCRIPTION("AMD SoundWire driver");
a4774642 1206MODULE_LICENSE("Dual BSD/GPL");
d8f48fbd 1207MODULE_ALIAS("platform:" DRV_NAME);
Linux 6.x block layer and io_uring tree(s)