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Merge tag 'soundwire-6.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul...
[linux-block.git] / drivers / soundwire / amd_manager.c
CommitLineData
a4774642 1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
d8f48fbd
VM		 2/*
3 * SoundWire AMD Manager driver
4 *
ed5e8741 5 * Copyright 2023-24 Advanced Micro Devices, Inc.
d8f48fbd
VM		 6 */
7
8#include <linux/completion.h>
9#include <linux/device.h>
10#include <linux/io.h>
11#include <linux/jiffies.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/slab.h>
15#include <linux/soundwire/sdw.h>
16#include <linux/soundwire/sdw_registers.h>
81ff58ff 17#include <linux/pm_runtime.h>
d8f48fbd
VM		 18#include <linux/wait.h>
19#include <sound/pcm_params.h>
20#include <sound/soc.h>
21#include "bus.h"
ed5e8741 22#include "amd_init.h"
d8f48fbd
VM		 23#include "amd_manager.h"
24
25#define DRV_NAME "amd_sdw_manager"
26
27#define to_amd_sdw(b) container_of(b, struct amd_sdw_manager, bus)
28
d8f48fbd
VM		 29static int amd_init_sdw_manager(struct amd_sdw_manager *amd_manager)
30{
31 u32 val;
32 int ret;
33
34 writel(AMD_SDW_ENABLE, amd_manager->mmio + ACP_SW_EN);
35 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, val, ACP_DELAY_US,
36 AMD_SDW_TIMEOUT);
37 if (ret)
38 return ret;
39
40 /* SoundWire manager bus reset */
41 writel(AMD_SDW_BUS_RESET_REQ, amd_manager->mmio + ACP_SW_BUS_RESET_CTRL);
42 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_BUS_RESET_CTRL, val,
43 (val & AMD_SDW_BUS_RESET_DONE), ACP_DELAY_US, AMD_SDW_TIMEOUT);
44 if (ret)
45 return ret;
46
47 writel(AMD_SDW_BUS_RESET_CLEAR_REQ, amd_manager->mmio + ACP_SW_BUS_RESET_CTRL);
48 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_BUS_RESET_CTRL, val, !val,
49 ACP_DELAY_US, AMD_SDW_TIMEOUT);
50 if (ret) {
51 dev_err(amd_manager->dev, "Failed to reset SoundWire manager instance%d\n",
52 amd_manager->instance);
53 return ret;
54 }
55
56 writel(AMD_SDW_DISABLE, amd_manager->mmio + ACP_SW_EN);
57 return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, !val, ACP_DELAY_US,
58 AMD_SDW_TIMEOUT);
59}
60
61static int amd_enable_sdw_manager(struct amd_sdw_manager *amd_manager)
62{
63 u32 val;
64
65 writel(AMD_SDW_ENABLE, amd_manager->mmio + ACP_SW_EN);
66 return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, val, ACP_DELAY_US,
67 AMD_SDW_TIMEOUT);
68}
69
70static int amd_disable_sdw_manager(struct amd_sdw_manager *amd_manager)
71{
72 u32 val;
73
74 writel(AMD_SDW_DISABLE, amd_manager->mmio + ACP_SW_EN);
75 /*
76 * After invoking manager disable sequence, check whether
77 * manager has executed clock stop sequence. In this case,
78 * manager should ignore checking enable status register.
79 */
80 val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);
81 if (val)
82 return 0;
83 return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, !val, ACP_DELAY_US,
84 AMD_SDW_TIMEOUT);
85}
86
87static void amd_enable_sdw_interrupts(struct amd_sdw_manager *amd_manager)
88{
d8f48fbd
VM		 89 u32 val;
90
91 mutex_lock(amd_manager->acp_sdw_lock);
e05af1a4
VM		 92 val = sdw_manager_reg_mask_array[amd_manager->instance];
93 amd_updatel(amd_manager->acp_mmio, ACP_EXTERNAL_INTR_CNTL(amd_manager->instance), val, val);
d8f48fbd
VM		 94 mutex_unlock(amd_manager->acp_sdw_lock);
95
96 writel(AMD_SDW_IRQ_MASK_0TO7, amd_manager->mmio +
97 ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7);
98 writel(AMD_SDW_IRQ_MASK_8TO11, amd_manager->mmio +
99 ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);
100 writel(AMD_SDW_IRQ_ERROR_MASK, amd_manager->mmio + ACP_SW_ERROR_INTR_MASK);
101}
102
103static void amd_disable_sdw_interrupts(struct amd_sdw_manager *amd_manager)
104{
e05af1a4 105 u32 irq_mask;
d8f48fbd
VM		 106
107 mutex_lock(amd_manager->acp_sdw_lock);
e05af1a4
VM		 108 irq_mask = sdw_manager_reg_mask_array[amd_manager->instance];
109 amd_updatel(amd_manager->acp_mmio, ACP_EXTERNAL_INTR_CNTL(amd_manager->instance),
110 irq_mask, 0);
d8f48fbd
VM		 111 mutex_unlock(amd_manager->acp_sdw_lock);
112
113 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7);
114 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);
115 writel(0x00, amd_manager->mmio + ACP_SW_ERROR_INTR_MASK);
116}
117
81ff58ff
VM		 118static int amd_deinit_sdw_manager(struct amd_sdw_manager *amd_manager)
119{
120 amd_disable_sdw_interrupts(amd_manager);
121 return amd_disable_sdw_manager(amd_manager);
122}
123
d8f48fbd
VM		 124static void amd_sdw_set_frameshape(struct amd_sdw_manager *amd_manager)
125{
126 u32 frame_size;
127
128 frame_size = (amd_manager->rows_index << 3) | amd_manager->cols_index;
129 writel(frame_size, amd_manager->mmio + ACP_SW_FRAMESIZE);
130}
131
63dc588e
VM		 132static void amd_sdw_wake_enable(struct amd_sdw_manager *amd_manager, bool enable)
133{
134 u32 wake_ctrl;
135
136 wake_ctrl = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);
137 if (enable)
138 wake_ctrl |= AMD_SDW_WAKE_INTR_MASK;
139 else
140 wake_ctrl &= ~AMD_SDW_WAKE_INTR_MASK;
141
142 writel(wake_ctrl, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);
143}
144
d8f48fbd
VM		 145static void amd_sdw_ctl_word_prep(u32 *lower_word, u32 *upper_word, struct sdw_msg *msg,
146 int cmd_offset)
147{
148 u32 upper_data;
149 u32 lower_data = 0;
150 u16 addr;
151 u8 upper_addr, lower_addr;
152 u8 data = 0;
153
154 addr = msg->addr + cmd_offset;
155 upper_addr = (addr & 0xFF00) >> 8;
156 lower_addr = addr & 0xFF;
157
158 if (msg->flags == SDW_MSG_FLAG_WRITE)
159 data = msg->buf[cmd_offset];
160
161 upper_data = FIELD_PREP(AMD_SDW_MCP_CMD_DEV_ADDR, msg->dev_num);
162 upper_data |= FIELD_PREP(AMD_SDW_MCP_CMD_COMMAND, msg->flags + 2);
163 upper_data |= FIELD_PREP(AMD_SDW_MCP_CMD_REG_ADDR_HIGH, upper_addr);
164 lower_data |= FIELD_PREP(AMD_SDW_MCP_CMD_REG_ADDR_LOW, lower_addr);
165 lower_data |= FIELD_PREP(AMD_SDW_MCP_CMD_REG_DATA, data);
166
167 *upper_word = upper_data;
168 *lower_word = lower_data;
169}
170
171static u64 amd_sdw_send_cmd_get_resp(struct amd_sdw_manager *amd_manager, u32 lower_data,
172 u32 upper_data)
173{
174 u64 resp;
175 u32 lower_resp, upper_resp;
176 u32 sts;
177 int ret;
178
179 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_IMM_CMD_STS, sts,
180 !(sts & AMD_SDW_IMM_CMD_BUSY), ACP_DELAY_US, AMD_SDW_TIMEOUT);
181 if (ret) {
182 dev_err(amd_manager->dev, "SDW%x previous cmd status clear failed\n",
183 amd_manager->instance);
184 return ret;
185 }
186
187 if (sts & AMD_SDW_IMM_RES_VALID) {
188 dev_err(amd_manager->dev, "SDW%x manager is in bad state\n", amd_manager->instance);
189 writel(0x00, amd_manager->mmio + ACP_SW_IMM_CMD_STS);
190 }
191 writel(upper_data, amd_manager->mmio + ACP_SW_IMM_CMD_UPPER_WORD);
192 writel(lower_data, amd_manager->mmio + ACP_SW_IMM_CMD_LOWER_QWORD);
193
194 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_IMM_CMD_STS, sts,
195 (sts & AMD_SDW_IMM_RES_VALID), ACP_DELAY_US, AMD_SDW_TIMEOUT);
196 if (ret) {
197 dev_err(amd_manager->dev, "SDW%x cmd response timeout occurred\n",
198 amd_manager->instance);
199 return ret;
200 }
201 upper_resp = readl(amd_manager->mmio + ACP_SW_IMM_RESP_UPPER_WORD);
202 lower_resp = readl(amd_manager->mmio + ACP_SW_IMM_RESP_LOWER_QWORD);
203
204 writel(AMD_SDW_IMM_RES_VALID, amd_manager->mmio + ACP_SW_IMM_CMD_STS);
205 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_IMM_CMD_STS, sts,
206 !(sts & AMD_SDW_IMM_RES_VALID), ACP_DELAY_US, AMD_SDW_TIMEOUT);
207 if (ret) {
208 dev_err(amd_manager->dev, "SDW%x cmd status retry failed\n",
209 amd_manager->instance);
210 return ret;
211 }
212 resp = upper_resp;
213 resp = (resp << 32) | lower_resp;
214 return resp;
215}
216
217static enum sdw_command_response
218amd_program_scp_addr(struct amd_sdw_manager *amd_manager, struct sdw_msg *msg)
219{
220 struct sdw_msg scp_msg = {0};
221 u64 response_buf[2] = {0};
222 u32 upper_data = 0, lower_data = 0;
223 int index;
224
225 scp_msg.dev_num = msg->dev_num;
226 scp_msg.addr = SDW_SCP_ADDRPAGE1;
227 scp_msg.buf = &msg->addr_page1;
228 scp_msg.flags = SDW_MSG_FLAG_WRITE;
229 amd_sdw_ctl_word_prep(&lower_data, &upper_data, &scp_msg, 0);
230 response_buf[0] = amd_sdw_send_cmd_get_resp(amd_manager, lower_data, upper_data);
231 scp_msg.addr = SDW_SCP_ADDRPAGE2;
232 scp_msg.buf = &msg->addr_page2;
233 amd_sdw_ctl_word_prep(&lower_data, &upper_data, &scp_msg, 0);
234 response_buf[1] = amd_sdw_send_cmd_get_resp(amd_manager, lower_data, upper_data);
235
236 for (index = 0; index < 2; index++) {
237 if (response_buf[index] == -ETIMEDOUT) {
238 dev_err_ratelimited(amd_manager->dev,
239 "SCP_addrpage command timeout for Slave %d\n",
240 msg->dev_num);
241 return SDW_CMD_TIMEOUT;
242 } else if (!(response_buf[index] & AMD_SDW_MCP_RESP_ACK)) {
243 if (response_buf[index] & AMD_SDW_MCP_RESP_NACK) {
244 dev_err_ratelimited(amd_manager->dev,
245 "SCP_addrpage NACKed for Slave %d\n",
246 msg->dev_num);
247 return SDW_CMD_FAIL;
248 }
249 dev_dbg_ratelimited(amd_manager->dev, "SCP_addrpage ignored for Slave %d\n",
250 msg->dev_num);
251 return SDW_CMD_IGNORED;
252 }
253 }
254 return SDW_CMD_OK;
255}
256
257static int amd_prep_msg(struct amd_sdw_manager *amd_manager, struct sdw_msg *msg)
258{
259 int ret;
260
261 if (msg->page) {
262 ret = amd_program_scp_addr(amd_manager, msg);
263 if (ret) {
264 msg->len = 0;
265 return ret;
266 }
267 }
268 switch (msg->flags) {
269 case SDW_MSG_FLAG_READ:
270 case SDW_MSG_FLAG_WRITE:
271 break;
272 default:
273 dev_err(amd_manager->dev, "Invalid msg cmd: %d\n", msg->flags);
274 return -EINVAL;
275 }
276 return 0;
277}
278
279static enum sdw_command_response amd_sdw_fill_msg_resp(struct amd_sdw_manager *amd_manager,
280 struct sdw_msg *msg, u64 response,
281 int offset)
282{
283 if (response & AMD_SDW_MCP_RESP_ACK) {
284 if (msg->flags == SDW_MSG_FLAG_READ)
285 msg->buf[offset] = FIELD_GET(AMD_SDW_MCP_RESP_RDATA, response);
286 } else {
287 if (response == -ETIMEDOUT) {
288 dev_err_ratelimited(amd_manager->dev, "command timeout for Slave %d\n",
289 msg->dev_num);
290 return SDW_CMD_TIMEOUT;
291 } else if (response & AMD_SDW_MCP_RESP_NACK) {
292 dev_err_ratelimited(amd_manager->dev,
293 "command response NACK received for Slave %d\n",
294 msg->dev_num);
295 return SDW_CMD_FAIL;
296 }
297 dev_err_ratelimited(amd_manager->dev, "command is ignored for Slave %d\n",
298 msg->dev_num);
299 return SDW_CMD_IGNORED;
300 }
301 return SDW_CMD_OK;
302}
303
304static unsigned int _amd_sdw_xfer_msg(struct amd_sdw_manager *amd_manager, struct sdw_msg *msg,
305 int cmd_offset)
306{
307 u64 response;
308 u32 upper_data = 0, lower_data = 0;
309
310 amd_sdw_ctl_word_prep(&lower_data, &upper_data, msg, cmd_offset);
311 response = amd_sdw_send_cmd_get_resp(amd_manager, lower_data, upper_data);
312 return amd_sdw_fill_msg_resp(amd_manager, msg, response, cmd_offset);
313}
314
315static enum sdw_command_response amd_sdw_xfer_msg(struct sdw_bus *bus, struct sdw_msg *msg)
316{
317 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus);
318 int ret, i;
319
320 ret = amd_prep_msg(amd_manager, msg);
321 if (ret)
322 return SDW_CMD_FAIL_OTHER;
323 for (i = 0; i < msg->len; i++) {
324 ret = _amd_sdw_xfer_msg(amd_manager, msg, i);
325 if (ret)
326 return ret;
327 }
328 return SDW_CMD_OK;
329}
330
65f93e40
VM		 331static void amd_sdw_fill_slave_status(struct amd_sdw_manager *amd_manager, u16 index, u32 status)
332{
333 switch (status) {
334 case SDW_SLAVE_ATTACHED:
335 case SDW_SLAVE_UNATTACHED:
336 case SDW_SLAVE_ALERT:
337 amd_manager->status[index] = status;
338 break;
339 default:
340 amd_manager->status[index] = SDW_SLAVE_RESERVED;
341 break;
342 }
343}
344
345static void amd_sdw_process_ping_status(u64 response, struct amd_sdw_manager *amd_manager)
346{
347 u64 slave_stat;
348 u32 val;
349 u16 dev_index;
350
351 /* slave status response */
352 slave_stat = FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_0_3, response);
353 slave_stat |= FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_4_11, response) << 8;
354 dev_dbg(amd_manager->dev, "slave_stat:0x%llx\n", slave_stat);
355 for (dev_index = 0; dev_index <= SDW_MAX_DEVICES; ++dev_index) {
356 val = (slave_stat >> (dev_index * 2)) & AMD_SDW_MCP_SLAVE_STATUS_MASK;
357 dev_dbg(amd_manager->dev, "val:0x%x\n", val);
358 amd_sdw_fill_slave_status(amd_manager, dev_index, val);
359 }
360}
361
362static void amd_sdw_read_and_process_ping_status(struct amd_sdw_manager *amd_manager)
363{
364 u64 response;
365
366 mutex_lock(&amd_manager->bus.msg_lock);
367 response = amd_sdw_send_cmd_get_resp(amd_manager, 0, 0);
368 mutex_unlock(&amd_manager->bus.msg_lock);
369 amd_sdw_process_ping_status(response, amd_manager);
370}
371
d8f48fbd
VM		 372static u32 amd_sdw_read_ping_status(struct sdw_bus *bus)
373{
374 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus);
375 u64 response;
376 u32 slave_stat;
377
378 response = amd_sdw_send_cmd_get_resp(amd_manager, 0, 0);
379 /* slave status from ping response */
380 slave_stat = FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_0_3, response);
381 slave_stat |= FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_4_11, response) << 8;
382 dev_dbg(amd_manager->dev, "slave_stat:0x%x\n", slave_stat);
383 return slave_stat;
384}
385
386static int amd_sdw_compute_params(struct sdw_bus *bus)
387{
388 struct sdw_transport_data t_data = {0};
389 struct sdw_master_runtime *m_rt;
390 struct sdw_port_runtime *p_rt;
391 struct sdw_bus_params *b_params = &bus->params;
392 int port_bo, hstart, hstop, sample_int;
393 unsigned int rate, bps;
394
395 port_bo = 0;
396 hstart = 1;
397 hstop = bus->params.col - 1;
398 t_data.hstop = hstop;
399 t_data.hstart = hstart;
400
401 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
402 rate = m_rt->stream->params.rate;
403 bps = m_rt->stream->params.bps;
404 sample_int = (bus->params.curr_dr_freq / rate);
405 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
406 port_bo = (p_rt->num * 64) + 1;
407 dev_dbg(bus->dev, "p_rt->num=%d hstart=%d hstop=%d port_bo=%d\n",
408 p_rt->num, hstart, hstop, port_bo);
409 sdw_fill_xport_params(&p_rt->transport_params, p_rt->num,
410 false, SDW_BLK_GRP_CNT_1, sample_int,
411 port_bo, port_bo >> 8, hstart, hstop,
412 SDW_BLK_PKG_PER_PORT, 0x0);
413
414 sdw_fill_port_params(&p_rt->port_params,
415 p_rt->num, bps,
416 SDW_PORT_FLOW_MODE_ISOCH,
417 b_params->m_data_mode);
418 t_data.hstart = hstart;
419 t_data.hstop = hstop;
420 t_data.block_offset = port_bo;
421 t_data.sub_block_offset = 0;
422 }
423 sdw_compute_slave_ports(m_rt, &t_data);
424 }
425 return 0;
426}
427
428static int amd_sdw_port_params(struct sdw_bus *bus, struct sdw_port_params *p_params,
429 unsigned int bank)
430{
431 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus);
432 u32 frame_fmt_reg, dpn_frame_fmt;
433
434 dev_dbg(amd_manager->dev, "p_params->num:0x%x\n", p_params->num);
435 switch (amd_manager->instance) {
436 case ACP_SDW0:
437 frame_fmt_reg = sdw0_manager_dp_reg[p_params->num].frame_fmt_reg;
438 break;
439 case ACP_SDW1:
440 frame_fmt_reg = sdw1_manager_dp_reg[p_params->num].frame_fmt_reg;
441 break;
442 default:
443 return -EINVAL;
444 }
445
446 dpn_frame_fmt = readl(amd_manager->mmio + frame_fmt_reg);
447 u32p_replace_bits(&dpn_frame_fmt, p_params->flow_mode, AMD_DPN_FRAME_FMT_PFM);
448 u32p_replace_bits(&dpn_frame_fmt, p_params->data_mode, AMD_DPN_FRAME_FMT_PDM);
449 u32p_replace_bits(&dpn_frame_fmt, p_params->bps - 1, AMD_DPN_FRAME_FMT_WORD_LEN);
450 writel(dpn_frame_fmt, amd_manager->mmio + frame_fmt_reg);
451 return 0;
452}
453
454static int amd_sdw_transport_params(struct sdw_bus *bus,
455 struct sdw_transport_params *params,
456 enum sdw_reg_bank bank)
457{
458 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus);
459 u32 dpn_frame_fmt;
460 u32 dpn_sampleinterval;
461 u32 dpn_hctrl;
462 u32 dpn_offsetctrl;
463 u32 dpn_lanectrl;
464 u32 frame_fmt_reg, sample_int_reg, hctrl_dp0_reg;
465 u32 offset_reg, lane_ctrl_ch_en_reg;
466
467 switch (amd_manager->instance) {
468 case ACP_SDW0:
469 frame_fmt_reg = sdw0_manager_dp_reg[params->port_num].frame_fmt_reg;
470 sample_int_reg = sdw0_manager_dp_reg[params->port_num].sample_int_reg;
471 hctrl_dp0_reg = sdw0_manager_dp_reg[params->port_num].hctrl_dp0_reg;
472 offset_reg = sdw0_manager_dp_reg[params->port_num].offset_reg;
473 lane_ctrl_ch_en_reg = sdw0_manager_dp_reg[params->port_num].lane_ctrl_ch_en_reg;
474 break;
475 case ACP_SDW1:
476 frame_fmt_reg = sdw1_manager_dp_reg[params->port_num].frame_fmt_reg;
477 sample_int_reg = sdw1_manager_dp_reg[params->port_num].sample_int_reg;
478 hctrl_dp0_reg = sdw1_manager_dp_reg[params->port_num].hctrl_dp0_reg;
479 offset_reg = sdw1_manager_dp_reg[params->port_num].offset_reg;
480 lane_ctrl_ch_en_reg = sdw1_manager_dp_reg[params->port_num].lane_ctrl_ch_en_reg;
481 break;
482 default:
483 return -EINVAL;
484 }
485 writel(AMD_SDW_SSP_COUNTER_VAL, amd_manager->mmio + ACP_SW_SSP_COUNTER);
486
487 dpn_frame_fmt = readl(amd_manager->mmio + frame_fmt_reg);
488 u32p_replace_bits(&dpn_frame_fmt, params->blk_pkg_mode, AMD_DPN_FRAME_FMT_BLK_PKG_MODE);
489 u32p_replace_bits(&dpn_frame_fmt, params->blk_grp_ctrl, AMD_DPN_FRAME_FMT_BLK_GRP_CTRL);
490 u32p_replace_bits(&dpn_frame_fmt, SDW_STREAM_PCM, AMD_DPN_FRAME_FMT_PCM_OR_PDM);
491 writel(dpn_frame_fmt, amd_manager->mmio + frame_fmt_reg);
492
493 dpn_sampleinterval = params->sample_interval - 1;
494 writel(dpn_sampleinterval, amd_manager->mmio + sample_int_reg);
495
496 dpn_hctrl = FIELD_PREP(AMD_DPN_HCTRL_HSTOP, params->hstop);
497 dpn_hctrl |= FIELD_PREP(AMD_DPN_HCTRL_HSTART, params->hstart);
498 writel(dpn_hctrl, amd_manager->mmio + hctrl_dp0_reg);
499
500 dpn_offsetctrl = FIELD_PREP(AMD_DPN_OFFSET_CTRL_1, params->offset1);
501 dpn_offsetctrl |= FIELD_PREP(AMD_DPN_OFFSET_CTRL_2, params->offset2);
502 writel(dpn_offsetctrl, amd_manager->mmio + offset_reg);
503
504 /*
505 * lane_ctrl_ch_en_reg will be used to program lane_ctrl and ch_mask
506 * parameters.
507 */
508 dpn_lanectrl = readl(amd_manager->mmio + lane_ctrl_ch_en_reg);
509 u32p_replace_bits(&dpn_lanectrl, params->lane_ctrl, AMD_DPN_CH_EN_LCTRL);
510 writel(dpn_lanectrl, amd_manager->mmio + lane_ctrl_ch_en_reg);
511 return 0;
512}
513
514static int amd_sdw_port_enable(struct sdw_bus *bus,
515 struct sdw_enable_ch *enable_ch,
516 unsigned int bank)
517{
518 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus);
519 u32 dpn_ch_enable;
520 u32 lane_ctrl_ch_en_reg;
521
522 switch (amd_manager->instance) {
523 case ACP_SDW0:
524 lane_ctrl_ch_en_reg = sdw0_manager_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg;
525 break;
526 case ACP_SDW1:
527 lane_ctrl_ch_en_reg = sdw1_manager_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg;
528 break;
529 default:
530 return -EINVAL;
531 }
532
533 /*
534 * lane_ctrl_ch_en_reg will be used to program lane_ctrl and ch_mask
535 * parameters.
536 */
537 dpn_ch_enable = readl(amd_manager->mmio + lane_ctrl_ch_en_reg);
538 u32p_replace_bits(&dpn_ch_enable, enable_ch->ch_mask, AMD_DPN_CH_EN_CHMASK);
539 if (enable_ch->enable)
540 writel(dpn_ch_enable, amd_manager->mmio + lane_ctrl_ch_en_reg);
541 else
542 writel(0, amd_manager->mmio + lane_ctrl_ch_en_reg);
543 return 0;
544}
545
546static int sdw_master_read_amd_prop(struct sdw_bus *bus)
547{
548 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus);
549 struct fwnode_handle *link;
550 struct sdw_master_prop *prop;
551 u32 quirk_mask = 0;
552 u32 wake_en_mask = 0;
553 u32 power_mode_mask = 0;
554 char name[32];
555
556 prop = &bus->prop;
557 /* Find manager handle */
558 snprintf(name, sizeof(name), "mipi-sdw-link-%d-subproperties", bus->link_id);
559 link = device_get_named_child_node(bus->dev, name);
560 if (!link) {
561 dev_err(bus->dev, "Manager node %s not found\n", name);
562 return -EIO;
563 }
564 fwnode_property_read_u32(link, "amd-sdw-enable", &quirk_mask);
565 if (!(quirk_mask & AMD_SDW_QUIRK_MASK_BUS_ENABLE))
566 prop->hw_disabled = true;
567 prop->quirks = SDW_MASTER_QUIRKS_CLEAR_INITIAL_CLASH |
568 SDW_MASTER_QUIRKS_CLEAR_INITIAL_PARITY;
569
570 fwnode_property_read_u32(link, "amd-sdw-wakeup-enable", &wake_en_mask);
571 amd_manager->wake_en_mask = wake_en_mask;
572 fwnode_property_read_u32(link, "amd-sdw-power-mode", &power_mode_mask);
573 amd_manager->power_mode_mask = power_mode_mask;
574 return 0;
575}
576
577static int amd_prop_read(struct sdw_bus *bus)
578{
579 sdw_master_read_prop(bus);
580 sdw_master_read_amd_prop(bus);
581 return 0;
582}
583
584static const struct sdw_master_port_ops amd_sdw_port_ops = {
585 .dpn_set_port_params = amd_sdw_port_params,
586 .dpn_set_port_transport_params = amd_sdw_transport_params,
587 .dpn_port_enable_ch = amd_sdw_port_enable,
588};
589
590static const struct sdw_master_ops amd_sdw_ops = {
591 .read_prop = amd_prop_read,
592 .xfer_msg = amd_sdw_xfer_msg,
593 .read_ping_status = amd_sdw_read_ping_status,
594};
595
2b13596f
VM		 596static int amd_sdw_hw_params(struct snd_pcm_substream *substream,
597 struct snd_pcm_hw_params *params,
598 struct snd_soc_dai *dai)
599{
600 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai);
601 struct sdw_amd_dai_runtime *dai_runtime;
602 struct sdw_stream_config sconfig;
603 struct sdw_port_config *pconfig;
604 int ch, dir;
605 int ret;
606
607 dai_runtime = amd_manager->dai_runtime_array[dai->id];
608 if (!dai_runtime)
609 return -EIO;
610
611 ch = params_channels(params);
612 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
613 dir = SDW_DATA_DIR_RX;
614 else
615 dir = SDW_DATA_DIR_TX;
616 dev_dbg(amd_manager->dev, "dir:%d dai->id:0x%x\n", dir, dai->id);
617
618 sconfig.direction = dir;
619 sconfig.ch_count = ch;
620 sconfig.frame_rate = params_rate(params);
621 sconfig.type = dai_runtime->stream_type;
622
623 sconfig.bps = snd_pcm_format_width(params_format(params));
624
625 /* Port configuration */
626 pconfig = kzalloc(sizeof(*pconfig), GFP_KERNEL);
627 if (!pconfig) {
628 ret = -ENOMEM;
629 goto error;
630 }
631
632 pconfig->num = dai->id;
633 pconfig->ch_mask = (1 << ch) - 1;
634 ret = sdw_stream_add_master(&amd_manager->bus, &sconfig,
635 pconfig, 1, dai_runtime->stream);
636 if (ret)
637 dev_err(amd_manager->dev, "add manager to stream failed:%d\n", ret);
638
639 kfree(pconfig);
640error:
641 return ret;
642}
643
644static int amd_sdw_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
645{
646 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai);
647 struct sdw_amd_dai_runtime *dai_runtime;
648 int ret;
649
650 dai_runtime = amd_manager->dai_runtime_array[dai->id];
651 if (!dai_runtime)
652 return -EIO;
653
654 ret = sdw_stream_remove_master(&amd_manager->bus, dai_runtime->stream);
655 if (ret < 0)
656 dev_err(dai->dev, "remove manager from stream %s failed: %d\n",
657 dai_runtime->stream->name, ret);
658 return ret;
659}
660
661static int amd_set_sdw_stream(struct snd_soc_dai *dai, void *stream, int direction)
662{
663 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai);
664 struct sdw_amd_dai_runtime *dai_runtime;
665
666 dai_runtime = amd_manager->dai_runtime_array[dai->id];
667 if (stream) {
668 /* first paranoia check */
669 if (dai_runtime) {
670 dev_err(dai->dev, "dai_runtime already allocated for dai %s\n", dai->name);
671 return -EINVAL;
672 }
673
674 /* allocate and set dai_runtime info */
675 dai_runtime = kzalloc(sizeof(*dai_runtime), GFP_KERNEL);
676 if (!dai_runtime)
677 return -ENOMEM;
678
679 dai_runtime->stream_type = SDW_STREAM_PCM;
680 dai_runtime->bus = &amd_manager->bus;
681 dai_runtime->stream = stream;
682 amd_manager->dai_runtime_array[dai->id] = dai_runtime;
683 } else {
684 /* second paranoia check */
685 if (!dai_runtime) {
686 dev_err(dai->dev, "dai_runtime not allocated for dai %s\n", dai->name);
687 return -EINVAL;
688 }
689
690 /* for NULL stream we release allocated dai_runtime */
691 kfree(dai_runtime);
692 amd_manager->dai_runtime_array[dai->id] = NULL;
693 }
694 return 0;
695}
696
697static int amd_pcm_set_sdw_stream(struct snd_soc_dai *dai, void *stream, int direction)
698{
699 return amd_set_sdw_stream(dai, stream, direction);
700}
701
702static void *amd_get_sdw_stream(struct snd_soc_dai *dai, int direction)
703{
704 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai);
705 struct sdw_amd_dai_runtime *dai_runtime;
706
707 dai_runtime = amd_manager->dai_runtime_array[dai->id];
708 if (!dai_runtime)
709 return ERR_PTR(-EINVAL);
710
711 return dai_runtime->stream;
712}
713
714static const struct snd_soc_dai_ops amd_sdw_dai_ops = {
715 .hw_params = amd_sdw_hw_params,
716 .hw_free = amd_sdw_hw_free,
717 .set_stream = amd_pcm_set_sdw_stream,
718 .get_stream = amd_get_sdw_stream,
719};
720
721static const struct snd_soc_component_driver amd_sdw_dai_component = {
722 .name = "soundwire",
723};
724
725static int amd_sdw_register_dais(struct amd_sdw_manager *amd_manager)
726{
727 struct sdw_amd_dai_runtime **dai_runtime_array;
728 struct snd_soc_dai_driver *dais;
729 struct snd_soc_pcm_stream *stream;
730 struct device *dev;
731 int i, num_dais;
732
733 dev = amd_manager->dev;
734 num_dais = amd_manager->num_dout_ports + amd_manager->num_din_ports;
735 dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL);
736 if (!dais)
737 return -ENOMEM;
738
739 dai_runtime_array = devm_kcalloc(dev, num_dais,
740 sizeof(struct sdw_amd_dai_runtime *),
741 GFP_KERNEL);
742 if (!dai_runtime_array)
743 return -ENOMEM;
744 amd_manager->dai_runtime_array = dai_runtime_array;
745 for (i = 0; i < num_dais; i++) {
746 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW%d Pin%d", amd_manager->instance,
747 i);
748 if (!dais[i].name)
749 return -ENOMEM;
750 if (i < amd_manager->num_dout_ports)
751 stream = &dais[i].playback;
752 else
753 stream = &dais[i].capture;
754
755 stream->channels_min = 2;
756 stream->channels_max = 2;
757 stream->rates = SNDRV_PCM_RATE_48000;
758 stream->formats = SNDRV_PCM_FMTBIT_S16_LE;
759
760 dais[i].ops = &amd_sdw_dai_ops;
761 dais[i].id = i;
762 }
763
764 return devm_snd_soc_register_component(dev, &amd_sdw_dai_component,
765 dais, num_dais);
766}
767
65f93e40
VM		 768static void amd_sdw_update_slave_status_work(struct work_struct *work)
769{
770 struct amd_sdw_manager *amd_manager =
771 container_of(work, struct amd_sdw_manager, amd_sdw_work);
772 int retry_count = 0;
773
774 if (amd_manager->status[0] == SDW_SLAVE_ATTACHED) {
775 writel(0, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7);
776 writel(0, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);
777 }
778
779update_status:
780 sdw_handle_slave_status(&amd_manager->bus, amd_manager->status);
781 /*
782 * During the peripheral enumeration sequence, the SoundWire manager interrupts
783 * are masked. Once the device number programming is done for all peripherals,
784 * interrupts will be unmasked. Read the peripheral device status from ping command
785 * and process the response. This sequence will ensure all peripheral devices enumerated
786 * and initialized properly.
787 */
788 if (amd_manager->status[0] == SDW_SLAVE_ATTACHED) {
789 if (retry_count++ < SDW_MAX_DEVICES) {
790 writel(AMD_SDW_IRQ_MASK_0TO7, amd_manager->mmio +
791 ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7);
792 writel(AMD_SDW_IRQ_MASK_8TO11, amd_manager->mmio +
793 ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);
794 amd_sdw_read_and_process_ping_status(amd_manager);
795 goto update_status;
796 } else {
797 dev_err_ratelimited(amd_manager->dev,
798 "Device0 detected after %d iterations\n",
799 retry_count);
800 }
801 }
802}
803
804static void amd_sdw_update_slave_status(u32 status_change_0to7, u32 status_change_8to11,
805 struct amd_sdw_manager *amd_manager)
806{
807 u64 slave_stat;
808 u32 val;
809 int dev_index;
810
811 if (status_change_0to7 == AMD_SDW_SLAVE_0_ATTACHED)
812 memset(amd_manager->status, 0, sizeof(amd_manager->status));
813 slave_stat = status_change_0to7;
814 slave_stat |= FIELD_GET(AMD_SDW_MCP_SLAVE_STATUS_8TO_11, status_change_8to11) << 32;
815 dev_dbg(amd_manager->dev, "status_change_0to7:0x%x status_change_8to11:0x%x\n",
816 status_change_0to7, status_change_8to11);
817 if (slave_stat) {
818 for (dev_index = 0; dev_index <= SDW_MAX_DEVICES; ++dev_index) {
819 if (slave_stat & AMD_SDW_MCP_SLAVE_STATUS_VALID_MASK(dev_index)) {
820 val = (slave_stat >> AMD_SDW_MCP_SLAVE_STAT_SHIFT_MASK(dev_index)) &
821 AMD_SDW_MCP_SLAVE_STATUS_MASK;
822 amd_sdw_fill_slave_status(amd_manager, dev_index, val);
823 }
824 }
825 }
826}
827
66c87883
VM		 828static void amd_sdw_process_wake_event(struct amd_sdw_manager *amd_manager)
829{
830 pm_request_resume(amd_manager->dev);
831 writel(0x00, amd_manager->acp_mmio + ACP_SW_WAKE_EN(amd_manager->instance));
832 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11);
833}
834
65f93e40
VM		 835static void amd_sdw_irq_thread(struct work_struct *work)
836{
837 struct amd_sdw_manager *amd_manager =
838 container_of(work, struct amd_sdw_manager, amd_sdw_irq_thread);
839 u32 status_change_8to11;
840 u32 status_change_0to7;
841
842 status_change_8to11 = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11);
843 status_change_0to7 = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_0TO7);
844 dev_dbg(amd_manager->dev, "[SDW%d] SDW INT: 0to7=0x%x, 8to11=0x%x\n",
845 amd_manager->instance, status_change_0to7, status_change_8to11);
66c87883
VM		 846 if (status_change_8to11 & AMD_SDW_WAKE_STAT_MASK)
847 return amd_sdw_process_wake_event(amd_manager);
848
65f93e40
VM		 849 if (status_change_8to11 & AMD_SDW_PREQ_INTR_STAT) {
850 amd_sdw_read_and_process_ping_status(amd_manager);
851 } else {
852 /* Check for the updated status on peripheral device */
853 amd_sdw_update_slave_status(status_change_0to7, status_change_8to11, amd_manager);
854 }
855 if (status_change_8to11 || status_change_0to7)
856 schedule_work(&amd_manager->amd_sdw_work);
857 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11);
858 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_0TO7);
859}
860
ed5e8741 861int amd_sdw_manager_start(struct amd_sdw_manager *amd_manager)
d8f48fbd 862{
d8f48fbd
VM		 863 struct sdw_master_prop *prop;
864 int ret;
865
866 prop = &amd_manager->bus.prop;
867 if (!prop->hw_disabled) {
d8f48fbd
VM		 868 ret = amd_init_sdw_manager(amd_manager);
869 if (ret)
ed5e8741 870 return ret;
d8f48fbd
VM		 871 amd_enable_sdw_interrupts(amd_manager);
872 ret = amd_enable_sdw_manager(amd_manager);
873 if (ret)
ed5e8741 874 return ret;
d8f48fbd
VM		 875 amd_sdw_set_frameshape(amd_manager);
876 }
81ff58ff
VM		 877 /* Enable runtime PM */
878 pm_runtime_set_autosuspend_delay(amd_manager->dev, AMD_SDW_MASTER_SUSPEND_DELAY_MS);
879 pm_runtime_use_autosuspend(amd_manager->dev);
880 pm_runtime_mark_last_busy(amd_manager->dev);
881 pm_runtime_set_active(amd_manager->dev);
882 pm_runtime_enable(amd_manager->dev);
ed5e8741 883 return 0;
d8f48fbd
VM		 884}
885
886static int amd_sdw_manager_probe(struct platform_device *pdev)
887{
888 const struct acp_sdw_pdata *pdata = pdev->dev.platform_data;
889 struct resource *res;
890 struct device *dev = &pdev->dev;
891 struct sdw_master_prop *prop;
892 struct sdw_bus_params *params;
893 struct amd_sdw_manager *amd_manager;
894 int ret;
895
896 amd_manager = devm_kzalloc(dev, sizeof(struct amd_sdw_manager), GFP_KERNEL);
897 if (!amd_manager)
898 return -ENOMEM;
899
900 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
901 if (!res)
902 return -ENOMEM;
903
904 amd_manager->acp_mmio = devm_ioremap(dev, res->start, resource_size(res));
7891d0a5 905 if (!amd_manager->acp_mmio) {
d8f48fbd 906 dev_err(dev, "mmio not found\n");
7891d0a5 907 return -ENOMEM;
d8f48fbd
VM		 908 }
909 amd_manager->instance = pdata->instance;
910 amd_manager->mmio = amd_manager->acp_mmio +
911 (amd_manager->instance * SDW_MANAGER_REG_OFFSET);
912 amd_manager->acp_sdw_lock = pdata->acp_sdw_lock;
913 amd_manager->cols_index = sdw_find_col_index(AMD_SDW_DEFAULT_COLUMNS);
914 amd_manager->rows_index = sdw_find_row_index(AMD_SDW_DEFAULT_ROWS);
915 amd_manager->dev = dev;
916 amd_manager->bus.ops = &amd_sdw_ops;
917 amd_manager->bus.port_ops = &amd_sdw_port_ops;
918 amd_manager->bus.compute_params = &amd_sdw_compute_params;
919 amd_manager->bus.clk_stop_timeout = 200;
920 amd_manager->bus.link_id = amd_manager->instance;
921
6543ac13
PLB		 922 /*
923 * Due to BIOS compatibility, the two links are exposed within
924 * the scope of a single controller. If this changes, the
925 * controller_id will have to be updated with drv_data
926 * information.
927 */
928 amd_manager->bus.controller_id = 0;
929
d8f48fbd
VM		 930 switch (amd_manager->instance) {
931 case ACP_SDW0:
932 amd_manager->num_dout_ports = AMD_SDW0_MAX_TX_PORTS;
933 amd_manager->num_din_ports = AMD_SDW0_MAX_RX_PORTS;
934 break;
935 case ACP_SDW1:
936 amd_manager->num_dout_ports = AMD_SDW1_MAX_TX_PORTS;
937 amd_manager->num_din_ports = AMD_SDW1_MAX_RX_PORTS;
938 break;
939 default:
940 return -EINVAL;
941 }
942
d8f48fbd 943 params = &amd_manager->bus.params;
becfce52 944
d8f48fbd
VM		 945 params->col = AMD_SDW_DEFAULT_COLUMNS;
946 params->row = AMD_SDW_DEFAULT_ROWS;
947 prop = &amd_manager->bus.prop;
948 prop->clk_freq = &amd_sdw_freq_tbl[0];
949 prop->mclk_freq = AMD_SDW_BUS_BASE_FREQ;
becfce52 950 prop->max_clk_freq = AMD_SDW_DEFAULT_CLK_FREQ;
d8f48fbd
VM		 951
952 ret = sdw_bus_master_add(&amd_manager->bus, dev, dev->fwnode);
953 if (ret) {
954 dev_err(dev, "Failed to register SoundWire manager(%d)\n", ret);
955 return ret;
956 }
2b13596f
VM		 957 ret = amd_sdw_register_dais(amd_manager);
958 if (ret) {
959 dev_err(dev, "CPU DAI registration failed\n");
960 sdw_bus_master_delete(&amd_manager->bus);
961 return ret;
962 }
d8f48fbd 963 dev_set_drvdata(dev, amd_manager);
65f93e40
VM		 964 INIT_WORK(&amd_manager->amd_sdw_irq_thread, amd_sdw_irq_thread);
965 INIT_WORK(&amd_manager->amd_sdw_work, amd_sdw_update_slave_status_work);
d8f48fbd
VM		 966 return 0;
967}
968
1ec33e22 969static void amd_sdw_manager_remove(struct platform_device *pdev)
d8f48fbd
VM		 970{
971 struct amd_sdw_manager *amd_manager = dev_get_drvdata(&pdev->dev);
1ec33e22 972 int ret;
d8f48fbd 973
81ff58ff 974 pm_runtime_disable(&pdev->dev);
d8f48fbd
VM		 975 amd_disable_sdw_interrupts(amd_manager);
976 sdw_bus_master_delete(&amd_manager->bus);
1ec33e22
UKK		 977 ret = amd_disable_sdw_manager(amd_manager);
978 if (ret)
979 dev_err(&pdev->dev, "Failed to disable device (%pe)\n", ERR_PTR(ret));
d8f48fbd
VM		 980}
981
81ff58ff
VM		 982static int amd_sdw_clock_stop(struct amd_sdw_manager *amd_manager)
983{
984 u32 val;
985 int ret;
986
987 ret = sdw_bus_prep_clk_stop(&amd_manager->bus);
988 if (ret < 0 && ret != -ENODATA) {
989 dev_err(amd_manager->dev, "prepare clock stop failed %d", ret);
990 return 0;
991 }
992 ret = sdw_bus_clk_stop(&amd_manager->bus);
993 if (ret < 0 && ret != -ENODATA) {
994 dev_err(amd_manager->dev, "bus clock stop failed %d", ret);
995 return 0;
996 }
997
998 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL, val,
999 (val & AMD_SDW_CLK_STOP_DONE), ACP_DELAY_US, AMD_SDW_TIMEOUT);
1000 if (ret) {
1001 dev_err(amd_manager->dev, "SDW%x clock stop failed\n", amd_manager->instance);
1002 return 0;
1003 }
1004
1005 amd_manager->clk_stopped = true;
1006 if (amd_manager->wake_en_mask)
1007 writel(0x01, amd_manager->acp_mmio + ACP_SW_WAKE_EN(amd_manager->instance));
1008
1009 dev_dbg(amd_manager->dev, "SDW%x clock stop successful\n", amd_manager->instance);
1010 return 0;
1011}
1012
1013static int amd_sdw_clock_stop_exit(struct amd_sdw_manager *amd_manager)
1014{
1015 int ret;
1016 u32 val;
1017
1018 if (amd_manager->clk_stopped) {
1019 val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);
1020 val |= AMD_SDW_CLK_RESUME_REQ;
1021 writel(val, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);
1022 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL, val,
1023 (val & AMD_SDW_CLK_RESUME_DONE), ACP_DELAY_US,
1024 AMD_SDW_TIMEOUT);
1025 if (val & AMD_SDW_CLK_RESUME_DONE) {
1026 writel(0, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);
1027 ret = sdw_bus_exit_clk_stop(&amd_manager->bus);
1028 if (ret < 0)
1029 dev_err(amd_manager->dev, "bus failed to exit clock stop %d\n",
1030 ret);
1031 amd_manager->clk_stopped = false;
1032 }
1033 }
1034 if (amd_manager->clk_stopped) {
1035 dev_err(amd_manager->dev, "SDW%x clock stop exit failed\n", amd_manager->instance);
1036 return 0;
1037 }
1038 dev_dbg(amd_manager->dev, "SDW%x clock stop exit successful\n", amd_manager->instance);
1039 return 0;
1040}
1041
9cf1efc5
VM		 1042static int amd_resume_child_device(struct device *dev, void *data)
1043{
1044 struct sdw_slave *slave = dev_to_sdw_dev(dev);
1045 int ret;
1046
1047 if (!slave->probed) {
1048 dev_dbg(dev, "skipping device, no probed driver\n");
1049 return 0;
1050 }
1051 if (!slave->dev_num_sticky) {
1052 dev_dbg(dev, "skipping device, never detected on bus\n");
1053 return 0;
1054 }
1055 ret = pm_request_resume(dev);
1056 if (ret < 0) {
1057 dev_err(dev, "pm_request_resume failed: %d\n", ret);
1058 return ret;
1059 }
1060 return 0;
1061}
1062
1063static int __maybe_unused amd_pm_prepare(struct device *dev)
1064{
1065 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev);
1066 struct sdw_bus *bus = &amd_manager->bus;
1067 int ret;
1068
1069 if (bus->prop.hw_disabled) {
1070 dev_dbg(bus->dev, "SoundWire manager %d is disabled, ignoring\n",
1071 bus->link_id);
1072 return 0;
1073 }
1074 /*
1075 * When multiple peripheral devices connected over the same link, if SoundWire manager
1076 * device is not in runtime suspend state, observed that device alerts are missing
1077 * without pm_prepare on AMD platforms in clockstop mode0.
1078 */
1079 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) {
1080 ret = pm_request_resume(dev);
1081 if (ret < 0) {
1082 dev_err(bus->dev, "pm_request_resume failed: %d\n", ret);
1083 return 0;
1084 }
1085 }
1086 /* To force peripheral devices to system level suspend state, resume the devices
1087 * from runtime suspend state first. Without that unable to dispatch the alert
1088 * status to peripheral driver during system level resume as they are in runtime
1089 * suspend state.
1090 */
1091 ret = device_for_each_child(bus->dev, NULL, amd_resume_child_device);
1092 if (ret < 0)
1093 dev_err(dev, "amd_resume_child_device failed: %d\n", ret);
1094 return 0;
1095}
1096
1097static int __maybe_unused amd_suspend(struct device *dev)
1098{
1099 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev);
1100 struct sdw_bus *bus = &amd_manager->bus;
1101 int ret;
1102
1103 if (bus->prop.hw_disabled) {
1104 dev_dbg(bus->dev, "SoundWire manager %d is disabled, ignoring\n",
1105 bus->link_id);
1106 return 0;
1107 }
1108
1109 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) {
63dc588e 1110 amd_sdw_wake_enable(amd_manager, false);
9cf1efc5
VM		 1111 return amd_sdw_clock_stop(amd_manager);
1112 } else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) {
1113 /*
1114 * As per hardware programming sequence on AMD platforms,
1115 * clock stop should be invoked first before powering-off
1116 */
1117 ret = amd_sdw_clock_stop(amd_manager);
1118 if (ret)
1119 return ret;
1120 return amd_deinit_sdw_manager(amd_manager);
1121 }
1122 return 0;
1123}
1124
81ff58ff
VM		 1125static int __maybe_unused amd_suspend_runtime(struct device *dev)
1126{
1127 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev);
1128 struct sdw_bus *bus = &amd_manager->bus;
1129 int ret;
1130
1131 if (bus->prop.hw_disabled) {
1132 dev_dbg(bus->dev, "SoundWire manager %d is disabled,\n",
1133 bus->link_id);
1134 return 0;
1135 }
1136 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) {
63dc588e 1137 amd_sdw_wake_enable(amd_manager, true);
81ff58ff
VM		 1138 return amd_sdw_clock_stop(amd_manager);
1139 } else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) {
1140 ret = amd_sdw_clock_stop(amd_manager);
1141 if (ret)
1142 return ret;
1143 return amd_deinit_sdw_manager(amd_manager);
1144 }
1145 return 0;
1146}
1147
1148static int __maybe_unused amd_resume_runtime(struct device *dev)
1149{
1150 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev);
1151 struct sdw_bus *bus = &amd_manager->bus;
1152 int ret;
1153 u32 val;
1154
1155 if (bus->prop.hw_disabled) {
1156 dev_dbg(bus->dev, "SoundWire manager %d is disabled, ignoring\n",
1157 bus->link_id);
1158 return 0;
1159 }
1160
1161 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) {
1162 return amd_sdw_clock_stop_exit(amd_manager);
1163 } else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) {
1164 val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);
1165 if (val) {
1166 val |= AMD_SDW_CLK_RESUME_REQ;
1167 writel(val, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);
1168 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL, val,
1169 (val & AMD_SDW_CLK_RESUME_DONE), ACP_DELAY_US,
1170 AMD_SDW_TIMEOUT);
1171 if (val & AMD_SDW_CLK_RESUME_DONE) {
1172 writel(0, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);
1173 amd_manager->clk_stopped = false;
1174 }
1175 }
1176 sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET);
1177 amd_init_sdw_manager(amd_manager);
1178 amd_enable_sdw_interrupts(amd_manager);
1179 ret = amd_enable_sdw_manager(amd_manager);
1180 if (ret)
1181 return ret;
1182 amd_sdw_set_frameshape(amd_manager);
1183 }
1184 return 0;
1185}
1186
1187static const struct dev_pm_ops amd_pm = {
9cf1efc5
VM		 1188 .prepare = amd_pm_prepare,
1189 SET_SYSTEM_SLEEP_PM_OPS(amd_suspend, amd_resume_runtime)
81ff58ff
VM		 1190 SET_RUNTIME_PM_OPS(amd_suspend_runtime, amd_resume_runtime, NULL)
1191};
1192
d8f48fbd
VM		 1193static struct platform_driver amd_sdw_driver = {
1194 .probe = &amd_sdw_manager_probe,
1ec33e22 1195 .remove_new = &amd_sdw_manager_remove,
d8f48fbd
VM		 1196 .driver = {
1197 .name = "amd_sdw_manager",
81ff58ff 1198 .pm = &amd_pm,
d8f48fbd
VM		 1199 }
1200};
1201module_platform_driver(amd_sdw_driver);
1202
1203MODULE_AUTHOR("Vijendar.Mukunda@amd.com");
1204MODULE_DESCRIPTION("AMD SoundWire driver");
a4774642 1205MODULE_LICENSE("Dual BSD/GPL");
d8f48fbd 1206MODULE_ALIAS("platform:" DRV_NAME);
Linux 6.x block layer and io_uring tree(s)