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ARM: tegra: Add PMC thermtrip programming to Jetson TK1 device tree
[linux-2.6-block.git] / drivers / soc / tegra / pmc.c
CommitLineData
7232398a
TR		 1/*
2 * drivers/soc/tegra/pmc.c
3 *
4 * Copyright (c) 2010 Google, Inc
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/kernel.h>
21#include <linux/clk.h>
22#include <linux/clk/tegra.h>
23#include <linux/debugfs.h>
24#include <linux/delay.h>
25#include <linux/err.h>
26#include <linux/export.h>
27#include <linux/init.h>
28#include <linux/io.h>
29#include <linux/of.h>
30#include <linux/of_address.h>
31#include <linux/platform_device.h>
32#include <linux/reboot.h>
33#include <linux/reset.h>
34#include <linux/seq_file.h>
35#include <linux/spinlock.h>
36
37#include <soc/tegra/common.h>
38#include <soc/tegra/fuse.h>
39#include <soc/tegra/pmc.h>
40
41#define PMC_CNTRL 0x0
42#define PMC_CNTRL_SYSCLK_POLARITY (1 << 10) /* sys clk polarity */
43#define PMC_CNTRL_SYSCLK_OE (1 << 11) /* system clock enable */
44#define PMC_CNTRL_SIDE_EFFECT_LP0 (1 << 14) /* LP0 when CPU pwr gated */
45#define PMC_CNTRL_CPU_PWRREQ_POLARITY (1 << 15) /* CPU pwr req polarity */
46#define PMC_CNTRL_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */
47#define PMC_CNTRL_INTR_POLARITY (1 << 17) /* inverts INTR polarity */
48
49#define DPD_SAMPLE 0x020
50#define DPD_SAMPLE_ENABLE (1 << 0)
51#define DPD_SAMPLE_DISABLE (0 << 0)
52
53#define PWRGATE_TOGGLE 0x30
54#define PWRGATE_TOGGLE_START (1 << 8)
55
56#define REMOVE_CLAMPING 0x34
57
58#define PWRGATE_STATUS 0x38
59
60#define PMC_SCRATCH0 0x50
61#define PMC_SCRATCH0_MODE_RECOVERY (1 << 31)
62#define PMC_SCRATCH0_MODE_BOOTLOADER (1 << 30)
63#define PMC_SCRATCH0_MODE_RCM (1 << 1)
64#define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
65 PMC_SCRATCH0_MODE_BOOTLOADER | \
66 PMC_SCRATCH0_MODE_RCM)
67
68#define PMC_CPUPWRGOOD_TIMER 0xc8
69#define PMC_CPUPWROFF_TIMER 0xcc
70
71#define PMC_SCRATCH41 0x140
72
73#define IO_DPD_REQ 0x1b8
74#define IO_DPD_REQ_CODE_IDLE (0 << 30)
75#define IO_DPD_REQ_CODE_OFF (1 << 30)
76#define IO_DPD_REQ_CODE_ON (2 << 30)
77#define IO_DPD_REQ_CODE_MASK (3 << 30)
78
79#define IO_DPD_STATUS 0x1bc
80#define IO_DPD2_REQ 0x1c0
81#define IO_DPD2_STATUS 0x1c4
82#define SEL_DPD_TIM 0x1c8
83
84#define GPU_RG_CNTRL 0x2d4
85
86struct tegra_pmc_soc {
87 unsigned int num_powergates;
88 const char *const *powergates;
89 unsigned int num_cpu_powergates;
90 const u8 *cpu_powergates;
a9a40a4a
TR		 91
92 bool has_gpu_clamps;
7232398a
TR		 93};
94
95/**
96 * struct tegra_pmc - NVIDIA Tegra PMC
97 * @base: pointer to I/O remapped register region
98 * @clk: pointer to pclk clock
99 * @rate: currently configured rate of pclk
100 * @suspend_mode: lowest suspend mode available
101 * @cpu_good_time: CPU power good time (in microseconds)
102 * @cpu_off_time: CPU power off time (in microsecends)
103 * @core_osc_time: core power good OSC time (in microseconds)
104 * @core_pmu_time: core power good PMU time (in microseconds)
105 * @core_off_time: core power off time (in microseconds)
106 * @corereq_high: core power request is active-high
107 * @sysclkreq_high: system clock request is active-high
108 * @combined_req: combined power request for CPU & core
109 * @cpu_pwr_good_en: CPU power good signal is enabled
110 * @lp0_vec_phys: physical base address of the LP0 warm boot code
111 * @lp0_vec_size: size of the LP0 warm boot code
112 * @powergates_lock: mutex for power gate register access
113 */
114struct tegra_pmc {
115 void __iomem *base;
116 struct clk *clk;
117
118 const struct tegra_pmc_soc *soc;
119
120 unsigned long rate;
121
122 enum tegra_suspend_mode suspend_mode;
123 u32 cpu_good_time;
124 u32 cpu_off_time;
125 u32 core_osc_time;
126 u32 core_pmu_time;
127 u32 core_off_time;
128 bool corereq_high;
129 bool sysclkreq_high;
130 bool combined_req;
131 bool cpu_pwr_good_en;
132 u32 lp0_vec_phys;
133 u32 lp0_vec_size;
134
135 struct mutex powergates_lock;
136};
137
138static struct tegra_pmc *pmc = &(struct tegra_pmc) {
139 .base = NULL,
140 .suspend_mode = TEGRA_SUSPEND_NONE,
141};
142
143static u32 tegra_pmc_readl(unsigned long offset)
144{
145 return readl(pmc->base + offset);
146}
147
148static void tegra_pmc_writel(u32 value, unsigned long offset)
149{
150 writel(value, pmc->base + offset);
151}
152
153/**
154 * tegra_powergate_set() - set the state of a partition
155 * @id: partition ID
156 * @new_state: new state of the partition
157 */
158static int tegra_powergate_set(int id, bool new_state)
159{
160 bool status;
161
162 mutex_lock(&pmc->powergates_lock);
163
164 status = tegra_pmc_readl(PWRGATE_STATUS) & (1 << id);
165
166 if (status == new_state) {
167 mutex_unlock(&pmc->powergates_lock);
168 return 0;
169 }
170
171 tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
172
173 mutex_unlock(&pmc->powergates_lock);
174
175 return 0;
176}
177
178/**
179 * tegra_powergate_power_on() - power on partition
180 * @id: partition ID
181 */
182int tegra_powergate_power_on(int id)
183{
184 if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates)
185 return -EINVAL;
186
187 return tegra_powergate_set(id, true);
188}
189
190/**
191 * tegra_powergate_power_off() - power off partition
192 * @id: partition ID
193 */
194int tegra_powergate_power_off(int id)
195{
196 if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates)
197 return -EINVAL;
198
199 return tegra_powergate_set(id, false);
200}
201EXPORT_SYMBOL(tegra_powergate_power_off);
202
203/**
204 * tegra_powergate_is_powered() - check if partition is powered
205 * @id: partition ID
206 */
207int tegra_powergate_is_powered(int id)
208{
209 u32 status;
210
211 if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates)
212 return -EINVAL;
213
214 status = tegra_pmc_readl(PWRGATE_STATUS) & (1 << id);
215 return !!status;
216}
217
218/**
219 * tegra_powergate_remove_clamping() - remove power clamps for partition
220 * @id: partition ID
221 */
222int tegra_powergate_remove_clamping(int id)
223{
224 u32 mask;
225
226 if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates)
227 return -EINVAL;
228
229 /*
a9a40a4a
TR		 230 * On Tegra124 and later, the clamps for the GPU are controlled by a
231 * separate register (with different semantics).
7232398a 232 */
a9a40a4a
TR		 233 if (id == TEGRA_POWERGATE_3D) {
234 if (pmc->soc->has_gpu_clamps) {
7232398a
TR		 235 tegra_pmc_writel(0, GPU_RG_CNTRL);
236 return 0;
237 }
238 }
239
240 /*
241 * Tegra 2 has a bug where PCIE and VDE clamping masks are
242 * swapped relatively to the partition ids
243 */
244 if (id == TEGRA_POWERGATE_VDEC)
245 mask = (1 << TEGRA_POWERGATE_PCIE);
246 else if (id == TEGRA_POWERGATE_PCIE)
247 mask = (1 << TEGRA_POWERGATE_VDEC);
248 else
249 mask = (1 << id);
250
251 tegra_pmc_writel(mask, REMOVE_CLAMPING);
252
253 return 0;
254}
255EXPORT_SYMBOL(tegra_powergate_remove_clamping);
256
257/**
258 * tegra_powergate_sequence_power_up() - power up partition
259 * @id: partition ID
260 * @clk: clock for partition
261 * @rst: reset for partition
262 *
263 * Must be called with clk disabled, and returns with clk enabled.
264 */
265int tegra_powergate_sequence_power_up(int id, struct clk *clk,
266 struct reset_control *rst)
267{
268 int ret;
269
270 reset_control_assert(rst);
271
272 ret = tegra_powergate_power_on(id);
273 if (ret)
274 goto err_power;
275
276 ret = clk_prepare_enable(clk);
277 if (ret)
278 goto err_clk;
279
280 usleep_range(10, 20);
281
282 ret = tegra_powergate_remove_clamping(id);
283 if (ret)
284 goto err_clamp;
285
286 usleep_range(10, 20);
287 reset_control_deassert(rst);
288
289 return 0;
290
291err_clamp:
292 clk_disable_unprepare(clk);
293err_clk:
294 tegra_powergate_power_off(id);
295err_power:
296 return ret;
297}
298EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
299
300#ifdef CONFIG_SMP
301/**
302 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
303 * @cpuid: CPU partition ID
304 *
305 * Returns the partition ID corresponding to the CPU partition ID or a
306 * negative error code on failure.
307 */
308static int tegra_get_cpu_powergate_id(int cpuid)
309{
310 if (pmc->soc && cpuid > 0 && cpuid < pmc->soc->num_cpu_powergates)
311 return pmc->soc->cpu_powergates[cpuid];
312
313 return -EINVAL;
314}
315
316/**
317 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
318 * @cpuid: CPU partition ID
319 */
320bool tegra_pmc_cpu_is_powered(int cpuid)
321{
322 int id;
323
324 id = tegra_get_cpu_powergate_id(cpuid);
325 if (id < 0)
326 return false;
327
328 return tegra_powergate_is_powered(id);
329}
330
331/**
332 * tegra_pmc_cpu_power_on() - power on CPU partition
333 * @cpuid: CPU partition ID
334 */
335int tegra_pmc_cpu_power_on(int cpuid)
336{
337 int id;
338
339 id = tegra_get_cpu_powergate_id(cpuid);
340 if (id < 0)
341 return id;
342
343 return tegra_powergate_set(id, true);
344}
345
346/**
347 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
348 * @cpuid: CPU partition ID
349 */
350int tegra_pmc_cpu_remove_clamping(int cpuid)
351{
352 int id;
353
354 id = tegra_get_cpu_powergate_id(cpuid);
355 if (id < 0)
356 return id;
357
358 return tegra_powergate_remove_clamping(id);
359}
360#endif /* CONFIG_SMP */
361
362/**
363 * tegra_pmc_restart() - reboot the system
364 * @mode: which mode to reboot in
365 * @cmd: reboot command
366 */
367void tegra_pmc_restart(enum reboot_mode mode, const char *cmd)
368{
369 u32 value;
370
371 value = tegra_pmc_readl(PMC_SCRATCH0);
372 value &= ~PMC_SCRATCH0_MODE_MASK;
373
374 if (cmd) {
375 if (strcmp(cmd, "recovery") == 0)
376 value |= PMC_SCRATCH0_MODE_RECOVERY;
377
378 if (strcmp(cmd, "bootloader") == 0)
379 value |= PMC_SCRATCH0_MODE_BOOTLOADER;
380
381 if (strcmp(cmd, "forced-recovery") == 0)
382 value |= PMC_SCRATCH0_MODE_RCM;
383 }
384
385 tegra_pmc_writel(value, PMC_SCRATCH0);
386
387 value = tegra_pmc_readl(0);
388 value |= 0x10;
389 tegra_pmc_writel(value, 0);
390}
391
392static int powergate_show(struct seq_file *s, void *data)
393{
394 unsigned int i;
395
396 seq_printf(s, " powergate powered\n");
397 seq_printf(s, "------------------\n");
398
399 for (i = 0; i < pmc->soc->num_powergates; i++) {
400 if (!pmc->soc->powergates[i])
401 continue;
402
403 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
404 tegra_powergate_is_powered(i) ? "yes" : "no");
405 }
406
407 return 0;
408}
409
410static int powergate_open(struct inode *inode, struct file *file)
411{
412 return single_open(file, powergate_show, inode->i_private);
413}
414
415static const struct file_operations powergate_fops = {
416 .open = powergate_open,
417 .read = seq_read,
418 .llseek = seq_lseek,
419 .release = single_release,
420};
421
422static int tegra_powergate_debugfs_init(void)
423{
424 struct dentry *d;
425
426 d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
427 &powergate_fops);
428 if (!d)
429 return -ENOMEM;
430
431 return 0;
432}
433
434static int tegra_io_rail_prepare(int id, unsigned long *request,
435 unsigned long *status, unsigned int *bit)
436{
437 unsigned long rate, value;
438 struct clk *clk;
439
440 *bit = id % 32;
441
442 /*
443 * There are two sets of 30 bits to select IO rails, but bits 30 and
444 * 31 are control bits rather than IO rail selection bits.
445 */
446 if (id > 63 || *bit == 30 || *bit == 31)
447 return -EINVAL;
448
449 if (id < 32) {
450 *status = IO_DPD_STATUS;
451 *request = IO_DPD_REQ;
452 } else {
453 *status = IO_DPD2_STATUS;
454 *request = IO_DPD2_REQ;
455 }
456
457 clk = clk_get_sys(NULL, "pclk");
458 if (IS_ERR(clk))
459 return PTR_ERR(clk);
460
461 rate = clk_get_rate(clk);
462 clk_put(clk);
463
464 tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE);
465
466 /* must be at least 200 ns, in APB (PCLK) clock cycles */
467 value = DIV_ROUND_UP(1000000000, rate);
468 value = DIV_ROUND_UP(200, value);
469 tegra_pmc_writel(value, SEL_DPD_TIM);
470
471 return 0;
472}
473
474static int tegra_io_rail_poll(unsigned long offset, unsigned long mask,
475 unsigned long val, unsigned long timeout)
476{
477 unsigned long value;
478
479 timeout = jiffies + msecs_to_jiffies(timeout);
480
481 while (time_after(timeout, jiffies)) {
482 value = tegra_pmc_readl(offset);
483 if ((value & mask) == val)
484 return 0;
485
486 usleep_range(250, 1000);
487 }
488
489 return -ETIMEDOUT;
490}
491
492static void tegra_io_rail_unprepare(void)
493{
494 tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE);
495}
496
497int tegra_io_rail_power_on(int id)
498{
499 unsigned long request, status, value;
500 unsigned int bit, mask;
501 int err;
502
503 err = tegra_io_rail_prepare(id, &request, &status, &bit);
504 if (err < 0)
505 return err;
506
507 mask = 1 << bit;
508
509 value = tegra_pmc_readl(request);
510 value |= mask;
511 value &= ~IO_DPD_REQ_CODE_MASK;
512 value |= IO_DPD_REQ_CODE_OFF;
513 tegra_pmc_writel(value, request);
514
515 err = tegra_io_rail_poll(status, mask, 0, 250);
516 if (err < 0)
517 return err;
518
519 tegra_io_rail_unprepare();
520
521 return 0;
522}
523EXPORT_SYMBOL(tegra_io_rail_power_on);
524
525int tegra_io_rail_power_off(int id)
526{
527 unsigned long request, status, value;
528 unsigned int bit, mask;
529 int err;
530
531 err = tegra_io_rail_prepare(id, &request, &status, &bit);
532 if (err < 0)
533 return err;
534
535 mask = 1 << bit;
536
537 value = tegra_pmc_readl(request);
538 value |= mask;
539 value &= ~IO_DPD_REQ_CODE_MASK;
540 value |= IO_DPD_REQ_CODE_ON;
541 tegra_pmc_writel(value, request);
542
543 err = tegra_io_rail_poll(status, mask, mask, 250);
544 if (err < 0)
545 return err;
546
547 tegra_io_rail_unprepare();
548
549 return 0;
550}
551EXPORT_SYMBOL(tegra_io_rail_power_off);
552
553#ifdef CONFIG_PM_SLEEP
554enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
555{
556 return pmc->suspend_mode;
557}
558
559void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
560{
561 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
562 return;
563
564 pmc->suspend_mode = mode;
565}
566
567void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
568{
569 unsigned long long rate = 0;
570 u32 value;
571
572 switch (mode) {
573 case TEGRA_SUSPEND_LP1:
574 rate = 32768;
575 break;
576
577 case TEGRA_SUSPEND_LP2:
578 rate = clk_get_rate(pmc->clk);
579 break;
580
581 default:
582 break;
583 }
584
585 if (WARN_ON_ONCE(rate == 0))
586 rate = 100000000;
587
588 if (rate != pmc->rate) {
589 u64 ticks;
590
591 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
592 do_div(ticks, USEC_PER_SEC);
593 tegra_pmc_writel(ticks, PMC_CPUPWRGOOD_TIMER);
594
595 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
596 do_div(ticks, USEC_PER_SEC);
597 tegra_pmc_writel(ticks, PMC_CPUPWROFF_TIMER);
598
599 wmb();
600
601 pmc->rate = rate;
602 }
603
604 value = tegra_pmc_readl(PMC_CNTRL);
605 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
606 value |= PMC_CNTRL_CPU_PWRREQ_OE;
607 tegra_pmc_writel(value, PMC_CNTRL);
608}
609#endif
610
611static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
612{
613 u32 value, values[2];
614
615 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
616 } else {
617 switch (value) {
618 case 0:
619 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
620 break;
621
622 case 1:
623 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
624 break;
625
626 case 2:
627 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
628 break;
629
630 default:
631 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
632 break;
633 }
634 }
635
636 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
637
638 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
639 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
640
641 pmc->cpu_good_time = value;
642
643 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
644 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
645
646 pmc->cpu_off_time = value;
647
648 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
649 values, ARRAY_SIZE(values)))
650 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
651
652 pmc->core_osc_time = values[0];
653 pmc->core_pmu_time = values[1];
654
655 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
656 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
657
658 pmc->core_off_time = value;
659
660 pmc->corereq_high = of_property_read_bool(np,
661 "nvidia,core-power-req-active-high");
662
663 pmc->sysclkreq_high = of_property_read_bool(np,
664 "nvidia,sys-clock-req-active-high");
665
666 pmc->combined_req = of_property_read_bool(np,
667 "nvidia,combined-power-req");
668
669 pmc->cpu_pwr_good_en = of_property_read_bool(np,
670 "nvidia,cpu-pwr-good-en");
671
672 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
673 ARRAY_SIZE(values)))
674 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
675 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
676
677 pmc->lp0_vec_phys = values[0];
678 pmc->lp0_vec_size = values[1];
679
680 return 0;
681}
682
683static void tegra_pmc_init(struct tegra_pmc *pmc)
684{
685 u32 value;
686
687 /* Always enable CPU power request */
688 value = tegra_pmc_readl(PMC_CNTRL);
689 value |= PMC_CNTRL_CPU_PWRREQ_OE;
690 tegra_pmc_writel(value, PMC_CNTRL);
691
692 value = tegra_pmc_readl(PMC_CNTRL);
693
694 if (pmc->sysclkreq_high)
695 value &= ~PMC_CNTRL_SYSCLK_POLARITY;
696 else
697 value |= PMC_CNTRL_SYSCLK_POLARITY;
698
699 /* configure the output polarity while the request is tristated */
700 tegra_pmc_writel(value, PMC_CNTRL);
701
702 /* now enable the request */
703 value = tegra_pmc_readl(PMC_CNTRL);
704 value |= PMC_CNTRL_SYSCLK_OE;
705 tegra_pmc_writel(value, PMC_CNTRL);
706}
707
708static int tegra_pmc_probe(struct platform_device *pdev)
709{
710 void __iomem *base = pmc->base;
711 struct resource *res;
712 int err;
713
714 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
715 if (err < 0)
716 return err;
717
718 /* take over the memory region from the early initialization */
719 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
720 pmc->base = devm_ioremap_resource(&pdev->dev, res);
721 if (IS_ERR(pmc->base))
722 return PTR_ERR(pmc->base);
723
724 iounmap(base);
725
726 pmc->clk = devm_clk_get(&pdev->dev, "pclk");
727 if (IS_ERR(pmc->clk)) {
728 err = PTR_ERR(pmc->clk);
729 dev_err(&pdev->dev, "failed to get pclk: %d\n", err);
730 return err;
731 }
732
733 tegra_pmc_init(pmc);
734
735 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
736 err = tegra_powergate_debugfs_init();
737 if (err < 0)
738 return err;
739 }
740
741 return 0;
742}
743
2b20b616 744#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
7232398a
TR		 745static int tegra_pmc_suspend(struct device *dev)
746{
747 tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41);
748
749 return 0;
750}
751
752static int tegra_pmc_resume(struct device *dev)
753{
754 tegra_pmc_writel(0x0, PMC_SCRATCH41);
755
756 return 0;
757}
7232398a
TR		 758
759static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
760
2b20b616
PW		 761#endif
762
7232398a
TR		 763static const char * const tegra20_powergates[] = {
764 [TEGRA_POWERGATE_CPU] = "cpu",
765 [TEGRA_POWERGATE_3D] = "3d",
766 [TEGRA_POWERGATE_VENC] = "venc",
767 [TEGRA_POWERGATE_VDEC] = "vdec",
768 [TEGRA_POWERGATE_PCIE] = "pcie",
769 [TEGRA_POWERGATE_L2] = "l2",
770 [TEGRA_POWERGATE_MPE] = "mpe",
771};
772
773static const struct tegra_pmc_soc tegra20_pmc_soc = {
774 .num_powergates = ARRAY_SIZE(tegra20_powergates),
775 .powergates = tegra20_powergates,
776 .num_cpu_powergates = 0,
777 .cpu_powergates = NULL,
a9a40a4a 778 .has_gpu_clamps = false,
7232398a
TR		 779};
780
781static const char * const tegra30_powergates[] = {
782 [TEGRA_POWERGATE_CPU] = "cpu0",
783 [TEGRA_POWERGATE_3D] = "3d0",
784 [TEGRA_POWERGATE_VENC] = "venc",
785 [TEGRA_POWERGATE_VDEC] = "vdec",
786 [TEGRA_POWERGATE_PCIE] = "pcie",
787 [TEGRA_POWERGATE_L2] = "l2",
788 [TEGRA_POWERGATE_MPE] = "mpe",
789 [TEGRA_POWERGATE_HEG] = "heg",
790 [TEGRA_POWERGATE_SATA] = "sata",
791 [TEGRA_POWERGATE_CPU1] = "cpu1",
792 [TEGRA_POWERGATE_CPU2] = "cpu2",
793 [TEGRA_POWERGATE_CPU3] = "cpu3",
794 [TEGRA_POWERGATE_CELP] = "celp",
795 [TEGRA_POWERGATE_3D1] = "3d1",
796};
797
798static const u8 tegra30_cpu_powergates[] = {
799 TEGRA_POWERGATE_CPU,
800 TEGRA_POWERGATE_CPU1,
801 TEGRA_POWERGATE_CPU2,
802 TEGRA_POWERGATE_CPU3,
803};
804
805static const struct tegra_pmc_soc tegra30_pmc_soc = {
806 .num_powergates = ARRAY_SIZE(tegra30_powergates),
807 .powergates = tegra30_powergates,
808 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
809 .cpu_powergates = tegra30_cpu_powergates,
a9a40a4a 810 .has_gpu_clamps = false,
7232398a
TR		 811};
812
813static const char * const tegra114_powergates[] = {
814 [TEGRA_POWERGATE_CPU] = "crail",
815 [TEGRA_POWERGATE_3D] = "3d",
816 [TEGRA_POWERGATE_VENC] = "venc",
817 [TEGRA_POWERGATE_VDEC] = "vdec",
818 [TEGRA_POWERGATE_MPE] = "mpe",
819 [TEGRA_POWERGATE_HEG] = "heg",
820 [TEGRA_POWERGATE_CPU1] = "cpu1",
821 [TEGRA_POWERGATE_CPU2] = "cpu2",
822 [TEGRA_POWERGATE_CPU3] = "cpu3",
823 [TEGRA_POWERGATE_CELP] = "celp",
824 [TEGRA_POWERGATE_CPU0] = "cpu0",
825 [TEGRA_POWERGATE_C0NC] = "c0nc",
826 [TEGRA_POWERGATE_C1NC] = "c1nc",
827 [TEGRA_POWERGATE_DIS] = "dis",
828 [TEGRA_POWERGATE_DISB] = "disb",
829 [TEGRA_POWERGATE_XUSBA] = "xusba",
830 [TEGRA_POWERGATE_XUSBB] = "xusbb",
831 [TEGRA_POWERGATE_XUSBC] = "xusbc",
832};
833
834static const u8 tegra114_cpu_powergates[] = {
835 TEGRA_POWERGATE_CPU0,
836 TEGRA_POWERGATE_CPU1,
837 TEGRA_POWERGATE_CPU2,
838 TEGRA_POWERGATE_CPU3,
839};
840
841static const struct tegra_pmc_soc tegra114_pmc_soc = {
842 .num_powergates = ARRAY_SIZE(tegra114_powergates),
843 .powergates = tegra114_powergates,
844 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
845 .cpu_powergates = tegra114_cpu_powergates,
a9a40a4a 846 .has_gpu_clamps = false,
7232398a
TR		 847};
848
849static const char * const tegra124_powergates[] = {
850 [TEGRA_POWERGATE_CPU] = "crail",
851 [TEGRA_POWERGATE_3D] = "3d",
852 [TEGRA_POWERGATE_VENC] = "venc",
853 [TEGRA_POWERGATE_PCIE] = "pcie",
854 [TEGRA_POWERGATE_VDEC] = "vdec",
855 [TEGRA_POWERGATE_L2] = "l2",
856 [TEGRA_POWERGATE_MPE] = "mpe",
857 [TEGRA_POWERGATE_HEG] = "heg",
858 [TEGRA_POWERGATE_SATA] = "sata",
859 [TEGRA_POWERGATE_CPU1] = "cpu1",
860 [TEGRA_POWERGATE_CPU2] = "cpu2",
861 [TEGRA_POWERGATE_CPU3] = "cpu3",
862 [TEGRA_POWERGATE_CELP] = "celp",
863 [TEGRA_POWERGATE_CPU0] = "cpu0",
864 [TEGRA_POWERGATE_C0NC] = "c0nc",
865 [TEGRA_POWERGATE_C1NC] = "c1nc",
866 [TEGRA_POWERGATE_SOR] = "sor",
867 [TEGRA_POWERGATE_DIS] = "dis",
868 [TEGRA_POWERGATE_DISB] = "disb",
869 [TEGRA_POWERGATE_XUSBA] = "xusba",
870 [TEGRA_POWERGATE_XUSBB] = "xusbb",
871 [TEGRA_POWERGATE_XUSBC] = "xusbc",
872 [TEGRA_POWERGATE_VIC] = "vic",
873 [TEGRA_POWERGATE_IRAM] = "iram",
874};
875
876static const u8 tegra124_cpu_powergates[] = {
877 TEGRA_POWERGATE_CPU0,
878 TEGRA_POWERGATE_CPU1,
879 TEGRA_POWERGATE_CPU2,
880 TEGRA_POWERGATE_CPU3,
881};
882
883static const struct tegra_pmc_soc tegra124_pmc_soc = {
884 .num_powergates = ARRAY_SIZE(tegra124_powergates),
885 .powergates = tegra124_powergates,
886 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
887 .cpu_powergates = tegra124_cpu_powergates,
a9a40a4a 888 .has_gpu_clamps = true,
7232398a
TR		 889};
890
891static const struct of_device_id tegra_pmc_match[] = {
892 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
893 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
894 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
895 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
896 { }
897};
898
899static struct platform_driver tegra_pmc_driver = {
900 .driver = {
901 .name = "tegra-pmc",
902 .suppress_bind_attrs = true,
903 .of_match_table = tegra_pmc_match,
2b20b616 904#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
7232398a 905 .pm = &tegra_pmc_pm_ops,
2b20b616 906#endif
7232398a
TR		 907 },
908 .probe = tegra_pmc_probe,
909};
910module_platform_driver(tegra_pmc_driver);
911
912/*
913 * Early initialization to allow access to registers in the very early boot
914 * process.
915 */
916static int __init tegra_pmc_early_init(void)
917{
918 const struct of_device_id *match;
919 struct device_node *np;
920 struct resource regs;
921 bool invert;
922 u32 value;
923
924 if (!soc_is_tegra())
925 return 0;
926
927 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
928 if (!np) {
929 pr_warn("PMC device node not found, disabling powergating\n");
930
931 regs.start = 0x7000e400;
932 regs.end = 0x7000e7ff;
933 regs.flags = IORESOURCE_MEM;
934
935 pr_warn("Using memory region %pR\n", &regs);
936 } else {
937 pmc->soc = match->data;
938 }
939
940 if (of_address_to_resource(np, 0, &regs) < 0) {
941 pr_err("failed to get PMC registers\n");
942 return -ENXIO;
943 }
944
945 pmc->base = ioremap_nocache(regs.start, resource_size(&regs));
946 if (!pmc->base) {
947 pr_err("failed to map PMC registers\n");
948 return -ENXIO;
949 }
950
951 mutex_init(&pmc->powergates_lock);
952
953 invert = of_property_read_bool(np, "nvidia,invert-interrupt");
954
955 value = tegra_pmc_readl(PMC_CNTRL);
956
957 if (invert)
958 value |= PMC_CNTRL_INTR_POLARITY;
959 else
960 value &= ~PMC_CNTRL_INTR_POLARITY;
961
962 tegra_pmc_writel(value, PMC_CNTRL);
963
964 return 0;
965}
966early_initcall(tegra_pmc_early_init);
Linux 6.x block layer and io_uring tree(s)