[linux-2.6-block.git] / drivers / soc / tegra / fuse / speedo-tegra20.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2012-2014, NVIDIA CORPORATION.  All rights reserved.
 */

#include <linux/bug.h>
#include <linux/device.h>
#include <linux/kernel.h>

#include <soc/tegra/fuse.h>

#include "fuse.h"

#define CPU_SPEEDO_LSBIT		20
#define CPU_SPEEDO_MSBIT		29
#define CPU_SPEEDO_REDUND_LSBIT		30
#define CPU_SPEEDO_REDUND_MSBIT		39
#define CPU_SPEEDO_REDUND_OFFS	(CPU_SPEEDO_REDUND_MSBIT - CPU_SPEEDO_MSBIT)

#define SOC_SPEEDO_LSBIT		40
#define SOC_SPEEDO_MSBIT		47
#define SOC_SPEEDO_REDUND_LSBIT		48
#define SOC_SPEEDO_REDUND_MSBIT		55
#define SOC_SPEEDO_REDUND_OFFS	(SOC_SPEEDO_REDUND_MSBIT - SOC_SPEEDO_MSBIT)

#define SPEEDO_MULT			4

#define PROCESS_CORNERS_NUM		4

#define SPEEDO_ID_SELECT_0(rev)		((rev) <= 2)
#define SPEEDO_ID_SELECT_1(sku)		\
	(((sku) != 20) && ((sku) != 23) && ((sku) != 24) && \
	 ((sku) != 27) && ((sku) != 28))

enum {
	SPEEDO_ID_0,
	SPEEDO_ID_1,
	SPEEDO_ID_2,
	SPEEDO_ID_COUNT,
};

static const u32 __initconst cpu_process_speedos[][PROCESS_CORNERS_NUM] = {
	{315, 366, 420, UINT_MAX},
	{303, 368, 419, UINT_MAX},
	{316, 331, 383, UINT_MAX},
};

static const u32 __initconst soc_process_speedos[][PROCESS_CORNERS_NUM] = {
	{165, 195, 224, UINT_MAX},
	{165, 195, 224, UINT_MAX},
	{165, 195, 224, UINT_MAX},
};

void __init tegra20_init_speedo_data(struct tegra_sku_info *sku_info)
{
	u32 reg;
	u32 val;
	int i;

	BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) != SPEEDO_ID_COUNT);
	BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) != SPEEDO_ID_COUNT);

	if (SPEEDO_ID_SELECT_0(sku_info->revision))
		sku_info->soc_speedo_id = SPEEDO_ID_0;
	else if (SPEEDO_ID_SELECT_1(sku_info->sku_id))
		sku_info->soc_speedo_id = SPEEDO_ID_1;
	else
		sku_info->soc_speedo_id = SPEEDO_ID_2;

	val = 0;
	for (i = CPU_SPEEDO_MSBIT; i >= CPU_SPEEDO_LSBIT; i--) {
		reg = tegra_fuse_read_spare(i) |
			tegra_fuse_read_spare(i + CPU_SPEEDO_REDUND_OFFS);
		val = (val << 1) | (reg & 0x1);
	}
	val = val * SPEEDO_MULT;
	pr_debug("Tegra CPU speedo value %u\n", val);

	for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
		if (val <= cpu_process_speedos[sku_info->soc_speedo_id][i])
			break;
	}
	sku_info->cpu_process_id = i;

	val = 0;
	for (i = SOC_SPEEDO_MSBIT; i >= SOC_SPEEDO_LSBIT; i--) {
		reg = tegra_fuse_read_spare(i) |
			tegra_fuse_read_spare(i + SOC_SPEEDO_REDUND_OFFS);
		val = (val << 1) | (reg & 0x1);
	}
	val = val * SPEEDO_MULT;
	pr_debug("Core speedo value %u\n", val);

	for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
		if (val <= soc_process_speedos[sku_info->soc_speedo_id][i])
			break;
	}
	sku_info->soc_process_id = i;
}
Commit	Line	Data
9952f691	1	// SPDX-License-Identifier: GPL-2.0-only
25cd5a39	2	/*
783c8f4c	3	* Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved.
25cd5a39 DH	4	*/
25cd5a39 DH	5
25cd5a39	6	#include <linux/bug.h>
783c8f4c	7	#include <linux/device.h>
a0524acc	8	#include <linux/kernel.h>
25cd5a39	9
35874f36 PDS	10	#include <soc/tegra/fuse.h>
35874f36 PDS	11
25cd5a39 DH	12	#include "fuse.h"
	13
	14	#define CPU_SPEEDO_LSBIT 20
	15	#define CPU_SPEEDO_MSBIT 29
	16	#define CPU_SPEEDO_REDUND_LSBIT 30
	17	#define CPU_SPEEDO_REDUND_MSBIT 39
	18	#define CPU_SPEEDO_REDUND_OFFS (CPU_SPEEDO_REDUND_MSBIT - CPU_SPEEDO_MSBIT)
	19
03b3f4c8 TR	20	#define SOC_SPEEDO_LSBIT 40
	21	#define SOC_SPEEDO_MSBIT 47
	22	#define SOC_SPEEDO_REDUND_LSBIT 48
	23	#define SOC_SPEEDO_REDUND_MSBIT 55
	24	#define SOC_SPEEDO_REDUND_OFFS (SOC_SPEEDO_REDUND_MSBIT - SOC_SPEEDO_MSBIT)
25cd5a39 DH	25
	26	#define SPEEDO_MULT 4
	27
	28	#define PROCESS_CORNERS_NUM 4
	29
	30	#define SPEEDO_ID_SELECT_0(rev) ((rev) <= 2)
	31	#define SPEEDO_ID_SELECT_1(sku) \
	32	(((sku) != 20) && ((sku) != 23) && ((sku) != 24) && \
	33	((sku) != 27) && ((sku) != 28))
	34
	35	enum {
	36	SPEEDO_ID_0,
	37	SPEEDO_ID_1,
	38	SPEEDO_ID_2,
	39	SPEEDO_ID_COUNT,
	40	};
	41
783c8f4c	42	static const u32 __initconst cpu_process_speedos[][PROCESS_CORNERS_NUM] = {
25cd5a39 DH	43	{315, 366, 420, UINT_MAX},
	44	{303, 368, 419, UINT_MAX},
	45	{316, 331, 383, UINT_MAX},
	46	};
	47
03b3f4c8	48	static const u32 __initconst soc_process_speedos[][PROCESS_CORNERS_NUM] = {
25cd5a39 DH	49	{165, 195, 224, UINT_MAX},
	50	{165, 195, 224, UINT_MAX},
	51	{165, 195, 224, UINT_MAX},
	52	};
	53
783c8f4c	54	void __init tegra20_init_speedo_data(struct tegra_sku_info *sku_info)
25cd5a39 DH	55	{
	56	u32 reg;
	57	u32 val;
	58	int i;
	59
	60	BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) != SPEEDO_ID_COUNT);
03b3f4c8	61	BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) != SPEEDO_ID_COUNT);
25cd5a39	62
783c8f4c PDS	63	if (SPEEDO_ID_SELECT_0(sku_info->revision))
	64	sku_info->soc_speedo_id = SPEEDO_ID_0;
	65	else if (SPEEDO_ID_SELECT_1(sku_info->sku_id))
	66	sku_info->soc_speedo_id = SPEEDO_ID_1;
25cd5a39	67	else
783c8f4c	68	sku_info->soc_speedo_id = SPEEDO_ID_2;
25cd5a39 DH	69
	70	val = 0;
	71	for (i = CPU_SPEEDO_MSBIT; i >= CPU_SPEEDO_LSBIT; i--) {
7e939de1 TR	72	reg = tegra_fuse_read_spare(i) \|
7e939de1 TR	73	tegra_fuse_read_spare(i + CPU_SPEEDO_REDUND_OFFS);
25cd5a39 DH	74	val = (val << 1) \| (reg & 0x1);
	75	}
	76	val = val * SPEEDO_MULT;
783c8f4c	77	pr_debug("Tegra CPU speedo value %u\n", val);
25cd5a39 DH	78
25cd5a39 DH	79	for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
783c8f4c	80	if (val <= cpu_process_speedos[sku_info->soc_speedo_id][i])
25cd5a39 DH	81	break;
25cd5a39 DH	82	}
783c8f4c	83	sku_info->cpu_process_id = i;
25cd5a39 DH	84
25cd5a39 DH	85	val = 0;
03b3f4c8	86	for (i = SOC_SPEEDO_MSBIT; i >= SOC_SPEEDO_LSBIT; i--) {
7e939de1	87	reg = tegra_fuse_read_spare(i) \|
03b3f4c8	88	tegra_fuse_read_spare(i + SOC_SPEEDO_REDUND_OFFS);
25cd5a39 DH	89	val = (val << 1) \| (reg & 0x1);
	90	}
	91	val = val * SPEEDO_MULT;
783c8f4c	92	pr_debug("Core speedo value %u\n", val);
25cd5a39 DH	93
25cd5a39 DH	94	for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
03b3f4c8	95	if (val <= soc_process_speedos[sku_info->soc_speedo_id][i])
25cd5a39 DH	96	break;
25cd5a39 DH	97	}
03b3f4c8	98	sku_info->soc_process_id = i;
25cd5a39	99	}