[linux-2.6-block.git] / drivers / soc / tegra / fuse / speedo-tegra20.c

/*
 * Copyright (c) 2012-2014, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/bug.h>
#include <linux/device.h>
#include <linux/kernel.h>

#include <soc/tegra/fuse.h>

#include "fuse.h"

#define CPU_SPEEDO_LSBIT		20
#define CPU_SPEEDO_MSBIT		29
#define CPU_SPEEDO_REDUND_LSBIT		30
#define CPU_SPEEDO_REDUND_MSBIT		39
#define CPU_SPEEDO_REDUND_OFFS	(CPU_SPEEDO_REDUND_MSBIT - CPU_SPEEDO_MSBIT)

#define SOC_SPEEDO_LSBIT		40
#define SOC_SPEEDO_MSBIT		47
#define SOC_SPEEDO_REDUND_LSBIT		48
#define SOC_SPEEDO_REDUND_MSBIT		55
#define SOC_SPEEDO_REDUND_OFFS	(SOC_SPEEDO_REDUND_MSBIT - SOC_SPEEDO_MSBIT)

#define SPEEDO_MULT			4

#define PROCESS_CORNERS_NUM		4

#define SPEEDO_ID_SELECT_0(rev)		((rev) <= 2)
#define SPEEDO_ID_SELECT_1(sku)		\
	(((sku) != 20) && ((sku) != 23) && ((sku) != 24) && \
	 ((sku) != 27) && ((sku) != 28))

enum {
	SPEEDO_ID_0,
	SPEEDO_ID_1,
	SPEEDO_ID_2,
	SPEEDO_ID_COUNT,
};

static const u32 __initconst cpu_process_speedos[][PROCESS_CORNERS_NUM] = {
	{315, 366, 420, UINT_MAX},
	{303, 368, 419, UINT_MAX},
	{316, 331, 383, UINT_MAX},
};

static const u32 __initconst soc_process_speedos[][PROCESS_CORNERS_NUM] = {
	{165, 195, 224, UINT_MAX},
	{165, 195, 224, UINT_MAX},
	{165, 195, 224, UINT_MAX},
};

void __init tegra20_init_speedo_data(struct tegra_sku_info *sku_info)
{
	u32 reg;
	u32 val;
	int i;

	BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) != SPEEDO_ID_COUNT);
	BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) != SPEEDO_ID_COUNT);

	if (SPEEDO_ID_SELECT_0(sku_info->revision))
		sku_info->soc_speedo_id = SPEEDO_ID_0;
	else if (SPEEDO_ID_SELECT_1(sku_info->sku_id))
		sku_info->soc_speedo_id = SPEEDO_ID_1;
	else
		sku_info->soc_speedo_id = SPEEDO_ID_2;

	val = 0;
	for (i = CPU_SPEEDO_MSBIT; i >= CPU_SPEEDO_LSBIT; i--) {
		reg = tegra_fuse_read_spare(i) |
			tegra_fuse_read_spare(i + CPU_SPEEDO_REDUND_OFFS);
		val = (val << 1) | (reg & 0x1);
	}
	val = val * SPEEDO_MULT;
	pr_debug("Tegra CPU speedo value %u\n", val);

	for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
		if (val <= cpu_process_speedos[sku_info->soc_speedo_id][i])
			break;
	}
	sku_info->cpu_process_id = i;

	val = 0;
	for (i = SOC_SPEEDO_MSBIT; i >= SOC_SPEEDO_LSBIT; i--) {
		reg = tegra_fuse_read_spare(i) |
			tegra_fuse_read_spare(i + SOC_SPEEDO_REDUND_OFFS);
		val = (val << 1) | (reg & 0x1);
	}
	val = val * SPEEDO_MULT;
	pr_debug("Core speedo value %u\n", val);

	for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
		if (val <= soc_process_speedos[sku_info->soc_speedo_id][i])
			break;
	}
	sku_info->soc_process_id = i;
}
Commit	Line	Data
25cd5a39	1	/*
783c8f4c	2	* Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved.
25cd5a39 DH	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16
25cd5a39	17	#include <linux/bug.h>
783c8f4c	18	#include <linux/device.h>
a0524acc	19	#include <linux/kernel.h>
25cd5a39	20
35874f36 PDS	21	#include <soc/tegra/fuse.h>
35874f36 PDS	22
25cd5a39 DH	23	#include "fuse.h"
	24
	25	#define CPU_SPEEDO_LSBIT 20
	26	#define CPU_SPEEDO_MSBIT 29
	27	#define CPU_SPEEDO_REDUND_LSBIT 30
	28	#define CPU_SPEEDO_REDUND_MSBIT 39
	29	#define CPU_SPEEDO_REDUND_OFFS (CPU_SPEEDO_REDUND_MSBIT - CPU_SPEEDO_MSBIT)
	30
03b3f4c8 TR	31	#define SOC_SPEEDO_LSBIT 40
	32	#define SOC_SPEEDO_MSBIT 47
	33	#define SOC_SPEEDO_REDUND_LSBIT 48
	34	#define SOC_SPEEDO_REDUND_MSBIT 55
	35	#define SOC_SPEEDO_REDUND_OFFS (SOC_SPEEDO_REDUND_MSBIT - SOC_SPEEDO_MSBIT)
25cd5a39 DH	36
	37	#define SPEEDO_MULT 4
	38
	39	#define PROCESS_CORNERS_NUM 4
	40
	41	#define SPEEDO_ID_SELECT_0(rev) ((rev) <= 2)
	42	#define SPEEDO_ID_SELECT_1(sku) \
	43	(((sku) != 20) && ((sku) != 23) && ((sku) != 24) && \
	44	((sku) != 27) && ((sku) != 28))
	45
	46	enum {
	47	SPEEDO_ID_0,
	48	SPEEDO_ID_1,
	49	SPEEDO_ID_2,
	50	SPEEDO_ID_COUNT,
	51	};
	52
783c8f4c	53	static const u32 __initconst cpu_process_speedos[][PROCESS_CORNERS_NUM] = {
25cd5a39 DH	54	{315, 366, 420, UINT_MAX},
	55	{303, 368, 419, UINT_MAX},
	56	{316, 331, 383, UINT_MAX},
	57	};
	58
03b3f4c8	59	static const u32 __initconst soc_process_speedos[][PROCESS_CORNERS_NUM] = {
25cd5a39 DH	60	{165, 195, 224, UINT_MAX},
	61	{165, 195, 224, UINT_MAX},
	62	{165, 195, 224, UINT_MAX},
	63	};
	64
783c8f4c	65	void __init tegra20_init_speedo_data(struct tegra_sku_info *sku_info)
25cd5a39 DH	66	{
	67	u32 reg;
	68	u32 val;
	69	int i;
	70
	71	BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) != SPEEDO_ID_COUNT);
03b3f4c8	72	BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) != SPEEDO_ID_COUNT);
25cd5a39	73
783c8f4c PDS	74	if (SPEEDO_ID_SELECT_0(sku_info->revision))
	75	sku_info->soc_speedo_id = SPEEDO_ID_0;
	76	else if (SPEEDO_ID_SELECT_1(sku_info->sku_id))
	77	sku_info->soc_speedo_id = SPEEDO_ID_1;
25cd5a39	78	else
783c8f4c	79	sku_info->soc_speedo_id = SPEEDO_ID_2;
25cd5a39 DH	80
	81	val = 0;
	82	for (i = CPU_SPEEDO_MSBIT; i >= CPU_SPEEDO_LSBIT; i--) {
7e939de1 TR	83	reg = tegra_fuse_read_spare(i) \|
7e939de1 TR	84	tegra_fuse_read_spare(i + CPU_SPEEDO_REDUND_OFFS);
25cd5a39 DH	85	val = (val << 1) \| (reg & 0x1);
	86	}
	87	val = val * SPEEDO_MULT;
783c8f4c	88	pr_debug("Tegra CPU speedo value %u\n", val);
25cd5a39 DH	89
25cd5a39 DH	90	for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
783c8f4c	91	if (val <= cpu_process_speedos[sku_info->soc_speedo_id][i])
25cd5a39 DH	92	break;
25cd5a39 DH	93	}
783c8f4c	94	sku_info->cpu_process_id = i;
25cd5a39 DH	95
25cd5a39 DH	96	val = 0;
03b3f4c8	97	for (i = SOC_SPEEDO_MSBIT; i >= SOC_SPEEDO_LSBIT; i--) {
7e939de1	98	reg = tegra_fuse_read_spare(i) \|
03b3f4c8	99	tegra_fuse_read_spare(i + SOC_SPEEDO_REDUND_OFFS);
25cd5a39 DH	100	val = (val << 1) \| (reg & 0x1);
	101	}
	102	val = val * SPEEDO_MULT;
783c8f4c	103	pr_debug("Core speedo value %u\n", val);
25cd5a39 DH	104
25cd5a39 DH	105	for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
03b3f4c8	106	if (val <= soc_process_speedos[sku_info->soc_speedo_id][i])
25cd5a39 DH	107	break;
25cd5a39 DH	108	}
03b3f4c8	109	sku_info->soc_process_id = i;
25cd5a39	110	}