Commit | Line | Data |
---|---|---|
099a6644 TR |
1 | if ARCH_TEGRA |
2 | ||
3 | # 32-bit ARM SoCs | |
4 | if ARM | |
5 | ||
6 | config ARCH_TEGRA_2x_SOC | |
7 | bool "Enable support for Tegra20 family" | |
8 | select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP | |
9 | select ARM_ERRATA_720789 | |
10 | select ARM_ERRATA_754327 if SMP | |
11 | select ARM_ERRATA_764369 if SMP | |
12 | select PINCTRL_TEGRA20 | |
13 | select PL310_ERRATA_727915 if CACHE_L2X0 | |
14 | select PL310_ERRATA_769419 if CACHE_L2X0 | |
15 | select TEGRA_TIMER | |
16 | help | |
17 | Support for NVIDIA Tegra AP20 and T20 processors, based on the | |
18 | ARM CortexA9MP CPU and the ARM PL310 L2 cache controller | |
19 | ||
20 | config ARCH_TEGRA_3x_SOC | |
21 | bool "Enable support for Tegra30 family" | |
22 | select ARM_ERRATA_754322 | |
23 | select ARM_ERRATA_764369 if SMP | |
24 | select PINCTRL_TEGRA30 | |
25 | select PL310_ERRATA_769419 if CACHE_L2X0 | |
26 | select TEGRA_TIMER | |
27 | help | |
28 | Support for NVIDIA Tegra T30 processor family, based on the | |
29 | ARM CortexA9MP CPU and the ARM PL310 L2 cache controller | |
30 | ||
31 | config ARCH_TEGRA_114_SOC | |
32 | bool "Enable support for Tegra114 family" | |
33 | select ARM_ERRATA_798181 if SMP | |
34 | select ARM_L1_CACHE_SHIFT_6 | |
35 | select HAVE_ARM_ARCH_TIMER | |
36 | select PINCTRL_TEGRA114 | |
37 | select TEGRA_TIMER | |
38 | help | |
39 | Support for NVIDIA Tegra T114 processor family, based on the | |
40 | ARM CortexA15MP CPU | |
41 | ||
42 | config ARCH_TEGRA_124_SOC | |
43 | bool "Enable support for Tegra124 family" | |
44 | select ARM_L1_CACHE_SHIFT_6 | |
45 | select HAVE_ARM_ARCH_TIMER | |
46 | select PINCTRL_TEGRA124 | |
47 | select TEGRA_TIMER | |
48 | help | |
49 | Support for NVIDIA Tegra T124 processor family, based on the | |
50 | ARM CortexA15MP CPU | |
51 | ||
52 | endif | |
53 | ||
54 | # 64-bit ARM SoCs | |
55 | if ARM64 | |
56 | ||
57 | config ARCH_TEGRA_132_SOC | |
58 | bool "NVIDIA Tegra132 SoC" | |
59 | select PINCTRL_TEGRA124 | |
099a6644 TR |
60 | help |
61 | Enable support for NVIDIA Tegra132 SoC, based on the Denver | |
62 | ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC, | |
63 | but contains an NVIDIA Denver CPU complex in place of | |
64 | Tegra124's "4+1" Cortex-A15 CPU complex. | |
65 | ||
95445952 TR |
66 | config ARCH_TEGRA_210_SOC |
67 | bool "NVIDIA Tegra210 SoC" | |
68 | select PINCTRL_TEGRA210 | |
95445952 TR |
69 | help |
70 | Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1, | |
71 | the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 | |
72 | cores in a switched configuration. It features a GPU of the Maxwell | |
73 | architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 | |
74 | and providing 256 CUDA cores. It supports hardware-accelerated en- | |
75 | and decoding of various video standards including H.265, H.264 and | |
76 | VP8 at 4K resolution and up to 60 fps. | |
77 | ||
78 | Besides the multimedia features it also comes with a variety of I/O | |
79 | controllers, such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to | |
80 | name only a few. | |
81 | ||
099a6644 TR |
82 | endif |
83 | endif |