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1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Renesas RZ/G2M System Controller | |
4 | * Copyright (C) 2018 Renesas Electronics Corp. | |
5 | * | |
6 | * Based on Renesas R-Car M3-W System Controller | |
7 | * Copyright (C) 2016 Glider bvba | |
8 | */ | |
9 | ||
10 | #include <linux/bug.h> | |
11 | #include <linux/kernel.h> | |
12 | ||
13 | #include <dt-bindings/power/r8a774a1-sysc.h> | |
14 | ||
15 | #include "rcar-sysc.h" | |
16 | ||
17 | static const struct rcar_sysc_area r8a774a1_areas[] __initconst = { | |
18 | { "always-on", 0, 0, R8A774A1_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, | |
19 | { "ca57-scu", 0x1c0, 0, R8A774A1_PD_CA57_SCU, R8A774A1_PD_ALWAYS_ON, | |
20 | PD_SCU }, | |
21 | { "ca57-cpu0", 0x80, 0, R8A774A1_PD_CA57_CPU0, R8A774A1_PD_CA57_SCU, | |
22 | PD_CPU_NOCR }, | |
23 | { "ca57-cpu1", 0x80, 1, R8A774A1_PD_CA57_CPU1, R8A774A1_PD_CA57_SCU, | |
24 | PD_CPU_NOCR }, | |
25 | { "ca53-scu", 0x140, 0, R8A774A1_PD_CA53_SCU, R8A774A1_PD_ALWAYS_ON, | |
26 | PD_SCU }, | |
27 | { "ca53-cpu0", 0x200, 0, R8A774A1_PD_CA53_CPU0, R8A774A1_PD_CA53_SCU, | |
28 | PD_CPU_NOCR }, | |
29 | { "ca53-cpu1", 0x200, 1, R8A774A1_PD_CA53_CPU1, R8A774A1_PD_CA53_SCU, | |
30 | PD_CPU_NOCR }, | |
31 | { "ca53-cpu2", 0x200, 2, R8A774A1_PD_CA53_CPU2, R8A774A1_PD_CA53_SCU, | |
32 | PD_CPU_NOCR }, | |
33 | { "ca53-cpu3", 0x200, 3, R8A774A1_PD_CA53_CPU3, R8A774A1_PD_CA53_SCU, | |
34 | PD_CPU_NOCR }, | |
35 | { "a3vc", 0x380, 0, R8A774A1_PD_A3VC, R8A774A1_PD_ALWAYS_ON }, | |
36 | { "a2vc0", 0x3c0, 0, R8A774A1_PD_A2VC0, R8A774A1_PD_A3VC }, | |
37 | { "a2vc1", 0x3c0, 1, R8A774A1_PD_A2VC1, R8A774A1_PD_A3VC }, | |
38 | { "3dg-a", 0x100, 0, R8A774A1_PD_3DG_A, R8A774A1_PD_ALWAYS_ON }, | |
39 | { "3dg-b", 0x100, 1, R8A774A1_PD_3DG_B, R8A774A1_PD_3DG_A }, | |
40 | }; | |
41 | ||
42 | const struct rcar_sysc_info r8a774a1_sysc_info __initconst = { | |
43 | .areas = r8a774a1_areas, | |
44 | .num_areas = ARRAY_SIZE(r8a774a1_areas), | |
45 | }; |