[linux-2.6-block.git] / drivers / soc / qcom / qcom_gsbi.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2014, The Linux foundation. All rights reserved.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <dt-bindings/soc/qcom,gsbi.h>

#define GSBI_CTRL_REG		0x0000
#define GSBI_PROTOCOL_SHIFT	4
#define MAX_GSBI		12

#define TCSR_ADM_CRCI_BASE	0x70

struct crci_config {
	u32 num_rows;
	const u32 (*array)[MAX_GSBI];
};

static const u32 crci_ipq8064[][MAX_GSBI] = {
	{
		0x000003, 0x00000c, 0x000030, 0x0000c0,
		0x000300, 0x000c00, 0x003000, 0x00c000,
		0x030000, 0x0c0000, 0x300000, 0xc00000
	},
	{
		0x000003, 0x00000c, 0x000030, 0x0000c0,
		0x000300, 0x000c00, 0x003000, 0x00c000,
		0x030000, 0x0c0000, 0x300000, 0xc00000
	},
};

static const struct crci_config config_ipq8064 = {
	.num_rows = ARRAY_SIZE(crci_ipq8064),
	.array = crci_ipq8064,
};

static const unsigned int crci_apq8064[][MAX_GSBI] = {
	{
		0x001800, 0x006000, 0x000030, 0x0000c0,
		0x000300, 0x000400, 0x000000, 0x000000,
		0x000000, 0x000000, 0x000000, 0x000000
	},
	{
		0x000000, 0x000000, 0x000000, 0x000000,
		0x000000, 0x000020, 0x0000c0, 0x000000,
		0x000000, 0x000000, 0x000000, 0x000000
	},
};

static const struct crci_config config_apq8064 = {
	.num_rows = ARRAY_SIZE(crci_apq8064),
	.array = crci_apq8064,
};

static const unsigned int crci_msm8960[][MAX_GSBI] = {
	{
		0x000003, 0x00000c, 0x000030, 0x0000c0,
		0x000300, 0x000400, 0x000000, 0x000000,
		0x000000, 0x000000, 0x000000, 0x000000
	},
	{
		0x000000, 0x000000, 0x000000, 0x000000,
		0x000000, 0x000020, 0x0000c0, 0x000300,
		0x001800, 0x006000, 0x000000, 0x000000
	},
};

static const struct crci_config config_msm8960 = {
	.num_rows = ARRAY_SIZE(crci_msm8960),
	.array = crci_msm8960,
};

static const unsigned int crci_msm8660[][MAX_GSBI] = {
	{	/* ADM 0 - B */
		0x000003, 0x00000c, 0x000030, 0x0000c0,
		0x000300, 0x000c00, 0x003000, 0x00c000,
		0x030000, 0x0c0000, 0x300000, 0xc00000
	},
	{	/* ADM 0 - B */
		0x000003, 0x00000c, 0x000030, 0x0000c0,
		0x000300, 0x000c00, 0x003000, 0x00c000,
		0x030000, 0x0c0000, 0x300000, 0xc00000
	},
	{	/* ADM 1 - A */
		0x000003, 0x00000c, 0x000030, 0x0000c0,
		0x000300, 0x000c00, 0x003000, 0x00c000,
		0x030000, 0x0c0000, 0x300000, 0xc00000
	},
	{	/* ADM 1 - B */
		0x000003, 0x00000c, 0x000030, 0x0000c0,
		0x000300, 0x000c00, 0x003000, 0x00c000,
		0x030000, 0x0c0000, 0x300000, 0xc00000
	},
};

static const struct crci_config config_msm8660 = {
	.num_rows = ARRAY_SIZE(crci_msm8660),
	.array = crci_msm8660,
};

struct gsbi_info {
	struct clk *hclk;
	u32 mode;
	u32 crci;
	struct regmap *tcsr;
};

static const struct of_device_id tcsr_dt_match[] = {
	{ .compatible = "qcom,tcsr-ipq8064", .data = &config_ipq8064},
	{ .compatible = "qcom,tcsr-apq8064", .data = &config_apq8064},
	{ .compatible = "qcom,tcsr-msm8960", .data = &config_msm8960},
	{ .compatible = "qcom,tcsr-msm8660", .data = &config_msm8660},
	{ },
};

static int gsbi_probe(struct platform_device *pdev)
{
	struct device_node *node = pdev->dev.of_node;
	struct device_node *tcsr_node;
	const struct of_device_id *match;
	struct resource *res;
	void __iomem *base;
	struct gsbi_info *gsbi;
	int i, ret;
	u32 mask, gsbi_num;
	const struct crci_config *config = NULL;

	gsbi = devm_kzalloc(&pdev->dev, sizeof(*gsbi), GFP_KERNEL);

	if (!gsbi)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(base))
		return PTR_ERR(base);

	/* get the tcsr node and setup the config and regmap */
	gsbi->tcsr = syscon_regmap_lookup_by_phandle(node, "syscon-tcsr");

	if (!IS_ERR(gsbi->tcsr)) {
		tcsr_node = of_parse_phandle(node, "syscon-tcsr", 0);
		if (tcsr_node) {
			match = of_match_node(tcsr_dt_match, tcsr_node);
			if (match)
				config = match->data;
			else
				dev_warn(&pdev->dev, "no matching TCSR\n");

			of_node_put(tcsr_node);
		}
	}

	if (of_property_read_u32(node, "cell-index", &gsbi_num)) {
		dev_err(&pdev->dev, "missing cell-index\n");
		return -EINVAL;
	}

	if (gsbi_num < 1 || gsbi_num > MAX_GSBI) {
		dev_err(&pdev->dev, "invalid cell-index\n");
		return -EINVAL;
	}

	if (of_property_read_u32(node, "qcom,mode", &gsbi->mode)) {
		dev_err(&pdev->dev, "missing mode configuration\n");
		return -EINVAL;
	}

	/* not required, so default to 0 if not present */
	of_property_read_u32(node, "qcom,crci", &gsbi->crci);

	dev_info(&pdev->dev, "GSBI port protocol: %d crci: %d\n",
		 gsbi->mode, gsbi->crci);
	gsbi->hclk = devm_clk_get(&pdev->dev, "iface");
	if (IS_ERR(gsbi->hclk))
		return PTR_ERR(gsbi->hclk);

	clk_prepare_enable(gsbi->hclk);

	writel_relaxed((gsbi->mode << GSBI_PROTOCOL_SHIFT) | gsbi->crci,
				base + GSBI_CTRL_REG);

	/*
	 * modify tcsr to reflect mode and ADM CRCI mux
	 * Each gsbi contains a pair of bits, one for RX and one for TX
	 * SPI mode requires both bits cleared, otherwise they are set
	 */
	if (config) {
		for (i = 0; i < config->num_rows; i++) {
			mask = config->array[i][gsbi_num - 1];

			if (gsbi->mode == GSBI_PROT_SPI)
				regmap_update_bits(gsbi->tcsr,
					TCSR_ADM_CRCI_BASE + 4 * i, mask, 0);
			else
				regmap_update_bits(gsbi->tcsr,
					TCSR_ADM_CRCI_BASE + 4 * i, mask, mask);

		}
	}

	/* make sure the gsbi control write is not reordered */
	wmb();

	platform_set_drvdata(pdev, gsbi);

	ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
	if (ret)
		clk_disable_unprepare(gsbi->hclk);
	return ret;
}

static int gsbi_remove(struct platform_device *pdev)
{
	struct gsbi_info *gsbi = platform_get_drvdata(pdev);

	clk_disable_unprepare(gsbi->hclk);

	return 0;
}

static const struct of_device_id gsbi_dt_match[] = {
	{ .compatible = "qcom,gsbi-v1.0.0", },
	{ },
};

MODULE_DEVICE_TABLE(of, gsbi_dt_match);

static struct platform_driver gsbi_driver = {
	.driver = {
		.name		= "gsbi",
		.of_match_table	= gsbi_dt_match,
	},
	.probe = gsbi_probe,
	.remove	= gsbi_remove,
};

module_platform_driver(gsbi_driver);

MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
MODULE_DESCRIPTION("QCOM GSBI driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
ce718dfb	1	// SPDX-License-Identifier: GPL-2.0-only
5d144e36 AG	2	/*
5d144e36 AG	3	* Copyright (c) 2014, The Linux foundation. All rights reserved.
5d144e36 AG	4	*/
	5
	6	#include <linux/clk.h>
	7	#include <linux/err.h>
	8	#include <linux/io.h>
	9	#include <linux/module.h>
	10	#include <linux/of.h>
	11	#include <linux/of_platform.h>
	12	#include <linux/platform_device.h>
e5fdad68 AG	13	#include <linux/regmap.h>
	14	#include <linux/mfd/syscon.h>
	15	#include <dt-bindings/soc/qcom,gsbi.h>
5d144e36 AG	16
	17	#define GSBI_CTRL_REG 0x0000
	18	#define GSBI_PROTOCOL_SHIFT 4
e5fdad68 AG	19	#define MAX_GSBI 12
	20
	21	#define TCSR_ADM_CRCI_BASE 0x70
	22
	23	struct crci_config {
	24	u32 num_rows;
	25	const u32 (*array)[MAX_GSBI];
	26	};
	27
	28	static const u32 crci_ipq8064[][MAX_GSBI] = {
	29	{
	30	0x000003, 0x00000c, 0x000030, 0x0000c0,
	31	0x000300, 0x000c00, 0x003000, 0x00c000,
	32	0x030000, 0x0c0000, 0x300000, 0xc00000
	33	},
	34	{
	35	0x000003, 0x00000c, 0x000030, 0x0000c0,
	36	0x000300, 0x000c00, 0x003000, 0x00c000,
	37	0x030000, 0x0c0000, 0x300000, 0xc00000
	38	},
	39	};
	40
	41	static const struct crci_config config_ipq8064 = {
	42	.num_rows = ARRAY_SIZE(crci_ipq8064),
	43	.array = crci_ipq8064,
	44	};
	45
	46	static const unsigned int crci_apq8064[][MAX_GSBI] = {
	47	{
	48	0x001800, 0x006000, 0x000030, 0x0000c0,
	49	0x000300, 0x000400, 0x000000, 0x000000,
	50	0x000000, 0x000000, 0x000000, 0x000000
	51	},
	52	{
	53	0x000000, 0x000000, 0x000000, 0x000000,
	54	0x000000, 0x000020, 0x0000c0, 0x000000,
	55	0x000000, 0x000000, 0x000000, 0x000000
	56	},
	57	};
	58
	59	static const struct crci_config config_apq8064 = {
	60	.num_rows = ARRAY_SIZE(crci_apq8064),
	61	.array = crci_apq8064,
	62	};
	63
	64	static const unsigned int crci_msm8960[][MAX_GSBI] = {
	65	{
	66	0x000003, 0x00000c, 0x000030, 0x0000c0,
	67	0x000300, 0x000400, 0x000000, 0x000000,
	68	0x000000, 0x000000, 0x000000, 0x000000
	69	},
	70	{
	71	0x000000, 0x000000, 0x000000, 0x000000,
	72	0x000000, 0x000020, 0x0000c0, 0x000300,
	73	0x001800, 0x006000, 0x000000, 0x000000
	74	},
	75	};
	76
	77	static const struct crci_config config_msm8960 = {
	78	.num_rows = ARRAY_SIZE(crci_msm8960),
	79	.array = crci_msm8960,
	80	};
	81
	82	static const unsigned int crci_msm8660[][MAX_GSBI] = {
83	{ /* ADM 0 - B */
84	0x000003, 0x00000c, 0x000030, 0x0000c0,
85	0x000300, 0x000c00, 0x003000, 0x00c000,
86	0x030000, 0x0c0000, 0x300000, 0xc00000
87	},
88	{ /* ADM 0 - B */
89	0x000003, 0x00000c, 0x000030, 0x0000c0,
90	0x000300, 0x000c00, 0x003000, 0x00c000,
91	0x030000, 0x0c0000, 0x300000, 0xc00000
92	},
93	{ /* ADM 1 - A */
94	0x000003, 0x00000c, 0x000030, 0x0000c0,
95	0x000300, 0x000c00, 0x003000, 0x00c000,
96	0x030000, 0x0c0000, 0x300000, 0xc00000
97	},
98	{ /* ADM 1 - B */
99	0x000003, 0x00000c, 0x000030, 0x0000c0,
100	0x000300, 0x000c00, 0x003000, 0x00c000,
101	0x030000, 0x0c0000, 0x300000, 0xc00000
102	},
103	};
104
105	static const struct crci_config config_msm8660 = {
106	.num_rows = ARRAY_SIZE(crci_msm8660),
107	.array = crci_msm8660,
108	};
5d144e36	109
fa9eb324 SK	110	struct gsbi_info {
	111	struct clk *hclk;
	112	u32 mode;
	113	u32 crci;
e5fdad68 AG	114	struct regmap *tcsr;
	115	};
	116
	117	static const struct of_device_id tcsr_dt_match[] = {
	118	{ .compatible = "qcom,tcsr-ipq8064", .data = &config_ipq8064},
	119	{ .compatible = "qcom,tcsr-apq8064", .data = &config_apq8064},
	120	{ .compatible = "qcom,tcsr-msm8960", .data = &config_msm8960},
	121	{ .compatible = "qcom,tcsr-msm8660", .data = &config_msm8660},
	122	{ },
fa9eb324 SK	123	};
fa9eb324 SK	124
5d144e36 AG	125	static int gsbi_probe(struct platform_device *pdev)
	126	{
	127	struct device_node *node = pdev->dev.of_node;
e5fdad68 AG	128	struct device_node *tcsr_node;
e5fdad68 AG	129	const struct of_device_id *match;
5d144e36 AG	130	struct resource *res;
5d144e36 AG	131	void __iomem *base;
fa9eb324	132	struct gsbi_info *gsbi;
8cd09a3d	133	int i, ret;
e5fdad68 AG	134	u32 mask, gsbi_num;
e5fdad68 AG	135	const struct crci_config *config = NULL;
fa9eb324 SK	136
	137	gsbi = devm_kzalloc(&pdev->dev, sizeof(*gsbi), GFP_KERNEL);
	138
	139	if (!gsbi)
	140	return -ENOMEM;
5d144e36 AG	141
	142	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	143	base = devm_ioremap_resource(&pdev->dev, res);
	144	if (IS_ERR(base))
	145	return PTR_ERR(base);
	146
e5fdad68 AG	147	/* get the tcsr node and setup the config and regmap */
	148	gsbi->tcsr = syscon_regmap_lookup_by_phandle(node, "syscon-tcsr");
	149
	150	if (!IS_ERR(gsbi->tcsr)) {
	151	tcsr_node = of_parse_phandle(node, "syscon-tcsr", 0);
	152	if (tcsr_node) {
	153	match = of_match_node(tcsr_dt_match, tcsr_node);
	154	if (match)
	155	config = match->data;
	156	else
	157	dev_warn(&pdev->dev, "no matching TCSR\n");
	158
	159	of_node_put(tcsr_node);
	160	}
	161	}
	162
	163	if (of_property_read_u32(node, "cell-index", &gsbi_num)) {
	164	dev_err(&pdev->dev, "missing cell-index\n");
	165	return -EINVAL;
	166	}
	167
	168	if (gsbi_num < 1 \|\| gsbi_num > MAX_GSBI) {
	169	dev_err(&pdev->dev, "invalid cell-index\n");
	170	return -EINVAL;
	171	}
	172
fa9eb324	173	if (of_property_read_u32(node, "qcom,mode", &gsbi->mode)) {
5d144e36 AG	174	dev_err(&pdev->dev, "missing mode configuration\n");
	175	return -EINVAL;
	176	}
	177
	178	/* not required, so default to 0 if not present */
fa9eb324	179	of_property_read_u32(node, "qcom,crci", &gsbi->crci);
5d144e36	180
fa9eb324 SK	181	dev_info(&pdev->dev, "GSBI port protocol: %d crci: %d\n",
	182	gsbi->mode, gsbi->crci);
	183	gsbi->hclk = devm_clk_get(&pdev->dev, "iface");
	184	if (IS_ERR(gsbi->hclk))
	185	return PTR_ERR(gsbi->hclk);
5d144e36	186
fa9eb324	187	clk_prepare_enable(gsbi->hclk);
5d144e36	188
fa9eb324	189	writel_relaxed((gsbi->mode << GSBI_PROTOCOL_SHIFT) \| gsbi->crci,
5d144e36 AG	190	base + GSBI_CTRL_REG);
5d144e36 AG	191
e5fdad68 AG	192	/*
	193	* modify tcsr to reflect mode and ADM CRCI mux
	194	* Each gsbi contains a pair of bits, one for RX and one for TX
	195	* SPI mode requires both bits cleared, otherwise they are set
	196	*/
	197	if (config) {
	198	for (i = 0; i < config->num_rows; i++) {
	199	mask = config->array[i][gsbi_num - 1];
	200
	201	if (gsbi->mode == GSBI_PROT_SPI)
	202	regmap_update_bits(gsbi->tcsr,
	203	TCSR_ADM_CRCI_BASE + 4 * i, mask, 0);
	204	else
	205	regmap_update_bits(gsbi->tcsr,
	206	TCSR_ADM_CRCI_BASE + 4 * i, mask, mask);
	207
	208	}
	209	}
	210
5d144e36 AG	211	/* make sure the gsbi control write is not reordered */
	212	wmb();
	213
fa9eb324 SK	214	platform_set_drvdata(pdev, gsbi);
fa9eb324 SK	215
8cd09a3d AK	216	ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
	217	if (ret)
	218	clk_disable_unprepare(gsbi->hclk);
	219	return ret;
fa9eb324 SK	220	}
	221
	222	static int gsbi_remove(struct platform_device *pdev)
	223	{
	224	struct gsbi_info *gsbi = platform_get_drvdata(pdev);
	225
	226	clk_disable_unprepare(gsbi->hclk);
5d144e36	227
fa9eb324	228	return 0;
5d144e36 AG	229	}
	230
	231	static const struct of_device_id gsbi_dt_match[] = {
	232	{ .compatible = "qcom,gsbi-v1.0.0", },
1b7f0c7b	233	{ },
5d144e36 AG	234	};
	235
	236	MODULE_DEVICE_TABLE(of, gsbi_dt_match);
	237
	238	static struct platform_driver gsbi_driver = {
	239	.driver = {
	240	.name = "gsbi",
5d144e36 AG	241	.of_match_table = gsbi_dt_match,
	242	},
	243	.probe = gsbi_probe,
fa9eb324	244	.remove = gsbi_remove,
5d144e36 AG	245	};
	246
	247	module_platform_driver(gsbi_driver);
	248
	249	MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
	250	MODULE_DESCRIPTION("QCOM GSBI driver");
	251	MODULE_LICENSE("GPL v2");