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Merge tag 'scmi-fixes-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep...
[linux-2.6-block.git] / drivers / soc / qcom / qcom-geni-se.c
CommitLineData
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KR		 1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
3
8bc529b2 4#include <linux/acpi.h>
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KR		 5#include <linux/clk.h>
6#include <linux/slab.h>
7#include <linux/dma-mapping.h>
8#include <linux/io.h>
9#include <linux/module.h>
10#include <linux/of.h>
11#include <linux/of_platform.h>
12#include <linux/pinctrl/consumer.h>
13#include <linux/platform_device.h>
14#include <linux/qcom-geni-se.h>
15
16/**
17 * DOC: Overview
18 *
19 * Generic Interface (GENI) Serial Engine (SE) Wrapper driver is introduced
20 * to manage GENI firmware based Qualcomm Universal Peripheral (QUP) Wrapper
21 * controller. QUP Wrapper is designed to support various serial bus protocols
22 * like UART, SPI, I2C, I3C, etc.
23 */
24
25/**
26 * DOC: Hardware description
27 *
28 * GENI based QUP is a highly-flexible and programmable module for supporting
29 * a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single
30 * QUP module can provide upto 8 serial interfaces, using its internal
31 * serial engines. The actual configuration is determined by the target
32 * platform configuration. The protocol supported by each interface is
33 * determined by the firmware loaded to the serial engine. Each SE consists
34 * of a DMA Engine and GENI sub modules which enable serial engines to
35 * support FIFO and DMA modes of operation.
36 *
37 *
38 * +-----------------------------------------+
39 * |QUP Wrapper |
40 * | +----------------------------+ |
41 * --QUP & SE Clocks--> | Serial Engine N | +-IO------>
42 * | | ... | | Interface
43 * <---Clock Perf.----+ +----+-----------------------+ | |
44 * State Interface | | Serial Engine 1 | | |
45 * | | | | |
46 * | | | | |
47 * <--------AHB-------> | | | |
48 * | | +----+ |
49 * | | | |
50 * | | | |
51 * <------SE IRQ------+ +----------------------------+ |
52 * | |
53 * +-----------------------------------------+
54 *
55 * Figure 1: GENI based QUP Wrapper
56 *
57 * The GENI submodules include primary and secondary sequencers which are
58 * used to drive TX & RX operations. On serial interfaces that operate using
59 * master-slave model, primary sequencer drives both TX & RX operations. On
60 * serial interfaces that operate using peer-to-peer model, primary sequencer
61 * drives TX operation and secondary sequencer drives RX operation.
62 */
63
64/**
65 * DOC: Software description
66 *
67 * GENI SE Wrapper driver is structured into 2 parts:
68 *
69 * geni_wrapper represents QUP Wrapper controller. This part of the driver
70 * manages QUP Wrapper information such as hardware version, clock
71 * performance table that is common to all the internal serial engines.
72 *
73 * geni_se represents serial engine. This part of the driver manages serial
74 * engine information such as clocks, containing QUP Wrapper, etc. This part
75 * of driver also supports operations (eg. initialize the concerned serial
76 * engine, select between FIFO and DMA mode of operation etc.) that are
77 * common to all the serial engines and are independent of serial interfaces.
78 */
79
80#define MAX_CLK_PERF_LEVEL 32
81#define NUM_AHB_CLKS 2
82
83/**
84 * @struct geni_wrapper - Data structure to represent the QUP Wrapper Core
85 * @dev: Device pointer of the QUP wrapper core
86 * @base: Base address of this instance of QUP wrapper core
87 * @ahb_clks: Handle to the primary & secondary AHB clocks
88 */
89struct geni_wrapper {
90 struct device *dev;
91 void __iomem *base;
92 struct clk_bulk_data ahb_clks[NUM_AHB_CLKS];
93};
94
95#define QUP_HW_VER_REG 0x4
96
97/* Common SE registers */
98#define GENI_INIT_CFG_REVISION 0x0
99#define GENI_S_INIT_CFG_REVISION 0x4
100#define GENI_OUTPUT_CTRL 0x24
101#define GENI_CGC_CTRL 0x28
102#define GENI_CLK_CTRL_RO 0x60
103#define GENI_IF_DISABLE_RO 0x64
104#define GENI_FW_S_REVISION_RO 0x6c
105#define SE_GENI_BYTE_GRAN 0x254
106#define SE_GENI_TX_PACKING_CFG0 0x260
107#define SE_GENI_TX_PACKING_CFG1 0x264
108#define SE_GENI_RX_PACKING_CFG0 0x284
109#define SE_GENI_RX_PACKING_CFG1 0x288
110#define SE_GENI_M_GP_LENGTH 0x910
111#define SE_GENI_S_GP_LENGTH 0x914
112#define SE_DMA_TX_PTR_L 0xc30
113#define SE_DMA_TX_PTR_H 0xc34
114#define SE_DMA_TX_ATTR 0xc38
115#define SE_DMA_TX_LEN 0xc3c
116#define SE_DMA_TX_IRQ_EN 0xc48
117#define SE_DMA_TX_IRQ_EN_SET 0xc4c
118#define SE_DMA_TX_IRQ_EN_CLR 0xc50
119#define SE_DMA_TX_LEN_IN 0xc54
120#define SE_DMA_TX_MAX_BURST 0xc5c
121#define SE_DMA_RX_PTR_L 0xd30
122#define SE_DMA_RX_PTR_H 0xd34
123#define SE_DMA_RX_ATTR 0xd38
124#define SE_DMA_RX_LEN 0xd3c
125#define SE_DMA_RX_IRQ_EN 0xd48
126#define SE_DMA_RX_IRQ_EN_SET 0xd4c
127#define SE_DMA_RX_IRQ_EN_CLR 0xd50
128#define SE_DMA_RX_LEN_IN 0xd54
129#define SE_DMA_RX_MAX_BURST 0xd5c
130#define SE_DMA_RX_FLUSH 0xd60
131#define SE_GSI_EVENT_EN 0xe18
132#define SE_IRQ_EN 0xe1c
133#define SE_DMA_GENERAL_CFG 0xe30
134
135/* GENI_OUTPUT_CTRL fields */
136#define DEFAULT_IO_OUTPUT_CTRL_MSK GENMASK(6, 0)
137
138/* GENI_CGC_CTRL fields */
139#define CFG_AHB_CLK_CGC_ON BIT(0)
140#define CFG_AHB_WR_ACLK_CGC_ON BIT(1)
141#define DATA_AHB_CLK_CGC_ON BIT(2)
142#define SCLK_CGC_ON BIT(3)
143#define TX_CLK_CGC_ON BIT(4)
144#define RX_CLK_CGC_ON BIT(5)
145#define EXT_CLK_CGC_ON BIT(6)
146#define PROG_RAM_HCLK_OFF BIT(8)
147#define PROG_RAM_SCLK_OFF BIT(9)
148#define DEFAULT_CGC_EN GENMASK(6, 0)
149
150/* SE_GSI_EVENT_EN fields */
151#define DMA_RX_EVENT_EN BIT(0)
152#define DMA_TX_EVENT_EN BIT(1)
153#define GENI_M_EVENT_EN BIT(2)
154#define GENI_S_EVENT_EN BIT(3)
155
156/* SE_IRQ_EN fields */
157#define DMA_RX_IRQ_EN BIT(0)
158#define DMA_TX_IRQ_EN BIT(1)
159#define GENI_M_IRQ_EN BIT(2)
160#define GENI_S_IRQ_EN BIT(3)
161
162/* SE_DMA_GENERAL_CFG */
163#define DMA_RX_CLK_CGC_ON BIT(0)
164#define DMA_TX_CLK_CGC_ON BIT(1)
165#define DMA_AHB_SLV_CFG_ON BIT(2)
166#define AHB_SEC_SLV_CLK_CGC_ON BIT(3)
167#define DUMMY_RX_NON_BUFFERABLE BIT(4)
168#define RX_DMA_ZERO_PADDING_EN BIT(5)
169#define RX_DMA_IRQ_DELAY_MSK GENMASK(8, 6)
170#define RX_DMA_IRQ_DELAY_SHFT 6
171
172/**
173 * geni_se_get_qup_hw_version() - Read the QUP wrapper Hardware version
174 * @se: Pointer to the corresponding serial engine.
175 *
176 * Return: Hardware Version of the wrapper.
177 */
178u32 geni_se_get_qup_hw_version(struct geni_se *se)
179{
180 struct geni_wrapper *wrapper = se->wrapper;
181
182 return readl_relaxed(wrapper->base + QUP_HW_VER_REG);
183}
184EXPORT_SYMBOL(geni_se_get_qup_hw_version);
185
186static void geni_se_io_set_mode(void __iomem *base)
187{
188 u32 val;
189
190 val = readl_relaxed(base + SE_IRQ_EN);
191 val |= GENI_M_IRQ_EN | GENI_S_IRQ_EN;
192 val |= DMA_TX_IRQ_EN | DMA_RX_IRQ_EN;
193 writel_relaxed(val, base + SE_IRQ_EN);
194
195 val = readl_relaxed(base + SE_GENI_DMA_MODE_EN);
196 val &= ~GENI_DMA_MODE_EN;
197 writel_relaxed(val, base + SE_GENI_DMA_MODE_EN);
198
199 writel_relaxed(0, base + SE_GSI_EVENT_EN);
200}
201
202static void geni_se_io_init(void __iomem *base)
203{
204 u32 val;
205
206 val = readl_relaxed(base + GENI_CGC_CTRL);
207 val |= DEFAULT_CGC_EN;
208 writel_relaxed(val, base + GENI_CGC_CTRL);
209
210 val = readl_relaxed(base + SE_DMA_GENERAL_CFG);
211 val |= AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON;
212 val |= DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON;
213 writel_relaxed(val, base + SE_DMA_GENERAL_CFG);
214
215 writel_relaxed(DEFAULT_IO_OUTPUT_CTRL_MSK, base + GENI_OUTPUT_CTRL);
216 writel_relaxed(FORCE_DEFAULT, base + GENI_FORCE_DEFAULT_REG);
217}
218
279536a5
AC		 219static void geni_se_irq_clear(struct geni_se *se)
220{
221 writel_relaxed(0, se->base + SE_GSI_EVENT_EN);
222 writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR);
223 writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR);
224 writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR);
225 writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR);
226 writel_relaxed(0xffffffff, se->base + SE_IRQ_EN);
227}
228
eddac5af
KR		 229/**
230 * geni_se_init() - Initialize the GENI serial engine
231 * @se: Pointer to the concerned serial engine.
232 * @rx_wm: Receive watermark, in units of FIFO words.
233 * @rx_rfr_wm: Ready-for-receive watermark, in units of FIFO words.
234 *
235 * This function is used to initialize the GENI serial engine, configure
236 * receive watermark and ready-for-receive watermarks.
237 */
238void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr)
239{
240 u32 val;
241
279536a5 242 geni_se_irq_clear(se);
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KR		 243 geni_se_io_init(se->base);
244 geni_se_io_set_mode(se->base);
245
246 writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG);
247 writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG);
248
249 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
250 val |= M_COMMON_GENI_M_IRQ_EN;
251 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
252
253 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
254 val |= S_COMMON_GENI_S_IRQ_EN;
255 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
256}
257EXPORT_SYMBOL(geni_se_init);
258
259static void geni_se_select_fifo_mode(struct geni_se *se)
260{
261 u32 proto = geni_se_read_proto(se);
262 u32 val;
263
279536a5 264 geni_se_irq_clear(se);
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KR		 265
266 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
267 if (proto != GENI_SE_UART) {
268 val |= M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN;
269 val |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
270 }
271 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
272
273 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
274 if (proto != GENI_SE_UART)
275 val |= S_CMD_DONE_EN;
276 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
277
278 val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
279 val &= ~GENI_DMA_MODE_EN;
280 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);
281}
282
283static void geni_se_select_dma_mode(struct geni_se *se)
284{
285 u32 val;
286
279536a5 287 geni_se_irq_clear(se);
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KR		 288
289 val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
290 val |= GENI_DMA_MODE_EN;
291 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);
292}
293
294/**
295 * geni_se_select_mode() - Select the serial engine transfer mode
296 * @se: Pointer to the concerned serial engine.
297 * @mode: Transfer mode to be selected.
298 */
299void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode)
300{
301 WARN_ON(mode != GENI_SE_FIFO && mode != GENI_SE_DMA);
302
303 switch (mode) {
304 case GENI_SE_FIFO:
305 geni_se_select_fifo_mode(se);
306 break;
307 case GENI_SE_DMA:
308 geni_se_select_dma_mode(se);
309 break;
310 case GENI_SE_INVALID:
311 default:
312 break;
313 }
314}
315EXPORT_SYMBOL(geni_se_select_mode);
316
317/**
318 * DOC: Overview
319 *
320 * GENI FIFO packing is highly configurable. TX/RX packing/unpacking consist
321 * of up to 4 operations, each operation represented by 4 configuration vectors
322 * of 10 bits programmed in GENI_TX_PACKING_CFG0 and GENI_TX_PACKING_CFG1 for
323 * TX FIFO and in GENI_RX_PACKING_CFG0 and GENI_RX_PACKING_CFG1 for RX FIFO.
324 * Refer to below examples for detailed bit-field description.
325 *
326 * Example 1: word_size = 7, packing_mode = 4 x 8, msb_to_lsb = 1
327 *
328 * +-----------+-------+-------+-------+-------+
329 * | | vec_0 | vec_1 | vec_2 | vec_3 |
330 * +-----------+-------+-------+-------+-------+
331 * | start | 0x6 | 0xe | 0x16 | 0x1e |
332 * | direction | 1 | 1 | 1 | 1 |
333 * | length | 6 | 6 | 6 | 6 |
334 * | stop | 0 | 0 | 0 | 1 |
335 * +-----------+-------+-------+-------+-------+
336 *
337 * Example 2: word_size = 15, packing_mode = 2 x 16, msb_to_lsb = 0
338 *
339 * +-----------+-------+-------+-------+-------+
340 * | | vec_0 | vec_1 | vec_2 | vec_3 |
341 * +-----------+-------+-------+-------+-------+
342 * | start | 0x0 | 0x8 | 0x10 | 0x18 |
343 * | direction | 0 | 0 | 0 | 0 |
344 * | length | 7 | 6 | 7 | 6 |
345 * | stop | 0 | 0 | 0 | 1 |
346 * +-----------+-------+-------+-------+-------+
347 *
348 * Example 3: word_size = 23, packing_mode = 1 x 32, msb_to_lsb = 1
349 *
350 * +-----------+-------+-------+-------+-------+
351 * | | vec_0 | vec_1 | vec_2 | vec_3 |
352 * +-----------+-------+-------+-------+-------+
353 * | start | 0x16 | 0xe | 0x6 | 0x0 |
354 * | direction | 1 | 1 | 1 | 1 |
355 * | length | 7 | 7 | 6 | 0 |
356 * | stop | 0 | 0 | 1 | 0 |
357 * +-----------+-------+-------+-------+-------+
358 *
359 */
360
361#define NUM_PACKING_VECTORS 4
362#define PACKING_START_SHIFT 5
363#define PACKING_DIR_SHIFT 4
364#define PACKING_LEN_SHIFT 1
365#define PACKING_STOP_BIT BIT(0)
366#define PACKING_VECTOR_SHIFT 10
367/**
368 * geni_se_config_packing() - Packing configuration of the serial engine
369 * @se: Pointer to the concerned serial engine
370 * @bpw: Bits of data per transfer word.
371 * @pack_words: Number of words per fifo element.
372 * @msb_to_lsb: Transfer from MSB to LSB or vice-versa.
373 * @tx_cfg: Flag to configure the TX Packing.
374 * @rx_cfg: Flag to configure the RX Packing.
375 *
376 * This function is used to configure the packing rules for the current
377 * transfer.
378 */
379void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words,
380 bool msb_to_lsb, bool tx_cfg, bool rx_cfg)
381{
382 u32 cfg0, cfg1, cfg[NUM_PACKING_VECTORS] = {0};
383 int len;
384 int temp_bpw = bpw;
385 int idx_start = msb_to_lsb ? bpw - 1 : 0;
386 int idx = idx_start;
387 int idx_delta = msb_to_lsb ? -BITS_PER_BYTE : BITS_PER_BYTE;
388 int ceil_bpw = ALIGN(bpw, BITS_PER_BYTE);
389 int iter = (ceil_bpw * pack_words) / BITS_PER_BYTE;
390 int i;
391
392 if (iter <= 0 || iter > NUM_PACKING_VECTORS)
393 return;
394
395 for (i = 0; i < iter; i++) {
396 len = min_t(int, temp_bpw, BITS_PER_BYTE) - 1;
397 cfg[i] = idx << PACKING_START_SHIFT;
398 cfg[i] |= msb_to_lsb << PACKING_DIR_SHIFT;
399 cfg[i] |= len << PACKING_LEN_SHIFT;
400
401 if (temp_bpw <= BITS_PER_BYTE) {
402 idx = ((i + 1) * BITS_PER_BYTE) + idx_start;
403 temp_bpw = bpw;
404 } else {
405 idx = idx + idx_delta;
406 temp_bpw = temp_bpw - BITS_PER_BYTE;
407 }
408 }
409 cfg[iter - 1] |= PACKING_STOP_BIT;
410 cfg0 = cfg[0] | (cfg[1] << PACKING_VECTOR_SHIFT);
411 cfg1 = cfg[2] | (cfg[3] << PACKING_VECTOR_SHIFT);
412
413 if (tx_cfg) {
414 writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0);
415 writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1);
416 }
417 if (rx_cfg) {
418 writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0);
419 writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1);
420 }
421
422 /*
423 * Number of protocol words in each FIFO entry
424 * 0 - 4x8, four words in each entry, max word size of 8 bits
425 * 1 - 2x16, two words in each entry, max word size of 16 bits
426 * 2 - 1x32, one word in each entry, max word size of 32 bits
427 * 3 - undefined
428 */
429 if (pack_words || bpw == 32)
430 writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN);
431}
432EXPORT_SYMBOL(geni_se_config_packing);
433
434static void geni_se_clks_off(struct geni_se *se)
435{
436 struct geni_wrapper *wrapper = se->wrapper;
437
438 clk_disable_unprepare(se->clk);
439 clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks),
440 wrapper->ahb_clks);
441}
442
443/**
444 * geni_se_resources_off() - Turn off resources associated with the serial
445 * engine
446 * @se: Pointer to the concerned serial engine.
447 *
448 * Return: 0 on success, standard Linux error codes on failure/error.
449 */
450int geni_se_resources_off(struct geni_se *se)
451{
452 int ret;
453
8bc529b2
LJ		 454 if (has_acpi_companion(se->dev))
455 return 0;
456
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KR		 457 ret = pinctrl_pm_select_sleep_state(se->dev);
458 if (ret)
459 return ret;
460
461 geni_se_clks_off(se);
462 return 0;
463}
464EXPORT_SYMBOL(geni_se_resources_off);
465
466static int geni_se_clks_on(struct geni_se *se)
467{
468 int ret;
469 struct geni_wrapper *wrapper = se->wrapper;
470
471 ret = clk_bulk_prepare_enable(ARRAY_SIZE(wrapper->ahb_clks),
472 wrapper->ahb_clks);
473 if (ret)
474 return ret;
475
476 ret = clk_prepare_enable(se->clk);
477 if (ret)
478 clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks),
479 wrapper->ahb_clks);
480 return ret;
481}
482
483/**
484 * geni_se_resources_on() - Turn on resources associated with the serial
485 * engine
486 * @se: Pointer to the concerned serial engine.
487 *
488 * Return: 0 on success, standard Linux error codes on failure/error.
489 */
490int geni_se_resources_on(struct geni_se *se)
491{
492 int ret;
493
8bc529b2
LJ		 494 if (has_acpi_companion(se->dev))
495 return 0;
496
eddac5af
KR		 497 ret = geni_se_clks_on(se);
498 if (ret)
499 return ret;
500
501 ret = pinctrl_pm_select_default_state(se->dev);
502 if (ret)
503 geni_se_clks_off(se);
504
505 return ret;
506}
507EXPORT_SYMBOL(geni_se_resources_on);
508
509/**
510 * geni_se_clk_tbl_get() - Get the clock table to program DFS
511 * @se: Pointer to the concerned serial engine.
512 * @tbl: Table in which the output is returned.
513 *
514 * This function is called by the protocol drivers to determine the different
515 * clock frequencies supported by serial engine core clock. The protocol
516 * drivers use the output to determine the clock frequency index to be
517 * programmed into DFS.
518 *
519 * Return: number of valid performance levels in the table on success,
520 * standard Linux error codes on failure.
521 */
522int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl)
523{
abc1c944 524 long freq = 0;
eddac5af
KR		 525 int i;
526
527 if (se->clk_perf_tbl) {
528 *tbl = se->clk_perf_tbl;
529 return se->num_clk_levels;
530 }
531
532 se->clk_perf_tbl = devm_kcalloc(se->dev, MAX_CLK_PERF_LEVEL,
533 sizeof(*se->clk_perf_tbl),
534 GFP_KERNEL);
535 if (!se->clk_perf_tbl)
536 return -ENOMEM;
537
538 for (i = 0; i < MAX_CLK_PERF_LEVEL; i++) {
539 freq = clk_round_rate(se->clk, freq + 1);
abc1c944 540 if (freq <= 0 || freq == se->clk_perf_tbl[i - 1])
eddac5af
KR		 541 break;
542 se->clk_perf_tbl[i] = freq;
543 }
544 se->num_clk_levels = i;
545 *tbl = se->clk_perf_tbl;
546 return se->num_clk_levels;
547}
548EXPORT_SYMBOL(geni_se_clk_tbl_get);
549
550/**
551 * geni_se_clk_freq_match() - Get the matching or closest SE clock frequency
552 * @se: Pointer to the concerned serial engine.
553 * @req_freq: Requested clock frequency.
554 * @index: Index of the resultant frequency in the table.
969fc78c 555 * @res_freq: Resultant frequency of the source clock.
eddac5af
KR		 556 * @exact: Flag to indicate exact multiple requirement of the requested
557 * frequency.
558 *
969fc78c
DA		 559 * This function is called by the protocol drivers to determine the best match
560 * of the requested frequency as provided by the serial engine clock in order
561 * to meet the performance requirements.
562 *
563 * If we return success:
564 * - if @exact is true then @res_freq / <an_integer> == @req_freq
565 * - if @exact is false then @res_freq / <an_integer> <= @req_freq
eddac5af
KR		 566 *
567 * Return: 0 on success, standard Linux error codes on failure.
568 */
569int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq,
570 unsigned int *index, unsigned long *res_freq,
571 bool exact)
572{
573 unsigned long *tbl;
574 int num_clk_levels;
575 int i;
969fc78c
DA		 576 unsigned long best_delta;
577 unsigned long new_delta;
578 unsigned int divider;
eddac5af
KR		 579
580 num_clk_levels = geni_se_clk_tbl_get(se, &tbl);
581 if (num_clk_levels < 0)
582 return num_clk_levels;
583
584 if (num_clk_levels == 0)
585 return -EINVAL;
586
969fc78c 587 best_delta = ULONG_MAX;
eddac5af 588 for (i = 0; i < num_clk_levels; i++) {
969fc78c
DA		 589 divider = DIV_ROUND_UP(tbl[i], req_freq);
590 new_delta = req_freq - tbl[i] / divider;
591 if (new_delta < best_delta) {
592 /* We have a new best! */
eddac5af
KR		 593 *index = i;
594 *res_freq = tbl[i];
eddac5af 595
969fc78c
DA		 596 /* If the new best is exact then we're done */
597 if (new_delta == 0)
598 return 0;
599
600 /* Record how close we got */
601 best_delta = new_delta;
eddac5af
KR		 602 }
603 }
604
605 if (exact)
606 return -EINVAL;
607
608 return 0;
609}
610EXPORT_SYMBOL(geni_se_clk_freq_match);
611
612#define GENI_SE_DMA_DONE_EN BIT(0)
613#define GENI_SE_DMA_EOT_EN BIT(1)
614#define GENI_SE_DMA_AHB_ERR_EN BIT(2)
615#define GENI_SE_DMA_EOT_BUF BIT(0)
616/**
617 * geni_se_tx_dma_prep() - Prepare the serial engine for TX DMA transfer
618 * @se: Pointer to the concerned serial engine.
619 * @buf: Pointer to the TX buffer.
620 * @len: Length of the TX buffer.
621 * @iova: Pointer to store the mapped DMA address.
622 *
623 * This function is used to prepare the buffers for DMA TX.
624 *
625 * Return: 0 on success, standard Linux error codes on failure.
626 */
627int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len,
628 dma_addr_t *iova)
629{
630 struct geni_wrapper *wrapper = se->wrapper;
631 u32 val;
632
8928e917
LJ		 633 if (!wrapper)
634 return -EINVAL;
635
eddac5af
KR		 636 *iova = dma_map_single(wrapper->dev, buf, len, DMA_TO_DEVICE);
637 if (dma_mapping_error(wrapper->dev, *iova))
638 return -EIO;
639
640 val = GENI_SE_DMA_DONE_EN;
641 val |= GENI_SE_DMA_EOT_EN;
642 val |= GENI_SE_DMA_AHB_ERR_EN;
643 writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET);
644 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_TX_PTR_L);
645 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_TX_PTR_H);
646 writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR);
647 writel_relaxed(len, se->base + SE_DMA_TX_LEN);
648 return 0;
649}
650EXPORT_SYMBOL(geni_se_tx_dma_prep);
651
652/**
653 * geni_se_rx_dma_prep() - Prepare the serial engine for RX DMA transfer
654 * @se: Pointer to the concerned serial engine.
655 * @buf: Pointer to the RX buffer.
656 * @len: Length of the RX buffer.
657 * @iova: Pointer to store the mapped DMA address.
658 *
659 * This function is used to prepare the buffers for DMA RX.
660 *
661 * Return: 0 on success, standard Linux error codes on failure.
662 */
663int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len,
664 dma_addr_t *iova)
665{
666 struct geni_wrapper *wrapper = se->wrapper;
667 u32 val;
668
8928e917
LJ		 669 if (!wrapper)
670 return -EINVAL;
671
eddac5af
KR		 672 *iova = dma_map_single(wrapper->dev, buf, len, DMA_FROM_DEVICE);
673 if (dma_mapping_error(wrapper->dev, *iova))
674 return -EIO;
675
676 val = GENI_SE_DMA_DONE_EN;
677 val |= GENI_SE_DMA_EOT_EN;
678 val |= GENI_SE_DMA_AHB_ERR_EN;
679 writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET);
680 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_RX_PTR_L);
681 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_RX_PTR_H);
682 /* RX does not have EOT buffer type bit. So just reset RX_ATTR */
683 writel_relaxed(0, se->base + SE_DMA_RX_ATTR);
684 writel_relaxed(len, se->base + SE_DMA_RX_LEN);
685 return 0;
686}
687EXPORT_SYMBOL(geni_se_rx_dma_prep);
688
689/**
690 * geni_se_tx_dma_unprep() - Unprepare the serial engine after TX DMA transfer
691 * @se: Pointer to the concerned serial engine.
692 * @iova: DMA address of the TX buffer.
693 * @len: Length of the TX buffer.
694 *
695 * This function is used to unprepare the DMA buffers after DMA TX.
696 */
697void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len)
698{
699 struct geni_wrapper *wrapper = se->wrapper;
700
701 if (iova && !dma_mapping_error(wrapper->dev, iova))
702 dma_unmap_single(wrapper->dev, iova, len, DMA_TO_DEVICE);
703}
704EXPORT_SYMBOL(geni_se_tx_dma_unprep);
705
706/**
707 * geni_se_rx_dma_unprep() - Unprepare the serial engine after RX DMA transfer
708 * @se: Pointer to the concerned serial engine.
709 * @iova: DMA address of the RX buffer.
710 * @len: Length of the RX buffer.
711 *
712 * This function is used to unprepare the DMA buffers after DMA RX.
713 */
714void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len)
715{
716 struct geni_wrapper *wrapper = se->wrapper;
717
718 if (iova && !dma_mapping_error(wrapper->dev, iova))
719 dma_unmap_single(wrapper->dev, iova, len, DMA_FROM_DEVICE);
720}
721EXPORT_SYMBOL(geni_se_rx_dma_unprep);
722
723static int geni_se_probe(struct platform_device *pdev)
724{
725 struct device *dev = &pdev->dev;
726 struct resource *res;
727 struct geni_wrapper *wrapper;
728 int ret;
729
730 wrapper = devm_kzalloc(dev, sizeof(*wrapper), GFP_KERNEL);
731 if (!wrapper)
732 return -ENOMEM;
733
734 wrapper->dev = dev;
735 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
736 wrapper->base = devm_ioremap_resource(dev, res);
737 if (IS_ERR(wrapper->base))
738 return PTR_ERR(wrapper->base);
739
8bc529b2
LJ		 740 if (!has_acpi_companion(&pdev->dev)) {
741 wrapper->ahb_clks[0].id = "m-ahb";
742 wrapper->ahb_clks[1].id = "s-ahb";
743 ret = devm_clk_bulk_get(dev, NUM_AHB_CLKS, wrapper->ahb_clks);
744 if (ret) {
745 dev_err(dev, "Err getting AHB clks %d\n", ret);
746 return ret;
747 }
eddac5af
KR		 748 }
749
750 dev_set_drvdata(dev, wrapper);
751 dev_dbg(dev, "GENI SE Driver probed\n");
752 return devm_of_platform_populate(dev);
753}
754
755static const struct of_device_id geni_se_dt_match[] = {
756 { .compatible = "qcom,geni-se-qup", },
757 {}
758};
759MODULE_DEVICE_TABLE(of, geni_se_dt_match);
760
761static struct platform_driver geni_se_driver = {
762 .driver = {
763 .name = "geni_se_qup",
764 .of_match_table = geni_se_dt_match,
765 },
766 .probe = geni_se_probe,
767};
768module_platform_driver(geni_se_driver);
769
770MODULE_DESCRIPTION("GENI Serial Engine Driver");
771MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)