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a3134fb0 RB |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
a14b8203 | 3 | * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. |
a3134fb0 RB |
4 | * |
5 | */ | |
6 | ||
916c0c05 | 7 | #include <linux/bitfield.h> |
a3134fb0 RB |
8 | #include <linux/bitmap.h> |
9 | #include <linux/bitops.h> | |
04e60d7a | 10 | #include <linux/cleanup.h> |
a3134fb0 RB |
11 | #include <linux/device.h> |
12 | #include <linux/io.h> | |
13 | #include <linux/kernel.h> | |
4da3b045 | 14 | #include <linux/module.h> |
a3134fb0 | 15 | #include <linux/mutex.h> |
a78502a4 | 16 | #include <linux/nvmem-consumer.h> |
a14b8203 | 17 | #include <linux/of.h> |
a3134fb0 | 18 | #include <linux/regmap.h> |
da8eaf9a | 19 | #include <linux/sizes.h> |
a3134fb0 RB |
20 | #include <linux/slab.h> |
21 | #include <linux/soc/qcom/llcc-qcom.h> | |
22 | ||
23 | #define ACTIVATE BIT(0) | |
24 | #define DEACTIVATE BIT(1) | |
c72ca343 AV |
25 | #define ACT_CLEAR BIT(0) |
26 | #define ACT_COMPLETE BIT(4) | |
a3134fb0 RB |
27 | #define ACT_CTRL_OPCODE_ACTIVATE BIT(0) |
28 | #define ACT_CTRL_OPCODE_DEACTIVATE BIT(1) | |
29 | #define ACT_CTRL_ACT_TRIG BIT(0) | |
30 | #define ACT_CTRL_OPCODE_SHIFT 0x01 | |
31 | #define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x02 | |
32 | #define ATTR1_FIXED_SIZE_SHIFT 0x03 | |
33 | #define ATTR1_PRIORITY_SHIFT 0x04 | |
34 | #define ATTR1_MAX_CAP_SHIFT 0x10 | |
06b24ab3 HY |
35 | #define ATTR0_RES_WAYS_MASK GENMASK(15, 0) |
36 | #define ATTR0_BONUS_WAYS_MASK GENMASK(31, 16) | |
a3134fb0 RB |
37 | #define ATTR0_BONUS_WAYS_SHIFT 0x10 |
38 | #define LLCC_STATUS_READ_DELAY 100 | |
39 | ||
40 | #define CACHE_LINE_SIZE_SHIFT 6 | |
41 | ||
a3134fb0 RB |
42 | #define LLCC_LB_CNT_MASK GENMASK(31, 28) |
43 | #define LLCC_LB_CNT_SHIFT 28 | |
44 | ||
45 | #define MAX_CAP_TO_BYTES(n) (n * SZ_1K) | |
46 | #define LLCC_TRP_ACT_CTRLn(n) (n * SZ_4K) | |
c72ca343 | 47 | #define LLCC_TRP_ACT_CLEARn(n) (8 + n * SZ_4K) |
a3134fb0 RB |
48 | #define LLCC_TRP_STATUSn(n) (4 + n * SZ_4K) |
49 | #define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n) | |
50 | #define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n) | |
110cb8d8 | 51 | #define LLCC_TRP_ATTR2_CFGn(n) (0x21100 + SZ_4 * n) |
a3134fb0 | 52 | |
c14e64b4 IM |
53 | #define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00 |
54 | #define LLCC_TRP_PCB_ACT 0x21f04 | |
c72ca343 AV |
55 | #define LLCC_TRP_ALGO_CFG1 0x21f0c |
56 | #define LLCC_TRP_ALGO_CFG2 0x21f10 | |
57 | #define LLCC_TRP_ALGO_CFG3 0x21f14 | |
58 | #define LLCC_TRP_ALGO_CFG4 0x21f18 | |
59 | #define LLCC_TRP_ALGO_CFG5 0x21f1c | |
c4df37fe | 60 | #define LLCC_TRP_WRSC_EN 0x21f20 |
c72ca343 AV |
61 | #define LLCC_TRP_ALGO_CFG6 0x21f24 |
62 | #define LLCC_TRP_ALGO_CFG7 0x21f28 | |
2b8175a1 | 63 | #define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c |
c72ca343 | 64 | #define LLCC_TRP_ALGO_CFG8 0x21f30 |
c14e64b4 | 65 | |
8008e790 | 66 | #define LLCC_VERSION_2_0_0_0 0x02000000 |
2b8175a1 | 67 | #define LLCC_VERSION_2_1_0_0 0x02010000 |
c72ca343 | 68 | #define LLCC_VERSION_4_1_0_0 0x04010000 |
8008e790 | 69 | |
99356b03 | 70 | /** |
171c0317 | 71 | * struct llcc_slice_config - Data associated with the llcc slice |
99356b03 VG |
72 | * @usecase_id: Unique id for the client's use case |
73 | * @slice_id: llcc slice id for each client | |
74 | * @max_cap: The maximum capacity of the cache slice provided in KB | |
75 | * @priority: Priority of the client used to select victim line for replacement | |
76 | * @fixed_size: Boolean indicating if the slice has a fixed capacity | |
77 | * @bonus_ways: Bonus ways are additional ways to be used for any slice, | |
78 | * if client ends up using more than reserved cache ways. Bonus | |
79 | * ways are allocated only if they are not reserved for some | |
80 | * other client. | |
81 | * @res_ways: Reserved ways for the cache slice, the reserved ways cannot | |
82 | * be used by any other client than the one its assigned to. | |
83 | * @cache_mode: Each slice operates as a cache, this controls the mode of the | |
84 | * slice: normal or TCM(Tightly Coupled Memory) | |
85 | * @probe_target_ways: Determines what ways to probe for access hit. When | |
86 | * configured to 1 only bonus and reserved ways are probed. | |
87 | * When configured to 0 all ways in llcc are probed. | |
88 | * @dis_cap_alloc: Disable capacity based allocation for a client | |
89 | * @retain_on_pc: If this bit is set and client has maintained active vote | |
90 | * then the ways assigned to this client are not flushed on power | |
91 | * collapse. | |
92 | * @activate_on_init: Activate the slice immediately after it is programmed | |
c4df37fe | 93 | * @write_scid_en: Bit enables write cache support for a given scid. |
2b8175a1 SPR |
94 | * @write_scid_cacheable_en: Enables write cache cacheable support for a |
95 | * given scid (not supported on v2 or older hardware). | |
fd4b634f AV |
96 | * @stale_en: Bit enables stale. |
97 | * @stale_cap_en: Bit enables stale only if current scid is over-cap. | |
98 | * @mru_uncap_en: Roll-over on reserved cache ways if current scid is | |
99 | * under-cap. | |
100 | * @mru_rollover: Roll-over on reserved cache ways. | |
101 | * @alloc_oneway_en: Allways allocate one way on over-cap even if there's no | |
102 | * same-scid lines for replacement. | |
103 | * @ovcap_en: Once current scid is over-capacity, allocate other over-cap SCID. | |
104 | * @ovcap_prio: Once current scid is over-capacity, allocate other low priority | |
105 | * over-cap scid. Depends on corresponding bit being set in | |
106 | * ovcap_en. | |
107 | * @vict_prio: When current scid is under-capacity, allocate over other | |
108 | * lower-than victim priority-line threshold scid. | |
99356b03 VG |
109 | */ |
110 | struct llcc_slice_config { | |
111 | u32 usecase_id; | |
112 | u32 slice_id; | |
113 | u32 max_cap; | |
114 | u32 priority; | |
115 | bool fixed_size; | |
116 | u32 bonus_ways; | |
117 | u32 res_ways; | |
118 | u32 cache_mode; | |
119 | u32 probe_target_ways; | |
120 | bool dis_cap_alloc; | |
121 | bool retain_on_pc; | |
122 | bool activate_on_init; | |
c4df37fe | 123 | bool write_scid_en; |
2b8175a1 | 124 | bool write_scid_cacheable_en; |
c72ca343 AV |
125 | bool stale_en; |
126 | bool stale_cap_en; | |
127 | bool mru_uncap_en; | |
128 | bool mru_rollover; | |
129 | bool alloc_oneway_en; | |
130 | bool ovcap_en; | |
131 | bool ovcap_prio; | |
132 | bool vict_prio; | |
99356b03 VG |
133 | }; |
134 | ||
99356b03 VG |
135 | struct qcom_llcc_config { |
136 | const struct llcc_slice_config *sct_data; | |
424ad93c | 137 | const u32 *reg_offset; |
c13d7d26 | 138 | const struct llcc_edac_reg_offset *edac_reg_offset; |
cca94f1d MS |
139 | int size; |
140 | bool need_llcc_cfg; | |
141 | bool no_edac; | |
424ad93c SPR |
142 | }; |
143 | ||
16fa9311 KB |
144 | struct qcom_sct_config { |
145 | const struct qcom_llcc_config *llcc_config; | |
146 | int num_config; | |
147 | }; | |
148 | ||
424ad93c SPR |
149 | enum llcc_reg_offset { |
150 | LLCC_COMMON_HW_INFO, | |
151 | LLCC_COMMON_STATUS0, | |
99356b03 VG |
152 | }; |
153 | ||
fed15196 TF |
154 | static const struct llcc_slice_config sa8775p_data[] = { |
155 | {LLCC_CPUSS, 1, 2048, 1, 0, 0x00FF, 0x0, 0, 0, 0, 1, 1, 0, 0}, | |
156 | {LLCC_VIDSC0, 2, 512, 3, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0}, | |
157 | {LLCC_CPUSS1, 3, 1024, 1, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0}, | |
158 | {LLCC_CPUHWT, 5, 512, 1, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0}, | |
159 | {LLCC_AUDIO, 6, 1024, 1, 1, 0x00FF, 0x0, 0, 0, 0, 0, 0, 0, 0}, | |
160 | {LLCC_CMPT, 10, 4096, 1, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0}, | |
161 | {LLCC_GPUHTW, 11, 1024, 1, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0}, | |
162 | {LLCC_GPU, 12, 1024, 1, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 1, 0}, | |
163 | {LLCC_MMUHWT, 13, 1024, 1, 1, 0x00FF, 0x0, 0, 0, 0, 0, 1, 0, 0}, | |
164 | {LLCC_CMPTDMA, 15, 1024, 1, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0}, | |
165 | {LLCC_DISP, 16, 4096, 2, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0}, | |
166 | {LLCC_VIDFW, 17, 3072, 1, 0, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0}, | |
167 | {LLCC_AUDHW, 22, 1024, 1, 1, 0x00FF, 0x0, 0, 0, 0, 0, 0, 0, 0}, | |
168 | {LLCC_CVP, 28, 256, 3, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0}, | |
169 | {LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0xF0, 1, 0, 0, 1, 0, 0, 0}, | |
170 | {LLCC_WRCACHE, 31, 512, 1, 1, 0x00FF, 0x0, 0, 0, 0, 0, 1, 0, 0}, | |
171 | }; | |
172 | ||
669f7880 VG |
173 | static const struct llcc_slice_config sc7180_data[] = { |
174 | { LLCC_CPUSS, 1, 256, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 1 }, | |
175 | { LLCC_MDM, 8, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, | |
176 | { LLCC_GPUHTW, 11, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, | |
177 | { LLCC_GPU, 12, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, | |
178 | }; | |
179 | ||
f6a07be6 SPR |
180 | static const struct llcc_slice_config sc7280_data[] = { |
181 | { LLCC_CPUSS, 1, 768, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 1, 0}, | |
182 | { LLCC_MDMHPGRW, 7, 512, 2, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, | |
183 | { LLCC_CMPT, 10, 768, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, | |
184 | { LLCC_GPUHTW, 11, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, | |
185 | { LLCC_GPU, 12, 512, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, | |
3a461009 | 186 | { LLCC_MMUHWT, 13, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 0, 1, 0}, |
f6a07be6 SPR |
187 | { LLCC_MDMPNG, 21, 768, 0, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, |
188 | { LLCC_WLHW, 24, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, | |
189 | { LLCC_MODPE, 29, 64, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, | |
190 | }; | |
191 | ||
ec69dfbd BA |
192 | static const struct llcc_slice_config sc8180x_data[] = { |
193 | { LLCC_CPUSS, 1, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1 }, | |
194 | { LLCC_VIDSC0, 2, 512, 2, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, | |
195 | { LLCC_VIDSC1, 3, 512, 2, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, | |
196 | { LLCC_AUDIO, 6, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, | |
197 | { LLCC_MDMHPGRW, 7, 3072, 1, 1, 0x3ff, 0xc00, 0, 0, 0, 1, 0 }, | |
198 | { LLCC_MDM, 8, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, | |
199 | { LLCC_MODHW, 9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, | |
200 | { LLCC_CMPT, 10, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, | |
201 | { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, | |
202 | { LLCC_GPU, 12, 5120, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, | |
203 | { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1 }, | |
204 | { LLCC_CMPTDMA, 15, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, | |
205 | { LLCC_DISP, 16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, | |
206 | { LLCC_VIDFW, 17, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, | |
207 | { LLCC_MDMHPFX, 20, 1024, 2, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, | |
208 | { LLCC_MDMPNG, 21, 1024, 0, 1, 0xc, 0x0, 0, 0, 0, 1, 0 }, | |
209 | { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, | |
210 | { LLCC_NPU, 23, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, | |
211 | { LLCC_WLHW, 24, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, | |
212 | { LLCC_MODPE, 29, 512, 1, 1, 0xc, 0x0, 0, 0, 0, 1, 0 }, | |
213 | { LLCC_APTCM, 30, 512, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0 }, | |
214 | { LLCC_WRCACHE, 31, 128, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0 }, | |
215 | }; | |
216 | ||
217 | static const struct llcc_slice_config sc8280xp_data[] = { | |
218 | { LLCC_CPUSS, 1, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 }, | |
219 | { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, | |
220 | { LLCC_AUDIO, 6, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, | |
221 | { LLCC_CMPT, 10, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, | |
222 | { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, | |
223 | { LLCC_GPU, 12, 4096, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 }, | |
224 | { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, | |
225 | { LLCC_DISP, 16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, | |
226 | { LLCC_AUDHW, 22, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, | |
0bc76be6 | 227 | { LLCC_ECC, 26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, |
ec69dfbd BA |
228 | { LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, |
229 | { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0, 0 }, | |
230 | { LLCC_WRCACHE, 31, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, | |
77bf4b3e AV |
231 | { LLCC_CVPFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, |
232 | { LLCC_CPUSS1, 3, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, | |
233 | { LLCC_CPUHWT, 5, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, | |
ec69dfbd BA |
234 | }; |
235 | ||
669f7880 | 236 | static const struct llcc_slice_config sdm845_data[] = { |
a14b8203 VG |
237 | { LLCC_CPUSS, 1, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 1 }, |
238 | { LLCC_VIDSC0, 2, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 }, | |
239 | { LLCC_VIDSC1, 3, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 }, | |
240 | { LLCC_ROTATOR, 4, 563, 2, 1, 0x0, 0x00e, 2, 0, 1, 1, 0 }, | |
241 | { LLCC_VOICE, 5, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, | |
242 | { LLCC_AUDIO, 6, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, | |
243 | { LLCC_MDMHPGRW, 7, 1024, 2, 0, 0xfc, 0xf00, 0, 0, 1, 1, 0 }, | |
244 | { LLCC_MDM, 8, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, | |
245 | { LLCC_CMPT, 10, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, | |
246 | { LLCC_GPUHTW, 11, 512, 1, 1, 0xc, 0x0, 0, 0, 1, 1, 0 }, | |
247 | { LLCC_GPU, 12, 2304, 1, 0, 0xff0, 0x2, 0, 0, 1, 1, 0 }, | |
248 | { LLCC_MMUHWT, 13, 256, 2, 0, 0x0, 0x1, 0, 0, 1, 0, 1 }, | |
249 | { LLCC_CMPTDMA, 15, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, | |
250 | { LLCC_DISP, 16, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, | |
251 | { LLCC_VIDFW, 17, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, | |
252 | { LLCC_MDMHPFX, 20, 1024, 2, 1, 0x0, 0xf00, 0, 0, 1, 1, 0 }, | |
253 | { LLCC_MDMPNG, 21, 1024, 0, 1, 0x1e, 0x0, 0, 0, 1, 1, 0 }, | |
254 | { LLCC_AUDHW, 22, 1024, 1, 1, 0xffc, 0x2, 0, 0, 1, 1, 0 }, | |
255 | }; | |
256 | ||
1f7b2b63 KD |
257 | static const struct llcc_slice_config sm6350_data[] = { |
258 | { LLCC_CPUSS, 1, 768, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 1 }, | |
259 | { LLCC_MDM, 8, 512, 2, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, | |
260 | { LLCC_GPUHTW, 11, 256, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, | |
261 | { LLCC_GPU, 12, 512, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, | |
262 | { LLCC_MDMPNG, 21, 768, 0, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, | |
263 | { LLCC_NPU, 23, 768, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, | |
264 | { LLCC_MODPE, 29, 64, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, | |
265 | }; | |
266 | ||
92b9d862 DT |
267 | static const struct llcc_slice_config sm7150_data[] = { |
268 | { LLCC_CPUSS, 1, 512, 1, 0, 0xF, 0x0, 0, 0, 0, 1, 1 }, | |
269 | { LLCC_MDM, 8, 128, 2, 0, 0xF, 0x0, 0, 0, 0, 1, 0 }, | |
270 | { LLCC_GPUHTW, 11, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 }, | |
271 | { LLCC_GPU, 12, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 }, | |
272 | { LLCC_NPU, 23, 512, 1, 0, 0xF, 0x0, 0, 0, 0, 1, 0 }, | |
273 | }; | |
274 | ||
ded5ed04 SC |
275 | static const struct llcc_slice_config sm8150_data[] = { |
276 | { LLCC_CPUSS, 1, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 1 }, | |
277 | { LLCC_VIDSC0, 2, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, | |
278 | { LLCC_VIDSC1, 3, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, | |
279 | { LLCC_AUDIO, 6, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, | |
280 | { LLCC_MDMHPGRW, 7, 3072, 1, 0, 0xFF, 0xF00, 0, 0, 0, 1, 0 }, | |
281 | { LLCC_MDM, 8, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, | |
282 | { LLCC_MODHW, 9, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, | |
283 | { LLCC_CMPT, 10, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, | |
284 | { LLCC_GPUHTW , 11, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, | |
285 | { LLCC_GPU, 12, 2560, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, | |
286 | { LLCC_MMUHWT, 13, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1 }, | |
287 | { LLCC_CMPTDMA, 15, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, | |
288 | { LLCC_DISP, 16, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, | |
289 | { LLCC_MDMHPFX, 20, 1024, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, | |
290 | { LLCC_MDMHPFX, 21, 1024, 0, 1, 0xF, 0x0, 0, 0, 0, 1, 0 }, | |
291 | { LLCC_AUDHW, 22, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, | |
292 | { LLCC_NPU, 23, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, | |
293 | { LLCC_WLHW, 24, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, | |
294 | { LLCC_MODPE, 29, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 }, | |
295 | { LLCC_APTCM, 30, 256, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0 }, | |
296 | { LLCC_WRCACHE, 31, 128, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0 }, | |
297 | }; | |
298 | ||
c4df37fe MS |
299 | static const struct llcc_slice_config sm8250_data[] = { |
300 | { LLCC_CPUSS, 1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 }, | |
301 | { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, | |
302 | { LLCC_AUDIO, 6, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, | |
303 | { LLCC_CMPT, 10, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, | |
304 | { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, | |
305 | { LLCC_GPU, 12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 }, | |
306 | { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, | |
307 | { LLCC_CMPTDMA, 15, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, | |
308 | { LLCC_DISP, 16, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, | |
309 | { LLCC_VIDFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, | |
310 | { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, | |
311 | { LLCC_NPU, 23, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, | |
312 | { LLCC_WLHW, 24, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, | |
313 | { LLCC_CVP, 28, 256, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, | |
314 | { LLCC_APTCM, 30, 128, 3, 0, 0x0, 0x3, 1, 0, 0, 1, 0, 0 }, | |
315 | { LLCC_WRCACHE, 31, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, | |
316 | }; | |
317 | ||
6fc61c39 KD |
318 | static const struct llcc_slice_config sm8350_data[] = { |
319 | { LLCC_CPUSS, 1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 1 }, | |
320 | { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, | |
321 | { LLCC_AUDIO, 6, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, | |
322 | { LLCC_MDMHPGRW, 7, 1024, 3, 0, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, | |
323 | { LLCC_MODHW, 9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, | |
324 | { LLCC_CMPT, 10, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, | |
325 | { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, | |
326 | { LLCC_GPU, 12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 }, | |
327 | { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 }, | |
328 | { LLCC_DISP, 16, 3072, 2, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, | |
329 | { LLCC_MDMPNG, 21, 1024, 0, 1, 0xf, 0x0, 0, 0, 0, 0, 1, 0 }, | |
330 | { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, | |
331 | { LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, | |
332 | { LLCC_MODPE, 29, 256, 1, 1, 0xf, 0x0, 0, 0, 0, 0, 1, 0 }, | |
333 | { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 0, 1, 0 }, | |
334 | { LLCC_WRCACHE, 31, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 }, | |
335 | { LLCC_CVPFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, | |
336 | { LLCC_CPUSS1, 3, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, | |
337 | { LLCC_CPUHWT, 5, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 }, | |
338 | }; | |
339 | ||
a6e9d7ef SPR |
340 | static const struct llcc_slice_config sm8450_data[] = { |
341 | {LLCC_CPUSS, 1, 3072, 1, 0, 0xFFFF, 0x0, 0, 0, 0, 1, 1, 0, 0 }, | |
342 | {LLCC_VIDSC0, 2, 512, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, | |
343 | {LLCC_AUDIO, 6, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 }, | |
344 | {LLCC_MDMHPGRW, 7, 1024, 3, 0, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, | |
345 | {LLCC_MODHW, 9, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, | |
346 | {LLCC_CMPT, 10, 4096, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, | |
347 | {LLCC_GPUHTW, 11, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, | |
348 | {LLCC_GPU, 12, 2048, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 1, 0 }, | |
349 | {LLCC_MMUHWT, 13, 768, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0 }, | |
350 | {LLCC_DISP, 16, 4096, 2, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, | |
351 | {LLCC_MDMPNG, 21, 1024, 1, 1, 0xF000, 0x0, 0, 0, 0, 1, 0, 0, 0 }, | |
352 | {LLCC_AUDHW, 22, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 }, | |
353 | {LLCC_CVP, 28, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, | |
354 | {LLCC_MODPE, 29, 64, 1, 1, 0xF000, 0x0, 0, 0, 0, 1, 0, 0, 0 }, | |
355 | {LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0xF0, 1, 0, 0, 1, 0, 0, 0 }, | |
356 | {LLCC_WRCACHE, 31, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0 }, | |
357 | {LLCC_CVPFW, 17, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, | |
358 | {LLCC_CPUSS1, 3, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, | |
359 | {LLCC_CAMEXP0, 4, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, | |
360 | {LLCC_CPUMTE, 23, 256, 1, 1, 0x0FFF, 0x0, 0, 0, 0, 0, 1, 0, 0 }, | |
361 | {LLCC_CPUHWT, 5, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 1, 0, 0 }, | |
362 | {LLCC_CAMEXP1, 27, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, | |
363 | {LLCC_AENPU, 8, 2048, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 }, | |
364 | }; | |
365 | ||
8c045cd2 AV |
366 | static const struct llcc_slice_config sm8550_data[] = { |
367 | {LLCC_CPUSS, 1, 5120, 1, 0, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, | |
368 | {LLCC_VIDSC0, 2, 512, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, | |
369 | {LLCC_AUDIO, 6, 1024, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, | |
370 | {LLCC_MDMHPGRW, 25, 1024, 4, 0, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, | |
371 | {LLCC_MODHW, 26, 1024, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, | |
372 | {LLCC_CMPT, 10, 4096, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, | |
373 | {LLCC_GPUHTW, 11, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, | |
374 | {LLCC_GPU, 9, 3096, 1, 0, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, }, | |
375 | {LLCC_MMUHWT, 18, 768, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, | |
376 | {LLCC_DISP, 16, 6144, 1, 1, 0xFFFFFF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, | |
377 | {LLCC_MDMPNG, 27, 1024, 0, 1, 0xF00000, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, | |
378 | {LLCC_AUDHW, 22, 1024, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, | |
379 | {LLCC_CVP, 8, 256, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, | |
380 | {LLCC_MODPE, 29, 64, 1, 1, 0xF00000, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, }, | |
381 | {LLCC_WRCACHE, 31, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, | |
382 | {LLCC_CAMEXP0, 4, 256, 4, 1, 0xF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, | |
383 | {LLCC_CPUHWT, 5, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, | |
384 | {LLCC_CAMEXP1, 7, 3200, 3, 1, 0xFFFFF0, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, | |
385 | {LLCC_CMPTHCP, 17, 256, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, | |
386 | {LLCC_LCPDARE, 30, 128, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, }, | |
387 | {LLCC_AENPU, 3, 3072, 1, 1, 0xFE01FF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, | |
388 | {LLCC_ISLAND1, 12, 1792, 7, 1, 0xFE00, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, | |
389 | {LLCC_ISLAND4, 15, 256, 7, 1, 0x10000, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, | |
390 | {LLCC_CAMEXP2, 19, 3200, 3, 1, 0xFFFFF0, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, | |
391 | {LLCC_CAMEXP3, 20, 3200, 2, 1, 0xFFFFF0, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, | |
392 | {LLCC_CAMEXP4, 21, 3200, 2, 1, 0xFFFFF0, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, | |
393 | {LLCC_DISP_WB, 23, 1024, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, | |
394 | {LLCC_DISP_1, 24, 6144, 1, 1, 0xFFFFFF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, | |
395 | {LLCC_VIDVSP, 28, 256, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, | |
396 | }; | |
397 | ||
7a280fec NA |
398 | static const struct llcc_slice_config sm8650_data[] = { |
399 | {LLCC_CPUSS, 1, 5120, 1, 0, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0}, | |
400 | {LLCC_VIDSC0, 2, 512, 3, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
401 | {LLCC_AUDIO, 6, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
402 | {LLCC_MDMHPGRW, 25, 1024, 3, 0, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
403 | {LLCC_MODHW, 26, 1024, 1, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
404 | {LLCC_CMPT, 10, 4096, 1, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
405 | {LLCC_GPUHTW, 11, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
406 | {LLCC_GPU, 9, 3096, 1, 0, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0}, | |
407 | {LLCC_MMUHWT, 18, 768, 1, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
408 | {LLCC_DISP, 16, 6144, 1, 1, 0xFFFFFF, 0x0, 2, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
409 | {LLCC_MDMHPFX, 24, 1024, 3, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
410 | {LLCC_MDMPNG, 27, 1024, 0, 1, 0x000000, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
411 | {LLCC_AUDHW, 22, 1024, 1, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
412 | {LLCC_CVP, 8, 256, 3, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
413 | {LLCC_MODPE, 29, 128, 1, 1, 0xF00000, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0}, | |
414 | {LLCC_WRCACHE, 31, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
415 | {LLCC_CAMEXP0, 4, 256, 3, 1, 0xF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
416 | {LLCC_CAMEXP1, 7, 3200, 3, 1, 0xFFFFF0, 0x0, 2, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
417 | {LLCC_CMPTHCP, 17, 256, 3, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
418 | {LLCC_LCPDARE, 30, 128, 3, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0}, | |
419 | {LLCC_AENPU, 3, 3072, 1, 1, 0xFFFFFF, 0x0, 2, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
420 | {LLCC_ISLAND1, 12, 5888, 7, 1, 0x0, 0x7FFFFF, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
421 | {LLCC_DISP_WB, 23, 1024, 3, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
422 | {LLCC_VIDVSP, 28, 256, 3, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
423 | }; | |
424 | ||
db1e5792 KB |
425 | static const struct llcc_slice_config qdu1000_data_2ch[] = { |
426 | { LLCC_MDMHPGRW, 7, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 }, | |
427 | { LLCC_MODHW, 9, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 }, | |
428 | { LLCC_MDMPNG, 21, 256, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 }, | |
429 | { LLCC_ECC, 26, 512, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 }, | |
430 | { LLCC_MODPE, 29, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 }, | |
431 | { LLCC_APTCM, 30, 256, 3, 1, 0x0, 0xc, 1, 0, 0, 1, 0, 0, 0 }, | |
432 | { LLCC_WRCACHE, 31, 128, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 }, | |
433 | }; | |
434 | ||
435 | static const struct llcc_slice_config qdu1000_data_4ch[] = { | |
436 | { LLCC_MDMHPGRW, 7, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 }, | |
437 | { LLCC_MODHW, 9, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 }, | |
438 | { LLCC_MDMPNG, 21, 512, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 }, | |
439 | { LLCC_ECC, 26, 1024, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 }, | |
440 | { LLCC_MODPE, 29, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 }, | |
441 | { LLCC_APTCM, 30, 512, 3, 1, 0x0, 0xc, 1, 0, 0, 1, 0, 0, 0 }, | |
442 | { LLCC_WRCACHE, 31, 256, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 }, | |
443 | }; | |
444 | ||
445 | static const struct llcc_slice_config qdu1000_data_8ch[] = { | |
446 | { LLCC_MDMHPGRW, 7, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 }, | |
447 | { LLCC_MODHW, 9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 }, | |
448 | { LLCC_MDMPNG, 21, 1024, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 }, | |
449 | { LLCC_ECC, 26, 2048, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 }, | |
450 | { LLCC_MODPE, 29, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 }, | |
451 | { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0xc, 1, 0, 0, 1, 0, 0, 0 }, | |
452 | { LLCC_WRCACHE, 31, 512, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 }, | |
453 | }; | |
454 | ||
b3cf69a4 RN |
455 | static const struct llcc_slice_config x1e80100_data[] = { |
456 | {LLCC_CPUSS, 1, 6144, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
457 | {LLCC_VIDSC0, 2, 512, 3, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
458 | {LLCC_AUDIO, 6, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
459 | {LLCC_CMPT, 10, 6144, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
460 | {LLCC_GPUHTW, 11, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
461 | {LLCC_GPU, 9, 4096, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0}, | |
462 | {LLCC_MMUHWT, 18, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
463 | {LLCC_AUDHW, 22, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
464 | {LLCC_CVP, 8, 512, 3, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
465 | {LLCC_WRCACHE, 31, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
466 | {LLCC_CAMEXP1, 7, 3072, 2, 1, 0xFFF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
467 | {LLCC_LCPDARE, 30, 512, 3, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
468 | {LLCC_AENPU, 3, 3072, 1, 1, 0xFFF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
469 | {LLCC_ISLAND1, 12, 512, 7, 1, 0x1, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
470 | {LLCC_ISLAND2, 13, 512, 7, 1, 0x2, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
471 | {LLCC_ISLAND3, 14, 512, 7, 1, 0x3, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
472 | {LLCC_ISLAND4, 15, 512, 7, 1, 0x4, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
473 | {LLCC_CAMEXP2, 19, 3072, 3, 1, 0xFFF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
474 | {LLCC_CAMEXP3, 20, 3072, 3, 1, 0xFFF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
475 | {LLCC_CAMEXP4, 21, 3072, 3, 1, 0xFFF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
476 | }; | |
477 | ||
c13d7d26 MS |
478 | static const struct llcc_edac_reg_offset llcc_v1_edac_reg_offset = { |
479 | .trp_ecc_error_status0 = 0x20344, | |
480 | .trp_ecc_error_status1 = 0x20348, | |
481 | .trp_ecc_sb_err_syn0 = 0x2304c, | |
482 | .trp_ecc_db_err_syn0 = 0x20370, | |
483 | .trp_ecc_error_cntr_clear = 0x20440, | |
484 | .trp_interrupt_0_status = 0x20480, | |
485 | .trp_interrupt_0_clear = 0x20484, | |
486 | .trp_interrupt_0_enable = 0x20488, | |
487 | ||
488 | /* LLCC Common registers */ | |
489 | .cmn_status0 = 0x3000c, | |
490 | .cmn_interrupt_0_enable = 0x3001c, | |
491 | .cmn_interrupt_2_enable = 0x3003c, | |
492 | ||
493 | /* LLCC DRP registers */ | |
494 | .drp_ecc_error_cfg = 0x40000, | |
495 | .drp_ecc_error_cntr_clear = 0x40004, | |
496 | .drp_interrupt_status = 0x41000, | |
497 | .drp_interrupt_clear = 0x41008, | |
498 | .drp_interrupt_enable = 0x4100c, | |
499 | .drp_ecc_error_status0 = 0x42044, | |
500 | .drp_ecc_error_status1 = 0x42048, | |
501 | .drp_ecc_sb_err_syn0 = 0x4204c, | |
502 | .drp_ecc_db_err_syn0 = 0x42070, | |
503 | }; | |
504 | ||
505 | static const struct llcc_edac_reg_offset llcc_v2_1_edac_reg_offset = { | |
506 | .trp_ecc_error_status0 = 0x20344, | |
507 | .trp_ecc_error_status1 = 0x20348, | |
508 | .trp_ecc_sb_err_syn0 = 0x2034c, | |
509 | .trp_ecc_db_err_syn0 = 0x20370, | |
510 | .trp_ecc_error_cntr_clear = 0x20440, | |
511 | .trp_interrupt_0_status = 0x20480, | |
512 | .trp_interrupt_0_clear = 0x20484, | |
513 | .trp_interrupt_0_enable = 0x20488, | |
514 | ||
515 | /* LLCC Common registers */ | |
516 | .cmn_status0 = 0x3400c, | |
517 | .cmn_interrupt_0_enable = 0x3401c, | |
518 | .cmn_interrupt_2_enable = 0x3403c, | |
519 | ||
520 | /* LLCC DRP registers */ | |
521 | .drp_ecc_error_cfg = 0x50000, | |
522 | .drp_ecc_error_cntr_clear = 0x50004, | |
523 | .drp_interrupt_status = 0x50020, | |
524 | .drp_interrupt_clear = 0x50028, | |
525 | .drp_interrupt_enable = 0x5002c, | |
526 | .drp_ecc_error_status0 = 0x520f4, | |
527 | .drp_ecc_error_status1 = 0x520f8, | |
528 | .drp_ecc_sb_err_syn0 = 0x520fc, | |
529 | .drp_ecc_db_err_syn0 = 0x52120, | |
530 | }; | |
531 | ||
5365cea1 MS |
532 | /* LLCC register offset starting from v1.0.0 */ |
533 | static const u32 llcc_v1_reg_offset[] = { | |
424ad93c SPR |
534 | [LLCC_COMMON_HW_INFO] = 0x00030000, |
535 | [LLCC_COMMON_STATUS0] = 0x0003000c, | |
536 | }; | |
537 | ||
5365cea1 MS |
538 | /* LLCC register offset starting from v2.0.1 */ |
539 | static const u32 llcc_v2_1_reg_offset[] = { | |
424ad93c SPR |
540 | [LLCC_COMMON_HW_INFO] = 0x00034000, |
541 | [LLCC_COMMON_STATUS0] = 0x0003400c, | |
542 | }; | |
543 | ||
db1e5792 KB |
544 | static const struct qcom_llcc_config qdu1000_cfg[] = { |
545 | { | |
546 | .sct_data = qdu1000_data_8ch, | |
547 | .size = ARRAY_SIZE(qdu1000_data_8ch), | |
548 | .need_llcc_cfg = true, | |
549 | .reg_offset = llcc_v2_1_reg_offset, | |
550 | .edac_reg_offset = &llcc_v2_1_edac_reg_offset, | |
551 | }, | |
552 | { | |
553 | .sct_data = qdu1000_data_4ch, | |
554 | .size = ARRAY_SIZE(qdu1000_data_4ch), | |
555 | .need_llcc_cfg = true, | |
556 | .reg_offset = llcc_v2_1_reg_offset, | |
557 | .edac_reg_offset = &llcc_v2_1_edac_reg_offset, | |
558 | }, | |
559 | { | |
560 | .sct_data = qdu1000_data_4ch, | |
561 | .size = ARRAY_SIZE(qdu1000_data_4ch), | |
562 | .need_llcc_cfg = true, | |
563 | .reg_offset = llcc_v2_1_reg_offset, | |
564 | .edac_reg_offset = &llcc_v2_1_edac_reg_offset, | |
565 | }, | |
566 | { | |
567 | .sct_data = qdu1000_data_2ch, | |
568 | .size = ARRAY_SIZE(qdu1000_data_2ch), | |
569 | .need_llcc_cfg = true, | |
570 | .reg_offset = llcc_v2_1_reg_offset, | |
571 | .edac_reg_offset = &llcc_v2_1_edac_reg_offset, | |
572 | }, | |
573 | }; | |
574 | ||
fed15196 TF |
575 | static const struct qcom_llcc_config sa8775p_cfg[] = { |
576 | { | |
577 | .sct_data = sa8775p_data, | |
578 | .size = ARRAY_SIZE(sa8775p_data), | |
579 | .need_llcc_cfg = true, | |
580 | .reg_offset = llcc_v2_1_reg_offset, | |
581 | .edac_reg_offset = &llcc_v2_1_edac_reg_offset, | |
582 | }, | |
583 | }; | |
584 | ||
16fa9311 KB |
585 | static const struct qcom_llcc_config sc7180_cfg[] = { |
586 | { | |
587 | .sct_data = sc7180_data, | |
588 | .size = ARRAY_SIZE(sc7180_data), | |
589 | .need_llcc_cfg = true, | |
590 | .reg_offset = llcc_v1_reg_offset, | |
591 | .edac_reg_offset = &llcc_v1_edac_reg_offset, | |
592 | }, | |
593 | }; | |
594 | ||
595 | static const struct qcom_llcc_config sc7280_cfg[] = { | |
596 | { | |
597 | .sct_data = sc7280_data, | |
598 | .size = ARRAY_SIZE(sc7280_data), | |
599 | .need_llcc_cfg = true, | |
600 | .reg_offset = llcc_v1_reg_offset, | |
601 | .edac_reg_offset = &llcc_v1_edac_reg_offset, | |
602 | }, | |
603 | }; | |
604 | ||
605 | static const struct qcom_llcc_config sc8180x_cfg[] = { | |
606 | { | |
607 | .sct_data = sc8180x_data, | |
608 | .size = ARRAY_SIZE(sc8180x_data), | |
609 | .need_llcc_cfg = true, | |
610 | .reg_offset = llcc_v1_reg_offset, | |
611 | .edac_reg_offset = &llcc_v1_edac_reg_offset, | |
612 | }, | |
613 | }; | |
614 | ||
615 | static const struct qcom_llcc_config sc8280xp_cfg[] = { | |
616 | { | |
617 | .sct_data = sc8280xp_data, | |
618 | .size = ARRAY_SIZE(sc8280xp_data), | |
619 | .need_llcc_cfg = true, | |
620 | .reg_offset = llcc_v1_reg_offset, | |
621 | .edac_reg_offset = &llcc_v1_edac_reg_offset, | |
622 | }, | |
623 | }; | |
624 | ||
625 | static const struct qcom_llcc_config sdm845_cfg[] = { | |
626 | { | |
627 | .sct_data = sdm845_data, | |
628 | .size = ARRAY_SIZE(sdm845_data), | |
629 | .need_llcc_cfg = false, | |
630 | .reg_offset = llcc_v1_reg_offset, | |
631 | .edac_reg_offset = &llcc_v1_edac_reg_offset, | |
632 | .no_edac = true, | |
633 | }, | |
634 | }; | |
635 | ||
636 | static const struct qcom_llcc_config sm6350_cfg[] = { | |
637 | { | |
638 | .sct_data = sm6350_data, | |
639 | .size = ARRAY_SIZE(sm6350_data), | |
640 | .need_llcc_cfg = true, | |
641 | .reg_offset = llcc_v1_reg_offset, | |
642 | .edac_reg_offset = &llcc_v1_edac_reg_offset, | |
643 | }, | |
644 | }; | |
645 | ||
646 | static const struct qcom_llcc_config sm7150_cfg[] = { | |
647 | { | |
648 | .sct_data = sm7150_data, | |
649 | .size = ARRAY_SIZE(sm7150_data), | |
650 | .need_llcc_cfg = true, | |
651 | .reg_offset = llcc_v1_reg_offset, | |
652 | .edac_reg_offset = &llcc_v1_edac_reg_offset, | |
653 | }, | |
654 | }; | |
655 | ||
656 | static const struct qcom_llcc_config sm8150_cfg[] = { | |
657 | { | |
658 | .sct_data = sm8150_data, | |
659 | .size = ARRAY_SIZE(sm8150_data), | |
660 | .need_llcc_cfg = true, | |
661 | .reg_offset = llcc_v1_reg_offset, | |
662 | .edac_reg_offset = &llcc_v1_edac_reg_offset, | |
663 | }, | |
664 | }; | |
665 | ||
666 | static const struct qcom_llcc_config sm8250_cfg[] = { | |
667 | { | |
668 | .sct_data = sm8250_data, | |
669 | .size = ARRAY_SIZE(sm8250_data), | |
670 | .need_llcc_cfg = true, | |
671 | .reg_offset = llcc_v1_reg_offset, | |
672 | .edac_reg_offset = &llcc_v1_edac_reg_offset, | |
673 | }, | |
674 | }; | |
675 | ||
676 | static const struct qcom_llcc_config sm8350_cfg[] = { | |
677 | { | |
678 | .sct_data = sm8350_data, | |
679 | .size = ARRAY_SIZE(sm8350_data), | |
680 | .need_llcc_cfg = true, | |
681 | .reg_offset = llcc_v1_reg_offset, | |
682 | .edac_reg_offset = &llcc_v1_edac_reg_offset, | |
683 | }, | |
669f7880 VG |
684 | }; |
685 | ||
16fa9311 KB |
686 | static const struct qcom_llcc_config sm8450_cfg[] = { |
687 | { | |
688 | .sct_data = sm8450_data, | |
689 | .size = ARRAY_SIZE(sm8450_data), | |
690 | .need_llcc_cfg = true, | |
691 | .reg_offset = llcc_v2_1_reg_offset, | |
692 | .edac_reg_offset = &llcc_v2_1_edac_reg_offset, | |
693 | }, | |
694 | }; | |
695 | ||
696 | static const struct qcom_llcc_config sm8550_cfg[] = { | |
697 | { | |
698 | .sct_data = sm8550_data, | |
699 | .size = ARRAY_SIZE(sm8550_data), | |
700 | .need_llcc_cfg = true, | |
701 | .reg_offset = llcc_v2_1_reg_offset, | |
702 | .edac_reg_offset = &llcc_v2_1_edac_reg_offset, | |
703 | }, | |
704 | }; | |
705 | ||
7a280fec NA |
706 | static const struct qcom_llcc_config sm8650_cfg[] = { |
707 | { | |
708 | .sct_data = sm8650_data, | |
709 | .size = ARRAY_SIZE(sm8650_data), | |
710 | .need_llcc_cfg = true, | |
711 | .reg_offset = llcc_v2_1_reg_offset, | |
712 | .edac_reg_offset = &llcc_v2_1_edac_reg_offset, | |
713 | }, | |
714 | }; | |
715 | ||
b3cf69a4 RN |
716 | static const struct qcom_llcc_config x1e80100_cfg[] = { |
717 | { | |
718 | .sct_data = x1e80100_data, | |
719 | .size = ARRAY_SIZE(x1e80100_data), | |
720 | .need_llcc_cfg = true, | |
721 | .reg_offset = llcc_v2_1_reg_offset, | |
722 | .edac_reg_offset = &llcc_v2_1_edac_reg_offset, | |
723 | }, | |
724 | }; | |
725 | ||
db1e5792 KB |
726 | static const struct qcom_sct_config qdu1000_cfgs = { |
727 | .llcc_config = qdu1000_cfg, | |
728 | .num_config = ARRAY_SIZE(qdu1000_cfg), | |
729 | }; | |
730 | ||
fed15196 TF |
731 | static const struct qcom_sct_config sa8775p_cfgs = { |
732 | .llcc_config = sa8775p_cfg, | |
733 | .num_config = ARRAY_SIZE(sa8775p_cfg), | |
734 | }; | |
735 | ||
16fa9311 KB |
736 | static const struct qcom_sct_config sc7180_cfgs = { |
737 | .llcc_config = sc7180_cfg, | |
738 | .num_config = ARRAY_SIZE(sc7180_cfg), | |
739 | }; | |
740 | ||
741 | static const struct qcom_sct_config sc7280_cfgs = { | |
742 | .llcc_config = sc7280_cfg, | |
743 | .num_config = ARRAY_SIZE(sc7280_cfg), | |
f6a07be6 SPR |
744 | }; |
745 | ||
16fa9311 KB |
746 | static const struct qcom_sct_config sc8180x_cfgs = { |
747 | .llcc_config = sc8180x_cfg, | |
748 | .num_config = ARRAY_SIZE(sc8180x_cfg), | |
ec69dfbd BA |
749 | }; |
750 | ||
16fa9311 KB |
751 | static const struct qcom_sct_config sc8280xp_cfgs = { |
752 | .llcc_config = sc8280xp_cfg, | |
753 | .num_config = ARRAY_SIZE(sc8280xp_cfg), | |
ec69dfbd BA |
754 | }; |
755 | ||
16fa9311 KB |
756 | static const struct qcom_sct_config sdm845_cfgs = { |
757 | .llcc_config = sdm845_cfg, | |
758 | .num_config = ARRAY_SIZE(sdm845_cfg), | |
99356b03 VG |
759 | }; |
760 | ||
16fa9311 KB |
761 | static const struct qcom_sct_config sm6350_cfgs = { |
762 | .llcc_config = sm6350_cfg, | |
763 | .num_config = ARRAY_SIZE(sm6350_cfg), | |
1f7b2b63 KD |
764 | }; |
765 | ||
16fa9311 KB |
766 | static const struct qcom_sct_config sm7150_cfgs = { |
767 | .llcc_config = sm7150_cfg, | |
768 | .num_config = ARRAY_SIZE(sm7150_cfg), | |
92b9d862 DT |
769 | }; |
770 | ||
16fa9311 KB |
771 | static const struct qcom_sct_config sm8150_cfgs = { |
772 | .llcc_config = sm8150_cfg, | |
773 | .num_config = ARRAY_SIZE(sm8150_cfg), | |
ded5ed04 SC |
774 | }; |
775 | ||
16fa9311 KB |
776 | static const struct qcom_sct_config sm8250_cfgs = { |
777 | .llcc_config = sm8250_cfg, | |
778 | .num_config = ARRAY_SIZE(sm8250_cfg), | |
c4df37fe MS |
779 | }; |
780 | ||
16fa9311 KB |
781 | static const struct qcom_sct_config sm8350_cfgs = { |
782 | .llcc_config = sm8350_cfg, | |
783 | .num_config = ARRAY_SIZE(sm8350_cfg), | |
6fc61c39 KD |
784 | }; |
785 | ||
16fa9311 KB |
786 | static const struct qcom_sct_config sm8450_cfgs = { |
787 | .llcc_config = sm8450_cfg, | |
788 | .num_config = ARRAY_SIZE(sm8450_cfg), | |
a6e9d7ef SPR |
789 | }; |
790 | ||
16fa9311 KB |
791 | static const struct qcom_sct_config sm8550_cfgs = { |
792 | .llcc_config = sm8550_cfg, | |
793 | .num_config = ARRAY_SIZE(sm8550_cfg), | |
8c045cd2 AV |
794 | }; |
795 | ||
7a280fec NA |
796 | static const struct qcom_sct_config sm8650_cfgs = { |
797 | .llcc_config = sm8650_cfg, | |
798 | .num_config = ARRAY_SIZE(sm8650_cfg), | |
799 | }; | |
800 | ||
b3cf69a4 RN |
801 | static const struct qcom_sct_config x1e80100_cfgs = { |
802 | .llcc_config = x1e80100_cfg, | |
803 | .num_config = ARRAY_SIZE(x1e80100_cfg), | |
804 | }; | |
805 | ||
72d1cd03 | 806 | static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; |
a3134fb0 | 807 | |
a3134fb0 RB |
808 | /** |
809 | * llcc_slice_getd - get llcc slice descriptor | |
810 | * @uid: usecase_id for the client | |
811 | * | |
a3e7259f | 812 | * A pointer to llcc slice descriptor will be returned on success |
a3134fb0 RB |
813 | * and error pointer is returned on failure |
814 | */ | |
815 | struct llcc_slice_desc *llcc_slice_getd(u32 uid) | |
816 | { | |
817 | const struct llcc_slice_config *cfg; | |
818 | struct llcc_slice_desc *desc; | |
819 | u32 sz, count; | |
820 | ||
72d1cd03 JC |
821 | if (IS_ERR(drv_data)) |
822 | return ERR_CAST(drv_data); | |
823 | ||
a3134fb0 RB |
824 | cfg = drv_data->cfg; |
825 | sz = drv_data->cfg_size; | |
826 | ||
827 | for (count = 0; cfg && count < sz; count++, cfg++) | |
828 | if (cfg->usecase_id == uid) | |
829 | break; | |
830 | ||
831 | if (count == sz || !cfg) | |
832 | return ERR_PTR(-ENODEV); | |
833 | ||
834 | desc = kzalloc(sizeof(*desc), GFP_KERNEL); | |
835 | if (!desc) | |
836 | return ERR_PTR(-ENOMEM); | |
837 | ||
838 | desc->slice_id = cfg->slice_id; | |
839 | desc->slice_size = cfg->max_cap; | |
840 | ||
841 | return desc; | |
842 | } | |
843 | EXPORT_SYMBOL_GPL(llcc_slice_getd); | |
844 | ||
845 | /** | |
ff5fed86 | 846 | * llcc_slice_putd - llcc slice descriptor |
a3134fb0 RB |
847 | * @desc: Pointer to llcc slice descriptor |
848 | */ | |
849 | void llcc_slice_putd(struct llcc_slice_desc *desc) | |
850 | { | |
e0f2cfeb JC |
851 | if (!IS_ERR_OR_NULL(desc)) |
852 | kfree(desc); | |
a3134fb0 RB |
853 | } |
854 | EXPORT_SYMBOL_GPL(llcc_slice_putd); | |
855 | ||
856 | static int llcc_update_act_ctrl(u32 sid, | |
857 | u32 act_ctrl_reg_val, u32 status) | |
858 | { | |
055afc34 | 859 | struct regmap *regmap; |
a3134fb0 | 860 | u32 act_ctrl_reg; |
c72ca343 | 861 | u32 act_clear_reg; |
a3134fb0 RB |
862 | u32 status_reg; |
863 | u32 slice_status; | |
864 | int ret; | |
865 | ||
72d1cd03 JC |
866 | if (IS_ERR(drv_data)) |
867 | return PTR_ERR(drv_data); | |
868 | ||
7f9c1362 | 869 | act_ctrl_reg = LLCC_TRP_ACT_CTRLn(sid); |
c72ca343 | 870 | act_clear_reg = LLCC_TRP_ACT_CLEARn(sid); |
7f9c1362 | 871 | status_reg = LLCC_TRP_STATUSn(sid); |
a3134fb0 RB |
872 | |
873 | /* Set the ACTIVE trigger */ | |
874 | act_ctrl_reg_val |= ACT_CTRL_ACT_TRIG; | |
7f9c1362 VNKG |
875 | ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg, |
876 | act_ctrl_reg_val); | |
a3134fb0 RB |
877 | if (ret) |
878 | return ret; | |
879 | ||
880 | /* Clear the ACTIVE trigger */ | |
881 | act_ctrl_reg_val &= ~ACT_CTRL_ACT_TRIG; | |
7f9c1362 VNKG |
882 | ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg, |
883 | act_ctrl_reg_val); | |
a3134fb0 RB |
884 | if (ret) |
885 | return ret; | |
886 | ||
c72ca343 | 887 | if (drv_data->version >= LLCC_VERSION_4_1_0_0) { |
055afc34 UC |
888 | regmap = drv_data->bcast_and_regmap ?: drv_data->bcast_regmap; |
889 | ret = regmap_read_poll_timeout(regmap, status_reg, | |
c72ca343 AV |
890 | slice_status, (slice_status & ACT_COMPLETE), |
891 | 0, LLCC_STATUS_READ_DELAY); | |
892 | if (ret) | |
893 | return ret; | |
894 | } | |
895 | ||
7f9c1362 | 896 | ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg, |
a3134fb0 RB |
897 | slice_status, !(slice_status & status), |
898 | 0, LLCC_STATUS_READ_DELAY); | |
ceeaddc1 UC |
899 | if (ret) |
900 | return ret; | |
c72ca343 AV |
901 | |
902 | if (drv_data->version >= LLCC_VERSION_4_1_0_0) | |
903 | ret = regmap_write(drv_data->bcast_regmap, act_clear_reg, | |
904 | ACT_CLEAR); | |
905 | ||
a3134fb0 RB |
906 | return ret; |
907 | } | |
908 | ||
909 | /** | |
910 | * llcc_slice_activate - Activate the llcc slice | |
911 | * @desc: Pointer to llcc slice descriptor | |
912 | * | |
913 | * A value of zero will be returned on success and a negative errno will | |
914 | * be returned in error cases | |
915 | */ | |
916 | int llcc_slice_activate(struct llcc_slice_desc *desc) | |
917 | { | |
918 | int ret; | |
919 | u32 act_ctrl_val; | |
920 | ||
32616b21 | 921 | if (IS_ERR(drv_data)) |
72d1cd03 JC |
922 | return PTR_ERR(drv_data); |
923 | ||
e0f2cfeb JC |
924 | if (IS_ERR_OR_NULL(desc)) |
925 | return -EINVAL; | |
926 | ||
a3134fb0 RB |
927 | mutex_lock(&drv_data->lock); |
928 | if (test_bit(desc->slice_id, drv_data->bitmap)) { | |
929 | mutex_unlock(&drv_data->lock); | |
930 | return 0; | |
931 | } | |
932 | ||
933 | act_ctrl_val = ACT_CTRL_OPCODE_ACTIVATE << ACT_CTRL_OPCODE_SHIFT; | |
934 | ||
935 | ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val, | |
936 | DEACTIVATE); | |
937 | if (ret) { | |
938 | mutex_unlock(&drv_data->lock); | |
939 | return ret; | |
940 | } | |
941 | ||
942 | __set_bit(desc->slice_id, drv_data->bitmap); | |
943 | mutex_unlock(&drv_data->lock); | |
944 | ||
945 | return ret; | |
946 | } | |
947 | EXPORT_SYMBOL_GPL(llcc_slice_activate); | |
948 | ||
949 | /** | |
950 | * llcc_slice_deactivate - Deactivate the llcc slice | |
951 | * @desc: Pointer to llcc slice descriptor | |
952 | * | |
953 | * A value of zero will be returned on success and a negative errno will | |
954 | * be returned in error cases | |
955 | */ | |
956 | int llcc_slice_deactivate(struct llcc_slice_desc *desc) | |
957 | { | |
958 | u32 act_ctrl_val; | |
959 | int ret; | |
960 | ||
32616b21 | 961 | if (IS_ERR(drv_data)) |
72d1cd03 JC |
962 | return PTR_ERR(drv_data); |
963 | ||
e0f2cfeb JC |
964 | if (IS_ERR_OR_NULL(desc)) |
965 | return -EINVAL; | |
966 | ||
a3134fb0 RB |
967 | mutex_lock(&drv_data->lock); |
968 | if (!test_bit(desc->slice_id, drv_data->bitmap)) { | |
969 | mutex_unlock(&drv_data->lock); | |
970 | return 0; | |
971 | } | |
972 | act_ctrl_val = ACT_CTRL_OPCODE_DEACTIVATE << ACT_CTRL_OPCODE_SHIFT; | |
973 | ||
974 | ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val, | |
975 | ACTIVATE); | |
976 | if (ret) { | |
977 | mutex_unlock(&drv_data->lock); | |
978 | return ret; | |
979 | } | |
980 | ||
981 | __clear_bit(desc->slice_id, drv_data->bitmap); | |
982 | mutex_unlock(&drv_data->lock); | |
983 | ||
984 | return ret; | |
985 | } | |
986 | EXPORT_SYMBOL_GPL(llcc_slice_deactivate); | |
987 | ||
988 | /** | |
989 | * llcc_get_slice_id - return the slice id | |
990 | * @desc: Pointer to llcc slice descriptor | |
991 | */ | |
992 | int llcc_get_slice_id(struct llcc_slice_desc *desc) | |
993 | { | |
e0f2cfeb JC |
994 | if (IS_ERR_OR_NULL(desc)) |
995 | return -EINVAL; | |
996 | ||
a3134fb0 RB |
997 | return desc->slice_id; |
998 | } | |
999 | EXPORT_SYMBOL_GPL(llcc_get_slice_id); | |
1000 | ||
1001 | /** | |
1002 | * llcc_get_slice_size - return the slice id | |
1003 | * @desc: Pointer to llcc slice descriptor | |
1004 | */ | |
1005 | size_t llcc_get_slice_size(struct llcc_slice_desc *desc) | |
1006 | { | |
e0f2cfeb JC |
1007 | if (IS_ERR_OR_NULL(desc)) |
1008 | return 0; | |
1009 | ||
a3134fb0 RB |
1010 | return desc->slice_size; |
1011 | } | |
1012 | EXPORT_SYMBOL_GPL(llcc_get_slice_size); | |
1013 | ||
c14e64b4 IM |
1014 | static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config, |
1015 | const struct qcom_llcc_config *cfg) | |
a3134fb0 | 1016 | { |
af7244c0 | 1017 | int ret; |
c72ca343 | 1018 | u32 attr2_cfg; |
a3134fb0 RB |
1019 | u32 attr1_cfg; |
1020 | u32 attr0_cfg; | |
c72ca343 | 1021 | u32 attr2_val; |
a3134fb0 RB |
1022 | u32 attr1_val; |
1023 | u32 attr0_val; | |
1024 | u32 max_cap_cacheline; | |
af7244c0 SPR |
1025 | struct llcc_slice_desc desc; |
1026 | ||
1027 | attr1_val = config->cache_mode; | |
1028 | attr1_val |= config->probe_target_ways << ATTR1_PROBE_TARGET_WAYS_SHIFT; | |
1029 | attr1_val |= config->fixed_size << ATTR1_FIXED_SIZE_SHIFT; | |
1030 | attr1_val |= config->priority << ATTR1_PRIORITY_SHIFT; | |
1031 | ||
1032 | max_cap_cacheline = MAX_CAP_TO_BYTES(config->max_cap); | |
1033 | ||
1034 | /* | |
1035 | * LLCC instances can vary for each target. | |
1036 | * The SW writes to broadcast register which gets propagated | |
1037 | * to each llcc instance (llcc0,.. llccN). | |
1038 | * Since the size of the memory is divided equally amongst the | |
1039 | * llcc instances, we need to configure the max cap accordingly. | |
1040 | */ | |
1041 | max_cap_cacheline = max_cap_cacheline / drv_data->num_banks; | |
1042 | max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT; | |
1043 | attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT; | |
1044 | ||
1045 | attr1_cfg = LLCC_TRP_ATTR1_CFGn(config->slice_id); | |
1046 | ||
1047 | ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val); | |
1048 | if (ret) | |
1049 | return ret; | |
1050 | ||
c72ca343 AV |
1051 | if (drv_data->version >= LLCC_VERSION_4_1_0_0) { |
1052 | attr2_cfg = LLCC_TRP_ATTR2_CFGn(config->slice_id); | |
1053 | attr0_val = config->res_ways; | |
1054 | attr2_val = config->bonus_ways; | |
1055 | } else { | |
1056 | attr0_val = config->res_ways & ATTR0_RES_WAYS_MASK; | |
1057 | attr0_val |= config->bonus_ways << ATTR0_BONUS_WAYS_SHIFT; | |
1058 | } | |
af7244c0 SPR |
1059 | |
1060 | attr0_cfg = LLCC_TRP_ATTR0_CFGn(config->slice_id); | |
1061 | ||
1062 | ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val); | |
1063 | if (ret) | |
1064 | return ret; | |
1065 | ||
c72ca343 AV |
1066 | if (drv_data->version >= LLCC_VERSION_4_1_0_0) { |
1067 | ret = regmap_write(drv_data->bcast_regmap, attr2_cfg, attr2_val); | |
1068 | if (ret) | |
1069 | return ret; | |
1070 | } | |
1071 | ||
c14e64b4 IM |
1072 | if (cfg->need_llcc_cfg) { |
1073 | u32 disable_cap_alloc, retain_pc; | |
1074 | ||
1075 | disable_cap_alloc = config->dis_cap_alloc << config->slice_id; | |
eed6e57e AD |
1076 | ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_SCID_DIS_CAP_ALLOC, |
1077 | BIT(config->slice_id), disable_cap_alloc); | |
c14e64b4 IM |
1078 | if (ret) |
1079 | return ret; | |
1080 | ||
c72ca343 AV |
1081 | if (drv_data->version < LLCC_VERSION_4_1_0_0) { |
1082 | retain_pc = config->retain_on_pc << config->slice_id; | |
eed6e57e AD |
1083 | ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_PCB_ACT, |
1084 | BIT(config->slice_id), retain_pc); | |
c72ca343 AV |
1085 | if (ret) |
1086 | return ret; | |
1087 | } | |
c14e64b4 IM |
1088 | } |
1089 | ||
8008e790 | 1090 | if (drv_data->version >= LLCC_VERSION_2_0_0_0) { |
c4df37fe MS |
1091 | u32 wren; |
1092 | ||
1093 | wren = config->write_scid_en << config->slice_id; | |
1094 | ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_EN, | |
1095 | BIT(config->slice_id), wren); | |
1096 | if (ret) | |
1097 | return ret; | |
1098 | } | |
1099 | ||
2b8175a1 SPR |
1100 | if (drv_data->version >= LLCC_VERSION_2_1_0_0) { |
1101 | u32 wr_cache_en; | |
1102 | ||
1103 | wr_cache_en = config->write_scid_cacheable_en << config->slice_id; | |
1104 | ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_CACHEABLE_EN, | |
1105 | BIT(config->slice_id), wr_cache_en); | |
1106 | if (ret) | |
1107 | return ret; | |
1108 | } | |
1109 | ||
c72ca343 AV |
1110 | if (drv_data->version >= LLCC_VERSION_4_1_0_0) { |
1111 | u32 stale_en; | |
1112 | u32 stale_cap_en; | |
1113 | u32 mru_uncap_en; | |
1114 | u32 mru_rollover; | |
1115 | u32 alloc_oneway_en; | |
1116 | u32 ovcap_en; | |
1117 | u32 ovcap_prio; | |
1118 | u32 vict_prio; | |
1119 | ||
1120 | stale_en = config->stale_en << config->slice_id; | |
1121 | ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG1, | |
1122 | BIT(config->slice_id), stale_en); | |
1123 | if (ret) | |
1124 | return ret; | |
1125 | ||
1126 | stale_cap_en = config->stale_cap_en << config->slice_id; | |
1127 | ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG2, | |
1128 | BIT(config->slice_id), stale_cap_en); | |
1129 | if (ret) | |
1130 | return ret; | |
1131 | ||
1132 | mru_uncap_en = config->mru_uncap_en << config->slice_id; | |
1133 | ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG3, | |
1134 | BIT(config->slice_id), mru_uncap_en); | |
1135 | if (ret) | |
1136 | return ret; | |
1137 | ||
1138 | mru_rollover = config->mru_rollover << config->slice_id; | |
1139 | ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG4, | |
1140 | BIT(config->slice_id), mru_rollover); | |
1141 | if (ret) | |
1142 | return ret; | |
1143 | ||
1144 | alloc_oneway_en = config->alloc_oneway_en << config->slice_id; | |
1145 | ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG5, | |
1146 | BIT(config->slice_id), alloc_oneway_en); | |
1147 | if (ret) | |
1148 | return ret; | |
1149 | ||
1150 | ovcap_en = config->ovcap_en << config->slice_id; | |
1151 | ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG6, | |
1152 | BIT(config->slice_id), ovcap_en); | |
1153 | if (ret) | |
1154 | return ret; | |
1155 | ||
1156 | ovcap_prio = config->ovcap_prio << config->slice_id; | |
1157 | ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG7, | |
1158 | BIT(config->slice_id), ovcap_prio); | |
1159 | if (ret) | |
1160 | return ret; | |
1161 | ||
1162 | vict_prio = config->vict_prio << config->slice_id; | |
1163 | ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG8, | |
1164 | BIT(config->slice_id), vict_prio); | |
1165 | if (ret) | |
1166 | return ret; | |
1167 | } | |
1168 | ||
af7244c0 SPR |
1169 | if (config->activate_on_init) { |
1170 | desc.slice_id = config->slice_id; | |
1171 | ret = llcc_slice_activate(&desc); | |
1172 | } | |
1173 | ||
1174 | return ret; | |
1175 | } | |
1176 | ||
c14e64b4 IM |
1177 | static int qcom_llcc_cfg_program(struct platform_device *pdev, |
1178 | const struct qcom_llcc_config *cfg) | |
af7244c0 SPR |
1179 | { |
1180 | int i; | |
a3134fb0 | 1181 | u32 sz; |
c081f306 | 1182 | int ret = 0; |
a3134fb0 | 1183 | const struct llcc_slice_config *llcc_table; |
a3134fb0 RB |
1184 | |
1185 | sz = drv_data->cfg_size; | |
1186 | llcc_table = drv_data->cfg; | |
1187 | ||
1188 | for (i = 0; i < sz; i++) { | |
c14e64b4 | 1189 | ret = _qcom_llcc_cfg_program(&llcc_table[i], cfg); |
a3134fb0 RB |
1190 | if (ret) |
1191 | return ret; | |
a3134fb0 | 1192 | } |
af7244c0 | 1193 | |
a3134fb0 RB |
1194 | return ret; |
1195 | } | |
1196 | ||
a78502a4 KB |
1197 | static int qcom_llcc_get_cfg_index(struct platform_device *pdev, u8 *cfg_index, int num_config) |
1198 | { | |
1199 | int ret; | |
1200 | ||
1201 | ret = nvmem_cell_read_u8(&pdev->dev, "multi-chan-ddr", cfg_index); | |
1202 | if (ret == -ENOENT || ret == -EOPNOTSUPP) { | |
1203 | if (num_config > 1) | |
1204 | return -EINVAL; | |
1205 | *cfg_index = 0; | |
1206 | return 0; | |
1207 | } | |
1208 | ||
1209 | if (!ret && *cfg_index >= num_config) | |
1210 | ret = -EINVAL; | |
1211 | ||
1212 | return ret; | |
1213 | } | |
1214 | ||
d85a9d18 | 1215 | static void qcom_llcc_remove(struct platform_device *pdev) |
72d1cd03 JC |
1216 | { |
1217 | /* Set the global pointer to a error code to avoid referencing it */ | |
1218 | drv_data = ERR_PTR(-ENODEV); | |
72d1cd03 | 1219 | } |
72d1cd03 | 1220 | |
ee13b500 MS |
1221 | static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, u8 index, |
1222 | const char *name) | |
ed10a259 | 1223 | { |
ed10a259 | 1224 | void __iomem *base; |
acbf73bf SB |
1225 | struct regmap_config llcc_regmap_config = { |
1226 | .reg_bits = 32, | |
1227 | .reg_stride = 4, | |
1228 | .val_bits = 32, | |
1229 | .fast_io = true, | |
1230 | }; | |
ed10a259 | 1231 | |
ee13b500 | 1232 | base = devm_platform_ioremap_resource(pdev, index); |
ed10a259 JC |
1233 | if (IS_ERR(base)) |
1234 | return ERR_CAST(base); | |
1235 | ||
2bfd3e76 | 1236 | llcc_regmap_config.name = name; |
ed10a259 JC |
1237 | return devm_regmap_init_mmio(&pdev->dev, base, &llcc_regmap_config); |
1238 | } | |
1239 | ||
99356b03 | 1240 | static int qcom_llcc_probe(struct platform_device *pdev) |
a3134fb0 RB |
1241 | { |
1242 | u32 num_banks; | |
1243 | struct device *dev = &pdev->dev; | |
a3134fb0 | 1244 | int ret, i; |
c081f306 | 1245 | struct platform_device *llcc_edac; |
16fa9311 | 1246 | const struct qcom_sct_config *cfgs; |
99356b03 VG |
1247 | const struct qcom_llcc_config *cfg; |
1248 | const struct llcc_slice_config *llcc_cfg; | |
1249 | u32 sz; | |
a78502a4 | 1250 | u8 cfg_index; |
916c0c05 | 1251 | u32 version; |
ee13b500 | 1252 | struct regmap *regmap; |
a3134fb0 | 1253 | |
f1a1bc87 UKK |
1254 | if (!IS_ERR(drv_data)) |
1255 | return -EBUSY; | |
1256 | ||
a3134fb0 | 1257 | drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); |
72d1cd03 JC |
1258 | if (!drv_data) { |
1259 | ret = -ENOMEM; | |
1260 | goto err; | |
1261 | } | |
a3134fb0 | 1262 | |
ee13b500 MS |
1263 | /* Initialize the first LLCC bank regmap */ |
1264 | regmap = qcom_llcc_init_mmio(pdev, 0, "llcc0_base"); | |
1265 | if (IS_ERR(regmap)) { | |
1266 | ret = PTR_ERR(regmap); | |
72d1cd03 JC |
1267 | goto err; |
1268 | } | |
a3134fb0 | 1269 | |
16fa9311 KB |
1270 | cfgs = of_device_get_match_data(&pdev->dev); |
1271 | if (!cfgs) { | |
1272 | ret = -EINVAL; | |
1273 | goto err; | |
1274 | } | |
a78502a4 KB |
1275 | ret = qcom_llcc_get_cfg_index(pdev, &cfg_index, cfgs->num_config); |
1276 | if (ret) | |
1277 | goto err; | |
1278 | cfg = &cfgs->llcc_config[cfg_index]; | |
ee13b500 MS |
1279 | |
1280 | ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks); | |
1281 | if (ret) | |
1282 | goto err; | |
1283 | ||
1284 | num_banks &= LLCC_LB_CNT_MASK; | |
1285 | num_banks >>= LLCC_LB_CNT_SHIFT; | |
1286 | drv_data->num_banks = num_banks; | |
1287 | ||
1288 | drv_data->regmaps = devm_kcalloc(dev, num_banks, sizeof(*drv_data->regmaps), GFP_KERNEL); | |
1289 | if (!drv_data->regmaps) { | |
1290 | ret = -ENOMEM; | |
72d1cd03 JC |
1291 | goto err; |
1292 | } | |
a3134fb0 | 1293 | |
ee13b500 MS |
1294 | drv_data->regmaps[0] = regmap; |
1295 | ||
1296 | /* Initialize rest of LLCC bank regmaps */ | |
1297 | for (i = 1; i < num_banks; i++) { | |
04e60d7a | 1298 | char *base __free(kfree) = kasprintf(GFP_KERNEL, "llcc%d_base", i); |
ee13b500 MS |
1299 | |
1300 | drv_data->regmaps[i] = qcom_llcc_init_mmio(pdev, i, base); | |
1301 | if (IS_ERR(drv_data->regmaps[i])) { | |
1302 | ret = PTR_ERR(drv_data->regmaps[i]); | |
ee13b500 MS |
1303 | goto err; |
1304 | } | |
ee13b500 MS |
1305 | } |
1306 | ||
1307 | drv_data->bcast_regmap = qcom_llcc_init_mmio(pdev, i, "llcc_broadcast_base"); | |
72d1cd03 JC |
1308 | if (IS_ERR(drv_data->bcast_regmap)) { |
1309 | ret = PTR_ERR(drv_data->bcast_regmap); | |
1310 | goto err; | |
1311 | } | |
7f9c1362 | 1312 | |
8008e790 | 1313 | /* Extract version of the IP */ |
424ad93c SPR |
1314 | ret = regmap_read(drv_data->bcast_regmap, cfg->reg_offset[LLCC_COMMON_HW_INFO], |
1315 | &version); | |
916c0c05 SPR |
1316 | if (ret) |
1317 | goto err; | |
1318 | ||
8008e790 | 1319 | drv_data->version = version; |
916c0c05 | 1320 | |
055afc34 UC |
1321 | /* Applicable only when drv_data->version >= 4.1 */ |
1322 | if (drv_data->version >= LLCC_VERSION_4_1_0_0) { | |
1323 | drv_data->bcast_and_regmap = qcom_llcc_init_mmio(pdev, i + 1, "llcc_broadcast_and_base"); | |
1324 | if (IS_ERR(drv_data->bcast_and_regmap)) { | |
1325 | ret = PTR_ERR(drv_data->bcast_and_regmap); | |
1326 | if (ret == -EINVAL) | |
1327 | drv_data->bcast_and_regmap = NULL; | |
1328 | else | |
1329 | goto err; | |
1330 | } | |
1331 | } | |
1332 | ||
99356b03 VG |
1333 | llcc_cfg = cfg->sct_data; |
1334 | sz = cfg->size; | |
1335 | ||
a3134fb0 RB |
1336 | for (i = 0; i < sz; i++) |
1337 | if (llcc_cfg[i].slice_id > drv_data->max_slices) | |
1338 | drv_data->max_slices = llcc_cfg[i].slice_id; | |
1339 | ||
a9ff0638 CJ |
1340 | drv_data->bitmap = devm_bitmap_zalloc(dev, drv_data->max_slices, |
1341 | GFP_KERNEL); | |
72d1cd03 JC |
1342 | if (!drv_data->bitmap) { |
1343 | ret = -ENOMEM; | |
1344 | goto err; | |
1345 | } | |
a3134fb0 RB |
1346 | |
1347 | drv_data->cfg = llcc_cfg; | |
1348 | drv_data->cfg_size = sz; | |
c13d7d26 | 1349 | drv_data->edac_reg_offset = cfg->edac_reg_offset; |
a3134fb0 RB |
1350 | mutex_init(&drv_data->lock); |
1351 | platform_set_drvdata(pdev, drv_data); | |
1352 | ||
c14e64b4 | 1353 | ret = qcom_llcc_cfg_program(pdev, cfg); |
c081f306 | 1354 | if (ret) |
72d1cd03 | 1355 | goto err; |
c081f306 | 1356 | |
c882c899 | 1357 | drv_data->ecc_irq = platform_get_irq_optional(pdev, 0); |
721d3e91 | 1358 | |
cca94f1d MS |
1359 | /* |
1360 | * On some platforms, the access to EDAC registers will be locked by | |
1361 | * the bootloader. So probing the EDAC driver will result in a crash. | |
1362 | * Hence, disable the creation of EDAC platform device for the | |
1363 | * problematic platforms. | |
1364 | */ | |
1365 | if (!cfg->no_edac) { | |
c081f306 VNKG |
1366 | llcc_edac = platform_device_register_data(&pdev->dev, |
1367 | "qcom_llcc_edac", -1, drv_data, | |
1368 | sizeof(*drv_data)); | |
1369 | if (IS_ERR(llcc_edac)) | |
1370 | dev_err(dev, "Failed to register llcc edac driver\n"); | |
1371 | } | |
1372 | ||
72d1cd03 JC |
1373 | return 0; |
1374 | err: | |
1375 | drv_data = ERR_PTR(-ENODEV); | |
c081f306 | 1376 | return ret; |
a3134fb0 | 1377 | } |
a14b8203 | 1378 | |
99356b03 | 1379 | static const struct of_device_id qcom_llcc_of_match[] = { |
db1e5792 | 1380 | { .compatible = "qcom,qdu1000-llcc", .data = &qdu1000_cfgs}, |
fed15196 | 1381 | { .compatible = "qcom,sa8775p-llcc", .data = &sa8775p_cfgs }, |
16fa9311 KB |
1382 | { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfgs }, |
1383 | { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfgs }, | |
1384 | { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfgs }, | |
1385 | { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfgs }, | |
1386 | { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfgs }, | |
1387 | { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfgs }, | |
1388 | { .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfgs }, | |
1389 | { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfgs }, | |
1390 | { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfgs }, | |
1391 | { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfgs }, | |
1392 | { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfgs }, | |
1393 | { .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfgs }, | |
7a280fec | 1394 | { .compatible = "qcom,sm8650-llcc", .data = &sm8650_cfgs }, |
b3cf69a4 | 1395 | { .compatible = "qcom,x1e80100-llcc", .data = &x1e80100_cfgs }, |
a14b8203 VG |
1396 | { } |
1397 | }; | |
5334a3b1 | 1398 | MODULE_DEVICE_TABLE(of, qcom_llcc_of_match); |
a14b8203 | 1399 | |
99356b03 | 1400 | static struct platform_driver qcom_llcc_driver = { |
a14b8203 | 1401 | .driver = { |
99356b03 VG |
1402 | .name = "qcom-llcc", |
1403 | .of_match_table = qcom_llcc_of_match, | |
a14b8203 | 1404 | }, |
99356b03 | 1405 | .probe = qcom_llcc_probe, |
d85a9d18 | 1406 | .remove_new = qcom_llcc_remove, |
a14b8203 | 1407 | }; |
99356b03 | 1408 | module_platform_driver(qcom_llcc_driver); |
a14b8203 | 1409 | |
99356b03 | 1410 | MODULE_DESCRIPTION("Qualcomm Last Level Cache Controller"); |
4da3b045 | 1411 | MODULE_LICENSE("GPL v2"); |