projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'qcom-drivers-for-6.7' of https://git.kernel.org/pub/scm/linux/kernel/git...
[linux-block.git] / drivers / soc / qcom / llcc-qcom.c
CommitLineData
a3134fb0
RB		 1// SPDX-License-Identifier: GPL-2.0
2/*
a14b8203 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
a3134fb0
RB		 4 *
5 */
6
916c0c05 7#include <linux/bitfield.h>
a3134fb0
RB		 8#include <linux/bitmap.h>
9#include <linux/bitops.h>
10#include <linux/device.h>
11#include <linux/io.h>
12#include <linux/kernel.h>
4da3b045 13#include <linux/module.h>
a3134fb0 14#include <linux/mutex.h>
a78502a4 15#include <linux/nvmem-consumer.h>
a14b8203 16#include <linux/of.h>
a3134fb0 17#include <linux/regmap.h>
da8eaf9a 18#include <linux/sizes.h>
a3134fb0
RB		 19#include <linux/slab.h>
20#include <linux/soc/qcom/llcc-qcom.h>
21
22#define ACTIVATE BIT(0)
23#define DEACTIVATE BIT(1)
c72ca343
AV		 24#define ACT_CLEAR BIT(0)
25#define ACT_COMPLETE BIT(4)
a3134fb0
RB		 26#define ACT_CTRL_OPCODE_ACTIVATE BIT(0)
27#define ACT_CTRL_OPCODE_DEACTIVATE BIT(1)
28#define ACT_CTRL_ACT_TRIG BIT(0)
29#define ACT_CTRL_OPCODE_SHIFT 0x01
30#define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x02
31#define ATTR1_FIXED_SIZE_SHIFT 0x03
32#define ATTR1_PRIORITY_SHIFT 0x04
33#define ATTR1_MAX_CAP_SHIFT 0x10
06b24ab3
HY		 34#define ATTR0_RES_WAYS_MASK GENMASK(15, 0)
35#define ATTR0_BONUS_WAYS_MASK GENMASK(31, 16)
a3134fb0
RB		 36#define ATTR0_BONUS_WAYS_SHIFT 0x10
37#define LLCC_STATUS_READ_DELAY 100
38
39#define CACHE_LINE_SIZE_SHIFT 6
40
a3134fb0
RB		 41#define LLCC_LB_CNT_MASK GENMASK(31, 28)
42#define LLCC_LB_CNT_SHIFT 28
43
44#define MAX_CAP_TO_BYTES(n) (n * SZ_1K)
45#define LLCC_TRP_ACT_CTRLn(n) (n * SZ_4K)
c72ca343 46#define LLCC_TRP_ACT_CLEARn(n) (8 + n * SZ_4K)
a3134fb0
RB		 47#define LLCC_TRP_STATUSn(n) (4 + n * SZ_4K)
48#define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n)
49#define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n)
c72ca343 50#define LLCC_TRP_ATTR2_CFGn(n) (0x21100 + SZ_8 * n)
a3134fb0 51
c14e64b4
IM		 52#define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00
53#define LLCC_TRP_PCB_ACT 0x21f04
c72ca343
AV		 54#define LLCC_TRP_ALGO_CFG1 0x21f0c
55#define LLCC_TRP_ALGO_CFG2 0x21f10
56#define LLCC_TRP_ALGO_CFG3 0x21f14
57#define LLCC_TRP_ALGO_CFG4 0x21f18
58#define LLCC_TRP_ALGO_CFG5 0x21f1c
c4df37fe 59#define LLCC_TRP_WRSC_EN 0x21f20
c72ca343
AV		 60#define LLCC_TRP_ALGO_CFG6 0x21f24
61#define LLCC_TRP_ALGO_CFG7 0x21f28
2b8175a1 62#define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c
c72ca343 63#define LLCC_TRP_ALGO_CFG8 0x21f30
c14e64b4 64
8008e790 65#define LLCC_VERSION_2_0_0_0 0x02000000
2b8175a1 66#define LLCC_VERSION_2_1_0_0 0x02010000
c72ca343 67#define LLCC_VERSION_4_1_0_0 0x04010000
8008e790 68
99356b03 69/**
171c0317 70 * struct llcc_slice_config - Data associated with the llcc slice
99356b03
VG		 71 * @usecase_id: Unique id for the client's use case
72 * @slice_id: llcc slice id for each client
73 * @max_cap: The maximum capacity of the cache slice provided in KB
74 * @priority: Priority of the client used to select victim line for replacement
75 * @fixed_size: Boolean indicating if the slice has a fixed capacity
76 * @bonus_ways: Bonus ways are additional ways to be used for any slice,
77 * if client ends up using more than reserved cache ways. Bonus
78 * ways are allocated only if they are not reserved for some
79 * other client.
80 * @res_ways: Reserved ways for the cache slice, the reserved ways cannot
81 * be used by any other client than the one its assigned to.
82 * @cache_mode: Each slice operates as a cache, this controls the mode of the
83 * slice: normal or TCM(Tightly Coupled Memory)
84 * @probe_target_ways: Determines what ways to probe for access hit. When
85 * configured to 1 only bonus and reserved ways are probed.
86 * When configured to 0 all ways in llcc are probed.
87 * @dis_cap_alloc: Disable capacity based allocation for a client
88 * @retain_on_pc: If this bit is set and client has maintained active vote
89 * then the ways assigned to this client are not flushed on power
90 * collapse.
91 * @activate_on_init: Activate the slice immediately after it is programmed
c4df37fe 92 * @write_scid_en: Bit enables write cache support for a given scid.
2b8175a1
SPR		 93 * @write_scid_cacheable_en: Enables write cache cacheable support for a
94 * given scid (not supported on v2 or older hardware).
99356b03
VG		 95 */
96struct llcc_slice_config {
97 u32 usecase_id;
98 u32 slice_id;
99 u32 max_cap;
100 u32 priority;
101 bool fixed_size;
102 u32 bonus_ways;
103 u32 res_ways;
104 u32 cache_mode;
105 u32 probe_target_ways;
106 bool dis_cap_alloc;
107 bool retain_on_pc;
108 bool activate_on_init;
c4df37fe 109 bool write_scid_en;
2b8175a1 110 bool write_scid_cacheable_en;
c72ca343
AV		 111 bool stale_en;
112 bool stale_cap_en;
113 bool mru_uncap_en;
114 bool mru_rollover;
115 bool alloc_oneway_en;
116 bool ovcap_en;
117 bool ovcap_prio;
118 bool vict_prio;
99356b03
VG		 119};
120
99356b03
VG		 121struct qcom_llcc_config {
122 const struct llcc_slice_config *sct_data;
424ad93c 123 const u32 *reg_offset;
c13d7d26 124 const struct llcc_edac_reg_offset *edac_reg_offset;
cca94f1d
MS		 125 int size;
126 bool need_llcc_cfg;
127 bool no_edac;
424ad93c
SPR		 128};
129
16fa9311
KB		 130struct qcom_sct_config {
131 const struct qcom_llcc_config *llcc_config;
132 int num_config;
133};
134
424ad93c
SPR		 135enum llcc_reg_offset {
136 LLCC_COMMON_HW_INFO,
137 LLCC_COMMON_STATUS0,
99356b03
VG		 138};
139
669f7880
VG		 140static const struct llcc_slice_config sc7180_data[] = {
141 { LLCC_CPUSS, 1, 256, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 1 },
142 { LLCC_MDM, 8, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
143 { LLCC_GPUHTW, 11, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
144 { LLCC_GPU, 12, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
145};
146
f6a07be6
SPR		 147static const struct llcc_slice_config sc7280_data[] = {
148 { LLCC_CPUSS, 1, 768, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 1, 0},
149 { LLCC_MDMHPGRW, 7, 512, 2, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
150 { LLCC_CMPT, 10, 768, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
151 { LLCC_GPUHTW, 11, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
152 { LLCC_GPU, 12, 512, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
3a461009 153 { LLCC_MMUHWT, 13, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 0, 1, 0},
f6a07be6
SPR		 154 { LLCC_MDMPNG, 21, 768, 0, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
155 { LLCC_WLHW, 24, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
156 { LLCC_MODPE, 29, 64, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
157};
158
ec69dfbd
BA		 159static const struct llcc_slice_config sc8180x_data[] = {
160 { LLCC_CPUSS, 1, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1 },
161 { LLCC_VIDSC0, 2, 512, 2, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
162 { LLCC_VIDSC1, 3, 512, 2, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
163 { LLCC_AUDIO, 6, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
164 { LLCC_MDMHPGRW, 7, 3072, 1, 1, 0x3ff, 0xc00, 0, 0, 0, 1, 0 },
165 { LLCC_MDM, 8, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
166 { LLCC_MODHW, 9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
167 { LLCC_CMPT, 10, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
168 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
169 { LLCC_GPU, 12, 5120, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
170 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1 },
171 { LLCC_CMPTDMA, 15, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
172 { LLCC_DISP, 16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
173 { LLCC_VIDFW, 17, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
174 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
175 { LLCC_MDMPNG, 21, 1024, 0, 1, 0xc, 0x0, 0, 0, 0, 1, 0 },
176 { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
177 { LLCC_NPU, 23, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
178 { LLCC_WLHW, 24, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
179 { LLCC_MODPE, 29, 512, 1, 1, 0xc, 0x0, 0, 0, 0, 1, 0 },
180 { LLCC_APTCM, 30, 512, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0 },
181 { LLCC_WRCACHE, 31, 128, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0 },
182};
183
184static const struct llcc_slice_config sc8280xp_data[] = {
185 { LLCC_CPUSS, 1, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 },
186 { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
187 { LLCC_AUDIO, 6, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 },
188 { LLCC_CMPT, 10, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 },
189 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
190 { LLCC_GPU, 12, 4096, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 },
191 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
192 { LLCC_DISP, 16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
193 { LLCC_AUDHW, 22, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
0bc76be6 194 { LLCC_ECC, 26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
ec69dfbd
BA		 195 { LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
196 { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0, 0 },
197 { LLCC_WRCACHE, 31, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
77bf4b3e
AV		 198 { LLCC_CVPFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
199 { LLCC_CPUSS1, 3, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
200 { LLCC_CPUHWT, 5, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
ec69dfbd
BA		 201};
202
669f7880 203static const struct llcc_slice_config sdm845_data[] = {
a14b8203
VG		 204 { LLCC_CPUSS, 1, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 1 },
205 { LLCC_VIDSC0, 2, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 },
206 { LLCC_VIDSC1, 3, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 },
207 { LLCC_ROTATOR, 4, 563, 2, 1, 0x0, 0x00e, 2, 0, 1, 1, 0 },
208 { LLCC_VOICE, 5, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
209 { LLCC_AUDIO, 6, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
210 { LLCC_MDMHPGRW, 7, 1024, 2, 0, 0xfc, 0xf00, 0, 0, 1, 1, 0 },
211 { LLCC_MDM, 8, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
212 { LLCC_CMPT, 10, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
213 { LLCC_GPUHTW, 11, 512, 1, 1, 0xc, 0x0, 0, 0, 1, 1, 0 },
214 { LLCC_GPU, 12, 2304, 1, 0, 0xff0, 0x2, 0, 0, 1, 1, 0 },
215 { LLCC_MMUHWT, 13, 256, 2, 0, 0x0, 0x1, 0, 0, 1, 0, 1 },
216 { LLCC_CMPTDMA, 15, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
217 { LLCC_DISP, 16, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
218 { LLCC_VIDFW, 17, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
219 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0x0, 0xf00, 0, 0, 1, 1, 0 },
220 { LLCC_MDMPNG, 21, 1024, 0, 1, 0x1e, 0x0, 0, 0, 1, 1, 0 },
221 { LLCC_AUDHW, 22, 1024, 1, 1, 0xffc, 0x2, 0, 0, 1, 1, 0 },
222};
223
1f7b2b63
KD		 224static const struct llcc_slice_config sm6350_data[] = {
225 { LLCC_CPUSS, 1, 768, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 1 },
226 { LLCC_MDM, 8, 512, 2, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
227 { LLCC_GPUHTW, 11, 256, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
228 { LLCC_GPU, 12, 512, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
229 { LLCC_MDMPNG, 21, 768, 0, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
230 { LLCC_NPU, 23, 768, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
231 { LLCC_MODPE, 29, 64, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
232};
233
92b9d862
DT		 234static const struct llcc_slice_config sm7150_data[] = {
235 { LLCC_CPUSS, 1, 512, 1, 0, 0xF, 0x0, 0, 0, 0, 1, 1 },
236 { LLCC_MDM, 8, 128, 2, 0, 0xF, 0x0, 0, 0, 0, 1, 0 },
237 { LLCC_GPUHTW, 11, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 },
238 { LLCC_GPU, 12, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 },
239 { LLCC_NPU, 23, 512, 1, 0, 0xF, 0x0, 0, 0, 0, 1, 0 },
240};
241
ded5ed04
SC		 242static const struct llcc_slice_config sm8150_data[] = {
243 { LLCC_CPUSS, 1, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 1 },
244 { LLCC_VIDSC0, 2, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
245 { LLCC_VIDSC1, 3, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
246 { LLCC_AUDIO, 6, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
247 { LLCC_MDMHPGRW, 7, 3072, 1, 0, 0xFF, 0xF00, 0, 0, 0, 1, 0 },
248 { LLCC_MDM, 8, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
249 { LLCC_MODHW, 9, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
250 { LLCC_CMPT, 10, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
251 { LLCC_GPUHTW , 11, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
252 { LLCC_GPU, 12, 2560, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
253 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1 },
254 { LLCC_CMPTDMA, 15, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
255 { LLCC_DISP, 16, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
256 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
257 { LLCC_MDMHPFX, 21, 1024, 0, 1, 0xF, 0x0, 0, 0, 0, 1, 0 },
258 { LLCC_AUDHW, 22, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
259 { LLCC_NPU, 23, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
260 { LLCC_WLHW, 24, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
261 { LLCC_MODPE, 29, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 },
262 { LLCC_APTCM, 30, 256, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0 },
263 { LLCC_WRCACHE, 31, 128, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0 },
264};
265
c4df37fe
MS		 266static const struct llcc_slice_config sm8250_data[] = {
267 { LLCC_CPUSS, 1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 },
268 { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
269 { LLCC_AUDIO, 6, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 },
270 { LLCC_CMPT, 10, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 },
271 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
272 { LLCC_GPU, 12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 },
273 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
274 { LLCC_CMPTDMA, 15, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
275 { LLCC_DISP, 16, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
276 { LLCC_VIDFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
277 { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
278 { LLCC_NPU, 23, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
279 { LLCC_WLHW, 24, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
280 { LLCC_CVP, 28, 256, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
281 { LLCC_APTCM, 30, 128, 3, 0, 0x0, 0x3, 1, 0, 0, 1, 0, 0 },
282 { LLCC_WRCACHE, 31, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
283};
284
6fc61c39
KD		 285static const struct llcc_slice_config sm8350_data[] = {
286 { LLCC_CPUSS, 1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 1 },
287 { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
288 { LLCC_AUDIO, 6, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 },
289 { LLCC_MDMHPGRW, 7, 1024, 3, 0, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
290 { LLCC_MODHW, 9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
291 { LLCC_CMPT, 10, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
292 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
293 { LLCC_GPU, 12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 },
294 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 },
295 { LLCC_DISP, 16, 3072, 2, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
296 { LLCC_MDMPNG, 21, 1024, 0, 1, 0xf, 0x0, 0, 0, 0, 0, 1, 0 },
297 { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
298 { LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
299 { LLCC_MODPE, 29, 256, 1, 1, 0xf, 0x0, 0, 0, 0, 0, 1, 0 },
300 { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 0, 1, 0 },
301 { LLCC_WRCACHE, 31, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 },
302 { LLCC_CVPFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
303 { LLCC_CPUSS1, 3, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
304 { LLCC_CPUHWT, 5, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 },
305};
306
a6e9d7ef
SPR		 307static const struct llcc_slice_config sm8450_data[] = {
308 {LLCC_CPUSS, 1, 3072, 1, 0, 0xFFFF, 0x0, 0, 0, 0, 1, 1, 0, 0 },
309 {LLCC_VIDSC0, 2, 512, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
310 {LLCC_AUDIO, 6, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 },
311 {LLCC_MDMHPGRW, 7, 1024, 3, 0, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
312 {LLCC_MODHW, 9, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
313 {LLCC_CMPT, 10, 4096, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
314 {LLCC_GPUHTW, 11, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
315 {LLCC_GPU, 12, 2048, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 1, 0 },
316 {LLCC_MMUHWT, 13, 768, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0 },
317 {LLCC_DISP, 16, 4096, 2, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
318 {LLCC_MDMPNG, 21, 1024, 1, 1, 0xF000, 0x0, 0, 0, 0, 1, 0, 0, 0 },
319 {LLCC_AUDHW, 22, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 },
320 {LLCC_CVP, 28, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
321 {LLCC_MODPE, 29, 64, 1, 1, 0xF000, 0x0, 0, 0, 0, 1, 0, 0, 0 },
322 {LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0xF0, 1, 0, 0, 1, 0, 0, 0 },
323 {LLCC_WRCACHE, 31, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0 },
324 {LLCC_CVPFW, 17, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
325 {LLCC_CPUSS1, 3, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
326 {LLCC_CAMEXP0, 4, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
327 {LLCC_CPUMTE, 23, 256, 1, 1, 0x0FFF, 0x0, 0, 0, 0, 0, 1, 0, 0 },
328 {LLCC_CPUHWT, 5, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 1, 0, 0 },
329 {LLCC_CAMEXP1, 27, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
330 {LLCC_AENPU, 8, 2048, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 },
331};
332
8c045cd2
AV		 333static const struct llcc_slice_config sm8550_data[] = {
334 {LLCC_CPUSS, 1, 5120, 1, 0, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
335 {LLCC_VIDSC0, 2, 512, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
336 {LLCC_AUDIO, 6, 1024, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
337 {LLCC_MDMHPGRW, 25, 1024, 4, 0, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
338 {LLCC_MODHW, 26, 1024, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
339 {LLCC_CMPT, 10, 4096, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
340 {LLCC_GPUHTW, 11, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
341 {LLCC_GPU, 9, 3096, 1, 0, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, },
342 {LLCC_MMUHWT, 18, 768, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
343 {LLCC_DISP, 16, 6144, 1, 1, 0xFFFFFF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
344 {LLCC_MDMPNG, 27, 1024, 0, 1, 0xF00000, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
345 {LLCC_AUDHW, 22, 1024, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
346 {LLCC_CVP, 8, 256, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
347 {LLCC_MODPE, 29, 64, 1, 1, 0xF00000, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, },
348 {LLCC_WRCACHE, 31, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
349 {LLCC_CAMEXP0, 4, 256, 4, 1, 0xF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
350 {LLCC_CPUHWT, 5, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
351 {LLCC_CAMEXP1, 7, 3200, 3, 1, 0xFFFFF0, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
352 {LLCC_CMPTHCP, 17, 256, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
353 {LLCC_LCPDARE, 30, 128, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, },
354 {LLCC_AENPU, 3, 3072, 1, 1, 0xFE01FF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
355 {LLCC_ISLAND1, 12, 1792, 7, 1, 0xFE00, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
356 {LLCC_ISLAND4, 15, 256, 7, 1, 0x10000, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
357 {LLCC_CAMEXP2, 19, 3200, 3, 1, 0xFFFFF0, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
358 {LLCC_CAMEXP3, 20, 3200, 2, 1, 0xFFFFF0, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
359 {LLCC_CAMEXP4, 21, 3200, 2, 1, 0xFFFFF0, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
360 {LLCC_DISP_WB, 23, 1024, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
361 {LLCC_DISP_1, 24, 6144, 1, 1, 0xFFFFFF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
362 {LLCC_VIDVSP, 28, 256, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
363};
364
db1e5792
KB		 365static const struct llcc_slice_config qdu1000_data_2ch[] = {
366 { LLCC_MDMHPGRW, 7, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
367 { LLCC_MODHW, 9, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
368 { LLCC_MDMPNG, 21, 256, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 },
369 { LLCC_ECC, 26, 512, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
370 { LLCC_MODPE, 29, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
371 { LLCC_APTCM, 30, 256, 3, 1, 0x0, 0xc, 1, 0, 0, 1, 0, 0, 0 },
372 { LLCC_WRCACHE, 31, 128, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 },
373};
374
375static const struct llcc_slice_config qdu1000_data_4ch[] = {
376 { LLCC_MDMHPGRW, 7, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
377 { LLCC_MODHW, 9, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
378 { LLCC_MDMPNG, 21, 512, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 },
379 { LLCC_ECC, 26, 1024, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
380 { LLCC_MODPE, 29, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
381 { LLCC_APTCM, 30, 512, 3, 1, 0x0, 0xc, 1, 0, 0, 1, 0, 0, 0 },
382 { LLCC_WRCACHE, 31, 256, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 },
383};
384
385static const struct llcc_slice_config qdu1000_data_8ch[] = {
386 { LLCC_MDMHPGRW, 7, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
387 { LLCC_MODHW, 9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
388 { LLCC_MDMPNG, 21, 1024, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 },
389 { LLCC_ECC, 26, 2048, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
390 { LLCC_MODPE, 29, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
391 { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0xc, 1, 0, 0, 1, 0, 0, 0 },
392 { LLCC_WRCACHE, 31, 512, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 },
393};
394
c13d7d26
MS		 395static const struct llcc_edac_reg_offset llcc_v1_edac_reg_offset = {
396 .trp_ecc_error_status0 = 0x20344,
397 .trp_ecc_error_status1 = 0x20348,
398 .trp_ecc_sb_err_syn0 = 0x2304c,
399 .trp_ecc_db_err_syn0 = 0x20370,
400 .trp_ecc_error_cntr_clear = 0x20440,
401 .trp_interrupt_0_status = 0x20480,
402 .trp_interrupt_0_clear = 0x20484,
403 .trp_interrupt_0_enable = 0x20488,
404
405 /* LLCC Common registers */
406 .cmn_status0 = 0x3000c,
407 .cmn_interrupt_0_enable = 0x3001c,
408 .cmn_interrupt_2_enable = 0x3003c,
409
410 /* LLCC DRP registers */
411 .drp_ecc_error_cfg = 0x40000,
412 .drp_ecc_error_cntr_clear = 0x40004,
413 .drp_interrupt_status = 0x41000,
414 .drp_interrupt_clear = 0x41008,
415 .drp_interrupt_enable = 0x4100c,
416 .drp_ecc_error_status0 = 0x42044,
417 .drp_ecc_error_status1 = 0x42048,
418 .drp_ecc_sb_err_syn0 = 0x4204c,
419 .drp_ecc_db_err_syn0 = 0x42070,
420};
421
422static const struct llcc_edac_reg_offset llcc_v2_1_edac_reg_offset = {
423 .trp_ecc_error_status0 = 0x20344,
424 .trp_ecc_error_status1 = 0x20348,
425 .trp_ecc_sb_err_syn0 = 0x2034c,
426 .trp_ecc_db_err_syn0 = 0x20370,
427 .trp_ecc_error_cntr_clear = 0x20440,
428 .trp_interrupt_0_status = 0x20480,
429 .trp_interrupt_0_clear = 0x20484,
430 .trp_interrupt_0_enable = 0x20488,
431
432 /* LLCC Common registers */
433 .cmn_status0 = 0x3400c,
434 .cmn_interrupt_0_enable = 0x3401c,
435 .cmn_interrupt_2_enable = 0x3403c,
436
437 /* LLCC DRP registers */
438 .drp_ecc_error_cfg = 0x50000,
439 .drp_ecc_error_cntr_clear = 0x50004,
440 .drp_interrupt_status = 0x50020,
441 .drp_interrupt_clear = 0x50028,
442 .drp_interrupt_enable = 0x5002c,
443 .drp_ecc_error_status0 = 0x520f4,
444 .drp_ecc_error_status1 = 0x520f8,
445 .drp_ecc_sb_err_syn0 = 0x520fc,
446 .drp_ecc_db_err_syn0 = 0x52120,
447};
448
5365cea1
MS		 449/* LLCC register offset starting from v1.0.0 */
450static const u32 llcc_v1_reg_offset[] = {
424ad93c
SPR		 451 [LLCC_COMMON_HW_INFO] = 0x00030000,
452 [LLCC_COMMON_STATUS0] = 0x0003000c,
453};
454
5365cea1
MS		 455/* LLCC register offset starting from v2.0.1 */
456static const u32 llcc_v2_1_reg_offset[] = {
424ad93c
SPR		 457 [LLCC_COMMON_HW_INFO] = 0x00034000,
458 [LLCC_COMMON_STATUS0] = 0x0003400c,
459};
460
db1e5792
KB		 461static const struct qcom_llcc_config qdu1000_cfg[] = {
462 {
463 .sct_data = qdu1000_data_8ch,
464 .size = ARRAY_SIZE(qdu1000_data_8ch),
465 .need_llcc_cfg = true,
466 .reg_offset = llcc_v2_1_reg_offset,
467 .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
468 },
469 {
470 .sct_data = qdu1000_data_4ch,
471 .size = ARRAY_SIZE(qdu1000_data_4ch),
472 .need_llcc_cfg = true,
473 .reg_offset = llcc_v2_1_reg_offset,
474 .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
475 },
476 {
477 .sct_data = qdu1000_data_4ch,
478 .size = ARRAY_SIZE(qdu1000_data_4ch),
479 .need_llcc_cfg = true,
480 .reg_offset = llcc_v2_1_reg_offset,
481 .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
482 },
483 {
484 .sct_data = qdu1000_data_2ch,
485 .size = ARRAY_SIZE(qdu1000_data_2ch),
486 .need_llcc_cfg = true,
487 .reg_offset = llcc_v2_1_reg_offset,
488 .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
489 },
490};
491
16fa9311
KB		 492static const struct qcom_llcc_config sc7180_cfg[] = {
493 {
494 .sct_data = sc7180_data,
495 .size = ARRAY_SIZE(sc7180_data),
496 .need_llcc_cfg = true,
497 .reg_offset = llcc_v1_reg_offset,
498 .edac_reg_offset = &llcc_v1_edac_reg_offset,
499 },
500};
501
502static const struct qcom_llcc_config sc7280_cfg[] = {
503 {
504 .sct_data = sc7280_data,
505 .size = ARRAY_SIZE(sc7280_data),
506 .need_llcc_cfg = true,
507 .reg_offset = llcc_v1_reg_offset,
508 .edac_reg_offset = &llcc_v1_edac_reg_offset,
509 },
510};
511
512static const struct qcom_llcc_config sc8180x_cfg[] = {
513 {
514 .sct_data = sc8180x_data,
515 .size = ARRAY_SIZE(sc8180x_data),
516 .need_llcc_cfg = true,
517 .reg_offset = llcc_v1_reg_offset,
518 .edac_reg_offset = &llcc_v1_edac_reg_offset,
519 },
520};
521
522static const struct qcom_llcc_config sc8280xp_cfg[] = {
523 {
524 .sct_data = sc8280xp_data,
525 .size = ARRAY_SIZE(sc8280xp_data),
526 .need_llcc_cfg = true,
527 .reg_offset = llcc_v1_reg_offset,
528 .edac_reg_offset = &llcc_v1_edac_reg_offset,
529 },
530};
531
532static const struct qcom_llcc_config sdm845_cfg[] = {
533 {
534 .sct_data = sdm845_data,
535 .size = ARRAY_SIZE(sdm845_data),
536 .need_llcc_cfg = false,
537 .reg_offset = llcc_v1_reg_offset,
538 .edac_reg_offset = &llcc_v1_edac_reg_offset,
539 .no_edac = true,
540 },
541};
542
543static const struct qcom_llcc_config sm6350_cfg[] = {
544 {
545 .sct_data = sm6350_data,
546 .size = ARRAY_SIZE(sm6350_data),
547 .need_llcc_cfg = true,
548 .reg_offset = llcc_v1_reg_offset,
549 .edac_reg_offset = &llcc_v1_edac_reg_offset,
550 },
551};
552
553static const struct qcom_llcc_config sm7150_cfg[] = {
554 {
555 .sct_data = sm7150_data,
556 .size = ARRAY_SIZE(sm7150_data),
557 .need_llcc_cfg = true,
558 .reg_offset = llcc_v1_reg_offset,
559 .edac_reg_offset = &llcc_v1_edac_reg_offset,
560 },
561};
562
563static const struct qcom_llcc_config sm8150_cfg[] = {
564 {
565 .sct_data = sm8150_data,
566 .size = ARRAY_SIZE(sm8150_data),
567 .need_llcc_cfg = true,
568 .reg_offset = llcc_v1_reg_offset,
569 .edac_reg_offset = &llcc_v1_edac_reg_offset,
570 },
571};
572
573static const struct qcom_llcc_config sm8250_cfg[] = {
574 {
575 .sct_data = sm8250_data,
576 .size = ARRAY_SIZE(sm8250_data),
577 .need_llcc_cfg = true,
578 .reg_offset = llcc_v1_reg_offset,
579 .edac_reg_offset = &llcc_v1_edac_reg_offset,
580 },
581};
582
583static const struct qcom_llcc_config sm8350_cfg[] = {
584 {
585 .sct_data = sm8350_data,
586 .size = ARRAY_SIZE(sm8350_data),
587 .need_llcc_cfg = true,
588 .reg_offset = llcc_v1_reg_offset,
589 .edac_reg_offset = &llcc_v1_edac_reg_offset,
590 },
669f7880
VG		 591};
592
16fa9311
KB		 593static const struct qcom_llcc_config sm8450_cfg[] = {
594 {
595 .sct_data = sm8450_data,
596 .size = ARRAY_SIZE(sm8450_data),
597 .need_llcc_cfg = true,
598 .reg_offset = llcc_v2_1_reg_offset,
599 .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
600 },
601};
602
603static const struct qcom_llcc_config sm8550_cfg[] = {
604 {
605 .sct_data = sm8550_data,
606 .size = ARRAY_SIZE(sm8550_data),
607 .need_llcc_cfg = true,
608 .reg_offset = llcc_v2_1_reg_offset,
609 .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
610 },
611};
612
db1e5792
KB		 613static const struct qcom_sct_config qdu1000_cfgs = {
614 .llcc_config = qdu1000_cfg,
615 .num_config = ARRAY_SIZE(qdu1000_cfg),
616};
617
16fa9311
KB		 618static const struct qcom_sct_config sc7180_cfgs = {
619 .llcc_config = sc7180_cfg,
620 .num_config = ARRAY_SIZE(sc7180_cfg),
621};
622
623static const struct qcom_sct_config sc7280_cfgs = {
624 .llcc_config = sc7280_cfg,
625 .num_config = ARRAY_SIZE(sc7280_cfg),
f6a07be6
SPR		 626};
627
16fa9311
KB		 628static const struct qcom_sct_config sc8180x_cfgs = {
629 .llcc_config = sc8180x_cfg,
630 .num_config = ARRAY_SIZE(sc8180x_cfg),
ec69dfbd
BA		 631};
632
16fa9311
KB		 633static const struct qcom_sct_config sc8280xp_cfgs = {
634 .llcc_config = sc8280xp_cfg,
635 .num_config = ARRAY_SIZE(sc8280xp_cfg),
ec69dfbd
BA		 636};
637
16fa9311
KB		 638static const struct qcom_sct_config sdm845_cfgs = {
639 .llcc_config = sdm845_cfg,
640 .num_config = ARRAY_SIZE(sdm845_cfg),
99356b03
VG		 641};
642
16fa9311
KB		 643static const struct qcom_sct_config sm6350_cfgs = {
644 .llcc_config = sm6350_cfg,
645 .num_config = ARRAY_SIZE(sm6350_cfg),
1f7b2b63
KD		 646};
647
16fa9311
KB		 648static const struct qcom_sct_config sm7150_cfgs = {
649 .llcc_config = sm7150_cfg,
650 .num_config = ARRAY_SIZE(sm7150_cfg),
92b9d862
DT		 651};
652
16fa9311
KB		 653static const struct qcom_sct_config sm8150_cfgs = {
654 .llcc_config = sm8150_cfg,
655 .num_config = ARRAY_SIZE(sm8150_cfg),
ded5ed04
SC		 656};
657
16fa9311
KB		 658static const struct qcom_sct_config sm8250_cfgs = {
659 .llcc_config = sm8250_cfg,
660 .num_config = ARRAY_SIZE(sm8250_cfg),
c4df37fe
MS		 661};
662
16fa9311
KB		 663static const struct qcom_sct_config sm8350_cfgs = {
664 .llcc_config = sm8350_cfg,
665 .num_config = ARRAY_SIZE(sm8350_cfg),
6fc61c39
KD		 666};
667
16fa9311
KB		 668static const struct qcom_sct_config sm8450_cfgs = {
669 .llcc_config = sm8450_cfg,
670 .num_config = ARRAY_SIZE(sm8450_cfg),
a6e9d7ef
SPR		 671};
672
16fa9311
KB		 673static const struct qcom_sct_config sm8550_cfgs = {
674 .llcc_config = sm8550_cfg,
675 .num_config = ARRAY_SIZE(sm8550_cfg),
8c045cd2
AV		 676};
677
72d1cd03 678static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
a3134fb0 679
a3134fb0
RB		 680/**
681 * llcc_slice_getd - get llcc slice descriptor
682 * @uid: usecase_id for the client
683 *
a3e7259f 684 * A pointer to llcc slice descriptor will be returned on success
a3134fb0
RB		 685 * and error pointer is returned on failure
686 */
687struct llcc_slice_desc *llcc_slice_getd(u32 uid)
688{
689 const struct llcc_slice_config *cfg;
690 struct llcc_slice_desc *desc;
691 u32 sz, count;
692
72d1cd03
JC		 693 if (IS_ERR(drv_data))
694 return ERR_CAST(drv_data);
695
a3134fb0
RB		 696 cfg = drv_data->cfg;
697 sz = drv_data->cfg_size;
698
699 for (count = 0; cfg && count < sz; count++, cfg++)
700 if (cfg->usecase_id == uid)
701 break;
702
703 if (count == sz || !cfg)
704 return ERR_PTR(-ENODEV);
705
706 desc = kzalloc(sizeof(*desc), GFP_KERNEL);
707 if (!desc)
708 return ERR_PTR(-ENOMEM);
709
710 desc->slice_id = cfg->slice_id;
711 desc->slice_size = cfg->max_cap;
712
713 return desc;
714}
715EXPORT_SYMBOL_GPL(llcc_slice_getd);
716
717/**
718 * llcc_slice_putd - llcc slice descritpor
719 * @desc: Pointer to llcc slice descriptor
720 */
721void llcc_slice_putd(struct llcc_slice_desc *desc)
722{
e0f2cfeb
JC		 723 if (!IS_ERR_OR_NULL(desc))
724 kfree(desc);
a3134fb0
RB		 725}
726EXPORT_SYMBOL_GPL(llcc_slice_putd);
727
728static int llcc_update_act_ctrl(u32 sid,
729 u32 act_ctrl_reg_val, u32 status)
730{
731 u32 act_ctrl_reg;
c72ca343 732 u32 act_clear_reg;
a3134fb0
RB		 733 u32 status_reg;
734 u32 slice_status;
735 int ret;
736
72d1cd03
JC		 737 if (IS_ERR(drv_data))
738 return PTR_ERR(drv_data);
739
7f9c1362 740 act_ctrl_reg = LLCC_TRP_ACT_CTRLn(sid);
c72ca343 741 act_clear_reg = LLCC_TRP_ACT_CLEARn(sid);
7f9c1362 742 status_reg = LLCC_TRP_STATUSn(sid);
a3134fb0
RB		 743
744 /* Set the ACTIVE trigger */
745 act_ctrl_reg_val |= ACT_CTRL_ACT_TRIG;
7f9c1362
VNKG		 746 ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg,
747 act_ctrl_reg_val);
a3134fb0
RB		 748 if (ret)
749 return ret;
750
751 /* Clear the ACTIVE trigger */
752 act_ctrl_reg_val &= ~ACT_CTRL_ACT_TRIG;
7f9c1362
VNKG		 753 ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg,
754 act_ctrl_reg_val);
a3134fb0
RB		 755 if (ret)
756 return ret;
757
c72ca343
AV		 758 if (drv_data->version >= LLCC_VERSION_4_1_0_0) {
759 ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg,
760 slice_status, (slice_status & ACT_COMPLETE),
761 0, LLCC_STATUS_READ_DELAY);
762 if (ret)
763 return ret;
764 }
765
7f9c1362 766 ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg,
a3134fb0
RB		 767 slice_status, !(slice_status & status),
768 0, LLCC_STATUS_READ_DELAY);
c72ca343
AV		 769
770 if (drv_data->version >= LLCC_VERSION_4_1_0_0)
771 ret = regmap_write(drv_data->bcast_regmap, act_clear_reg,
772 ACT_CLEAR);
773
a3134fb0
RB		 774 return ret;
775}
776
777/**
778 * llcc_slice_activate - Activate the llcc slice
779 * @desc: Pointer to llcc slice descriptor
780 *
781 * A value of zero will be returned on success and a negative errno will
782 * be returned in error cases
783 */
784int llcc_slice_activate(struct llcc_slice_desc *desc)
785{
786 int ret;
787 u32 act_ctrl_val;
788
32616b21 789 if (IS_ERR(drv_data))
72d1cd03
JC		 790 return PTR_ERR(drv_data);
791
e0f2cfeb
JC		 792 if (IS_ERR_OR_NULL(desc))
793 return -EINVAL;
794
a3134fb0
RB		 795 mutex_lock(&drv_data->lock);
796 if (test_bit(desc->slice_id, drv_data->bitmap)) {
797 mutex_unlock(&drv_data->lock);
798 return 0;
799 }
800
801 act_ctrl_val = ACT_CTRL_OPCODE_ACTIVATE << ACT_CTRL_OPCODE_SHIFT;
802
803 ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val,
804 DEACTIVATE);
805 if (ret) {
806 mutex_unlock(&drv_data->lock);
807 return ret;
808 }
809
810 __set_bit(desc->slice_id, drv_data->bitmap);
811 mutex_unlock(&drv_data->lock);
812
813 return ret;
814}
815EXPORT_SYMBOL_GPL(llcc_slice_activate);
816
817/**
818 * llcc_slice_deactivate - Deactivate the llcc slice
819 * @desc: Pointer to llcc slice descriptor
820 *
821 * A value of zero will be returned on success and a negative errno will
822 * be returned in error cases
823 */
824int llcc_slice_deactivate(struct llcc_slice_desc *desc)
825{
826 u32 act_ctrl_val;
827 int ret;
828
32616b21 829 if (IS_ERR(drv_data))
72d1cd03
JC		 830 return PTR_ERR(drv_data);
831
e0f2cfeb
JC		 832 if (IS_ERR_OR_NULL(desc))
833 return -EINVAL;
834
a3134fb0
RB		 835 mutex_lock(&drv_data->lock);
836 if (!test_bit(desc->slice_id, drv_data->bitmap)) {
837 mutex_unlock(&drv_data->lock);
838 return 0;
839 }
840 act_ctrl_val = ACT_CTRL_OPCODE_DEACTIVATE << ACT_CTRL_OPCODE_SHIFT;
841
842 ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val,
843 ACTIVATE);
844 if (ret) {
845 mutex_unlock(&drv_data->lock);
846 return ret;
847 }
848
849 __clear_bit(desc->slice_id, drv_data->bitmap);
850 mutex_unlock(&drv_data->lock);
851
852 return ret;
853}
854EXPORT_SYMBOL_GPL(llcc_slice_deactivate);
855
856/**
857 * llcc_get_slice_id - return the slice id
858 * @desc: Pointer to llcc slice descriptor
859 */
860int llcc_get_slice_id(struct llcc_slice_desc *desc)
861{
e0f2cfeb
JC		 862 if (IS_ERR_OR_NULL(desc))
863 return -EINVAL;
864
a3134fb0
RB		 865 return desc->slice_id;
866}
867EXPORT_SYMBOL_GPL(llcc_get_slice_id);
868
869/**
870 * llcc_get_slice_size - return the slice id
871 * @desc: Pointer to llcc slice descriptor
872 */
873size_t llcc_get_slice_size(struct llcc_slice_desc *desc)
874{
e0f2cfeb
JC		 875 if (IS_ERR_OR_NULL(desc))
876 return 0;
877
a3134fb0
RB		 878 return desc->slice_size;
879}
880EXPORT_SYMBOL_GPL(llcc_get_slice_size);
881
c14e64b4
IM		 882static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config,
883 const struct qcom_llcc_config *cfg)
a3134fb0 884{
af7244c0 885 int ret;
c72ca343 886 u32 attr2_cfg;
a3134fb0
RB		 887 u32 attr1_cfg;
888 u32 attr0_cfg;
c72ca343 889 u32 attr2_val;
a3134fb0
RB		 890 u32 attr1_val;
891 u32 attr0_val;
892 u32 max_cap_cacheline;
af7244c0
SPR		 893 struct llcc_slice_desc desc;
894
895 attr1_val = config->cache_mode;
896 attr1_val |= config->probe_target_ways << ATTR1_PROBE_TARGET_WAYS_SHIFT;
897 attr1_val |= config->fixed_size << ATTR1_FIXED_SIZE_SHIFT;
898 attr1_val |= config->priority << ATTR1_PRIORITY_SHIFT;
899
900 max_cap_cacheline = MAX_CAP_TO_BYTES(config->max_cap);
901
902 /*
903 * LLCC instances can vary for each target.
904 * The SW writes to broadcast register which gets propagated
905 * to each llcc instance (llcc0,.. llccN).
906 * Since the size of the memory is divided equally amongst the
907 * llcc instances, we need to configure the max cap accordingly.
908 */
909 max_cap_cacheline = max_cap_cacheline / drv_data->num_banks;
910 max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT;
911 attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT;
912
913 attr1_cfg = LLCC_TRP_ATTR1_CFGn(config->slice_id);
914
915 ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val);
916 if (ret)
917 return ret;
918
c72ca343
AV		 919 if (drv_data->version >= LLCC_VERSION_4_1_0_0) {
920 attr2_cfg = LLCC_TRP_ATTR2_CFGn(config->slice_id);
921 attr0_val = config->res_ways;
922 attr2_val = config->bonus_ways;
923 } else {
924 attr0_val = config->res_ways & ATTR0_RES_WAYS_MASK;
925 attr0_val |= config->bonus_ways << ATTR0_BONUS_WAYS_SHIFT;
926 }
af7244c0
SPR		 927
928 attr0_cfg = LLCC_TRP_ATTR0_CFGn(config->slice_id);
929
930 ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val);
931 if (ret)
932 return ret;
933
c72ca343
AV		 934 if (drv_data->version >= LLCC_VERSION_4_1_0_0) {
935 ret = regmap_write(drv_data->bcast_regmap, attr2_cfg, attr2_val);
936 if (ret)
937 return ret;
938 }
939
c14e64b4
IM		 940 if (cfg->need_llcc_cfg) {
941 u32 disable_cap_alloc, retain_pc;
942
943 disable_cap_alloc = config->dis_cap_alloc << config->slice_id;
944 ret = regmap_write(drv_data->bcast_regmap,
945 LLCC_TRP_SCID_DIS_CAP_ALLOC, disable_cap_alloc);
946 if (ret)
947 return ret;
948
c72ca343
AV		 949 if (drv_data->version < LLCC_VERSION_4_1_0_0) {
950 retain_pc = config->retain_on_pc << config->slice_id;
951 ret = regmap_write(drv_data->bcast_regmap,
952 LLCC_TRP_PCB_ACT, retain_pc);
953 if (ret)
954 return ret;
955 }
c14e64b4
IM		 956 }
957
8008e790 958 if (drv_data->version >= LLCC_VERSION_2_0_0_0) {
c4df37fe
MS		 959 u32 wren;
960
961 wren = config->write_scid_en << config->slice_id;
962 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_EN,
963 BIT(config->slice_id), wren);
964 if (ret)
965 return ret;
966 }
967
2b8175a1
SPR		 968 if (drv_data->version >= LLCC_VERSION_2_1_0_0) {
969 u32 wr_cache_en;
970
971 wr_cache_en = config->write_scid_cacheable_en << config->slice_id;
972 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_CACHEABLE_EN,
973 BIT(config->slice_id), wr_cache_en);
974 if (ret)
975 return ret;
976 }
977
c72ca343
AV		 978 if (drv_data->version >= LLCC_VERSION_4_1_0_0) {
979 u32 stale_en;
980 u32 stale_cap_en;
981 u32 mru_uncap_en;
982 u32 mru_rollover;
983 u32 alloc_oneway_en;
984 u32 ovcap_en;
985 u32 ovcap_prio;
986 u32 vict_prio;
987
988 stale_en = config->stale_en << config->slice_id;
989 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG1,
990 BIT(config->slice_id), stale_en);
991 if (ret)
992 return ret;
993
994 stale_cap_en = config->stale_cap_en << config->slice_id;
995 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG2,
996 BIT(config->slice_id), stale_cap_en);
997 if (ret)
998 return ret;
999
1000 mru_uncap_en = config->mru_uncap_en << config->slice_id;
1001 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG3,
1002 BIT(config->slice_id), mru_uncap_en);
1003 if (ret)
1004 return ret;
1005
1006 mru_rollover = config->mru_rollover << config->slice_id;
1007 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG4,
1008 BIT(config->slice_id), mru_rollover);
1009 if (ret)
1010 return ret;
1011
1012 alloc_oneway_en = config->alloc_oneway_en << config->slice_id;
1013 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG5,
1014 BIT(config->slice_id), alloc_oneway_en);
1015 if (ret)
1016 return ret;
1017
1018 ovcap_en = config->ovcap_en << config->slice_id;
1019 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG6,
1020 BIT(config->slice_id), ovcap_en);
1021 if (ret)
1022 return ret;
1023
1024 ovcap_prio = config->ovcap_prio << config->slice_id;
1025 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG7,
1026 BIT(config->slice_id), ovcap_prio);
1027 if (ret)
1028 return ret;
1029
1030 vict_prio = config->vict_prio << config->slice_id;
1031 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG8,
1032 BIT(config->slice_id), vict_prio);
1033 if (ret)
1034 return ret;
1035 }
1036
af7244c0
SPR		 1037 if (config->activate_on_init) {
1038 desc.slice_id = config->slice_id;
1039 ret = llcc_slice_activate(&desc);
1040 }
1041
1042 return ret;
1043}
1044
c14e64b4
IM		 1045static int qcom_llcc_cfg_program(struct platform_device *pdev,
1046 const struct qcom_llcc_config *cfg)
af7244c0
SPR		 1047{
1048 int i;
a3134fb0 1049 u32 sz;
c081f306 1050 int ret = 0;
a3134fb0 1051 const struct llcc_slice_config *llcc_table;
a3134fb0
RB		 1052
1053 sz = drv_data->cfg_size;
1054 llcc_table = drv_data->cfg;
1055
1056 for (i = 0; i < sz; i++) {
c14e64b4 1057 ret = _qcom_llcc_cfg_program(&llcc_table[i], cfg);
a3134fb0
RB		 1058 if (ret)
1059 return ret;
a3134fb0 1060 }
af7244c0 1061
a3134fb0
RB		 1062 return ret;
1063}
1064
a78502a4
KB		 1065static int qcom_llcc_get_cfg_index(struct platform_device *pdev, u8 *cfg_index, int num_config)
1066{
1067 int ret;
1068
1069 ret = nvmem_cell_read_u8(&pdev->dev, "multi-chan-ddr", cfg_index);
1070 if (ret == -ENOENT || ret == -EOPNOTSUPP) {
1071 if (num_config > 1)
1072 return -EINVAL;
1073 *cfg_index = 0;
1074 return 0;
1075 }
1076
1077 if (!ret && *cfg_index >= num_config)
1078 ret = -EINVAL;
1079
1080 return ret;
1081}
1082
d85a9d18 1083static void qcom_llcc_remove(struct platform_device *pdev)
72d1cd03
JC		 1084{
1085 /* Set the global pointer to a error code to avoid referencing it */
1086 drv_data = ERR_PTR(-ENODEV);
72d1cd03 1087}
72d1cd03 1088
ee13b500
MS		 1089static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, u8 index,
1090 const char *name)
ed10a259 1091{
ed10a259 1092 void __iomem *base;
acbf73bf
SB		 1093 struct regmap_config llcc_regmap_config = {
1094 .reg_bits = 32,
1095 .reg_stride = 4,
1096 .val_bits = 32,
1097 .fast_io = true,
1098 };
ed10a259 1099
ee13b500 1100 base = devm_platform_ioremap_resource(pdev, index);
ed10a259
JC		 1101 if (IS_ERR(base))
1102 return ERR_CAST(base);
1103
2bfd3e76 1104 llcc_regmap_config.name = name;
ed10a259
JC		 1105 return devm_regmap_init_mmio(&pdev->dev, base, &llcc_regmap_config);
1106}
1107
99356b03 1108static int qcom_llcc_probe(struct platform_device *pdev)
a3134fb0
RB		 1109{
1110 u32 num_banks;
1111 struct device *dev = &pdev->dev;
a3134fb0 1112 int ret, i;
c081f306 1113 struct platform_device *llcc_edac;
16fa9311 1114 const struct qcom_sct_config *cfgs;
99356b03
VG		 1115 const struct qcom_llcc_config *cfg;
1116 const struct llcc_slice_config *llcc_cfg;
1117 u32 sz;
a78502a4 1118 u8 cfg_index;
916c0c05 1119 u32 version;
ee13b500 1120 struct regmap *regmap;
a3134fb0 1121
f1a1bc87
UKK		 1122 if (!IS_ERR(drv_data))
1123 return -EBUSY;
1124
a3134fb0 1125 drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
72d1cd03
JC		 1126 if (!drv_data) {
1127 ret = -ENOMEM;
1128 goto err;
1129 }
a3134fb0 1130
ee13b500
MS		 1131 /* Initialize the first LLCC bank regmap */
1132 regmap = qcom_llcc_init_mmio(pdev, 0, "llcc0_base");
1133 if (IS_ERR(regmap)) {
1134 ret = PTR_ERR(regmap);
72d1cd03
JC		 1135 goto err;
1136 }
a3134fb0 1137
16fa9311
KB		 1138 cfgs = of_device_get_match_data(&pdev->dev);
1139 if (!cfgs) {
1140 ret = -EINVAL;
1141 goto err;
1142 }
a78502a4
KB		 1143 ret = qcom_llcc_get_cfg_index(pdev, &cfg_index, cfgs->num_config);
1144 if (ret)
1145 goto err;
1146 cfg = &cfgs->llcc_config[cfg_index];
ee13b500
MS		 1147
1148 ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks);
1149 if (ret)
1150 goto err;
1151
1152 num_banks &= LLCC_LB_CNT_MASK;
1153 num_banks >>= LLCC_LB_CNT_SHIFT;
1154 drv_data->num_banks = num_banks;
1155
1156 drv_data->regmaps = devm_kcalloc(dev, num_banks, sizeof(*drv_data->regmaps), GFP_KERNEL);
1157 if (!drv_data->regmaps) {
1158 ret = -ENOMEM;
72d1cd03
JC		 1159 goto err;
1160 }
a3134fb0 1161
ee13b500
MS		 1162 drv_data->regmaps[0] = regmap;
1163
1164 /* Initialize rest of LLCC bank regmaps */
1165 for (i = 1; i < num_banks; i++) {
1166 char *base = kasprintf(GFP_KERNEL, "llcc%d_base", i);
1167
1168 drv_data->regmaps[i] = qcom_llcc_init_mmio(pdev, i, base);
1169 if (IS_ERR(drv_data->regmaps[i])) {
1170 ret = PTR_ERR(drv_data->regmaps[i]);
1171 kfree(base);
1172 goto err;
1173 }
1174
1175 kfree(base);
1176 }
1177
1178 drv_data->bcast_regmap = qcom_llcc_init_mmio(pdev, i, "llcc_broadcast_base");
72d1cd03
JC		 1179 if (IS_ERR(drv_data->bcast_regmap)) {
1180 ret = PTR_ERR(drv_data->bcast_regmap);
1181 goto err;
1182 }
7f9c1362 1183
8008e790 1184 /* Extract version of the IP */
424ad93c
SPR		 1185 ret = regmap_read(drv_data->bcast_regmap, cfg->reg_offset[LLCC_COMMON_HW_INFO],
1186 &version);
916c0c05
SPR		 1187 if (ret)
1188 goto err;
1189
8008e790 1190 drv_data->version = version;
916c0c05 1191
99356b03
VG		 1192 llcc_cfg = cfg->sct_data;
1193 sz = cfg->size;
1194
a3134fb0
RB		 1195 for (i = 0; i < sz; i++)
1196 if (llcc_cfg[i].slice_id > drv_data->max_slices)
1197 drv_data->max_slices = llcc_cfg[i].slice_id;
1198
a9ff0638
CJ		 1199 drv_data->bitmap = devm_bitmap_zalloc(dev, drv_data->max_slices,
1200 GFP_KERNEL);
72d1cd03
JC		 1201 if (!drv_data->bitmap) {
1202 ret = -ENOMEM;
1203 goto err;
1204 }
a3134fb0
RB		 1205
1206 drv_data->cfg = llcc_cfg;
1207 drv_data->cfg_size = sz;
c13d7d26 1208 drv_data->edac_reg_offset = cfg->edac_reg_offset;
a3134fb0
RB		 1209 mutex_init(&drv_data->lock);
1210 platform_set_drvdata(pdev, drv_data);
1211
c14e64b4 1212 ret = qcom_llcc_cfg_program(pdev, cfg);
c081f306 1213 if (ret)
72d1cd03 1214 goto err;
c081f306 1215
c882c899 1216 drv_data->ecc_irq = platform_get_irq_optional(pdev, 0);
721d3e91 1217
cca94f1d
MS		 1218 /*
1219 * On some platforms, the access to EDAC registers will be locked by
1220 * the bootloader. So probing the EDAC driver will result in a crash.
1221 * Hence, disable the creation of EDAC platform device for the
1222 * problematic platforms.
1223 */
1224 if (!cfg->no_edac) {
c081f306
VNKG		 1225 llcc_edac = platform_device_register_data(&pdev->dev,
1226 "qcom_llcc_edac", -1, drv_data,
1227 sizeof(*drv_data));
1228 if (IS_ERR(llcc_edac))
1229 dev_err(dev, "Failed to register llcc edac driver\n");
1230 }
1231
72d1cd03
JC		 1232 return 0;
1233err:
1234 drv_data = ERR_PTR(-ENODEV);
c081f306 1235 return ret;
a3134fb0 1236}
a14b8203 1237
99356b03 1238static const struct of_device_id qcom_llcc_of_match[] = {
db1e5792 1239 { .compatible = "qcom,qdu1000-llcc", .data = &qdu1000_cfgs},
16fa9311
KB		 1240 { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfgs },
1241 { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfgs },
1242 { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfgs },
1243 { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfgs },
1244 { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfgs },
1245 { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfgs },
1246 { .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfgs },
1247 { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfgs },
1248 { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfgs },
1249 { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfgs },
1250 { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfgs },
1251 { .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfgs },
a14b8203
VG		 1252 { }
1253};
5334a3b1 1254MODULE_DEVICE_TABLE(of, qcom_llcc_of_match);
a14b8203 1255
99356b03 1256static struct platform_driver qcom_llcc_driver = {
a14b8203 1257 .driver = {
99356b03
VG		 1258 .name = "qcom-llcc",
1259 .of_match_table = qcom_llcc_of_match,
a14b8203 1260 },
99356b03 1261 .probe = qcom_llcc_probe,
d85a9d18 1262 .remove_new = qcom_llcc_remove,
a14b8203 1263};
99356b03 1264module_platform_driver(qcom_llcc_driver);
a14b8203 1265
99356b03 1266MODULE_DESCRIPTION("Qualcomm Last Level Cache Controller");
4da3b045 1267MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)