[linux-2.6-block.git] / drivers / soc / mediatek / mtk-cmdq-helper.c

// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2018 MediaTek Inc.

#include <linux/completion.h>
#include <linux/errno.h>
#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/mailbox_controller.h>
#include <linux/of.h>
#include <linux/soc/mediatek/mtk-cmdq.h>

#define CMDQ_WRITE_ENABLE_MASK	BIT(0)
#define CMDQ_POLL_ENABLE_MASK	BIT(0)
/* dedicate the last GPR_R15 to assign the register address to be poll */
#define CMDQ_POLL_ADDR_GPR	(15)
#define CMDQ_EOC_IRQ_EN		BIT(0)
#define CMDQ_IMMEDIATE_VALUE	0
#define CMDQ_REG_TYPE		1
#define CMDQ_JUMP_RELATIVE	0
#define CMDQ_JUMP_ABSOLUTE	1

struct cmdq_instruction {
	union {
		u32 value;
		u32 mask;
		struct {
			u16 arg_c;
			u16 src_reg;
		};
	};
	union {
		u16 offset;
		u16 event;
		u16 reg_dst;
	};
	union {
		u8 subsys;
		struct {
			u8 sop:5;
			u8 arg_c_t:1;
			u8 src_t:1;
			u8 dst_t:1;
		};
	};
	u8 op;
};

static inline u8 cmdq_operand_get_type(struct cmdq_operand *op)
{
	return op->reg ? CMDQ_REG_TYPE : CMDQ_IMMEDIATE_VALUE;
}

static inline u16 cmdq_operand_get_idx_value(struct cmdq_operand *op)
{
	return op->reg ? op->idx : op->value;
}

int cmdq_dev_get_client_reg(struct device *dev,
			    struct cmdq_client_reg *client_reg, int idx)
{
	struct of_phandle_args spec;
	int err;

	if (!client_reg)
		return -ENOENT;

	err = of_parse_phandle_with_fixed_args(dev->of_node,
					       "mediatek,gce-client-reg",
					       3, idx, &spec);
	if (err < 0) {
		dev_warn(dev,
			"error %d can't parse gce-client-reg property (%d)",
			err, idx);

		return err;
	}

	client_reg->subsys = (u8)spec.args[0];
	client_reg->offset = (u16)spec.args[1];
	client_reg->size = (u16)spec.args[2];
	of_node_put(spec.np);

	return 0;
}
EXPORT_SYMBOL(cmdq_dev_get_client_reg);

struct cmdq_client *cmdq_mbox_create(struct device *dev, int index)
{
	struct cmdq_client *client;

	client = kzalloc(sizeof(*client), GFP_KERNEL);
	if (!client)
		return (struct cmdq_client *)-ENOMEM;

	client->client.dev = dev;
	client->client.tx_block = false;
	client->client.knows_txdone = true;
	client->chan = mbox_request_channel(&client->client, index);

	if (IS_ERR(client->chan)) {
		long err;

		dev_err(dev, "failed to request channel\n");
		err = PTR_ERR(client->chan);
		kfree(client);

		return ERR_PTR(err);
	}

	return client;
}
EXPORT_SYMBOL(cmdq_mbox_create);

void cmdq_mbox_destroy(struct cmdq_client *client)
{
	mbox_free_channel(client->chan);
	kfree(client);
}
EXPORT_SYMBOL(cmdq_mbox_destroy);

int cmdq_pkt_create(struct cmdq_client *client, struct cmdq_pkt *pkt, size_t size)
{
	struct device *dev;
	dma_addr_t dma_addr;

	pkt->va_base = kzalloc(size, GFP_KERNEL);
	if (!pkt->va_base)
		return -ENOMEM;

	pkt->buf_size = size;

	dev = client->chan->mbox->dev;
	dma_addr = dma_map_single(dev, pkt->va_base, pkt->buf_size,
				  DMA_TO_DEVICE);
	if (dma_mapping_error(dev, dma_addr)) {
		dev_err(dev, "dma map failed, size=%u\n", (u32)(u64)size);
		kfree(pkt->va_base);
		return -ENOMEM;
	}

	pkt->pa_base = dma_addr;

	return 0;
}
EXPORT_SYMBOL(cmdq_pkt_create);

void cmdq_pkt_destroy(struct cmdq_client *client, struct cmdq_pkt *pkt)
{
	dma_unmap_single(client->chan->mbox->dev, pkt->pa_base, pkt->buf_size,
			 DMA_TO_DEVICE);
	kfree(pkt->va_base);
}
EXPORT_SYMBOL(cmdq_pkt_destroy);

static int cmdq_pkt_append_command(struct cmdq_pkt *pkt,
				   struct cmdq_instruction inst)
{
	struct cmdq_instruction *cmd_ptr;

	if (unlikely(pkt->cmd_buf_size + CMDQ_INST_SIZE > pkt->buf_size)) {
		/*
		 * In the case of allocated buffer size (pkt->buf_size) is used
		 * up, the real required size (pkt->cmdq_buf_size) is still
		 * increased, so that the user knows how much memory should be
		 * ultimately allocated after appending all commands and
		 * flushing the command packet. Therefor, the user can call
		 * cmdq_pkt_create() again with the real required buffer size.
		 */
		pkt->cmd_buf_size += CMDQ_INST_SIZE;
		WARN_ONCE(1, "%s: buffer size %u is too small !\n",
			__func__, (u32)pkt->buf_size);
		return -ENOMEM;
	}

	cmd_ptr = pkt->va_base + pkt->cmd_buf_size;
	*cmd_ptr = inst;
	pkt->cmd_buf_size += CMDQ_INST_SIZE;

	return 0;
}

int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value)
{
	struct cmdq_instruction inst;

	inst.op = CMDQ_CODE_WRITE;
	inst.value = value;
	inst.offset = offset;
	inst.subsys = subsys;

	return cmdq_pkt_append_command(pkt, inst);
}
EXPORT_SYMBOL(cmdq_pkt_write);

int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
			u16 offset, u32 value, u32 mask)
{
	struct cmdq_instruction inst = { {0} };
	u16 offset_mask = offset;
	int err;

	if (mask != 0xffffffff) {
		inst.op = CMDQ_CODE_MASK;
		inst.mask = ~mask;
		err = cmdq_pkt_append_command(pkt, inst);
		if (err < 0)
			return err;

		offset_mask |= CMDQ_WRITE_ENABLE_MASK;
	}
	err = cmdq_pkt_write(pkt, subsys, offset_mask, value);

	return err;
}
EXPORT_SYMBOL(cmdq_pkt_write_mask);

int cmdq_pkt_read_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx, u16 addr_low,
		    u16 reg_idx)
{
	struct cmdq_instruction inst = {};

	inst.op = CMDQ_CODE_READ_S;
	inst.dst_t = CMDQ_REG_TYPE;
	inst.sop = high_addr_reg_idx;
	inst.reg_dst = reg_idx;
	inst.src_reg = addr_low;

	return cmdq_pkt_append_command(pkt, inst);
}
EXPORT_SYMBOL(cmdq_pkt_read_s);

int cmdq_pkt_write_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
		     u16 addr_low, u16 src_reg_idx)
{
	struct cmdq_instruction inst = {};

	inst.op = CMDQ_CODE_WRITE_S;
	inst.src_t = CMDQ_REG_TYPE;
	inst.sop = high_addr_reg_idx;
	inst.offset = addr_low;
	inst.src_reg = src_reg_idx;

	return cmdq_pkt_append_command(pkt, inst);
}
EXPORT_SYMBOL(cmdq_pkt_write_s);

int cmdq_pkt_write_s_mask(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
			  u16 addr_low, u16 src_reg_idx, u32 mask)
{
	struct cmdq_instruction inst = {};
	int err;

	inst.op = CMDQ_CODE_MASK;
	inst.mask = ~mask;
	err = cmdq_pkt_append_command(pkt, inst);
	if (err < 0)
		return err;

	inst.mask = 0;
	inst.op = CMDQ_CODE_WRITE_S_MASK;
	inst.src_t = CMDQ_REG_TYPE;
	inst.sop = high_addr_reg_idx;
	inst.offset = addr_low;
	inst.src_reg = src_reg_idx;

	return cmdq_pkt_append_command(pkt, inst);
}
EXPORT_SYMBOL(cmdq_pkt_write_s_mask);

int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx,
			   u16 addr_low, u32 value)
{
	struct cmdq_instruction inst = {};

	inst.op = CMDQ_CODE_WRITE_S;
	inst.sop = high_addr_reg_idx;
	inst.offset = addr_low;
	inst.value = value;

	return cmdq_pkt_append_command(pkt, inst);
}
EXPORT_SYMBOL(cmdq_pkt_write_s_value);

int cmdq_pkt_write_s_mask_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx,
				u16 addr_low, u32 value, u32 mask)
{
	struct cmdq_instruction inst = {};
	int err;

	inst.op = CMDQ_CODE_MASK;
	inst.mask = ~mask;
	err = cmdq_pkt_append_command(pkt, inst);
	if (err < 0)
		return err;

	inst.op = CMDQ_CODE_WRITE_S_MASK;
	inst.sop = high_addr_reg_idx;
	inst.offset = addr_low;
	inst.value = value;

	return cmdq_pkt_append_command(pkt, inst);
}
EXPORT_SYMBOL(cmdq_pkt_write_s_mask_value);

int cmdq_pkt_mem_move(struct cmdq_pkt *pkt, dma_addr_t src_addr, dma_addr_t dst_addr)
{
	const u16 high_addr_reg_idx  = CMDQ_THR_SPR_IDX0;
	const u16 value_reg_idx = CMDQ_THR_SPR_IDX1;
	int ret;

	/* read the value of src_addr into high_addr_reg_idx */
	ret = cmdq_pkt_assign(pkt, high_addr_reg_idx, CMDQ_ADDR_HIGH(src_addr));
	if (ret < 0)
		return ret;
	ret = cmdq_pkt_read_s(pkt, high_addr_reg_idx, CMDQ_ADDR_LOW(src_addr), value_reg_idx);
	if (ret < 0)
		return ret;

	/* write the value of value_reg_idx into dst_addr */
	ret = cmdq_pkt_assign(pkt, high_addr_reg_idx, CMDQ_ADDR_HIGH(dst_addr));
	if (ret < 0)
		return ret;
	ret = cmdq_pkt_write_s(pkt, high_addr_reg_idx, CMDQ_ADDR_LOW(dst_addr), value_reg_idx);
	if (ret < 0)
		return ret;

	return 0;
}
EXPORT_SYMBOL(cmdq_pkt_mem_move);

int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event, bool clear)
{
	struct cmdq_instruction inst = { {0} };
	u32 clear_option = clear ? CMDQ_WFE_UPDATE : 0;

	if (event >= CMDQ_MAX_EVENT)
		return -EINVAL;

	inst.op = CMDQ_CODE_WFE;
	inst.value = CMDQ_WFE_OPTION | clear_option;
	inst.event = event;

	return cmdq_pkt_append_command(pkt, inst);
}
EXPORT_SYMBOL(cmdq_pkt_wfe);

int cmdq_pkt_acquire_event(struct cmdq_pkt *pkt, u16 event)
{
	struct cmdq_instruction inst = {};

	if (event >= CMDQ_MAX_EVENT)
		return -EINVAL;

	inst.op = CMDQ_CODE_WFE;
	inst.value = CMDQ_WFE_UPDATE | CMDQ_WFE_UPDATE_VALUE | CMDQ_WFE_WAIT;
	inst.event = event;

	return cmdq_pkt_append_command(pkt, inst);
}
EXPORT_SYMBOL(cmdq_pkt_acquire_event);

int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event)
{
	struct cmdq_instruction inst = { {0} };

	if (event >= CMDQ_MAX_EVENT)
		return -EINVAL;

	inst.op = CMDQ_CODE_WFE;
	inst.value = CMDQ_WFE_UPDATE;
	inst.event = event;

	return cmdq_pkt_append_command(pkt, inst);
}
EXPORT_SYMBOL(cmdq_pkt_clear_event);

int cmdq_pkt_set_event(struct cmdq_pkt *pkt, u16 event)
{
	struct cmdq_instruction inst = {};

	if (event >= CMDQ_MAX_EVENT)
		return -EINVAL;

	inst.op = CMDQ_CODE_WFE;
	inst.value = CMDQ_WFE_UPDATE | CMDQ_WFE_UPDATE_VALUE;
	inst.event = event;

	return cmdq_pkt_append_command(pkt, inst);
}
EXPORT_SYMBOL(cmdq_pkt_set_event);

int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys,
		  u16 offset, u32 value)
{
	struct cmdq_instruction inst = { {0} };
	int err;

	inst.op = CMDQ_CODE_POLL;
	inst.value = value;
	inst.offset = offset;
	inst.subsys = subsys;
	err = cmdq_pkt_append_command(pkt, inst);

	return err;
}
EXPORT_SYMBOL(cmdq_pkt_poll);

int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys,
		       u16 offset, u32 value, u32 mask)
{
	struct cmdq_instruction inst = { {0} };
	int err;

	inst.op = CMDQ_CODE_MASK;
	inst.mask = ~mask;
	err = cmdq_pkt_append_command(pkt, inst);
	if (err < 0)
		return err;

	offset = offset | CMDQ_POLL_ENABLE_MASK;
	err = cmdq_pkt_poll(pkt, subsys, offset, value);

	return err;
}
EXPORT_SYMBOL(cmdq_pkt_poll_mask);

int cmdq_pkt_poll_addr(struct cmdq_pkt *pkt, dma_addr_t addr, u32 value, u32 mask)
{
	struct cmdq_instruction inst = { {0} };
	u8 use_mask = 0;
	int ret;

	/*
	 * Append an MASK instruction to set the mask for following POLL instruction
	 * which enables use_mask bit.
	 */
	if (mask != GENMASK(31, 0)) {
		inst.op = CMDQ_CODE_MASK;
		inst.mask = ~mask;
		ret = cmdq_pkt_append_command(pkt, inst);
		if (ret < 0)
			return ret;
		use_mask = CMDQ_POLL_ENABLE_MASK;
	}

	/*
	 * POLL is an legacy operation in GCE and it does not support SPR and CMDQ_CODE_LOGIC,
	 * so it can not use cmdq_pkt_assign to keep polling register address to SPR.
	 * If user wants to poll a register address which doesn't have a subsys id,
	 * user needs to use GPR and CMDQ_CODE_MASK to move polling register address to GPR.
	 */
	inst.op = CMDQ_CODE_MASK;
	inst.dst_t = CMDQ_REG_TYPE;
	inst.sop = CMDQ_POLL_ADDR_GPR;
	inst.value = addr;
	ret = cmdq_pkt_append_command(pkt, inst);
	if (ret < 0)
		return ret;

	/* Append POLL instruction to poll the register address assign to GPR previously. */
	inst.op = CMDQ_CODE_POLL;
	inst.dst_t = CMDQ_REG_TYPE;
	inst.sop = CMDQ_POLL_ADDR_GPR;
	inst.offset = use_mask;
	inst.value = value;
	ret = cmdq_pkt_append_command(pkt, inst);
	if (ret < 0)
		return ret;

	return 0;
}
EXPORT_SYMBOL(cmdq_pkt_poll_addr);

int cmdq_pkt_logic_command(struct cmdq_pkt *pkt, u16 result_reg_idx,
			   struct cmdq_operand *left_operand,
			   enum cmdq_logic_op s_op,
			   struct cmdq_operand *right_operand)
{
	struct cmdq_instruction inst = { {0} };

	if (!left_operand || !right_operand || s_op >= CMDQ_LOGIC_MAX)
		return -EINVAL;

	inst.op = CMDQ_CODE_LOGIC;
	inst.dst_t = CMDQ_REG_TYPE;
	inst.src_t = cmdq_operand_get_type(left_operand);
	inst.arg_c_t = cmdq_operand_get_type(right_operand);
	inst.sop = s_op;
	inst.reg_dst = result_reg_idx;
	inst.src_reg = cmdq_operand_get_idx_value(left_operand);
	inst.arg_c = cmdq_operand_get_idx_value(right_operand);

	return cmdq_pkt_append_command(pkt, inst);
}
EXPORT_SYMBOL(cmdq_pkt_logic_command);

int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value)
{
	struct cmdq_instruction inst = {};

	inst.op = CMDQ_CODE_LOGIC;
	inst.dst_t = CMDQ_REG_TYPE;
	inst.reg_dst = reg_idx;
	inst.value = value;
	return cmdq_pkt_append_command(pkt, inst);
}
EXPORT_SYMBOL(cmdq_pkt_assign);

int cmdq_pkt_jump_abs(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa)
{
	struct cmdq_instruction inst = {};

	inst.op = CMDQ_CODE_JUMP;
	inst.offset = CMDQ_JUMP_ABSOLUTE;
	inst.value = addr >> shift_pa;
	return cmdq_pkt_append_command(pkt, inst);
}
EXPORT_SYMBOL(cmdq_pkt_jump_abs);

int cmdq_pkt_jump_rel(struct cmdq_pkt *pkt, s32 offset, u8 shift_pa)
{
	struct cmdq_instruction inst = { {0} };

	inst.op = CMDQ_CODE_JUMP;
	inst.value = (u32)offset >> shift_pa;
	return cmdq_pkt_append_command(pkt, inst);
}
EXPORT_SYMBOL(cmdq_pkt_jump_rel);

int cmdq_pkt_eoc(struct cmdq_pkt *pkt)
{
	struct cmdq_instruction inst = { {0} };

	inst.op = CMDQ_CODE_EOC;
	inst.value = CMDQ_EOC_IRQ_EN;
	return cmdq_pkt_append_command(pkt, inst);
}
EXPORT_SYMBOL(cmdq_pkt_eoc);

int cmdq_pkt_finalize(struct cmdq_pkt *pkt)
{
	struct cmdq_instruction inst = { {0} };
	int err;

	/* insert EOC and generate IRQ for each command iteration */
	inst.op = CMDQ_CODE_EOC;
	inst.value = CMDQ_EOC_IRQ_EN;
	err = cmdq_pkt_append_command(pkt, inst);
	if (err < 0)
		return err;

	/* JUMP to end */
	inst.op = CMDQ_CODE_JUMP;
	inst.value = CMDQ_JUMP_PASS >>
		cmdq_get_shift_pa(((struct cmdq_client *)pkt->cl)->chan);
	err = cmdq_pkt_append_command(pkt, inst);

	return err;
}
EXPORT_SYMBOL(cmdq_pkt_finalize);

MODULE_DESCRIPTION("MediaTek Command Queue (CMDQ) driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
576f1b4b HW	1	// SPDX-License-Identifier: GPL-2.0
	2	//
	3	// Copyright (c) 2018 MediaTek Inc.
	4
	5	#include <linux/completion.h>
	6	#include <linux/errno.h>
	7	#include <linux/dma-mapping.h>
	8	#include <linux/module.h>
	9	#include <linux/mailbox_controller.h>
d01e0aec	10	#include <linux/of.h>
576f1b4b HW	11	#include <linux/soc/mediatek/mtk-cmdq.h>
576f1b4b HW	12
576f1b4b	13	#define CMDQ_WRITE_ENABLE_MASK BIT(0)
b2ff2356	14	#define CMDQ_POLL_ENABLE_MASK BIT(0)
400e2fa8 JJL	15	/* dedicate the last GPR_R15 to assign the register address to be poll */
400e2fa8 JJL	16	#define CMDQ_POLL_ADDR_GPR (15)
576f1b4b	17	#define CMDQ_EOC_IRQ_EN BIT(0)
58de63dd	18	#define CMDQ_IMMEDIATE_VALUE 0
613c2e2c	19	#define CMDQ_REG_TYPE 1
ed4d5ab1 CKH	20	#define CMDQ_JUMP_RELATIVE 0
ed4d5ab1 CKH	21	#define CMDQ_JUMP_ABSOLUTE 1
576f1b4b	22
5c8b718c BH	23	struct cmdq_instruction {
	24	union {
	25	u32 value;
	26	u32 mask;
5f6e560c DYH	27	struct {
	28	u16 arg_c;
	29	u16 src_reg;
	30	};
5c8b718c BH	31	};
	32	union {
	33	u16 offset;
	34	u16 event;
613c2e2c DYH	35	u16 reg_dst;
	36	};
	37	union {
	38	u8 subsys;
	39	struct {
	40	u8 sop:5;
	41	u8 arg_c_t:1;
	42	u8 src_t:1;
	43	u8 dst_t:1;
	44	};
5c8b718c	45	};
5c8b718c BH	46	u8 op;
	47	};
	48
58de63dd JJL	49	static inline u8 cmdq_operand_get_type(struct cmdq_operand *op)
	50	{
	51	return op->reg ? CMDQ_REG_TYPE : CMDQ_IMMEDIATE_VALUE;
	52	}
	53
	54	static inline u16 cmdq_operand_get_idx_value(struct cmdq_operand *op)
	55	{
	56	return op->reg ? op->idx : op->value;
	57	}
	58
d412f18c BH	59	int cmdq_dev_get_client_reg(struct device *dev,
	60	struct cmdq_client_reg *client_reg, int idx)
	61	{
	62	struct of_phandle_args spec;
	63	int err;
	64
	65	if (!client_reg)
	66	return -ENOENT;
	67
	68	err = of_parse_phandle_with_fixed_args(dev->of_node,
	69	"mediatek,gce-client-reg",
	70	3, idx, &spec);
	71	if (err < 0) {
27e69538	72	dev_warn(dev,
d412f18c BH	73	"error %d can't parse gce-client-reg property (%d)",
	74	err, idx);
	75
	76	return err;
	77	}
	78
	79	client_reg->subsys = (u8)spec.args[0];
	80	client_reg->offset = (u16)spec.args[1];
	81	client_reg->size = (u16)spec.args[2];
	82	of_node_put(spec.np);
	83
	84	return 0;
	85	}
	86	EXPORT_SYMBOL(cmdq_dev_get_client_reg);
	87
a69dcdfc	88	struct cmdq_client cmdq_mbox_create(struct device dev, int index)
576f1b4b HW	89	{
	90	struct cmdq_client *client;
	91
	92	client = kzalloc(sizeof(*client), GFP_KERNEL);
	93	if (!client)
	94	return (struct cmdq_client *)-ENOMEM;
	95
576f1b4b HW	96	client->client.dev = dev;
576f1b4b HW	97	client->client.tx_block = false;
ce35e21d	98	client->client.knows_txdone = true;
576f1b4b HW	99	client->chan = mbox_request_channel(&client->client, index);
	100
	101	if (IS_ERR(client->chan)) {
	102	long err;
	103
	104	dev_err(dev, "failed to request channel\n");
	105	err = PTR_ERR(client->chan);
	106	kfree(client);
	107
	108	return ERR_PTR(err);
	109	}
	110
	111	return client;
	112	}
	113	EXPORT_SYMBOL(cmdq_mbox_create);
	114
	115	void cmdq_mbox_destroy(struct cmdq_client *client)
	116	{
576f1b4b HW	117	mbox_free_channel(client->chan);
	118	kfree(client);
	119	}
	120	EXPORT_SYMBOL(cmdq_mbox_destroy);
	121
b81b2d55	122	int cmdq_pkt_create(struct cmdq_client client, struct cmdq_pkt pkt, size_t size)
576f1b4b	123	{
576f1b4b HW	124	struct device *dev;
	125	dma_addr_t dma_addr;
	126
576f1b4b	127	pkt->va_base = kzalloc(size, GFP_KERNEL);
b81b2d55 CKH	128	if (!pkt->va_base)
	129	return -ENOMEM;
	130
576f1b4b	131	pkt->buf_size = size;
576f1b4b HW	132
	133	dev = client->chan->mbox->dev;
	134	dma_addr = dma_map_single(dev, pkt->va_base, pkt->buf_size,
	135	DMA_TO_DEVICE);
	136	if (dma_mapping_error(dev, dma_addr)) {
	137	dev_err(dev, "dma map failed, size=%u\n", (u32)(u64)size);
	138	kfree(pkt->va_base);
b81b2d55	139	return -ENOMEM;
576f1b4b HW	140	}
	141
	142	pkt->pa_base = dma_addr;
	143
b81b2d55	144	return 0;
576f1b4b HW	145	}
	146	EXPORT_SYMBOL(cmdq_pkt_create);
	147
b81b2d55	148	void cmdq_pkt_destroy(struct cmdq_client client, struct cmdq_pkt pkt)
576f1b4b	149	{
576f1b4b HW	150	dma_unmap_single(client->chan->mbox->dev, pkt->pa_base, pkt->buf_size,
	151	DMA_TO_DEVICE);
	152	kfree(pkt->va_base);
576f1b4b HW	153	}
	154	EXPORT_SYMBOL(cmdq_pkt_destroy);
	155
5c8b718c BH	156	static int cmdq_pkt_append_command(struct cmdq_pkt *pkt,
5c8b718c BH	157	struct cmdq_instruction inst)
576f1b4b	158	{
5c8b718c	159	struct cmdq_instruction *cmd_ptr;
576f1b4b HW	160
	161	if (unlikely(pkt->cmd_buf_size + CMDQ_INST_SIZE > pkt->buf_size)) {
	162	/*
	163	* In the case of allocated buffer size (pkt->buf_size) is used
	164	* up, the real required size (pkt->cmdq_buf_size) is still
	165	* increased, so that the user knows how much memory should be
	166	* ultimately allocated after appending all commands and
	167	* flushing the command packet. Therefor, the user can call
	168	* cmdq_pkt_create() again with the real required buffer size.
	169	*/
	170	pkt->cmd_buf_size += CMDQ_INST_SIZE;
	171	WARN_ONCE(1, "%s: buffer size %u is too small !\n",
	172	__func__, (u32)pkt->buf_size);
	173	return -ENOMEM;
	174	}
5c8b718c	175
576f1b4b	176	cmd_ptr = pkt->va_base + pkt->cmd_buf_size;
5c8b718c	177	*cmd_ptr = inst;
576f1b4b HW	178	pkt->cmd_buf_size += CMDQ_INST_SIZE;
	179
	180	return 0;
	181	}
	182
556030f0	183	int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value)
576f1b4b	184	{
5c8b718c	185	struct cmdq_instruction inst;
576f1b4b	186
5c8b718c BH	187	inst.op = CMDQ_CODE_WRITE;
	188	inst.value = value;
	189	inst.offset = offset;
	190	inst.subsys = subsys;
576f1b4b	191
5c8b718c	192	return cmdq_pkt_append_command(pkt, inst);
576f1b4b HW	193	}
	194	EXPORT_SYMBOL(cmdq_pkt_write);
	195
556030f0 BH	196	int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
556030f0 BH	197	u16 offset, u32 value, u32 mask)
576f1b4b	198	{
5c8b718c BH	199	struct cmdq_instruction inst = { {0} };
5c8b718c BH	200	u16 offset_mask = offset;
01d1b408	201	int err;
576f1b4b HW	202
576f1b4b HW	203	if (mask != 0xffffffff) {
5c8b718c BH	204	inst.op = CMDQ_CODE_MASK;
	205	inst.mask = ~mask;
	206	err = cmdq_pkt_append_command(pkt, inst);
01d1b408 BH	207	if (err < 0)
	208	return err;
	209
576f1b4b HW	210	offset_mask \|= CMDQ_WRITE_ENABLE_MASK;
576f1b4b HW	211	}
01d1b408	212	err = cmdq_pkt_write(pkt, subsys, offset_mask, value);
576f1b4b HW	213
	214	return err;
	215	}
	216	EXPORT_SYMBOL(cmdq_pkt_write_mask);
	217
d3b04aab DYH	218	int cmdq_pkt_read_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx, u16 addr_low,
	219	u16 reg_idx)
	220	{
	221	struct cmdq_instruction inst = {};
	222
	223	inst.op = CMDQ_CODE_READ_S;
	224	inst.dst_t = CMDQ_REG_TYPE;
	225	inst.sop = high_addr_reg_idx;
	226	inst.reg_dst = reg_idx;
	227	inst.src_reg = addr_low;
	228
	229	return cmdq_pkt_append_command(pkt, inst);
	230	}
	231	EXPORT_SYMBOL(cmdq_pkt_read_s);
	232
5f6e560c DYH	233	int cmdq_pkt_write_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
	234	u16 addr_low, u16 src_reg_idx)
	235	{
	236	struct cmdq_instruction inst = {};
	237
	238	inst.op = CMDQ_CODE_WRITE_S;
	239	inst.src_t = CMDQ_REG_TYPE;
	240	inst.sop = high_addr_reg_idx;
	241	inst.offset = addr_low;
	242	inst.src_reg = src_reg_idx;
	243
	244	return cmdq_pkt_append_command(pkt, inst);
	245	}
	246	EXPORT_SYMBOL(cmdq_pkt_write_s);
	247
11c7842d DYH	248	int cmdq_pkt_write_s_mask(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
	249	u16 addr_low, u16 src_reg_idx, u32 mask)
	250	{
	251	struct cmdq_instruction inst = {};
	252	int err;
	253
	254	inst.op = CMDQ_CODE_MASK;
	255	inst.mask = ~mask;
	256	err = cmdq_pkt_append_command(pkt, inst);
	257	if (err < 0)
	258	return err;
	259
	260	inst.mask = 0;
	261	inst.op = CMDQ_CODE_WRITE_S_MASK;
	262	inst.src_t = CMDQ_REG_TYPE;
	263	inst.sop = high_addr_reg_idx;
	264	inst.offset = addr_low;
	265	inst.src_reg = src_reg_idx;
	266
	267	return cmdq_pkt_append_command(pkt, inst);
	268	}
	269	EXPORT_SYMBOL(cmdq_pkt_write_s_mask);
	270
1af43fce DYH	271	int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx,
	272	u16 addr_low, u32 value)
	273	{
	274	struct cmdq_instruction inst = {};
	275
	276	inst.op = CMDQ_CODE_WRITE_S;
	277	inst.sop = high_addr_reg_idx;
	278	inst.offset = addr_low;
	279	inst.value = value;
	280
	281	return cmdq_pkt_append_command(pkt, inst);
	282	}
	283	EXPORT_SYMBOL(cmdq_pkt_write_s_value);
	284
88a2ffc4 DYH	285	int cmdq_pkt_write_s_mask_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx,
	286	u16 addr_low, u32 value, u32 mask)
	287	{
	288	struct cmdq_instruction inst = {};
	289	int err;
	290
	291	inst.op = CMDQ_CODE_MASK;
	292	inst.mask = ~mask;
	293	err = cmdq_pkt_append_command(pkt, inst);
	294	if (err < 0)
	295	return err;
	296
	297	inst.op = CMDQ_CODE_WRITE_S_MASK;
	298	inst.sop = high_addr_reg_idx;
	299	inst.offset = addr_low;
	300	inst.value = value;
	301
	302	return cmdq_pkt_append_command(pkt, inst);
	303	}
	304	EXPORT_SYMBOL(cmdq_pkt_write_s_mask_value);
	305
263801f8 JJL	306	int cmdq_pkt_mem_move(struct cmdq_pkt *pkt, dma_addr_t src_addr, dma_addr_t dst_addr)
	307	{
	308	const u16 high_addr_reg_idx = CMDQ_THR_SPR_IDX0;
	309	const u16 value_reg_idx = CMDQ_THR_SPR_IDX1;
	310	int ret;
	311
	312	/* read the value of src_addr into high_addr_reg_idx */
	313	ret = cmdq_pkt_assign(pkt, high_addr_reg_idx, CMDQ_ADDR_HIGH(src_addr));
	314	if (ret < 0)
	315	return ret;
	316	ret = cmdq_pkt_read_s(pkt, high_addr_reg_idx, CMDQ_ADDR_LOW(src_addr), value_reg_idx);
	317	if (ret < 0)
	318	return ret;
	319
	320	/* write the value of value_reg_idx into dst_addr */
	321	ret = cmdq_pkt_assign(pkt, high_addr_reg_idx, CMDQ_ADDR_HIGH(dst_addr));
	322	if (ret < 0)
	323	return ret;
	324	ret = cmdq_pkt_write_s(pkt, high_addr_reg_idx, CMDQ_ADDR_LOW(dst_addr), value_reg_idx);
	325	if (ret < 0)
	326	return ret;
	327
	328	return 0;
	329	}
	330	EXPORT_SYMBOL(cmdq_pkt_mem_move);
	331
23c22299	332	int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event, bool clear)
576f1b4b	333	{
5c8b718c	334	struct cmdq_instruction inst = { {0} };
23c22299	335	u32 clear_option = clear ? CMDQ_WFE_UPDATE : 0;
576f1b4b HW	336
	337	if (event >= CMDQ_MAX_EVENT)
	338	return -EINVAL;
	339
5c8b718c	340	inst.op = CMDQ_CODE_WFE;
23c22299	341	inst.value = CMDQ_WFE_OPTION \| clear_option;
5c8b718c	342	inst.event = event;
576f1b4b	343
5c8b718c	344	return cmdq_pkt_append_command(pkt, inst);
576f1b4b HW	345	}
	346	EXPORT_SYMBOL(cmdq_pkt_wfe);
	347
69ff6833 JJL	348	int cmdq_pkt_acquire_event(struct cmdq_pkt *pkt, u16 event)
	349	{
	350	struct cmdq_instruction inst = {};
	351
	352	if (event >= CMDQ_MAX_EVENT)
	353	return -EINVAL;
	354
	355	inst.op = CMDQ_CODE_WFE;
	356	inst.value = CMDQ_WFE_UPDATE \| CMDQ_WFE_UPDATE_VALUE \| CMDQ_WFE_WAIT;
	357	inst.event = event;
	358
	359	return cmdq_pkt_append_command(pkt, inst);
	360	}
	361	EXPORT_SYMBOL(cmdq_pkt_acquire_event);
	362
556030f0	363	int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event)
576f1b4b	364	{
5c8b718c BH	365	struct cmdq_instruction inst = { {0} };
5c8b718c BH	366
576f1b4b HW	367	if (event >= CMDQ_MAX_EVENT)
	368	return -EINVAL;
	369
5c8b718c BH	370	inst.op = CMDQ_CODE_WFE;
	371	inst.value = CMDQ_WFE_UPDATE;
	372	inst.event = event;
	373
	374	return cmdq_pkt_append_command(pkt, inst);
576f1b4b HW	375	}
	376	EXPORT_SYMBOL(cmdq_pkt_clear_event);
	377
7de796ca DYH	378	int cmdq_pkt_set_event(struct cmdq_pkt *pkt, u16 event)
	379	{
	380	struct cmdq_instruction inst = {};
	381
	382	if (event >= CMDQ_MAX_EVENT)
	383	return -EINVAL;
	384
	385	inst.op = CMDQ_CODE_WFE;
	386	inst.value = CMDQ_WFE_UPDATE \| CMDQ_WFE_UPDATE_VALUE;
	387	inst.event = event;
	388
	389	return cmdq_pkt_append_command(pkt, inst);
	390	}
	391	EXPORT_SYMBOL(cmdq_pkt_set_event);
	392
b2ff2356 BH	393	int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys,
	394	u16 offset, u32 value)
	395	{
	396	struct cmdq_instruction inst = { {0} };
	397	int err;
	398
	399	inst.op = CMDQ_CODE_POLL;
	400	inst.value = value;
	401	inst.offset = offset;
	402	inst.subsys = subsys;
	403	err = cmdq_pkt_append_command(pkt, inst);
	404
	405	return err;
	406	}
	407	EXPORT_SYMBOL(cmdq_pkt_poll);
	408
	409	int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys,
	410	u16 offset, u32 value, u32 mask)
	411	{
	412	struct cmdq_instruction inst = { {0} };
	413	int err;
	414
	415	inst.op = CMDQ_CODE_MASK;
	416	inst.mask = ~mask;
	417	err = cmdq_pkt_append_command(pkt, inst);
	418	if (err < 0)
	419	return err;
	420
	421	offset = offset \| CMDQ_POLL_ENABLE_MASK;
	422	err = cmdq_pkt_poll(pkt, subsys, offset, value);
	423
	424	return err;
	425	}
	426	EXPORT_SYMBOL(cmdq_pkt_poll_mask);
	427
400e2fa8 JJL	428	int cmdq_pkt_poll_addr(struct cmdq_pkt *pkt, dma_addr_t addr, u32 value, u32 mask)
	429	{
	430	struct cmdq_instruction inst = { {0} };
	431	u8 use_mask = 0;
	432	int ret;
	433
	434	/*
	435	* Append an MASK instruction to set the mask for following POLL instruction
	436	* which enables use_mask bit.
	437	*/
	438	if (mask != GENMASK(31, 0)) {
	439	inst.op = CMDQ_CODE_MASK;
	440	inst.mask = ~mask;
	441	ret = cmdq_pkt_append_command(pkt, inst);
	442	if (ret < 0)
	443	return ret;
	444	use_mask = CMDQ_POLL_ENABLE_MASK;
	445	}
	446
	447	/*
	448	* POLL is an legacy operation in GCE and it does not support SPR and CMDQ_CODE_LOGIC,
	449	* so it can not use cmdq_pkt_assign to keep polling register address to SPR.
	450	* If user wants to poll a register address which doesn't have a subsys id,
	451	* user needs to use GPR and CMDQ_CODE_MASK to move polling register address to GPR.
	452	*/
	453	inst.op = CMDQ_CODE_MASK;
	454	inst.dst_t = CMDQ_REG_TYPE;
	455	inst.sop = CMDQ_POLL_ADDR_GPR;
	456	inst.value = addr;
	457	ret = cmdq_pkt_append_command(pkt, inst);
	458	if (ret < 0)
	459	return ret;
	460
	461	/* Append POLL instruction to poll the register address assign to GPR previously. */
	462	inst.op = CMDQ_CODE_POLL;
	463	inst.dst_t = CMDQ_REG_TYPE;
	464	inst.sop = CMDQ_POLL_ADDR_GPR;
	465	inst.offset = use_mask;
	466	inst.value = value;
	467	ret = cmdq_pkt_append_command(pkt, inst);
	468	if (ret < 0)
	469	return ret;
	470
	471	return 0;
	472	}
	473	EXPORT_SYMBOL(cmdq_pkt_poll_addr);
	474
58de63dd JJL	475	int cmdq_pkt_logic_command(struct cmdq_pkt *pkt, u16 result_reg_idx,
	476	struct cmdq_operand *left_operand,
	477	enum cmdq_logic_op s_op,
	478	struct cmdq_operand *right_operand)
	479	{
	480	struct cmdq_instruction inst = { {0} };
	481
	482	if (!left_operand \|\| !right_operand \|\| s_op >= CMDQ_LOGIC_MAX)
	483	return -EINVAL;
	484
	485	inst.op = CMDQ_CODE_LOGIC;
	486	inst.dst_t = CMDQ_REG_TYPE;
	487	inst.src_t = cmdq_operand_get_type(left_operand);
	488	inst.arg_c_t = cmdq_operand_get_type(right_operand);
	489	inst.sop = s_op;
	490	inst.reg_dst = result_reg_idx;
	491	inst.src_reg = cmdq_operand_get_idx_value(left_operand);
	492	inst.arg_c = cmdq_operand_get_idx_value(right_operand);
	493
	494	return cmdq_pkt_append_command(pkt, inst);
	495	}
	496	EXPORT_SYMBOL(cmdq_pkt_logic_command);
	497
613c2e2c DYH	498	int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value)
	499	{
	500	struct cmdq_instruction inst = {};
	501
	502	inst.op = CMDQ_CODE_LOGIC;
	503	inst.dst_t = CMDQ_REG_TYPE;
	504	inst.reg_dst = reg_idx;
	505	inst.value = value;
	506	return cmdq_pkt_append_command(pkt, inst);
	507	}
	508	EXPORT_SYMBOL(cmdq_pkt_assign);
	509
7218be3b	510	int cmdq_pkt_jump_abs(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa)
946f1792 DYH	511	{
	512	struct cmdq_instruction inst = {};
	513
	514	inst.op = CMDQ_CODE_JUMP;
ed4d5ab1	515	inst.offset = CMDQ_JUMP_ABSOLUTE;
ade17653	516	inst.value = addr >> shift_pa;
946f1792 DYH	517	return cmdq_pkt_append_command(pkt, inst);
946f1792 DYH	518	}
7218be3b	519	EXPORT_SYMBOL(cmdq_pkt_jump_abs);
946f1792	520
698cdcb1 CKH	521	int cmdq_pkt_jump_rel(struct cmdq_pkt *pkt, s32 offset, u8 shift_pa)
	522	{
	523	struct cmdq_instruction inst = { {0} };
	524
	525	inst.op = CMDQ_CODE_JUMP;
	526	inst.value = (u32)offset >> shift_pa;
	527	return cmdq_pkt_append_command(pkt, inst);
	528	}
	529	EXPORT_SYMBOL(cmdq_pkt_jump_rel);
	530
3d86ced9 CKH	531	int cmdq_pkt_eoc(struct cmdq_pkt *pkt)
	532	{
	533	struct cmdq_instruction inst = { {0} };
	534
	535	inst.op = CMDQ_CODE_EOC;
	536	inst.value = CMDQ_EOC_IRQ_EN;
	537	return cmdq_pkt_append_command(pkt, inst);
	538	}
	539	EXPORT_SYMBOL(cmdq_pkt_eoc);
	540
99581858	541	int cmdq_pkt_finalize(struct cmdq_pkt *pkt)
576f1b4b	542	{
5c8b718c	543	struct cmdq_instruction inst = { {0} };
576f1b4b HW	544	int err;
	545
	546	/* insert EOC and generate IRQ for each command iteration */
5c8b718c BH	547	inst.op = CMDQ_CODE_EOC;
	548	inst.value = CMDQ_EOC_IRQ_EN;
	549	err = cmdq_pkt_append_command(pkt, inst);
01d1b408 BH	550	if (err < 0)
01d1b408 BH	551	return err;
576f1b4b HW	552
576f1b4b HW	553	/* JUMP to end */
5c8b718c	554	inst.op = CMDQ_CODE_JUMP;
2b8cf383 DYH	555	inst.value = CMDQ_JUMP_PASS >>
2b8cf383 DYH	556	cmdq_get_shift_pa(((struct cmdq_client *)pkt->cl)->chan);
5c8b718c	557	err = cmdq_pkt_append_command(pkt, inst);
576f1b4b HW	558
	559	return err;
	560	}
99581858	561	EXPORT_SYMBOL(cmdq_pkt_finalize);
576f1b4b	562
a862a3f7	563	MODULE_DESCRIPTION("MediaTek Command Queue (CMDQ) driver");
576f1b4b	564	MODULE_LICENSE("GPL v2");