Commit | Line | Data |
---|---|---|
bc3fc5c0 FP |
1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | ||
3 | #ifndef __SOC_MEDIATEK_MT8365_MMSYS_H | |
4 | #define __SOC_MEDIATEK_MT8365_MMSYS_H | |
5 | ||
6 | #define MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0xf3c | |
7 | #define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL 0xf4c | |
8 | #define MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN 0xf50 | |
9 | #define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN 0xf54 | |
10 | #define MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN 0xf60 | |
11 | #define MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0xf64 | |
12 | #define MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN 0xf68 | |
13 | ||
14 | #define MT8365_RDMA0_SOUT_COLOR0 0x1 | |
15 | #define MT8365_DITHER_MOUT_EN_DSI0 0x1 | |
16 | #define MT8365_DSI0_SEL_IN_DITHER 0x1 | |
17 | #define MT8365_RDMA0_SEL_IN_OVL0 0x0 | |
18 | #define MT8365_RDMA0_RSZ0_SEL_IN_RDMA0 0x0 | |
19 | #define MT8365_DISP_COLOR_SEL_IN_COLOR0 0x0 | |
20 | #define MT8365_OVL0_MOUT_PATH0_SEL BIT(0) | |
21 | ||
22 | static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = { | |
23 | { | |
24 | DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, | |
25 | MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, | |
26 | MT8365_OVL0_MOUT_PATH0_SEL, MT8365_OVL0_MOUT_PATH0_SEL | |
27 | }, | |
28 | { | |
29 | DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, | |
30 | MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN, | |
31 | MT8365_RDMA0_SEL_IN_OVL0, MT8365_RDMA0_SEL_IN_OVL0 | |
32 | }, | |
33 | { | |
34 | DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, | |
35 | MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL, | |
36 | MT8365_RDMA0_SOUT_COLOR0, MT8365_RDMA0_SOUT_COLOR0 | |
37 | }, | |
38 | { | |
39 | DDP_COMPONENT_COLOR0, DDP_COMPONENT_CCORR, | |
40 | MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, | |
41 | MT8365_DISP_COLOR_SEL_IN_COLOR0,MT8365_DISP_COLOR_SEL_IN_COLOR0 | |
42 | }, | |
43 | { | |
44 | DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, | |
45 | MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN, | |
46 | MT8365_DITHER_MOUT_EN_DSI0, MT8365_DITHER_MOUT_EN_DSI0 | |
47 | }, | |
48 | { | |
49 | DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, | |
50 | MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, | |
51 | MT8365_DSI0_SEL_IN_DITHER, MT8365_DSI0_SEL_IN_DITHER | |
52 | }, | |
53 | { | |
54 | DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, | |
55 | MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN, | |
56 | MT8365_RDMA0_RSZ0_SEL_IN_RDMA0, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0 | |
57 | }, | |
58 | }; | |
59 | ||
60 | #endif /* __SOC_MEDIATEK_MT8365_MMSYS_H */ |