[linux-block.git] / drivers / soc / amlogic / meson-gx-pwrc-vpu.c

/*
 * Copyright (c) 2017 BayLibre, SAS
 * Author: Neil Armstrong <narmstrong@baylibre.com>
 *
 * SPDX-License-Identifier: GPL-2.0+
 */

#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/bitfield.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <linux/of_device.h>
#include <linux/reset.h>
#include <linux/clk.h>
#include <linux/module.h>

/* AO Offsets */

#define AO_RTI_GEN_PWR_SLEEP0		(0x3a << 2)

#define GEN_PWR_VPU_HDMI		BIT(8)
#define GEN_PWR_VPU_HDMI_ISO		BIT(9)

/* HHI Offsets */

#define HHI_MEM_PD_REG0			(0x40 << 2)
#define HHI_VPU_MEM_PD_REG0		(0x41 << 2)
#define HHI_VPU_MEM_PD_REG1		(0x42 << 2)
#define HHI_VPU_MEM_PD_REG2		(0x4d << 2)

struct meson_gx_pwrc_vpu {
	struct generic_pm_domain genpd;
	struct regmap *regmap_ao;
	struct regmap *regmap_hhi;
	struct reset_control *rstc;
	struct clk *vpu_clk;
	struct clk *vapb_clk;
};

static inline
struct meson_gx_pwrc_vpu *genpd_to_pd(struct generic_pm_domain *d)
{
	return container_of(d, struct meson_gx_pwrc_vpu, genpd);
}

static int meson_gx_pwrc_vpu_power_off(struct generic_pm_domain *genpd)
{
	struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
	int i;

	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
			   GEN_PWR_VPU_HDMI_ISO, GEN_PWR_VPU_HDMI_ISO);
	udelay(20);

	/* Power Down Memories */
	for (i = 0; i < 32; i += 2) {
		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
				   0x3 << i, 0x3 << i);
		udelay(5);
	}
	for (i = 0; i < 32; i += 2) {
		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
				   0x3 << i, 0x3 << i);
		udelay(5);
	}
	for (i = 8; i < 16; i++) {
		regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
				   BIT(i), BIT(i));
		udelay(5);
	}
	udelay(20);

	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
			   GEN_PWR_VPU_HDMI, GEN_PWR_VPU_HDMI);

	msleep(20);

	clk_disable_unprepare(pd->vpu_clk);
	clk_disable_unprepare(pd->vapb_clk);

	return 0;
}

static int meson_g12a_pwrc_vpu_power_off(struct generic_pm_domain *genpd)
{
	struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
	int i;

	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
			   GEN_PWR_VPU_HDMI_ISO, GEN_PWR_VPU_HDMI_ISO);
	udelay(20);

	/* Power Down Memories */
	for (i = 0; i < 32; i += 2) {
		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
				   0x3 << i, 0x3 << i);
		udelay(5);
	}
	for (i = 0; i < 32; i += 2) {
		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
				   0x3 << i, 0x3 << i);
		udelay(5);
	}
	for (i = 0; i < 32; i += 2) {
		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG2,
				   0x3 << i, 0x3 << i);
		udelay(5);
	}
	for (i = 8; i < 16; i++) {
		regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
				   BIT(i), BIT(i));
		udelay(5);
	}
	udelay(20);

	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
			   GEN_PWR_VPU_HDMI, GEN_PWR_VPU_HDMI);

	msleep(20);

	clk_disable_unprepare(pd->vpu_clk);
	clk_disable_unprepare(pd->vapb_clk);

	return 0;
}

static int meson_gx_pwrc_vpu_setup_clk(struct meson_gx_pwrc_vpu *pd)
{
	int ret;

	ret = clk_prepare_enable(pd->vpu_clk);
	if (ret)
		return ret;

	ret = clk_prepare_enable(pd->vapb_clk);
	if (ret)
		clk_disable_unprepare(pd->vpu_clk);

	return ret;
}

static int meson_gx_pwrc_vpu_power_on(struct generic_pm_domain *genpd)
{
	struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
	int ret;
	int i;

	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
			   GEN_PWR_VPU_HDMI, 0);
	udelay(20);

	/* Power Up Memories */
	for (i = 0; i < 32; i += 2) {
		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
				   0x3 << i, 0);
		udelay(5);
	}

	for (i = 0; i < 32; i += 2) {
		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
				   0x3 << i, 0);
		udelay(5);
	}

	for (i = 8; i < 16; i++) {
		regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
				   BIT(i), 0);
		udelay(5);
	}
	udelay(20);

	ret = reset_control_assert(pd->rstc);
	if (ret)
		return ret;

	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
			   GEN_PWR_VPU_HDMI_ISO, 0);

	ret = reset_control_deassert(pd->rstc);
	if (ret)
		return ret;

	ret = meson_gx_pwrc_vpu_setup_clk(pd);
	if (ret)
		return ret;

	return 0;
}

static int meson_g12a_pwrc_vpu_power_on(struct generic_pm_domain *genpd)
{
	struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
	int ret;
	int i;

	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
			   GEN_PWR_VPU_HDMI, 0);
	udelay(20);

	/* Power Up Memories */
	for (i = 0; i < 32; i += 2) {
		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
				   0x3 << i, 0);
		udelay(5);
	}

	for (i = 0; i < 32; i += 2) {
		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
				   0x3 << i, 0);
		udelay(5);
	}

	for (i = 0; i < 32; i += 2) {
		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG2,
				   0x3 << i, 0);
		udelay(5);
	}

	for (i = 8; i < 16; i++) {
		regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
				   BIT(i), 0);
		udelay(5);
	}
	udelay(20);

	ret = reset_control_assert(pd->rstc);
	if (ret)
		return ret;

	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
			   GEN_PWR_VPU_HDMI_ISO, 0);

	ret = reset_control_deassert(pd->rstc);
	if (ret)
		return ret;

	ret = meson_gx_pwrc_vpu_setup_clk(pd);
	if (ret)
		return ret;

	return 0;
}

static bool meson_gx_pwrc_vpu_get_power(struct meson_gx_pwrc_vpu *pd)
{
	u32 reg;

	regmap_read(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0, &reg);

	return (reg & GEN_PWR_VPU_HDMI);
}

static struct meson_gx_pwrc_vpu vpu_hdmi_pd = {
	.genpd = {
		.name = "vpu_hdmi",
		.power_off = meson_gx_pwrc_vpu_power_off,
		.power_on = meson_gx_pwrc_vpu_power_on,
	},
};

static struct meson_gx_pwrc_vpu vpu_hdmi_pd_g12a = {
	.genpd = {
		.name = "vpu_hdmi",
		.power_off = meson_g12a_pwrc_vpu_power_off,
		.power_on = meson_g12a_pwrc_vpu_power_on,
	},
};

static int meson_gx_pwrc_vpu_probe(struct platform_device *pdev)
{
	const struct meson_gx_pwrc_vpu *vpu_pd_match;
	struct regmap *regmap_ao, *regmap_hhi;
	struct meson_gx_pwrc_vpu *vpu_pd;
	struct device_node *parent_np;
	struct reset_control *rstc;
	struct clk *vpu_clk;
	struct clk *vapb_clk;
	bool powered_off;
	int ret;

	vpu_pd_match = of_device_get_match_data(&pdev->dev);
	if (!vpu_pd_match) {
		dev_err(&pdev->dev, "failed to get match data\n");
		return -ENODEV;
	}

	vpu_pd = devm_kzalloc(&pdev->dev, sizeof(*vpu_pd), GFP_KERNEL);
	if (!vpu_pd)
		return -ENOMEM;

	memcpy(vpu_pd, vpu_pd_match, sizeof(*vpu_pd));

	parent_np = of_get_parent(pdev->dev.of_node);
	regmap_ao = syscon_node_to_regmap(parent_np);
	of_node_put(parent_np);
	if (IS_ERR(regmap_ao)) {
		dev_err(&pdev->dev, "failed to get regmap\n");
		return PTR_ERR(regmap_ao);
	}

	regmap_hhi = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
						     "amlogic,hhi-sysctrl");
	if (IS_ERR(regmap_hhi)) {
		dev_err(&pdev->dev, "failed to get HHI regmap\n");
		return PTR_ERR(regmap_hhi);
	}

	rstc = devm_reset_control_array_get_exclusive(&pdev->dev);
	if (IS_ERR(rstc)) {
		if (PTR_ERR(rstc) != -EPROBE_DEFER)
			dev_err(&pdev->dev, "failed to get reset lines\n");
		return PTR_ERR(rstc);
	}

	vpu_clk = devm_clk_get(&pdev->dev, "vpu");
	if (IS_ERR(vpu_clk)) {
		dev_err(&pdev->dev, "vpu clock request failed\n");
		return PTR_ERR(vpu_clk);
	}

	vapb_clk = devm_clk_get(&pdev->dev, "vapb");
	if (IS_ERR(vapb_clk)) {
		dev_err(&pdev->dev, "vapb clock request failed\n");
		return PTR_ERR(vapb_clk);
	}

	vpu_pd->regmap_ao = regmap_ao;
	vpu_pd->regmap_hhi = regmap_hhi;
	vpu_pd->rstc = rstc;
	vpu_pd->vpu_clk = vpu_clk;
	vpu_pd->vapb_clk = vapb_clk;

	platform_set_drvdata(pdev, vpu_pd);

	powered_off = meson_gx_pwrc_vpu_get_power(vpu_pd);

	/* If already powered, sync the clock states */
	if (!powered_off) {
		ret = meson_gx_pwrc_vpu_setup_clk(vpu_pd);
		if (ret)
			return ret;
	}

	vpu_pd->genpd.flags = GENPD_FLAG_ALWAYS_ON;
	pm_genpd_init(&vpu_pd->genpd, NULL, powered_off);

	return of_genpd_add_provider_simple(pdev->dev.of_node,
					    &vpu_pd->genpd);
}

static void meson_gx_pwrc_vpu_shutdown(struct platform_device *pdev)
{
	struct meson_gx_pwrc_vpu *vpu_pd = platform_get_drvdata(pdev);
	bool powered_off;

	powered_off = meson_gx_pwrc_vpu_get_power(vpu_pd);
	if (!powered_off)
		vpu_pd->genpd.power_off(&vpu_pd->genpd);
}

static const struct of_device_id meson_gx_pwrc_vpu_match_table[] = {
	{ .compatible = "amlogic,meson-gx-pwrc-vpu", .data = &vpu_hdmi_pd },
	{
	  .compatible = "amlogic,meson-g12a-pwrc-vpu",
	  .data = &vpu_hdmi_pd_g12a
	},
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, meson_gx_pwrc_vpu_match_table);

static struct platform_driver meson_gx_pwrc_vpu_driver = {
	.probe	= meson_gx_pwrc_vpu_probe,
	.shutdown = meson_gx_pwrc_vpu_shutdown,
	.driver = {
		.name		= "meson_gx_pwrc_vpu",
		.of_match_table	= meson_gx_pwrc_vpu_match_table,
	},
};
module_platform_driver(meson_gx_pwrc_vpu_driver);
MODULE_LICENSE("GPL v2");
Commit	Line	Data
75fcb5ca NA	1	/*
	2	* Copyright (c) 2017 BayLibre, SAS
	3	* Author: Neil Armstrong <narmstrong@baylibre.com>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <linux/of_address.h>
	9	#include <linux/platform_device.h>
	10	#include <linux/pm_domain.h>
	11	#include <linux/bitfield.h>
	12	#include <linux/regmap.h>
	13	#include <linux/mfd/syscon.h>
bb1dca3a	14	#include <linux/of_device.h>
75fcb5ca NA	15	#include <linux/reset.h>
75fcb5ca NA	16	#include <linux/clk.h>
d9da1785	17	#include <linux/module.h>
75fcb5ca NA	18
	19	/* AO Offsets */
	20
	21	#define AO_RTI_GEN_PWR_SLEEP0 (0x3a << 2)
	22
	23	#define GEN_PWR_VPU_HDMI BIT(8)
	24	#define GEN_PWR_VPU_HDMI_ISO BIT(9)
	25
	26	/* HHI Offsets */
	27
	28	#define HHI_MEM_PD_REG0 (0x40 << 2)
	29	#define HHI_VPU_MEM_PD_REG0 (0x41 << 2)
	30	#define HHI_VPU_MEM_PD_REG1 (0x42 << 2)
bb1dca3a	31	#define HHI_VPU_MEM_PD_REG2 (0x4d << 2)
75fcb5ca NA	32
	33	struct meson_gx_pwrc_vpu {
	34	struct generic_pm_domain genpd;
	35	struct regmap *regmap_ao;
	36	struct regmap *regmap_hhi;
	37	struct reset_control *rstc;
	38	struct clk *vpu_clk;
	39	struct clk *vapb_clk;
75fcb5ca NA	40	};
	41
	42	static inline
	43	struct meson_gx_pwrc_vpu genpd_to_pd(struct generic_pm_domain d)
	44	{
	45	return container_of(d, struct meson_gx_pwrc_vpu, genpd);
	46	}
	47
	48	static int meson_gx_pwrc_vpu_power_off(struct generic_pm_domain *genpd)
	49	{
	50	struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
	51	int i;
	52
	53	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
	54	GEN_PWR_VPU_HDMI_ISO, GEN_PWR_VPU_HDMI_ISO);
	55	udelay(20);
	56
	57	/* Power Down Memories */
	58	for (i = 0; i < 32; i += 2) {
	59	regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
2fe3b4bb	60	0x3 << i, 0x3 << i);
75fcb5ca NA	61	udelay(5);
	62	}
	63	for (i = 0; i < 32; i += 2) {
	64	regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
2fe3b4bb	65	0x3 << i, 0x3 << i);
75fcb5ca NA	66	udelay(5);
	67	}
	68	for (i = 8; i < 16; i++) {
	69	regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
	70	BIT(i), BIT(i));
	71	udelay(5);
	72	}
	73	udelay(20);
	74
	75	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
	76	GEN_PWR_VPU_HDMI, GEN_PWR_VPU_HDMI);
	77
	78	msleep(20);
	79
	80	clk_disable_unprepare(pd->vpu_clk);
	81	clk_disable_unprepare(pd->vapb_clk);
	82
75fcb5ca NA	83	return 0;
	84	}
	85
bb1dca3a NA	86	static int meson_g12a_pwrc_vpu_power_off(struct generic_pm_domain *genpd)
	87	{
	88	struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
	89	int i;
	90
	91	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
	92	GEN_PWR_VPU_HDMI_ISO, GEN_PWR_VPU_HDMI_ISO);
	93	udelay(20);
	94
	95	/* Power Down Memories */
	96	for (i = 0; i < 32; i += 2) {
	97	regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
	98	0x3 << i, 0x3 << i);
	99	udelay(5);
	100	}
	101	for (i = 0; i < 32; i += 2) {
	102	regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
	103	0x3 << i, 0x3 << i);
	104	udelay(5);
	105	}
	106	for (i = 0; i < 32; i += 2) {
	107	regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG2,
	108	0x3 << i, 0x3 << i);
	109	udelay(5);
	110	}
	111	for (i = 8; i < 16; i++) {
	112	regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
	113	BIT(i), BIT(i));
	114	udelay(5);
	115	}
	116	udelay(20);
	117
	118	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
	119	GEN_PWR_VPU_HDMI, GEN_PWR_VPU_HDMI);
	120
	121	msleep(20);
	122
	123	clk_disable_unprepare(pd->vpu_clk);
	124	clk_disable_unprepare(pd->vapb_clk);
	125
	126	return 0;
	127	}
	128
75fcb5ca NA	129	static int meson_gx_pwrc_vpu_setup_clk(struct meson_gx_pwrc_vpu *pd)
	130	{
	131	int ret;
	132
	133	ret = clk_prepare_enable(pd->vpu_clk);
	134	if (ret)
	135	return ret;
	136
339cd0ea NA	137	ret = clk_prepare_enable(pd->vapb_clk);
	138	if (ret)
	139	clk_disable_unprepare(pd->vpu_clk);
	140
	141	return ret;
75fcb5ca NA	142	}
	143
	144	static int meson_gx_pwrc_vpu_power_on(struct generic_pm_domain *genpd)
	145	{
	146	struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
	147	int ret;
	148	int i;
	149
	150	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
	151	GEN_PWR_VPU_HDMI, 0);
	152	udelay(20);
	153
	154	/* Power Up Memories */
	155	for (i = 0; i < 32; i += 2) {
	156	regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
2fe3b4bb	157	0x3 << i, 0);
75fcb5ca NA	158	udelay(5);
	159	}
	160
	161	for (i = 0; i < 32; i += 2) {
	162	regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
2fe3b4bb	163	0x3 << i, 0);
75fcb5ca NA	164	udelay(5);
	165	}
	166
	167	for (i = 8; i < 16; i++) {
	168	regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
	169	BIT(i), 0);
	170	udelay(5);
	171	}
	172	udelay(20);
	173
	174	ret = reset_control_assert(pd->rstc);
	175	if (ret)
	176	return ret;
	177
	178	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
	179	GEN_PWR_VPU_HDMI_ISO, 0);
	180
	181	ret = reset_control_deassert(pd->rstc);
	182	if (ret)
	183	return ret;
	184
	185	ret = meson_gx_pwrc_vpu_setup_clk(pd);
	186	if (ret)
	187	return ret;
	188
75fcb5ca NA	189	return 0;
	190	}
	191
bb1dca3a NA	192	static int meson_g12a_pwrc_vpu_power_on(struct generic_pm_domain *genpd)
	193	{
	194	struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
	195	int ret;
	196	int i;
	197
	198	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
	199	GEN_PWR_VPU_HDMI, 0);
	200	udelay(20);
	201
	202	/* Power Up Memories */
	203	for (i = 0; i < 32; i += 2) {
	204	regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
	205	0x3 << i, 0);
	206	udelay(5);
	207	}
	208
	209	for (i = 0; i < 32; i += 2) {
	210	regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
	211	0x3 << i, 0);
	212	udelay(5);
	213	}
	214
	215	for (i = 0; i < 32; i += 2) {
	216	regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG2,
	217	0x3 << i, 0);
	218	udelay(5);
	219	}
	220
	221	for (i = 8; i < 16; i++) {
	222	regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
	223	BIT(i), 0);
	224	udelay(5);
	225	}
	226	udelay(20);
	227
	228	ret = reset_control_assert(pd->rstc);
	229	if (ret)
	230	return ret;
	231
	232	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
	233	GEN_PWR_VPU_HDMI_ISO, 0);
	234
	235	ret = reset_control_deassert(pd->rstc);
	236	if (ret)
	237	return ret;
	238
	239	ret = meson_gx_pwrc_vpu_setup_clk(pd);
	240	if (ret)
	241	return ret;
	242
	243	return 0;
	244	}
	245
75fcb5ca NA	246	static bool meson_gx_pwrc_vpu_get_power(struct meson_gx_pwrc_vpu *pd)
	247	{
	248	u32 reg;
	249
	250	regmap_read(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0, &reg);
	251
	252	return (reg & GEN_PWR_VPU_HDMI);
	253	}
	254
	255	static struct meson_gx_pwrc_vpu vpu_hdmi_pd = {
	256	.genpd = {
	257	.name = "vpu_hdmi",
	258	.power_off = meson_gx_pwrc_vpu_power_off,
	259	.power_on = meson_gx_pwrc_vpu_power_on,
	260	},
	261	};
	262
bb1dca3a NA	263	static struct meson_gx_pwrc_vpu vpu_hdmi_pd_g12a = {
	264	.genpd = {
	265	.name = "vpu_hdmi",
	266	.power_off = meson_g12a_pwrc_vpu_power_off,
	267	.power_on = meson_g12a_pwrc_vpu_power_on,
	268	},
	269	};
	270
75fcb5ca NA	271	static int meson_gx_pwrc_vpu_probe(struct platform_device *pdev)
75fcb5ca NA	272	{
bb1dca3a	273	const struct meson_gx_pwrc_vpu *vpu_pd_match;
75fcb5ca	274	struct regmap regmap_ao, regmap_hhi;
bb1dca3a	275	struct meson_gx_pwrc_vpu *vpu_pd;
9491cff1	276	struct device_node *parent_np;
75fcb5ca NA	277	struct reset_control *rstc;
	278	struct clk *vpu_clk;
	279	struct clk *vapb_clk;
339cd0ea NA	280	bool powered_off;
339cd0ea NA	281	int ret;
75fcb5ca	282
bb1dca3a NA	283	vpu_pd_match = of_device_get_match_data(&pdev->dev);
	284	if (!vpu_pd_match) {
	285	dev_err(&pdev->dev, "failed to get match data\n");
	286	return -ENODEV;
	287	}
	288
	289	vpu_pd = devm_kzalloc(&pdev->dev, sizeof(*vpu_pd), GFP_KERNEL);
	290	if (!vpu_pd)
	291	return -ENOMEM;
	292
	293	memcpy(vpu_pd, vpu_pd_match, sizeof(*vpu_pd));
	294
9491cff1 LH	295	parent_np = of_get_parent(pdev->dev.of_node);
	296	regmap_ao = syscon_node_to_regmap(parent_np);
	297	of_node_put(parent_np);
75fcb5ca NA	298	if (IS_ERR(regmap_ao)) {
	299	dev_err(&pdev->dev, "failed to get regmap\n");
	300	return PTR_ERR(regmap_ao);
	301	}
	302
	303	regmap_hhi = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
	304	"amlogic,hhi-sysctrl");
	305	if (IS_ERR(regmap_hhi)) {
	306	dev_err(&pdev->dev, "failed to get HHI regmap\n");
	307	return PTR_ERR(regmap_hhi);
	308	}
	309
1116e43e	310	rstc = devm_reset_control_array_get_exclusive(&pdev->dev);
75fcb5ca	311	if (IS_ERR(rstc)) {
3a2ad7bd HK	312	if (PTR_ERR(rstc) != -EPROBE_DEFER)
3a2ad7bd HK	313	dev_err(&pdev->dev, "failed to get reset lines\n");
75fcb5ca NA	314	return PTR_ERR(rstc);
	315	}
	316
	317	vpu_clk = devm_clk_get(&pdev->dev, "vpu");
	318	if (IS_ERR(vpu_clk)) {
	319	dev_err(&pdev->dev, "vpu clock request failed\n");
	320	return PTR_ERR(vpu_clk);
	321	}
	322
	323	vapb_clk = devm_clk_get(&pdev->dev, "vapb");
	324	if (IS_ERR(vapb_clk)) {
	325	dev_err(&pdev->dev, "vapb clock request failed\n");
	326	return PTR_ERR(vapb_clk);
	327	}
	328
bb1dca3a NA	329	vpu_pd->regmap_ao = regmap_ao;
	330	vpu_pd->regmap_hhi = regmap_hhi;
	331	vpu_pd->rstc = rstc;
	332	vpu_pd->vpu_clk = vpu_clk;
	333	vpu_pd->vapb_clk = vapb_clk;
	334
	335	platform_set_drvdata(pdev, vpu_pd);
75fcb5ca	336
bb1dca3a	337	powered_off = meson_gx_pwrc_vpu_get_power(vpu_pd);
339cd0ea NA	338
	339	/* If already powered, sync the clock states */
	340	if (!powered_off) {
bb1dca3a	341	ret = meson_gx_pwrc_vpu_setup_clk(vpu_pd);
339cd0ea NA	342	if (ret)
	343	return ret;
	344	}
	345
5aabf118 KH	346	vpu_pd->genpd.flags = GENPD_FLAG_ALWAYS_ON;
5aabf118 KH	347	pm_genpd_init(&vpu_pd->genpd, NULL, powered_off);
75fcb5ca NA	348
75fcb5ca NA	349	return of_genpd_add_provider_simple(pdev->dev.of_node,
bb1dca3a	350	&vpu_pd->genpd);
75fcb5ca NA	351	}
	352
	353	static void meson_gx_pwrc_vpu_shutdown(struct platform_device *pdev)
	354	{
bb1dca3a	355	struct meson_gx_pwrc_vpu *vpu_pd = platform_get_drvdata(pdev);
87f88732 HK	356	bool powered_off;
87f88732 HK	357
bb1dca3a	358	powered_off = meson_gx_pwrc_vpu_get_power(vpu_pd);
87f88732	359	if (!powered_off)
bb1dca3a	360	vpu_pd->genpd.power_off(&vpu_pd->genpd);
75fcb5ca NA	361	}
	362
	363	static const struct of_device_id meson_gx_pwrc_vpu_match_table[] = {
bb1dca3a NA	364	{ .compatible = "amlogic,meson-gx-pwrc-vpu", .data = &vpu_hdmi_pd },
	365	{
	366	.compatible = "amlogic,meson-g12a-pwrc-vpu",
	367	.data = &vpu_hdmi_pd_g12a
	368	},
75fcb5ca NA	369	{ /* sentinel */ }
75fcb5ca NA	370	};
d9da1785	371	MODULE_DEVICE_TABLE(of, meson_gx_pwrc_vpu_match_table);
75fcb5ca NA	372
	373	static struct platform_driver meson_gx_pwrc_vpu_driver = {
	374	.probe = meson_gx_pwrc_vpu_probe,
	375	.shutdown = meson_gx_pwrc_vpu_shutdown,
	376	.driver = {
	377	.name = "meson_gx_pwrc_vpu",
	378	.of_match_table = meson_gx_pwrc_vpu_match_table,
	379	},
	380	};
d9da1785 KH	381	module_platform_driver(meson_gx_pwrc_vpu_driver);
d9da1785 KH	382	MODULE_LICENSE("GPL v2");