[linux-2.6-block.git] / drivers / slimbus / qcom-ctrl.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2011-2017, The Linux Foundation
 */

#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/pm_runtime.h>
#include "slimbus.h"

/* Manager registers */
#define	MGR_CFG		0x200
#define	MGR_STATUS	0x204
#define	MGR_INT_EN	0x210
#define	MGR_INT_STAT	0x214
#define	MGR_INT_CLR	0x218
#define	MGR_TX_MSG	0x230
#define	MGR_RX_MSG	0x270
#define	MGR_IE_STAT	0x2F0
#define	MGR_VE_STAT	0x300
#define	MGR_CFG_ENABLE	1

/* Framer registers */
#define	FRM_CFG		0x400
#define	FRM_STAT	0x404
#define	FRM_INT_EN	0x410
#define	FRM_INT_STAT	0x414
#define	FRM_INT_CLR	0x418
#define	FRM_WAKEUP	0x41C
#define	FRM_CLKCTL_DONE	0x420
#define	FRM_IE_STAT	0x430
#define	FRM_VE_STAT	0x440

/* Interface registers */
#define	INTF_CFG	0x600
#define	INTF_STAT	0x604
#define	INTF_INT_EN	0x610
#define	INTF_INT_STAT	0x614
#define	INTF_INT_CLR	0x618
#define	INTF_IE_STAT	0x630
#define	INTF_VE_STAT	0x640

/* Interrupt status bits */
#define	MGR_INT_TX_NACKED_2	BIT(25)
#define	MGR_INT_MSG_BUF_CONTE	BIT(26)
#define	MGR_INT_RX_MSG_RCVD	BIT(30)
#define	MGR_INT_TX_MSG_SENT	BIT(31)

/* Framer config register settings */
#define	FRM_ACTIVE	1
#define	CLK_GEAR	7
#define	ROOT_FREQ	11
#define	REF_CLK_GEAR	15
#define	INTR_WAKE	19

#define SLIM_MSG_ASM_FIRST_WORD(l, mt, mc, dt, ad) \
		((l) | ((mt) << 5) | ((mc) << 8) | ((dt) << 15) | ((ad) << 16))

#define SLIM_ROOT_FREQ 24576000
#define QCOM_SLIM_AUTOSUSPEND 1000

/* MAX message size over control channel */
#define SLIM_MSGQ_BUF_LEN	40
#define QCOM_TX_MSGS 2
#define QCOM_RX_MSGS	8
#define QCOM_BUF_ALLOC_RETRIES	10

#define CFG_PORT(r, v) ((v) ? CFG_PORT_V2(r) : CFG_PORT_V1(r))

/* V2 Component registers */
#define CFG_PORT_V2(r) ((r ## _V2))
#define	COMP_CFG_V2		4
#define	COMP_TRUST_CFG_V2	0x3000

/* V1 Component registers */
#define CFG_PORT_V1(r) ((r ## _V1))
#define	COMP_CFG_V1		0
#define	COMP_TRUST_CFG_V1	0x14

/* Resource group info for manager, and non-ported generic device-components */
#define EE_MGR_RSC_GRP	(1 << 10)
#define EE_NGD_2	(2 << 6)
#define EE_NGD_1	0

struct slim_ctrl_buf {
	void		*base;
	spinlock_t	lock;
	int		head;
	int		tail;
	int		sl_sz;
	int		n;
};

struct qcom_slim_ctrl {
	struct slim_controller  ctrl;
	struct slim_framer	framer;
	struct device		*dev;
	void __iomem		*base;
	void __iomem		*slew_reg;

	struct slim_ctrl_buf	rx;
	struct slim_ctrl_buf	tx;

	struct completion	**wr_comp;
	int			irq;
	struct workqueue_struct *rxwq;
	struct work_struct	wd;
	struct clk		*rclk;
	struct clk		*hclk;
};

static void qcom_slim_queue_tx(struct qcom_slim_ctrl *ctrl, void *buf,
			       u8 len, u32 tx_reg)
{
	int count = (len + 3) >> 2;

	__iowrite32_copy(ctrl->base + tx_reg, buf, count);

	/* Ensure Oder of subsequent writes */
	mb();
}

static void *slim_alloc_rxbuf(struct qcom_slim_ctrl *ctrl)
{
	unsigned long flags;
	int idx;

	spin_lock_irqsave(&ctrl->rx.lock, flags);
	if ((ctrl->rx.tail + 1) % ctrl->rx.n == ctrl->rx.head) {
		spin_unlock_irqrestore(&ctrl->rx.lock, flags);
		dev_err(ctrl->dev, "RX QUEUE full!");
		return NULL;
	}
	idx = ctrl->rx.tail;
	ctrl->rx.tail = (ctrl->rx.tail + 1) % ctrl->rx.n;
	spin_unlock_irqrestore(&ctrl->rx.lock, flags);

	return ctrl->rx.base + (idx * ctrl->rx.sl_sz);
}

static void slim_ack_txn(struct qcom_slim_ctrl *ctrl, int err)
{
	struct completion *comp;
	unsigned long flags;
	int idx;

	spin_lock_irqsave(&ctrl->tx.lock, flags);
	idx = ctrl->tx.head;
	ctrl->tx.head = (ctrl->tx.head + 1) % ctrl->tx.n;
	spin_unlock_irqrestore(&ctrl->tx.lock, flags);

	comp = ctrl->wr_comp[idx];
	ctrl->wr_comp[idx] = NULL;

	complete(comp);
}

static irqreturn_t qcom_slim_handle_tx_irq(struct qcom_slim_ctrl *ctrl,
					   u32 stat)
{
	int err = 0;

	if (stat & MGR_INT_TX_MSG_SENT)
		writel_relaxed(MGR_INT_TX_MSG_SENT,
			       ctrl->base + MGR_INT_CLR);

	if (stat & MGR_INT_TX_NACKED_2) {
		u32 mgr_stat = readl_relaxed(ctrl->base + MGR_STATUS);
		u32 mgr_ie_stat = readl_relaxed(ctrl->base + MGR_IE_STAT);
		u32 frm_stat = readl_relaxed(ctrl->base + FRM_STAT);
		u32 frm_cfg = readl_relaxed(ctrl->base + FRM_CFG);
		u32 frm_intr_stat = readl_relaxed(ctrl->base + FRM_INT_STAT);
		u32 frm_ie_stat = readl_relaxed(ctrl->base + FRM_IE_STAT);
		u32 intf_stat = readl_relaxed(ctrl->base + INTF_STAT);
		u32 intf_intr_stat = readl_relaxed(ctrl->base + INTF_INT_STAT);
		u32 intf_ie_stat = readl_relaxed(ctrl->base + INTF_IE_STAT);

		writel_relaxed(MGR_INT_TX_NACKED_2, ctrl->base + MGR_INT_CLR);

		dev_err(ctrl->dev, "TX Nack MGR:int:0x%x, stat:0x%x\n",
			stat, mgr_stat);
		dev_err(ctrl->dev, "TX Nack MGR:ie:0x%x\n", mgr_ie_stat);
		dev_err(ctrl->dev, "TX Nack FRM:int:0x%x, stat:0x%x\n",
			frm_intr_stat, frm_stat);
		dev_err(ctrl->dev, "TX Nack FRM:cfg:0x%x, ie:0x%x\n",
			frm_cfg, frm_ie_stat);
		dev_err(ctrl->dev, "TX Nack INTF:intr:0x%x, stat:0x%x\n",
			intf_intr_stat, intf_stat);
		dev_err(ctrl->dev, "TX Nack INTF:ie:0x%x\n",
			intf_ie_stat);
		err = -ENOTCONN;
	}

	slim_ack_txn(ctrl, err);

	return IRQ_HANDLED;
}

static irqreturn_t qcom_slim_handle_rx_irq(struct qcom_slim_ctrl *ctrl,
					   u32 stat)
{
	u32 *rx_buf, pkt[10];
	bool q_rx = false;
	u8 mc, mt, len;

	pkt[0] = readl_relaxed(ctrl->base + MGR_RX_MSG);
	mt = SLIM_HEADER_GET_MT(pkt[0]);
	len = SLIM_HEADER_GET_RL(pkt[0]);
	mc = SLIM_HEADER_GET_MC(pkt[0]>>8);

	/*
	 * this message cannot be handled by ISR, so
	 * let work-queue handle it
	 */
	if (mt == SLIM_MSG_MT_CORE && mc == SLIM_MSG_MC_REPORT_PRESENT) {
		rx_buf = (u32 *)slim_alloc_rxbuf(ctrl);
		if (!rx_buf) {
			dev_err(ctrl->dev, "dropping RX:0x%x due to RX full\n",
					pkt[0]);
			goto rx_ret_irq;
		}
		rx_buf[0] = pkt[0];

	} else {
		rx_buf = pkt;
	}

	__ioread32_copy(rx_buf + 1, ctrl->base + MGR_RX_MSG + 4,
			DIV_ROUND_UP(len, 4));

	switch (mc) {

	case SLIM_MSG_MC_REPORT_PRESENT:
		q_rx = true;
		break;
	case SLIM_MSG_MC_REPLY_INFORMATION:
	case SLIM_MSG_MC_REPLY_VALUE:
		slim_msg_response(&ctrl->ctrl, (u8 *)(rx_buf + 1),
				  (u8)(*rx_buf >> 24), (len - 4));
		break;
	default:
		dev_err(ctrl->dev, "unsupported MC,%x MT:%x\n",
			mc, mt);
		break;
	}
rx_ret_irq:
	writel(MGR_INT_RX_MSG_RCVD, ctrl->base +
		       MGR_INT_CLR);
	if (q_rx)
		queue_work(ctrl->rxwq, &ctrl->wd);

	return IRQ_HANDLED;
}

static irqreturn_t qcom_slim_interrupt(int irq, void *d)
{
	struct qcom_slim_ctrl *ctrl = d;
	u32 stat = readl_relaxed(ctrl->base + MGR_INT_STAT);
	int ret = IRQ_NONE;

	if (stat & MGR_INT_TX_MSG_SENT || stat & MGR_INT_TX_NACKED_2)
		ret = qcom_slim_handle_tx_irq(ctrl, stat);

	if (stat & MGR_INT_RX_MSG_RCVD)
		ret = qcom_slim_handle_rx_irq(ctrl, stat);

	return ret;
}

static int qcom_clk_pause_wakeup(struct slim_controller *sctrl)
{
	struct qcom_slim_ctrl *ctrl = dev_get_drvdata(sctrl->dev);

	clk_prepare_enable(ctrl->hclk);
	clk_prepare_enable(ctrl->rclk);
	enable_irq(ctrl->irq);

	writel_relaxed(1, ctrl->base + FRM_WAKEUP);
	/* Make sure framer wakeup write goes through before ISR fires */
	mb();
	/*
	 * HW Workaround: Currently, slave is reporting lost-sync messages
	 * after SLIMbus comes out of clock pause.
	 * Transaction with slave fail before slave reports that message
	 * Give some time for that report to come
	 * SLIMbus wakes up in clock gear 10 at 24.576MHz. With each superframe
	 * being 250 usecs, we wait for 5-10 superframes here to ensure
	 * we get the message
	 */
	usleep_range(1250, 2500);
	return 0;
}

static void *slim_alloc_txbuf(struct qcom_slim_ctrl *ctrl,
			      struct slim_msg_txn *txn,
			      struct completion *done)
{
	unsigned long flags;
	int idx;

	spin_lock_irqsave(&ctrl->tx.lock, flags);
	if (((ctrl->tx.head + 1) % ctrl->tx.n) == ctrl->tx.tail) {
		spin_unlock_irqrestore(&ctrl->tx.lock, flags);
		dev_err(ctrl->dev, "controller TX buf unavailable");
		return NULL;
	}
	idx = ctrl->tx.tail;
	ctrl->wr_comp[idx] = done;
	ctrl->tx.tail = (ctrl->tx.tail + 1) % ctrl->tx.n;

	spin_unlock_irqrestore(&ctrl->tx.lock, flags);

	return ctrl->tx.base + (idx * ctrl->tx.sl_sz);
}


static int qcom_xfer_msg(struct slim_controller *sctrl,
			 struct slim_msg_txn *txn)
{
	struct qcom_slim_ctrl *ctrl = dev_get_drvdata(sctrl->dev);
	DECLARE_COMPLETION_ONSTACK(done);
	void *pbuf = slim_alloc_txbuf(ctrl, txn, &done);
	unsigned long ms = txn->rl + HZ;
	u8 *puc;
	int ret = 0, timeout, retries = QCOM_BUF_ALLOC_RETRIES;
	u8 la = txn->la;
	u32 *head;
	/* HW expects length field to be excluded */
	txn->rl--;

	/* spin till buffer is made available */
	if (!pbuf) {
		while (retries--) {
			usleep_range(10000, 15000);
			pbuf = slim_alloc_txbuf(ctrl, txn, &done);
			if (pbuf)
				break;
		}
	}

	if (retries < 0 && !pbuf)
		return -ENOMEM;

	puc = (u8 *)pbuf;
	head = (u32 *)pbuf;

	if (txn->dt == SLIM_MSG_DEST_LOGICALADDR) {
		*head = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt,
						txn->mc, 0, la);
		puc += 3;
	} else {
		*head = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt,
						txn->mc, 1, la);
		puc += 2;
	}

	if (slim_tid_txn(txn->mt, txn->mc))
		*(puc++) = txn->tid;

	if (slim_ec_txn(txn->mt, txn->mc)) {
		*(puc++) = (txn->ec & 0xFF);
		*(puc++) = (txn->ec >> 8) & 0xFF;
	}

	if (txn->msg && txn->msg->wbuf)
		memcpy(puc, txn->msg->wbuf, txn->msg->num_bytes);

	qcom_slim_queue_tx(ctrl, head, txn->rl, MGR_TX_MSG);
	timeout = wait_for_completion_timeout(&done, msecs_to_jiffies(ms));

	if (!timeout) {
		dev_err(ctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc,
					txn->mt);
		ret = -ETIMEDOUT;
	}

	return ret;

}

static int qcom_set_laddr(struct slim_controller *sctrl,
				struct slim_eaddr *ead, u8 laddr)
{
	struct qcom_slim_ctrl *ctrl = dev_get_drvdata(sctrl->dev);
	struct {
		__be16 manf_id;
		__be16 prod_code;
		u8 dev_index;
		u8 instance;
		u8 laddr;
	} __packed p;
	struct slim_val_inf msg = {0};
	DEFINE_SLIM_EDEST_TXN(txn, SLIM_MSG_MC_ASSIGN_LOGICAL_ADDRESS,
			      10, laddr, &msg);
	int ret;

	p.manf_id = cpu_to_be16(ead->manf_id);
	p.prod_code = cpu_to_be16(ead->prod_code);
	p.dev_index = ead->dev_index;
	p.instance = ead->instance;
	p.laddr = laddr;

	msg.wbuf = (void *)&p;
	msg.num_bytes = 7;
	ret = slim_do_transfer(&ctrl->ctrl, &txn);

	if (ret)
		dev_err(ctrl->dev, "set LA:0x%x failed:ret:%d\n",
				  laddr, ret);
	return ret;
}

static int slim_get_current_rxbuf(struct qcom_slim_ctrl *ctrl, void *buf)
{
	unsigned long flags;

	spin_lock_irqsave(&ctrl->rx.lock, flags);
	if (ctrl->rx.tail == ctrl->rx.head) {
		spin_unlock_irqrestore(&ctrl->rx.lock, flags);
		return -ENODATA;
	}
	memcpy(buf, ctrl->rx.base + (ctrl->rx.head * ctrl->rx.sl_sz),
				ctrl->rx.sl_sz);

	ctrl->rx.head = (ctrl->rx.head + 1) % ctrl->rx.n;
	spin_unlock_irqrestore(&ctrl->rx.lock, flags);

	return 0;
}

static void qcom_slim_rxwq(struct work_struct *work)
{
	u8 buf[SLIM_MSGQ_BUF_LEN];
	u8 mc, mt;
	int ret;
	struct qcom_slim_ctrl *ctrl = container_of(work, struct qcom_slim_ctrl,
						 wd);

	while ((slim_get_current_rxbuf(ctrl, buf)) != -ENODATA) {
		mt = SLIM_HEADER_GET_MT(buf[0]);
		mc = SLIM_HEADER_GET_MC(buf[1]);
		if (mt == SLIM_MSG_MT_CORE &&
			mc == SLIM_MSG_MC_REPORT_PRESENT) {
			struct slim_eaddr ea;
			u8 laddr;

			ea.manf_id = be16_to_cpup((__be16 *)&buf[2]);
			ea.prod_code = be16_to_cpup((__be16 *)&buf[4]);
			ea.dev_index = buf[6];
			ea.instance = buf[7];

			ret = slim_device_report_present(&ctrl->ctrl, &ea,
							 &laddr);
			if (ret < 0)
				dev_err(ctrl->dev, "assign laddr failed:%d\n",
					ret);
		} else {
			dev_err(ctrl->dev, "unexpected message:mc:%x, mt:%x\n",
				mc, mt);
		}
	}
}

static void qcom_slim_prg_slew(struct platform_device *pdev,
				struct qcom_slim_ctrl *ctrl)
{
	if (!ctrl->slew_reg) {
		/* SLEW RATE register for this SLIMbus */
		ctrl->slew_reg = devm_platform_ioremap_resource_byname(pdev, "slew");
		if (IS_ERR(ctrl->slew_reg))
			return;
	}

	writel_relaxed(1, ctrl->slew_reg);
	/* Make sure SLIMbus-slew rate enabling goes through */
	wmb();
}

static int qcom_slim_probe(struct platform_device *pdev)
{
	struct qcom_slim_ctrl *ctrl;
	struct slim_controller *sctrl;
	struct resource *slim_mem;
	int ret, ver;

	ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL);
	if (!ctrl)
		return -ENOMEM;

	ctrl->hclk = devm_clk_get(&pdev->dev, "iface");
	if (IS_ERR(ctrl->hclk))
		return PTR_ERR(ctrl->hclk);

	ctrl->rclk = devm_clk_get(&pdev->dev, "core");
	if (IS_ERR(ctrl->rclk))
		return PTR_ERR(ctrl->rclk);

	ret = clk_set_rate(ctrl->rclk, SLIM_ROOT_FREQ);
	if (ret) {
		dev_err(&pdev->dev, "ref-clock set-rate failed:%d\n", ret);
		return ret;
	}

	ctrl->irq = platform_get_irq(pdev, 0);
	if (!ctrl->irq) {
		dev_err(&pdev->dev, "no slimbus IRQ\n");
		return -ENODEV;
	}

	sctrl = &ctrl->ctrl;
	sctrl->dev = &pdev->dev;
	ctrl->dev = &pdev->dev;
	platform_set_drvdata(pdev, ctrl);
	dev_set_drvdata(ctrl->dev, ctrl);

	slim_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl");
	ctrl->base = devm_ioremap_resource(ctrl->dev, slim_mem);
	if (IS_ERR(ctrl->base))
		return PTR_ERR(ctrl->base);

	sctrl->set_laddr = qcom_set_laddr;
	sctrl->xfer_msg = qcom_xfer_msg;
	sctrl->wakeup =  qcom_clk_pause_wakeup;
	ctrl->tx.n = QCOM_TX_MSGS;
	ctrl->tx.sl_sz = SLIM_MSGQ_BUF_LEN;
	ctrl->rx.n = QCOM_RX_MSGS;
	ctrl->rx.sl_sz = SLIM_MSGQ_BUF_LEN;
	ctrl->wr_comp = kcalloc(QCOM_TX_MSGS, sizeof(struct completion *),
				GFP_KERNEL);
	if (!ctrl->wr_comp)
		return -ENOMEM;

	spin_lock_init(&ctrl->rx.lock);
	spin_lock_init(&ctrl->tx.lock);
	INIT_WORK(&ctrl->wd, qcom_slim_rxwq);
	ctrl->rxwq = create_singlethread_workqueue("qcom_slim_rx");
	if (!ctrl->rxwq) {
		dev_err(ctrl->dev, "Failed to start Rx WQ\n");
		return -ENOMEM;
	}

	ctrl->framer.rootfreq = SLIM_ROOT_FREQ / 8;
	ctrl->framer.superfreq =
		ctrl->framer.rootfreq / SLIM_CL_PER_SUPERFRAME_DIV8;
	sctrl->a_framer = &ctrl->framer;
	sctrl->clkgear = SLIM_MAX_CLK_GEAR;

	qcom_slim_prg_slew(pdev, ctrl);

	ret = devm_request_irq(&pdev->dev, ctrl->irq, qcom_slim_interrupt,
				IRQF_TRIGGER_HIGH, "qcom_slim_irq", ctrl);
	if (ret) {
		dev_err(&pdev->dev, "request IRQ failed\n");
		goto err_request_irq_failed;
	}

	ret = clk_prepare_enable(ctrl->hclk);
	if (ret)
		goto err_hclk_enable_failed;

	ret = clk_prepare_enable(ctrl->rclk);
	if (ret)
		goto err_rclk_enable_failed;

	ctrl->tx.base = devm_kcalloc(&pdev->dev, ctrl->tx.n, ctrl->tx.sl_sz,
				     GFP_KERNEL);
	if (!ctrl->tx.base) {
		ret = -ENOMEM;
		goto err;
	}

	ctrl->rx.base = devm_kcalloc(&pdev->dev,ctrl->rx.n, ctrl->rx.sl_sz,
				     GFP_KERNEL);
	if (!ctrl->rx.base) {
		ret = -ENOMEM;
		goto err;
	}

	/* Register with framework before enabling frame, clock */
	ret = slim_register_controller(&ctrl->ctrl);
	if (ret) {
		dev_err(ctrl->dev, "error adding controller\n");
		goto err;
	}

	ver = readl_relaxed(ctrl->base);
	/* Version info in 16 MSbits */
	ver >>= 16;
	/* Component register initialization */
	writel(1, ctrl->base + CFG_PORT(COMP_CFG, ver));
	writel((EE_MGR_RSC_GRP | EE_NGD_2 | EE_NGD_1),
				ctrl->base + CFG_PORT(COMP_TRUST_CFG, ver));

	writel((MGR_INT_TX_NACKED_2 |
			MGR_INT_MSG_BUF_CONTE | MGR_INT_RX_MSG_RCVD |
			MGR_INT_TX_MSG_SENT), ctrl->base + MGR_INT_EN);
	writel(1, ctrl->base + MGR_CFG);
	/* Framer register initialization */
	writel((1 << INTR_WAKE) | (0xA << REF_CLK_GEAR) |
		(0xA << CLK_GEAR) | (1 << ROOT_FREQ) | (1 << FRM_ACTIVE) | 1,
		ctrl->base + FRM_CFG);
	writel(MGR_CFG_ENABLE, ctrl->base + MGR_CFG);
	writel(1, ctrl->base + INTF_CFG);
	writel(1, ctrl->base + CFG_PORT(COMP_CFG, ver));

	pm_runtime_use_autosuspend(&pdev->dev);
	pm_runtime_set_autosuspend_delay(&pdev->dev, QCOM_SLIM_AUTOSUSPEND);
	pm_runtime_set_active(&pdev->dev);
	pm_runtime_mark_last_busy(&pdev->dev);
	pm_runtime_enable(&pdev->dev);

	dev_dbg(ctrl->dev, "QCOM SB controller is up:ver:0x%x!\n", ver);
	return 0;

err:
	clk_disable_unprepare(ctrl->rclk);
err_rclk_enable_failed:
	clk_disable_unprepare(ctrl->hclk);
err_hclk_enable_failed:
err_request_irq_failed:
	destroy_workqueue(ctrl->rxwq);
	return ret;
}

static int qcom_slim_remove(struct platform_device *pdev)
{
	struct qcom_slim_ctrl *ctrl = platform_get_drvdata(pdev);

	pm_runtime_disable(&pdev->dev);
	slim_unregister_controller(&ctrl->ctrl);
	clk_disable_unprepare(ctrl->rclk);
	clk_disable_unprepare(ctrl->hclk);
	destroy_workqueue(ctrl->rxwq);
	return 0;
}

/*
 * If PM_RUNTIME is not defined, these 2 functions become helper
 * functions to be called from system suspend/resume.
 */
#ifdef CONFIG_PM
static int qcom_slim_runtime_suspend(struct device *device)
{
	struct qcom_slim_ctrl *ctrl = dev_get_drvdata(device);
	int ret;

	dev_dbg(device, "pm_runtime: suspending...\n");
	ret = slim_ctrl_clk_pause(&ctrl->ctrl, false, SLIM_CLK_UNSPECIFIED);
	if (ret) {
		dev_err(device, "clk pause not entered:%d", ret);
	} else {
		disable_irq(ctrl->irq);
		clk_disable_unprepare(ctrl->hclk);
		clk_disable_unprepare(ctrl->rclk);
	}
	return ret;
}

static int qcom_slim_runtime_resume(struct device *device)
{
	struct qcom_slim_ctrl *ctrl = dev_get_drvdata(device);
	int ret = 0;

	dev_dbg(device, "pm_runtime: resuming...\n");
	ret = slim_ctrl_clk_pause(&ctrl->ctrl, true, 0);
	if (ret)
		dev_err(device, "clk pause not exited:%d", ret);
	return ret;
}
#endif

#ifdef CONFIG_PM_SLEEP
static int qcom_slim_suspend(struct device *dev)
{
	int ret = 0;

	if (!pm_runtime_enabled(dev) ||
		(!pm_runtime_suspended(dev))) {
		dev_dbg(dev, "system suspend");
		ret = qcom_slim_runtime_suspend(dev);
	}

	return ret;
}

static int qcom_slim_resume(struct device *dev)
{
	if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) {
		int ret;

		dev_dbg(dev, "system resume");
		ret = qcom_slim_runtime_resume(dev);
		if (!ret) {
			pm_runtime_mark_last_busy(dev);
			pm_request_autosuspend(dev);
		}
		return ret;

	}
	return 0;
}
#endif /* CONFIG_PM_SLEEP */

static const struct dev_pm_ops qcom_slim_dev_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(qcom_slim_suspend, qcom_slim_resume)
	SET_RUNTIME_PM_OPS(
			   qcom_slim_runtime_suspend,
			   qcom_slim_runtime_resume,
			   NULL
	)
};

static const struct of_device_id qcom_slim_dt_match[] = {
	{ .compatible = "qcom,slim", },
	{ .compatible = "qcom,apq8064-slim", },
	{}
};

static struct platform_driver qcom_slim_driver = {
	.probe = qcom_slim_probe,
	.remove = qcom_slim_remove,
	.driver	= {
		.name = "qcom_slim_ctrl",
		.of_match_table = qcom_slim_dt_match,
		.pm = &qcom_slim_dev_pm_ops,
	},
};
module_platform_driver(qcom_slim_driver);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Qualcomm SLIMbus Controller");
Commit	Line	Data
ad7fcbc3 SD	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (c) 2011-2017, The Linux Foundation
	4	*/
	5
	6	#include <linux/irq.h>
	7	#include <linux/kernel.h>
	8	#include <linux/init.h>
	9	#include <linux/slab.h>
	10	#include <linux/io.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/platform_device.h>
	13	#include <linux/delay.h>
	14	#include <linux/clk.h>
	15	#include <linux/of.h>
c088c335	16	#include <linux/pm_runtime.h>
ad7fcbc3 SD	17	#include "slimbus.h"
	18
	19	/* Manager registers */
	20	#define MGR_CFG 0x200
	21	#define MGR_STATUS 0x204
	22	#define MGR_INT_EN 0x210
	23	#define MGR_INT_STAT 0x214
	24	#define MGR_INT_CLR 0x218
	25	#define MGR_TX_MSG 0x230
	26	#define MGR_RX_MSG 0x270
	27	#define MGR_IE_STAT 0x2F0
	28	#define MGR_VE_STAT 0x300
	29	#define MGR_CFG_ENABLE 1
	30
	31	/* Framer registers */
	32	#define FRM_CFG 0x400
	33	#define FRM_STAT 0x404
	34	#define FRM_INT_EN 0x410
	35	#define FRM_INT_STAT 0x414
	36	#define FRM_INT_CLR 0x418
	37	#define FRM_WAKEUP 0x41C
	38	#define FRM_CLKCTL_DONE 0x420
	39	#define FRM_IE_STAT 0x430
	40	#define FRM_VE_STAT 0x440
	41
	42	/* Interface registers */
	43	#define INTF_CFG 0x600
	44	#define INTF_STAT 0x604
	45	#define INTF_INT_EN 0x610
	46	#define INTF_INT_STAT 0x614
	47	#define INTF_INT_CLR 0x618
	48	#define INTF_IE_STAT 0x630
	49	#define INTF_VE_STAT 0x640
	50
	51	/* Interrupt status bits */
	52	#define MGR_INT_TX_NACKED_2 BIT(25)
	53	#define MGR_INT_MSG_BUF_CONTE BIT(26)
	54	#define MGR_INT_RX_MSG_RCVD BIT(30)
	55	#define MGR_INT_TX_MSG_SENT BIT(31)
	56
	57	/* Framer config register settings */
	58	#define FRM_ACTIVE 1
	59	#define CLK_GEAR 7
	60	#define ROOT_FREQ 11
	61	#define REF_CLK_GEAR 15
	62	#define INTR_WAKE 19
	63
	64	#define SLIM_MSG_ASM_FIRST_WORD(l, mt, mc, dt, ad) \
	65	((l) \| ((mt) << 5) \| ((mc) << 8) \| ((dt) << 15) \| ((ad) << 16))
	66
	67	#define SLIM_ROOT_FREQ 24576000
c088c335	68	#define QCOM_SLIM_AUTOSUSPEND 1000
ad7fcbc3 SD	69
	70	/* MAX message size over control channel */
	71	#define SLIM_MSGQ_BUF_LEN 40
	72	#define QCOM_TX_MSGS 2
	73	#define QCOM_RX_MSGS 8
	74	#define QCOM_BUF_ALLOC_RETRIES 10
	75
	76	#define CFG_PORT(r, v) ((v) ? CFG_PORT_V2(r) : CFG_PORT_V1(r))
	77
	78	/* V2 Component registers */
	79	#define CFG_PORT_V2(r) ((r ## _V2))
	80	#define COMP_CFG_V2 4
	81	#define COMP_TRUST_CFG_V2 0x3000
	82
	83	/* V1 Component registers */
	84	#define CFG_PORT_V1(r) ((r ## _V1))
	85	#define COMP_CFG_V1 0
	86	#define COMP_TRUST_CFG_V1 0x14
	87
	88	/* Resource group info for manager, and non-ported generic device-components */
	89	#define EE_MGR_RSC_GRP (1 << 10)
	90	#define EE_NGD_2 (2 << 6)
	91	#define EE_NGD_1 0
	92
	93	struct slim_ctrl_buf {
	94	void *base;
ad7fcbc3 SD	95	spinlock_t lock;
	96	int head;
	97	int tail;
	98	int sl_sz;
	99	int n;
	100	};
	101
	102	struct qcom_slim_ctrl {
	103	struct slim_controller ctrl;
	104	struct slim_framer framer;
	105	struct device *dev;
	106	void __iomem *base;
	107	void __iomem *slew_reg;
	108
	109	struct slim_ctrl_buf rx;
	110	struct slim_ctrl_buf tx;
	111
	112	struct completion **wr_comp;
	113	int irq;
	114	struct workqueue_struct *rxwq;
	115	struct work_struct wd;
	116	struct clk *rclk;
	117	struct clk *hclk;
	118	};
	119
	120	static void qcom_slim_queue_tx(struct qcom_slim_ctrl ctrl, void buf,
	121	u8 len, u32 tx_reg)
	122	{
	123	int count = (len + 3) >> 2;
	124
	125	__iowrite32_copy(ctrl->base + tx_reg, buf, count);
	126
	127	/* Ensure Oder of subsequent writes */
	128	mb();
	129	}
	130
	131	static void slim_alloc_rxbuf(struct qcom_slim_ctrl ctrl)
	132	{
	133	unsigned long flags;
	134	int idx;
	135
	136	spin_lock_irqsave(&ctrl->rx.lock, flags);
	137	if ((ctrl->rx.tail + 1) % ctrl->rx.n == ctrl->rx.head) {
	138	spin_unlock_irqrestore(&ctrl->rx.lock, flags);
	139	dev_err(ctrl->dev, "RX QUEUE full!");
	140	return NULL;
	141	}
	142	idx = ctrl->rx.tail;
	143	ctrl->rx.tail = (ctrl->rx.tail + 1) % ctrl->rx.n;
	144	spin_unlock_irqrestore(&ctrl->rx.lock, flags);
	145
	146	return ctrl->rx.base + (idx * ctrl->rx.sl_sz);
	147	}
	148
c88c8d7a	149	static void slim_ack_txn(struct qcom_slim_ctrl *ctrl, int err)
ad7fcbc3 SD	150	{
	151	struct completion *comp;
	152	unsigned long flags;
	153	int idx;
	154
	155	spin_lock_irqsave(&ctrl->tx.lock, flags);
	156	idx = ctrl->tx.head;
	157	ctrl->tx.head = (ctrl->tx.head + 1) % ctrl->tx.n;
	158	spin_unlock_irqrestore(&ctrl->tx.lock, flags);
	159
	160	comp = ctrl->wr_comp[idx];
	161	ctrl->wr_comp[idx] = NULL;
	162
	163	complete(comp);
	164	}
	165
	166	static irqreturn_t qcom_slim_handle_tx_irq(struct qcom_slim_ctrl *ctrl,
	167	u32 stat)
	168	{
	169	int err = 0;
	170
	171	if (stat & MGR_INT_TX_MSG_SENT)
	172	writel_relaxed(MGR_INT_TX_MSG_SENT,
	173	ctrl->base + MGR_INT_CLR);
	174
	175	if (stat & MGR_INT_TX_NACKED_2) {
	176	u32 mgr_stat = readl_relaxed(ctrl->base + MGR_STATUS);
	177	u32 mgr_ie_stat = readl_relaxed(ctrl->base + MGR_IE_STAT);
	178	u32 frm_stat = readl_relaxed(ctrl->base + FRM_STAT);
	179	u32 frm_cfg = readl_relaxed(ctrl->base + FRM_CFG);
	180	u32 frm_intr_stat = readl_relaxed(ctrl->base + FRM_INT_STAT);
	181	u32 frm_ie_stat = readl_relaxed(ctrl->base + FRM_IE_STAT);
	182	u32 intf_stat = readl_relaxed(ctrl->base + INTF_STAT);
	183	u32 intf_intr_stat = readl_relaxed(ctrl->base + INTF_INT_STAT);
	184	u32 intf_ie_stat = readl_relaxed(ctrl->base + INTF_IE_STAT);
	185
	186	writel_relaxed(MGR_INT_TX_NACKED_2, ctrl->base + MGR_INT_CLR);
	187
	188	dev_err(ctrl->dev, "TX Nack MGR:int:0x%x, stat:0x%x\n",
	189	stat, mgr_stat);
	190	dev_err(ctrl->dev, "TX Nack MGR:ie:0x%x\n", mgr_ie_stat);
	191	dev_err(ctrl->dev, "TX Nack FRM:int:0x%x, stat:0x%x\n",
	192	frm_intr_stat, frm_stat);
	193	dev_err(ctrl->dev, "TX Nack FRM:cfg:0x%x, ie:0x%x\n",
	194	frm_cfg, frm_ie_stat);
	195	dev_err(ctrl->dev, "TX Nack INTF:intr:0x%x, stat:0x%x\n",
	196	intf_intr_stat, intf_stat);
	197	dev_err(ctrl->dev, "TX Nack INTF:ie:0x%x\n",
	198	intf_ie_stat);
	199	err = -ENOTCONN;
	200	}
	201
	202	slim_ack_txn(ctrl, err);
	203
	204	return IRQ_HANDLED;
	205	}
	206
	207	static irqreturn_t qcom_slim_handle_rx_irq(struct qcom_slim_ctrl *ctrl,
	208	u32 stat)
	209	{
	210	u32 *rx_buf, pkt[10];
	211	bool q_rx = false;
	212	u8 mc, mt, len;
	213
214	pkt[0] = readl_relaxed(ctrl->base + MGR_RX_MSG);
215	mt = SLIM_HEADER_GET_MT(pkt[0]);
216	len = SLIM_HEADER_GET_RL(pkt[0]);
217	mc = SLIM_HEADER_GET_MC(pkt[0]>>8);
218
219	/*
220	* this message cannot be handled by ISR, so
221	* let work-queue handle it
222	*/
223	if (mt == SLIM_MSG_MT_CORE && mc == SLIM_MSG_MC_REPORT_PRESENT) {
224	rx_buf = (u32 *)slim_alloc_rxbuf(ctrl);
225	if (!rx_buf) {
226	dev_err(ctrl->dev, "dropping RX:0x%x due to RX full\n",
227	pkt[0]);
228	goto rx_ret_irq;
229	}
230	rx_buf[0] = pkt[0];
231
232	} else {
233	rx_buf = pkt;
234	}
235
236	__ioread32_copy(rx_buf + 1, ctrl->base + MGR_RX_MSG + 4,
237	DIV_ROUND_UP(len, 4));
238
239	switch (mc) {
240
241	case SLIM_MSG_MC_REPORT_PRESENT:
242	q_rx = true;
243	break;
244	case SLIM_MSG_MC_REPLY_INFORMATION:
245	case SLIM_MSG_MC_REPLY_VALUE:
246	slim_msg_response(&ctrl->ctrl, (u8 *)(rx_buf + 1),
247	(u8)(*rx_buf >> 24), (len - 4));
248	break;
249	default:
250	dev_err(ctrl->dev, "unsupported MC,%x MT:%x\n",
251	mc, mt);
252	break;
253	}
254	rx_ret_irq:
255	writel(MGR_INT_RX_MSG_RCVD, ctrl->base +
256	MGR_INT_CLR);
257	if (q_rx)
258	queue_work(ctrl->rxwq, &ctrl->wd);
259
260	return IRQ_HANDLED;
261	}
262
263	static irqreturn_t qcom_slim_interrupt(int irq, void *d)
264	{
265	struct qcom_slim_ctrl *ctrl = d;
266	u32 stat = readl_relaxed(ctrl->base + MGR_INT_STAT);
267	int ret = IRQ_NONE;
268
269	if (stat & MGR_INT_TX_MSG_SENT \|\| stat & MGR_INT_TX_NACKED_2)
270	ret = qcom_slim_handle_tx_irq(ctrl, stat);
271
272	if (stat & MGR_INT_RX_MSG_RCVD)
273	ret = qcom_slim_handle_rx_irq(ctrl, stat);
274
275	return ret;
276	}
277
c088c335 SD	278	static int qcom_clk_pause_wakeup(struct slim_controller *sctrl)
	279	{
	280	struct qcom_slim_ctrl *ctrl = dev_get_drvdata(sctrl->dev);
	281
	282	clk_prepare_enable(ctrl->hclk);
	283	clk_prepare_enable(ctrl->rclk);
	284	enable_irq(ctrl->irq);
	285
	286	writel_relaxed(1, ctrl->base + FRM_WAKEUP);
	287	/* Make sure framer wakeup write goes through before ISR fires */
	288	mb();
	289	/*
	290	* HW Workaround: Currently, slave is reporting lost-sync messages
	291	* after SLIMbus comes out of clock pause.
	292	* Transaction with slave fail before slave reports that message
	293	* Give some time for that report to come
	294	* SLIMbus wakes up in clock gear 10 at 24.576MHz. With each superframe
	295	* being 250 usecs, we wait for 5-10 superframes here to ensure
	296	* we get the message
	297	*/
	298	usleep_range(1250, 2500);
	299	return 0;
	300	}
	301
c88c8d7a CIK	302	static void slim_alloc_txbuf(struct qcom_slim_ctrl ctrl,
	303	struct slim_msg_txn *txn,
	304	struct completion *done)
ad7fcbc3 SD	305	{
	306	unsigned long flags;
	307	int idx;
	308
	309	spin_lock_irqsave(&ctrl->tx.lock, flags);
	310	if (((ctrl->tx.head + 1) % ctrl->tx.n) == ctrl->tx.tail) {
	311	spin_unlock_irqrestore(&ctrl->tx.lock, flags);
	312	dev_err(ctrl->dev, "controller TX buf unavailable");
	313	return NULL;
	314	}
	315	idx = ctrl->tx.tail;
	316	ctrl->wr_comp[idx] = done;
	317	ctrl->tx.tail = (ctrl->tx.tail + 1) % ctrl->tx.n;
	318
	319	spin_unlock_irqrestore(&ctrl->tx.lock, flags);
	320
	321	return ctrl->tx.base + (idx * ctrl->tx.sl_sz);
	322	}
	323
	324
	325	static int qcom_xfer_msg(struct slim_controller *sctrl,
	326	struct slim_msg_txn *txn)
	327	{
	328	struct qcom_slim_ctrl *ctrl = dev_get_drvdata(sctrl->dev);
	329	DECLARE_COMPLETION_ONSTACK(done);
	330	void *pbuf = slim_alloc_txbuf(ctrl, txn, &done);
	331	unsigned long ms = txn->rl + HZ;
	332	u8 *puc;
	333	int ret = 0, timeout, retries = QCOM_BUF_ALLOC_RETRIES;
	334	u8 la = txn->la;
	335	u32 *head;
	336	/* HW expects length field to be excluded */
	337	txn->rl--;
	338
	339	/* spin till buffer is made available */
	340	if (!pbuf) {
	341	while (retries--) {
	342	usleep_range(10000, 15000);
	343	pbuf = slim_alloc_txbuf(ctrl, txn, &done);
	344	if (pbuf)
	345	break;
	346	}
	347	}
	348
551b9ee4	349	if (retries < 0 && !pbuf)
ad7fcbc3 SD	350	return -ENOMEM;
	351
	352	puc = (u8 *)pbuf;
	353	head = (u32 *)pbuf;
	354
	355	if (txn->dt == SLIM_MSG_DEST_LOGICALADDR) {
	356	*head = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt,
	357	txn->mc, 0, la);
	358	puc += 3;
	359	} else {
	360	*head = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt,
	361	txn->mc, 1, la);
	362	puc += 2;
	363	}
	364
	365	if (slim_tid_txn(txn->mt, txn->mc))
	366	*(puc++) = txn->tid;
	367
	368	if (slim_ec_txn(txn->mt, txn->mc)) {
	369	*(puc++) = (txn->ec & 0xFF);
	370	*(puc++) = (txn->ec >> 8) & 0xFF;
	371	}
	372
	373	if (txn->msg && txn->msg->wbuf)
	374	memcpy(puc, txn->msg->wbuf, txn->msg->num_bytes);
	375
	376	qcom_slim_queue_tx(ctrl, head, txn->rl, MGR_TX_MSG);
	377	timeout = wait_for_completion_timeout(&done, msecs_to_jiffies(ms));
	378
	379	if (!timeout) {
	380	dev_err(ctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc,
	381	txn->mt);
	382	ret = -ETIMEDOUT;
	383	}
	384
	385	return ret;
	386
	387	}
	388
	389	static int qcom_set_laddr(struct slim_controller *sctrl,
	390	struct slim_eaddr *ead, u8 laddr)
	391	{
	392	struct qcom_slim_ctrl *ctrl = dev_get_drvdata(sctrl->dev);
	393	struct {
	394	__be16 manf_id;
	395	__be16 prod_code;
	396	u8 dev_index;
	397	u8 instance;
	398	u8 laddr;
	399	} __packed p;
	400	struct slim_val_inf msg = {0};
	401	DEFINE_SLIM_EDEST_TXN(txn, SLIM_MSG_MC_ASSIGN_LOGICAL_ADDRESS,
	402	10, laddr, &msg);
	403	int ret;
	404
	405	p.manf_id = cpu_to_be16(ead->manf_id);
	406	p.prod_code = cpu_to_be16(ead->prod_code);
	407	p.dev_index = ead->dev_index;
	408	p.instance = ead->instance;
	409	p.laddr = laddr;
	410
	411	msg.wbuf = (void *)&p;
	412	msg.num_bytes = 7;
	413	ret = slim_do_transfer(&ctrl->ctrl, &txn);
414
415	if (ret)
416	dev_err(ctrl->dev, "set LA:0x%x failed:ret:%d\n",
417	laddr, ret);
418	return ret;
419	}
420
421	static int slim_get_current_rxbuf(struct qcom_slim_ctrl ctrl, void buf)
422	{
423	unsigned long flags;
424
425	spin_lock_irqsave(&ctrl->rx.lock, flags);
426	if (ctrl->rx.tail == ctrl->rx.head) {
427	spin_unlock_irqrestore(&ctrl->rx.lock, flags);
428	return -ENODATA;
429	}
430	memcpy(buf, ctrl->rx.base + (ctrl->rx.head * ctrl->rx.sl_sz),
431	ctrl->rx.sl_sz);
432
433	ctrl->rx.head = (ctrl->rx.head + 1) % ctrl->rx.n;
434	spin_unlock_irqrestore(&ctrl->rx.lock, flags);
435
436	return 0;
437	}
438
439	static void qcom_slim_rxwq(struct work_struct *work)
440	{
441	u8 buf[SLIM_MSGQ_BUF_LEN];
49cb93cb	442	u8 mc, mt;
ad7fcbc3 SD	443	int ret;
	444	struct qcom_slim_ctrl *ctrl = container_of(work, struct qcom_slim_ctrl,
	445	wd);
	446
	447	while ((slim_get_current_rxbuf(ctrl, buf)) != -ENODATA) {
ad7fcbc3 SD	448	mt = SLIM_HEADER_GET_MT(buf[0]);
	449	mc = SLIM_HEADER_GET_MC(buf[1]);
	450	if (mt == SLIM_MSG_MT_CORE &&
	451	mc == SLIM_MSG_MC_REPORT_PRESENT) {
	452	struct slim_eaddr ea;
	453	u8 laddr;
	454
	455	ea.manf_id = be16_to_cpup((__be16 *)&buf[2]);
	456	ea.prod_code = be16_to_cpup((__be16 *)&buf[4]);
	457	ea.dev_index = buf[6];
	458	ea.instance = buf[7];
	459
	460	ret = slim_device_report_present(&ctrl->ctrl, &ea,
	461	&laddr);
	462	if (ret < 0)
	463	dev_err(ctrl->dev, "assign laddr failed:%d\n",
	464	ret);
	465	} else {
	466	dev_err(ctrl->dev, "unexpected message:mc:%x, mt:%x\n",
	467	mc, mt);
	468	}
	469	}
	470	}
	471
	472	static void qcom_slim_prg_slew(struct platform_device *pdev,
	473	struct qcom_slim_ctrl *ctrl)
	474	{
ad7fcbc3 SD	475	if (!ctrl->slew_reg) {
ad7fcbc3 SD	476	/* SLEW RATE register for this SLIMbus */
428bb001 ZC	477	ctrl->slew_reg = devm_platform_ioremap_resource_byname(pdev, "slew");
428bb001 ZC	478	if (IS_ERR(ctrl->slew_reg))
ad7fcbc3 SD	479	return;
	480	}
	481
	482	writel_relaxed(1, ctrl->slew_reg);
	483	/* Make sure SLIMbus-slew rate enabling goes through */
	484	wmb();
	485	}
	486
	487	static int qcom_slim_probe(struct platform_device *pdev)
	488	{
	489	struct qcom_slim_ctrl *ctrl;
	490	struct slim_controller *sctrl;
	491	struct resource *slim_mem;
	492	int ret, ver;
	493
	494	ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL);
	495	if (!ctrl)
	496	return -ENOMEM;
	497
	498	ctrl->hclk = devm_clk_get(&pdev->dev, "iface");
	499	if (IS_ERR(ctrl->hclk))
	500	return PTR_ERR(ctrl->hclk);
	501
	502	ctrl->rclk = devm_clk_get(&pdev->dev, "core");
	503	if (IS_ERR(ctrl->rclk))
	504	return PTR_ERR(ctrl->rclk);
	505
	506	ret = clk_set_rate(ctrl->rclk, SLIM_ROOT_FREQ);
	507	if (ret) {
	508	dev_err(&pdev->dev, "ref-clock set-rate failed:%d\n", ret);
	509	return ret;
	510	}
	511
	512	ctrl->irq = platform_get_irq(pdev, 0);
	513	if (!ctrl->irq) {
	514	dev_err(&pdev->dev, "no slimbus IRQ\n");
	515	return -ENODEV;
	516	}
	517
	518	sctrl = &ctrl->ctrl;
	519	sctrl->dev = &pdev->dev;
	520	ctrl->dev = &pdev->dev;
	521	platform_set_drvdata(pdev, ctrl);
	522	dev_set_drvdata(ctrl->dev, ctrl);
	523
	524	slim_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl");
	525	ctrl->base = devm_ioremap_resource(ctrl->dev, slim_mem);
e9cd2519	526	if (IS_ERR(ctrl->base))
ff595a33	527	return PTR_ERR(ctrl->base);
ad7fcbc3 SD	528
	529	sctrl->set_laddr = qcom_set_laddr;
	530	sctrl->xfer_msg = qcom_xfer_msg;
c088c335	531	sctrl->wakeup = qcom_clk_pause_wakeup;
ad7fcbc3 SD	532	ctrl->tx.n = QCOM_TX_MSGS;
	533	ctrl->tx.sl_sz = SLIM_MSGQ_BUF_LEN;
	534	ctrl->rx.n = QCOM_RX_MSGS;
	535	ctrl->rx.sl_sz = SLIM_MSGQ_BUF_LEN;
6396bb22	536	ctrl->wr_comp = kcalloc(QCOM_TX_MSGS, sizeof(struct completion *),
ad7fcbc3 SD	537	GFP_KERNEL);
	538	if (!ctrl->wr_comp)
	539	return -ENOMEM;
	540
	541	spin_lock_init(&ctrl->rx.lock);
	542	spin_lock_init(&ctrl->tx.lock);
	543	INIT_WORK(&ctrl->wd, qcom_slim_rxwq);
	544	ctrl->rxwq = create_singlethread_workqueue("qcom_slim_rx");
	545	if (!ctrl->rxwq) {
	546	dev_err(ctrl->dev, "Failed to start Rx WQ\n");
	547	return -ENOMEM;
	548	}
	549
	550	ctrl->framer.rootfreq = SLIM_ROOT_FREQ / 8;
	551	ctrl->framer.superfreq =
	552	ctrl->framer.rootfreq / SLIM_CL_PER_SUPERFRAME_DIV8;
	553	sctrl->a_framer = &ctrl->framer;
	554	sctrl->clkgear = SLIM_MAX_CLK_GEAR;
	555
	556	qcom_slim_prg_slew(pdev, ctrl);
	557
	558	ret = devm_request_irq(&pdev->dev, ctrl->irq, qcom_slim_interrupt,
	559	IRQF_TRIGGER_HIGH, "qcom_slim_irq", ctrl);
	560	if (ret) {
	561	dev_err(&pdev->dev, "request IRQ failed\n");
	562	goto err_request_irq_failed;
	563	}
	564
	565	ret = clk_prepare_enable(ctrl->hclk);
	566	if (ret)
	567	goto err_hclk_enable_failed;
	568
	569	ret = clk_prepare_enable(ctrl->rclk);
	570	if (ret)
	571	goto err_rclk_enable_failed;
	572
c127f98b AB	573	ctrl->tx.base = devm_kcalloc(&pdev->dev, ctrl->tx.n, ctrl->tx.sl_sz,
c127f98b AB	574	GFP_KERNEL);
ad7fcbc3 SD	575	if (!ctrl->tx.base) {
	576	ret = -ENOMEM;
	577	goto err;
	578	}
	579
c127f98b AB	580	ctrl->rx.base = devm_kcalloc(&pdev->dev,ctrl->rx.n, ctrl->rx.sl_sz,
c127f98b AB	581	GFP_KERNEL);
ad7fcbc3 SD	582	if (!ctrl->rx.base) {
	583	ret = -ENOMEM;
	584	goto err;
	585	}
	586
	587	/* Register with framework before enabling frame, clock */
	588	ret = slim_register_controller(&ctrl->ctrl);
	589	if (ret) {
	590	dev_err(ctrl->dev, "error adding controller\n");
	591	goto err;
	592	}
	593
	594	ver = readl_relaxed(ctrl->base);
	595	/* Version info in 16 MSbits */
	596	ver >>= 16;
	597	/* Component register initialization */
	598	writel(1, ctrl->base + CFG_PORT(COMP_CFG, ver));
	599	writel((EE_MGR_RSC_GRP \| EE_NGD_2 \| EE_NGD_1),
	600	ctrl->base + CFG_PORT(COMP_TRUST_CFG, ver));
	601
	602	writel((MGR_INT_TX_NACKED_2 \|
	603	MGR_INT_MSG_BUF_CONTE \| MGR_INT_RX_MSG_RCVD \|
	604	MGR_INT_TX_MSG_SENT), ctrl->base + MGR_INT_EN);
	605	writel(1, ctrl->base + MGR_CFG);
	606	/* Framer register initialization */
	607	writel((1 << INTR_WAKE) \| (0xA << REF_CLK_GEAR) \|
	608	(0xA << CLK_GEAR) \| (1 << ROOT_FREQ) \| (1 << FRM_ACTIVE) \| 1,
	609	ctrl->base + FRM_CFG);
	610	writel(MGR_CFG_ENABLE, ctrl->base + MGR_CFG);
	611	writel(1, ctrl->base + INTF_CFG);
	612	writel(1, ctrl->base + CFG_PORT(COMP_CFG, ver));
	613
	614	pm_runtime_use_autosuspend(&pdev->dev);
	615	pm_runtime_set_autosuspend_delay(&pdev->dev, QCOM_SLIM_AUTOSUSPEND);
	616	pm_runtime_set_active(&pdev->dev);
	617	pm_runtime_mark_last_busy(&pdev->dev);
	618	pm_runtime_enable(&pdev->dev);
	619
	620	dev_dbg(ctrl->dev, "QCOM SB controller is up:ver:0x%x!\n", ver);
	621	return 0;
	622
	623	err:
	624	clk_disable_unprepare(ctrl->rclk);
	625	err_rclk_enable_failed:
	626	clk_disable_unprepare(ctrl->hclk);
	627	err_hclk_enable_failed:
	628	err_request_irq_failed:
	629	destroy_workqueue(ctrl->rxwq);
	630	return ret;
	631	}
	632
	633	static int qcom_slim_remove(struct platform_device *pdev)
	634	{
	635	struct qcom_slim_ctrl *ctrl = platform_get_drvdata(pdev);
	636
c088c335	637	pm_runtime_disable(&pdev->dev);
ad7fcbc3	638	slim_unregister_controller(&ctrl->ctrl);
89d93c6d CY	639	clk_disable_unprepare(ctrl->rclk);
89d93c6d CY	640	clk_disable_unprepare(ctrl->hclk);
ad7fcbc3 SD	641	destroy_workqueue(ctrl->rxwq);
	642	return 0;
	643	}
	644
c088c335 SD	645	/*
	646	* If PM_RUNTIME is not defined, these 2 functions become helper
	647	* functions to be called from system suspend/resume.
	648	*/
	649	#ifdef CONFIG_PM
	650	static int qcom_slim_runtime_suspend(struct device *device)
	651	{
d003c346	652	struct qcom_slim_ctrl *ctrl = dev_get_drvdata(device);
c088c335 SD	653	int ret;
	654
	655	dev_dbg(device, "pm_runtime: suspending...\n");
	656	ret = slim_ctrl_clk_pause(&ctrl->ctrl, false, SLIM_CLK_UNSPECIFIED);
	657	if (ret) {
	658	dev_err(device, "clk pause not entered:%d", ret);
	659	} else {
	660	disable_irq(ctrl->irq);
	661	clk_disable_unprepare(ctrl->hclk);
	662	clk_disable_unprepare(ctrl->rclk);
	663	}
	664	return ret;
	665	}
	666
	667	static int qcom_slim_runtime_resume(struct device *device)
	668	{
d003c346	669	struct qcom_slim_ctrl *ctrl = dev_get_drvdata(device);
c088c335 SD	670	int ret = 0;
	671
	672	dev_dbg(device, "pm_runtime: resuming...\n");
	673	ret = slim_ctrl_clk_pause(&ctrl->ctrl, true, 0);
	674	if (ret)
	675	dev_err(device, "clk pause not exited:%d", ret);
	676	return ret;
	677	}
	678	#endif
	679
	680	#ifdef CONFIG_PM_SLEEP
	681	static int qcom_slim_suspend(struct device *dev)
	682	{
	683	int ret = 0;
	684
	685	if (!pm_runtime_enabled(dev) \|\|
	686	(!pm_runtime_suspended(dev))) {
	687	dev_dbg(dev, "system suspend");
	688	ret = qcom_slim_runtime_suspend(dev);
	689	}
	690
	691	return ret;
	692	}
	693
	694	static int qcom_slim_resume(struct device *dev)
	695	{
	696	if (!pm_runtime_enabled(dev) \|\| !pm_runtime_suspended(dev)) {
	697	int ret;
	698
	699	dev_dbg(dev, "system resume");
	700	ret = qcom_slim_runtime_resume(dev);
	701	if (!ret) {
	702	pm_runtime_mark_last_busy(dev);
	703	pm_request_autosuspend(dev);
	704	}
	705	return ret;
	706
	707	}
	708	return 0;
	709	}
	710	#endif /* CONFIG_PM_SLEEP */
	711
ad7fcbc3 SD	712	static const struct dev_pm_ops qcom_slim_dev_pm_ops = {
	713	SET_SYSTEM_SLEEP_PM_OPS(qcom_slim_suspend, qcom_slim_resume)
	714	SET_RUNTIME_PM_OPS(
	715	qcom_slim_runtime_suspend,
	716	qcom_slim_runtime_resume,
	717	NULL
	718	)
	719	};
	720
	721	static const struct of_device_id qcom_slim_dt_match[] = {
	722	{ .compatible = "qcom,slim", },
	723	{ .compatible = "qcom,apq8064-slim", },
	724	{}
	725	};
	726
	727	static struct platform_driver qcom_slim_driver = {
	728	.probe = qcom_slim_probe,
	729	.remove = qcom_slim_remove,
	730	.driver = {
	731	.name = "qcom_slim_ctrl",
	732	.of_match_table = qcom_slim_dt_match,
c088c335	733	.pm = &qcom_slim_dev_pm_ops,
ad7fcbc3 SD	734	},
	735	};
	736	module_platform_driver(qcom_slim_driver);
	737
	738	MODULE_LICENSE("GPL v2");
	739	MODULE_DESCRIPTION("Qualcomm SLIMbus Controller");