Commit | Line | Data |
---|---|---|
02ab3f70 MD |
1 | /* |
2 | * Shared interrupt handling code for IPR and INTC2 types of IRQs. | |
3 | * | |
d58876e2 | 4 | * Copyright (C) 2007, 2008 Magnus Damm |
a8941dad | 5 | * Copyright (C) 2009, 2010 Paul Mundt |
02ab3f70 MD |
6 | * |
7 | * Based on intc2.c and ipr.c | |
8 | * | |
9 | * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi | |
10 | * Copyright (C) 2000 Kazumoto Kojima | |
11 | * Copyright (C) 2001 David J. Mckay (david.mckay@st.com) | |
12 | * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp> | |
13 | * Copyright (C) 2005, 2006 Paul Mundt | |
14 | * | |
15 | * This file is subject to the terms and conditions of the GNU General Public | |
16 | * License. See the file "COPYING" in the main directory of this archive | |
17 | * for more details. | |
18 | */ | |
19 | #include <linux/init.h> | |
20 | #include <linux/irq.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/interrupt.h> | |
bbfbd8b1 | 24 | #include <linux/sh_intc.h> |
2dcec7a9 MD |
25 | #include <linux/sysdev.h> |
26 | #include <linux/list.h> | |
54ff328b | 27 | #include <linux/topology.h> |
1ce7b039 | 28 | #include <linux/bitmap.h> |
a8941dad | 29 | #include <linux/cpumask.h> |
73505b44 MD |
30 | |
31 | #define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \ | |
32 | ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \ | |
33 | ((addr_e) << 16) | ((addr_d << 24))) | |
34 | ||
35 | #define _INTC_SHIFT(h) (h & 0x1f) | |
36 | #define _INTC_WIDTH(h) ((h >> 5) & 0xf) | |
37 | #define _INTC_FN(h) ((h >> 9) & 0xf) | |
38 | #define _INTC_MODE(h) ((h >> 13) & 0x7) | |
39 | #define _INTC_ADDR_E(h) ((h >> 16) & 0xff) | |
40 | #define _INTC_ADDR_D(h) ((h >> 24) & 0xff) | |
41 | ||
42 | struct intc_handle_int { | |
43 | unsigned int irq; | |
44 | unsigned long handle; | |
45 | }; | |
02ab3f70 | 46 | |
73505b44 | 47 | struct intc_desc_int { |
2dcec7a9 MD |
48 | struct list_head list; |
49 | struct sys_device sysdev; | |
7fd87b3f | 50 | pm_message_t state; |
73505b44 | 51 | unsigned long *reg; |
f18d533e MD |
52 | #ifdef CONFIG_SMP |
53 | unsigned long *smp; | |
54 | #endif | |
73505b44 MD |
55 | unsigned int nr_reg; |
56 | struct intc_handle_int *prio; | |
57 | unsigned int nr_prio; | |
58 | struct intc_handle_int *sense; | |
59 | unsigned int nr_sense; | |
60 | struct irq_chip chip; | |
61 | }; | |
02ab3f70 | 62 | |
2dcec7a9 MD |
63 | static LIST_HEAD(intc_list); |
64 | ||
1ce7b039 PM |
65 | /* |
66 | * The intc_irq_map provides a global map of bound IRQ vectors for a | |
67 | * given platform. Allocation of IRQs are either static through the CPU | |
68 | * vector map, or dynamic in the case of board mux vectors or MSI. | |
69 | * | |
70 | * As this is a central point for all IRQ controllers on the system, | |
71 | * each of the available sources are mapped out here. This combined with | |
72 | * sparseirq makes it quite trivial to keep the vector map tightly packed | |
73 | * when dynamically creating IRQs, as well as tying in to otherwise | |
74 | * unused irq_desc positions in the sparse array. | |
75 | */ | |
76 | static DECLARE_BITMAP(intc_irq_map, NR_IRQS); | |
77 | static DEFINE_SPINLOCK(vector_lock); | |
78 | ||
f18d533e MD |
79 | #ifdef CONFIG_SMP |
80 | #define IS_SMP(x) x.smp | |
81 | #define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c)) | |
82 | #define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1) | |
83 | #else | |
84 | #define IS_SMP(x) 0 | |
85 | #define INTC_REG(d, x, c) (d->reg[(x)]) | |
86 | #define SMP_NR(d, x) 1 | |
87 | #endif | |
88 | ||
73505b44 | 89 | static unsigned int intc_prio_level[NR_IRQS]; /* for now */ |
d58876e2 | 90 | static unsigned long ack_handle[NR_IRQS]; |
02ab3f70 | 91 | |
73505b44 | 92 | static inline struct intc_desc_int *get_intc_desc(unsigned int irq) |
02ab3f70 MD |
93 | { |
94 | struct irq_chip *chip = get_irq_chip(irq); | |
6000fc4d | 95 | return container_of(chip, struct intc_desc_int, chip); |
02ab3f70 MD |
96 | } |
97 | ||
98 | static inline unsigned int set_field(unsigned int value, | |
99 | unsigned int field_value, | |
73505b44 | 100 | unsigned int handle) |
02ab3f70 | 101 | { |
73505b44 MD |
102 | unsigned int width = _INTC_WIDTH(handle); |
103 | unsigned int shift = _INTC_SHIFT(handle); | |
104 | ||
02ab3f70 MD |
105 | value &= ~(((1 << width) - 1) << shift); |
106 | value |= field_value << shift; | |
107 | return value; | |
108 | } | |
109 | ||
73505b44 | 110 | static void write_8(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 111 | { |
62429e03 | 112 | __raw_writeb(set_field(0, data, h), addr); |
6000fc4d | 113 | (void)__raw_readb(addr); /* Defeat write posting */ |
02ab3f70 MD |
114 | } |
115 | ||
73505b44 | 116 | static void write_16(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 117 | { |
62429e03 | 118 | __raw_writew(set_field(0, data, h), addr); |
6000fc4d | 119 | (void)__raw_readw(addr); /* Defeat write posting */ |
02ab3f70 MD |
120 | } |
121 | ||
73505b44 | 122 | static void write_32(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 123 | { |
62429e03 | 124 | __raw_writel(set_field(0, data, h), addr); |
6000fc4d | 125 | (void)__raw_readl(addr); /* Defeat write posting */ |
02ab3f70 MD |
126 | } |
127 | ||
73505b44 | 128 | static void modify_8(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 129 | { |
4370fe1c MD |
130 | unsigned long flags; |
131 | local_irq_save(flags); | |
62429e03 | 132 | __raw_writeb(set_field(__raw_readb(addr), data, h), addr); |
6000fc4d | 133 | (void)__raw_readb(addr); /* Defeat write posting */ |
4370fe1c | 134 | local_irq_restore(flags); |
02ab3f70 MD |
135 | } |
136 | ||
73505b44 | 137 | static void modify_16(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 138 | { |
4370fe1c MD |
139 | unsigned long flags; |
140 | local_irq_save(flags); | |
62429e03 | 141 | __raw_writew(set_field(__raw_readw(addr), data, h), addr); |
6000fc4d | 142 | (void)__raw_readw(addr); /* Defeat write posting */ |
4370fe1c | 143 | local_irq_restore(flags); |
02ab3f70 MD |
144 | } |
145 | ||
73505b44 | 146 | static void modify_32(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 147 | { |
4370fe1c MD |
148 | unsigned long flags; |
149 | local_irq_save(flags); | |
62429e03 | 150 | __raw_writel(set_field(__raw_readl(addr), data, h), addr); |
6000fc4d | 151 | (void)__raw_readl(addr); /* Defeat write posting */ |
4370fe1c | 152 | local_irq_restore(flags); |
02ab3f70 MD |
153 | } |
154 | ||
73505b44 MD |
155 | enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 }; |
156 | ||
157 | static void (*intc_reg_fns[])(unsigned long addr, | |
158 | unsigned long h, | |
159 | unsigned long data) = { | |
160 | [REG_FN_WRITE_BASE + 0] = write_8, | |
161 | [REG_FN_WRITE_BASE + 1] = write_16, | |
162 | [REG_FN_WRITE_BASE + 3] = write_32, | |
163 | [REG_FN_MODIFY_BASE + 0] = modify_8, | |
164 | [REG_FN_MODIFY_BASE + 1] = modify_16, | |
165 | [REG_FN_MODIFY_BASE + 3] = modify_32, | |
166 | }; | |
02ab3f70 | 167 | |
73505b44 MD |
168 | enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */ |
169 | MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */ | |
170 | MODE_DUAL_REG, /* Two registers, set bit to enable / disable */ | |
171 | MODE_PRIO_REG, /* Priority value written to enable interrupt */ | |
172 | MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */ | |
173 | }; | |
02ab3f70 | 174 | |
73505b44 MD |
175 | static void intc_mode_field(unsigned long addr, |
176 | unsigned long handle, | |
177 | void (*fn)(unsigned long, | |
178 | unsigned long, | |
179 | unsigned long), | |
180 | unsigned int irq) | |
02ab3f70 | 181 | { |
73505b44 | 182 | fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1)); |
02ab3f70 MD |
183 | } |
184 | ||
73505b44 MD |
185 | static void intc_mode_zero(unsigned long addr, |
186 | unsigned long handle, | |
187 | void (*fn)(unsigned long, | |
188 | unsigned long, | |
189 | unsigned long), | |
190 | unsigned int irq) | |
51da6426 | 191 | { |
73505b44 | 192 | fn(addr, handle, 0); |
51da6426 MD |
193 | } |
194 | ||
73505b44 MD |
195 | static void intc_mode_prio(unsigned long addr, |
196 | unsigned long handle, | |
197 | void (*fn)(unsigned long, | |
198 | unsigned long, | |
199 | unsigned long), | |
200 | unsigned int irq) | |
51da6426 | 201 | { |
73505b44 | 202 | fn(addr, handle, intc_prio_level[irq]); |
51da6426 MD |
203 | } |
204 | ||
73505b44 MD |
205 | static void (*intc_enable_fns[])(unsigned long addr, |
206 | unsigned long handle, | |
207 | void (*fn)(unsigned long, | |
208 | unsigned long, | |
209 | unsigned long), | |
210 | unsigned int irq) = { | |
211 | [MODE_ENABLE_REG] = intc_mode_field, | |
212 | [MODE_MASK_REG] = intc_mode_zero, | |
213 | [MODE_DUAL_REG] = intc_mode_field, | |
214 | [MODE_PRIO_REG] = intc_mode_prio, | |
215 | [MODE_PCLR_REG] = intc_mode_prio, | |
216 | }; | |
51da6426 | 217 | |
73505b44 MD |
218 | static void (*intc_disable_fns[])(unsigned long addr, |
219 | unsigned long handle, | |
220 | void (*fn)(unsigned long, | |
221 | unsigned long, | |
222 | unsigned long), | |
223 | unsigned int irq) = { | |
224 | [MODE_ENABLE_REG] = intc_mode_zero, | |
225 | [MODE_MASK_REG] = intc_mode_field, | |
226 | [MODE_DUAL_REG] = intc_mode_field, | |
227 | [MODE_PRIO_REG] = intc_mode_zero, | |
228 | [MODE_PCLR_REG] = intc_mode_field, | |
229 | }; | |
51da6426 | 230 | |
73505b44 | 231 | static inline void _intc_enable(unsigned int irq, unsigned long handle) |
51da6426 | 232 | { |
73505b44 | 233 | struct intc_desc_int *d = get_intc_desc(irq); |
f18d533e MD |
234 | unsigned long addr; |
235 | unsigned int cpu; | |
51da6426 | 236 | |
f18d533e | 237 | for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) { |
a8941dad PM |
238 | #ifdef CONFIG_SMP |
239 | if (!cpumask_test_cpu(cpu, irq_to_desc(irq)->affinity)) | |
240 | continue; | |
241 | #endif | |
f18d533e MD |
242 | addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu); |
243 | intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\ | |
244 | [_INTC_FN(handle)], irq); | |
245 | } | |
51da6426 MD |
246 | } |
247 | ||
02ab3f70 MD |
248 | static void intc_enable(unsigned int irq) |
249 | { | |
73505b44 | 250 | _intc_enable(irq, (unsigned long)get_irq_chip_data(irq)); |
02ab3f70 MD |
251 | } |
252 | ||
253 | static void intc_disable(unsigned int irq) | |
254 | { | |
f18d533e | 255 | struct intc_desc_int *d = get_intc_desc(irq); |
73505b44 | 256 | unsigned long handle = (unsigned long) get_irq_chip_data(irq); |
f18d533e MD |
257 | unsigned long addr; |
258 | unsigned int cpu; | |
02ab3f70 | 259 | |
f18d533e | 260 | for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) { |
a8941dad PM |
261 | #ifdef CONFIG_SMP |
262 | if (!cpumask_test_cpu(cpu, irq_to_desc(irq)->affinity)) | |
263 | continue; | |
264 | #endif | |
f18d533e MD |
265 | addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu); |
266 | intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\ | |
267 | [_INTC_FN(handle)], irq); | |
268 | } | |
02ab3f70 MD |
269 | } |
270 | ||
d5190953 MD |
271 | static void (*intc_enable_noprio_fns[])(unsigned long addr, |
272 | unsigned long handle, | |
273 | void (*fn)(unsigned long, | |
274 | unsigned long, | |
275 | unsigned long), | |
276 | unsigned int irq) = { | |
277 | [MODE_ENABLE_REG] = intc_mode_field, | |
278 | [MODE_MASK_REG] = intc_mode_zero, | |
279 | [MODE_DUAL_REG] = intc_mode_field, | |
280 | [MODE_PRIO_REG] = intc_mode_field, | |
281 | [MODE_PCLR_REG] = intc_mode_field, | |
282 | }; | |
283 | ||
284 | static void intc_enable_disable(struct intc_desc_int *d, | |
285 | unsigned long handle, int do_enable) | |
286 | { | |
287 | unsigned long addr; | |
288 | unsigned int cpu; | |
289 | void (*fn)(unsigned long, unsigned long, | |
290 | void (*)(unsigned long, unsigned long, unsigned long), | |
291 | unsigned int); | |
292 | ||
293 | if (do_enable) { | |
294 | for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) { | |
295 | addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu); | |
296 | fn = intc_enable_noprio_fns[_INTC_MODE(handle)]; | |
297 | fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0); | |
298 | } | |
299 | } else { | |
300 | for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) { | |
301 | addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu); | |
302 | fn = intc_disable_fns[_INTC_MODE(handle)]; | |
303 | fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0); | |
304 | } | |
305 | } | |
306 | } | |
307 | ||
2dcec7a9 MD |
308 | static int intc_set_wake(unsigned int irq, unsigned int on) |
309 | { | |
310 | return 0; /* allow wakeup, but setup hardware in intc_suspend() */ | |
311 | } | |
312 | ||
a8941dad PM |
313 | #ifdef CONFIG_SMP |
314 | /* | |
315 | * This is held with the irq desc lock held, so we don't require any | |
316 | * additional locking here at the intc desc level. The affinity mask is | |
317 | * later tested in the enable/disable paths. | |
318 | */ | |
319 | static int intc_set_affinity(unsigned int irq, const struct cpumask *cpumask) | |
320 | { | |
321 | if (!cpumask_intersects(cpumask, cpu_online_mask)) | |
322 | return -1; | |
323 | ||
324 | cpumask_copy(irq_to_desc(irq)->affinity, cpumask); | |
325 | ||
326 | return 0; | |
327 | } | |
328 | #endif | |
329 | ||
d58876e2 MD |
330 | static void intc_mask_ack(unsigned int irq) |
331 | { | |
332 | struct intc_desc_int *d = get_intc_desc(irq); | |
333 | unsigned long handle = ack_handle[irq]; | |
334 | unsigned long addr; | |
335 | ||
336 | intc_disable(irq); | |
337 | ||
338 | /* read register and write zero only to the assocaited bit */ | |
339 | ||
340 | if (handle) { | |
341 | addr = INTC_REG(d, _INTC_ADDR_D(handle), 0); | |
6bdfb22a YS |
342 | switch (_INTC_FN(handle)) { |
343 | case REG_FN_MODIFY_BASE + 0: /* 8bit */ | |
62429e03 PM |
344 | __raw_readb(addr); |
345 | __raw_writeb(0xff ^ set_field(0, 1, handle), addr); | |
6bdfb22a YS |
346 | break; |
347 | case REG_FN_MODIFY_BASE + 1: /* 16bit */ | |
62429e03 PM |
348 | __raw_readw(addr); |
349 | __raw_writew(0xffff ^ set_field(0, 1, handle), addr); | |
6bdfb22a YS |
350 | break; |
351 | case REG_FN_MODIFY_BASE + 3: /* 32bit */ | |
62429e03 PM |
352 | __raw_readl(addr); |
353 | __raw_writel(0xffffffff ^ set_field(0, 1, handle), addr); | |
6bdfb22a YS |
354 | break; |
355 | default: | |
356 | BUG(); | |
357 | break; | |
358 | } | |
d58876e2 MD |
359 | } |
360 | } | |
d58876e2 | 361 | |
73505b44 MD |
362 | static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp, |
363 | unsigned int nr_hp, | |
364 | unsigned int irq) | |
02ab3f70 | 365 | { |
73505b44 MD |
366 | int i; |
367 | ||
3d37d94e MD |
368 | /* this doesn't scale well, but... |
369 | * | |
370 | * this function should only be used for cerain uncommon | |
371 | * operations such as intc_set_priority() and intc_set_sense() | |
372 | * and in those rare cases performance doesn't matter that much. | |
373 | * keeping the memory footprint low is more important. | |
374 | * | |
375 | * one rather simple way to speed this up and still keep the | |
376 | * memory footprint down is to make sure the array is sorted | |
377 | * and then perform a bisect to lookup the irq. | |
378 | */ | |
379 | ||
73505b44 MD |
380 | for (i = 0; i < nr_hp; i++) { |
381 | if ((hp + i)->irq != irq) | |
382 | continue; | |
383 | ||
384 | return hp + i; | |
385 | } | |
02ab3f70 | 386 | |
73505b44 | 387 | return NULL; |
02ab3f70 MD |
388 | } |
389 | ||
73505b44 | 390 | int intc_set_priority(unsigned int irq, unsigned int prio) |
02ab3f70 | 391 | { |
73505b44 MD |
392 | struct intc_desc_int *d = get_intc_desc(irq); |
393 | struct intc_handle_int *ihp; | |
394 | ||
395 | if (!intc_prio_level[irq] || prio <= 1) | |
396 | return -EINVAL; | |
397 | ||
398 | ihp = intc_find_irq(d->prio, d->nr_prio, irq); | |
399 | if (ihp) { | |
3d37d94e | 400 | if (prio >= (1 << _INTC_WIDTH(ihp->handle))) |
73505b44 | 401 | return -EINVAL; |
02ab3f70 | 402 | |
73505b44 MD |
403 | intc_prio_level[irq] = prio; |
404 | ||
405 | /* | |
406 | * only set secondary masking method directly | |
407 | * primary masking method is using intc_prio_level[irq] | |
408 | * priority level will be set during next enable() | |
409 | */ | |
410 | ||
3d37d94e | 411 | if (_INTC_FN(ihp->handle) != REG_FN_ERR) |
73505b44 MD |
412 | _intc_enable(irq, ihp->handle); |
413 | } | |
414 | return 0; | |
02ab3f70 MD |
415 | } |
416 | ||
417 | #define VALID(x) (x | 0x80) | |
418 | ||
419 | static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = { | |
420 | [IRQ_TYPE_EDGE_FALLING] = VALID(0), | |
421 | [IRQ_TYPE_EDGE_RISING] = VALID(1), | |
422 | [IRQ_TYPE_LEVEL_LOW] = VALID(2), | |
720be990 MD |
423 | /* SH7706, SH7707 and SH7709 do not support high level triggered */ |
424 | #if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \ | |
425 | !defined(CONFIG_CPU_SUBTYPE_SH7707) && \ | |
426 | !defined(CONFIG_CPU_SUBTYPE_SH7709) | |
02ab3f70 | 427 | [IRQ_TYPE_LEVEL_HIGH] = VALID(3), |
720be990 | 428 | #endif |
02ab3f70 MD |
429 | }; |
430 | ||
431 | static int intc_set_sense(unsigned int irq, unsigned int type) | |
432 | { | |
73505b44 | 433 | struct intc_desc_int *d = get_intc_desc(irq); |
02ab3f70 | 434 | unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK]; |
73505b44 MD |
435 | struct intc_handle_int *ihp; |
436 | unsigned long addr; | |
02ab3f70 | 437 | |
73505b44 | 438 | if (!value) |
02ab3f70 MD |
439 | return -EINVAL; |
440 | ||
73505b44 MD |
441 | ihp = intc_find_irq(d->sense, d->nr_sense, irq); |
442 | if (ihp) { | |
f18d533e | 443 | addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0); |
73505b44 | 444 | intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value); |
02ab3f70 | 445 | } |
73505b44 | 446 | return 0; |
02ab3f70 MD |
447 | } |
448 | ||
73505b44 MD |
449 | static unsigned int __init intc_get_reg(struct intc_desc_int *d, |
450 | unsigned long address) | |
02ab3f70 | 451 | { |
73505b44 | 452 | unsigned int k; |
02ab3f70 | 453 | |
73505b44 MD |
454 | for (k = 0; k < d->nr_reg; k++) { |
455 | if (d->reg[k] == address) | |
456 | return k; | |
51da6426 MD |
457 | } |
458 | ||
459 | BUG(); | |
73505b44 | 460 | return 0; |
51da6426 MD |
461 | } |
462 | ||
73505b44 MD |
463 | static intc_enum __init intc_grp_id(struct intc_desc *desc, |
464 | intc_enum enum_id) | |
680c4598 | 465 | { |
577cd758 | 466 | struct intc_group *g = desc->hw.groups; |
680c4598 MD |
467 | unsigned int i, j; |
468 | ||
577cd758 MD |
469 | for (i = 0; g && enum_id && i < desc->hw.nr_groups; i++) { |
470 | g = desc->hw.groups + i; | |
680c4598 MD |
471 | |
472 | for (j = 0; g->enum_ids[j]; j++) { | |
473 | if (g->enum_ids[j] != enum_id) | |
474 | continue; | |
475 | ||
476 | return g->enum_id; | |
477 | } | |
478 | } | |
479 | ||
480 | return 0; | |
481 | } | |
482 | ||
d5190953 MD |
483 | static unsigned int __init _intc_mask_data(struct intc_desc *desc, |
484 | struct intc_desc_int *d, | |
485 | intc_enum enum_id, | |
486 | unsigned int *reg_idx, | |
487 | unsigned int *fld_idx) | |
02ab3f70 | 488 | { |
577cd758 | 489 | struct intc_mask_reg *mr = desc->hw.mask_regs; |
d5190953 | 490 | unsigned int fn, mode; |
73505b44 | 491 | unsigned long reg_e, reg_d; |
02ab3f70 | 492 | |
d5190953 MD |
493 | while (mr && enum_id && *reg_idx < desc->hw.nr_mask_regs) { |
494 | mr = desc->hw.mask_regs + *reg_idx; | |
02ab3f70 | 495 | |
d5190953 MD |
496 | for (; *fld_idx < ARRAY_SIZE(mr->enum_ids); (*fld_idx)++) { |
497 | if (mr->enum_ids[*fld_idx] != enum_id) | |
02ab3f70 MD |
498 | continue; |
499 | ||
73505b44 MD |
500 | if (mr->set_reg && mr->clr_reg) { |
501 | fn = REG_FN_WRITE_BASE; | |
502 | mode = MODE_DUAL_REG; | |
503 | reg_e = mr->clr_reg; | |
504 | reg_d = mr->set_reg; | |
505 | } else { | |
506 | fn = REG_FN_MODIFY_BASE; | |
507 | if (mr->set_reg) { | |
508 | mode = MODE_ENABLE_REG; | |
509 | reg_e = mr->set_reg; | |
510 | reg_d = mr->set_reg; | |
511 | } else { | |
512 | mode = MODE_MASK_REG; | |
513 | reg_e = mr->clr_reg; | |
514 | reg_d = mr->clr_reg; | |
515 | } | |
51da6426 MD |
516 | } |
517 | ||
73505b44 MD |
518 | fn += (mr->reg_width >> 3) - 1; |
519 | return _INTC_MK(fn, mode, | |
520 | intc_get_reg(d, reg_e), | |
521 | intc_get_reg(d, reg_d), | |
522 | 1, | |
d5190953 | 523 | (mr->reg_width - 1) - *fld_idx); |
02ab3f70 | 524 | } |
d5190953 MD |
525 | |
526 | *fld_idx = 0; | |
527 | (*reg_idx)++; | |
02ab3f70 MD |
528 | } |
529 | ||
d5190953 MD |
530 | return 0; |
531 | } | |
532 | ||
533 | static unsigned int __init intc_mask_data(struct intc_desc *desc, | |
534 | struct intc_desc_int *d, | |
535 | intc_enum enum_id, int do_grps) | |
536 | { | |
537 | unsigned int i = 0; | |
538 | unsigned int j = 0; | |
539 | unsigned int ret; | |
540 | ||
541 | ret = _intc_mask_data(desc, d, enum_id, &i, &j); | |
542 | if (ret) | |
543 | return ret; | |
544 | ||
680c4598 | 545 | if (do_grps) |
73505b44 | 546 | return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0); |
680c4598 | 547 | |
02ab3f70 MD |
548 | return 0; |
549 | } | |
550 | ||
d5190953 MD |
551 | static unsigned int __init _intc_prio_data(struct intc_desc *desc, |
552 | struct intc_desc_int *d, | |
553 | intc_enum enum_id, | |
554 | unsigned int *reg_idx, | |
555 | unsigned int *fld_idx) | |
02ab3f70 | 556 | { |
577cd758 | 557 | struct intc_prio_reg *pr = desc->hw.prio_regs; |
d5190953 | 558 | unsigned int fn, n, mode, bit; |
73505b44 | 559 | unsigned long reg_e, reg_d; |
02ab3f70 | 560 | |
d5190953 MD |
561 | while (pr && enum_id && *reg_idx < desc->hw.nr_prio_regs) { |
562 | pr = desc->hw.prio_regs + *reg_idx; | |
02ab3f70 | 563 | |
d5190953 MD |
564 | for (; *fld_idx < ARRAY_SIZE(pr->enum_ids); (*fld_idx)++) { |
565 | if (pr->enum_ids[*fld_idx] != enum_id) | |
02ab3f70 MD |
566 | continue; |
567 | ||
73505b44 MD |
568 | if (pr->set_reg && pr->clr_reg) { |
569 | fn = REG_FN_WRITE_BASE; | |
570 | mode = MODE_PCLR_REG; | |
571 | reg_e = pr->set_reg; | |
572 | reg_d = pr->clr_reg; | |
573 | } else { | |
574 | fn = REG_FN_MODIFY_BASE; | |
575 | mode = MODE_PRIO_REG; | |
576 | if (!pr->set_reg) | |
577 | BUG(); | |
578 | reg_e = pr->set_reg; | |
579 | reg_d = pr->set_reg; | |
580 | } | |
02ab3f70 | 581 | |
73505b44 | 582 | fn += (pr->reg_width >> 3) - 1; |
d5190953 | 583 | n = *fld_idx + 1; |
02ab3f70 | 584 | |
d5190953 | 585 | BUG_ON(n * pr->field_width > pr->reg_width); |
b21a9104 | 586 | |
d5190953 | 587 | bit = pr->reg_width - (n * pr->field_width); |
02ab3f70 | 588 | |
73505b44 MD |
589 | return _INTC_MK(fn, mode, |
590 | intc_get_reg(d, reg_e), | |
591 | intc_get_reg(d, reg_d), | |
592 | pr->field_width, bit); | |
02ab3f70 | 593 | } |
d5190953 MD |
594 | |
595 | *fld_idx = 0; | |
596 | (*reg_idx)++; | |
02ab3f70 MD |
597 | } |
598 | ||
d5190953 MD |
599 | return 0; |
600 | } | |
601 | ||
602 | static unsigned int __init intc_prio_data(struct intc_desc *desc, | |
603 | struct intc_desc_int *d, | |
604 | intc_enum enum_id, int do_grps) | |
605 | { | |
606 | unsigned int i = 0; | |
607 | unsigned int j = 0; | |
608 | unsigned int ret; | |
609 | ||
610 | ret = _intc_prio_data(desc, d, enum_id, &i, &j); | |
611 | if (ret) | |
612 | return ret; | |
613 | ||
680c4598 | 614 | if (do_grps) |
73505b44 MD |
615 | return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0); |
616 | ||
617 | return 0; | |
618 | } | |
619 | ||
d5190953 MD |
620 | static void __init intc_enable_disable_enum(struct intc_desc *desc, |
621 | struct intc_desc_int *d, | |
622 | intc_enum enum_id, int enable) | |
623 | { | |
624 | unsigned int i, j, data; | |
625 | ||
626 | /* go through and enable/disable all mask bits */ | |
627 | i = j = 0; | |
628 | do { | |
629 | data = _intc_mask_data(desc, d, enum_id, &i, &j); | |
630 | if (data) | |
631 | intc_enable_disable(d, data, enable); | |
632 | j++; | |
633 | } while (data); | |
634 | ||
635 | /* go through and enable/disable all priority fields */ | |
636 | i = j = 0; | |
637 | do { | |
638 | data = _intc_prio_data(desc, d, enum_id, &i, &j); | |
639 | if (data) | |
640 | intc_enable_disable(d, data, enable); | |
641 | ||
642 | j++; | |
643 | } while (data); | |
644 | } | |
645 | ||
d58876e2 MD |
646 | static unsigned int __init intc_ack_data(struct intc_desc *desc, |
647 | struct intc_desc_int *d, | |
648 | intc_enum enum_id) | |
649 | { | |
577cd758 | 650 | struct intc_mask_reg *mr = desc->hw.ack_regs; |
d58876e2 MD |
651 | unsigned int i, j, fn, mode; |
652 | unsigned long reg_e, reg_d; | |
653 | ||
577cd758 MD |
654 | for (i = 0; mr && enum_id && i < desc->hw.nr_ack_regs; i++) { |
655 | mr = desc->hw.ack_regs + i; | |
d58876e2 MD |
656 | |
657 | for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) { | |
658 | if (mr->enum_ids[j] != enum_id) | |
659 | continue; | |
660 | ||
661 | fn = REG_FN_MODIFY_BASE; | |
662 | mode = MODE_ENABLE_REG; | |
663 | reg_e = mr->set_reg; | |
664 | reg_d = mr->set_reg; | |
665 | ||
666 | fn += (mr->reg_width >> 3) - 1; | |
667 | return _INTC_MK(fn, mode, | |
668 | intc_get_reg(d, reg_e), | |
669 | intc_get_reg(d, reg_d), | |
670 | 1, | |
671 | (mr->reg_width - 1) - j); | |
672 | } | |
673 | } | |
674 | ||
675 | return 0; | |
676 | } | |
d58876e2 | 677 | |
73505b44 MD |
678 | static unsigned int __init intc_sense_data(struct intc_desc *desc, |
679 | struct intc_desc_int *d, | |
680 | intc_enum enum_id) | |
681 | { | |
577cd758 | 682 | struct intc_sense_reg *sr = desc->hw.sense_regs; |
73505b44 MD |
683 | unsigned int i, j, fn, bit; |
684 | ||
577cd758 MD |
685 | for (i = 0; sr && enum_id && i < desc->hw.nr_sense_regs; i++) { |
686 | sr = desc->hw.sense_regs + i; | |
73505b44 MD |
687 | |
688 | for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) { | |
689 | if (sr->enum_ids[j] != enum_id) | |
690 | continue; | |
691 | ||
692 | fn = REG_FN_MODIFY_BASE; | |
693 | fn += (sr->reg_width >> 3) - 1; | |
73505b44 | 694 | |
b21a9104 | 695 | BUG_ON((j + 1) * sr->field_width > sr->reg_width); |
696 | ||
697 | bit = sr->reg_width - ((j + 1) * sr->field_width); | |
73505b44 MD |
698 | |
699 | return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg), | |
700 | 0, sr->field_width, bit); | |
701 | } | |
702 | } | |
680c4598 | 703 | |
02ab3f70 MD |
704 | return 0; |
705 | } | |
706 | ||
73505b44 MD |
707 | static void __init intc_register_irq(struct intc_desc *desc, |
708 | struct intc_desc_int *d, | |
709 | intc_enum enum_id, | |
02ab3f70 MD |
710 | unsigned int irq) |
711 | { | |
3d37d94e | 712 | struct intc_handle_int *hp; |
680c4598 MD |
713 | unsigned int data[2], primary; |
714 | ||
1ce7b039 PM |
715 | /* |
716 | * Register the IRQ position with the global IRQ map | |
717 | */ | |
718 | set_bit(irq, intc_irq_map); | |
719 | ||
680c4598 MD |
720 | /* Prefer single interrupt source bitmap over other combinations: |
721 | * 1. bitmap, single interrupt source | |
722 | * 2. priority, single interrupt source | |
723 | * 3. bitmap, multiple interrupt sources (groups) | |
724 | * 4. priority, multiple interrupt sources (groups) | |
725 | */ | |
02ab3f70 | 726 | |
73505b44 MD |
727 | data[0] = intc_mask_data(desc, d, enum_id, 0); |
728 | data[1] = intc_prio_data(desc, d, enum_id, 0); | |
680c4598 MD |
729 | |
730 | primary = 0; | |
731 | if (!data[0] && data[1]) | |
732 | primary = 1; | |
733 | ||
bdaa6e80 | 734 | if (!data[0] && !data[1]) |
f033599a PM |
735 | pr_warning("intc: missing unique irq mask for " |
736 | "irq %d (vect 0x%04x)\n", irq, irq2evt(irq)); | |
bdaa6e80 | 737 | |
73505b44 MD |
738 | data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1); |
739 | data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1); | |
680c4598 MD |
740 | |
741 | if (!data[primary]) | |
742 | primary ^= 1; | |
743 | ||
744 | BUG_ON(!data[primary]); /* must have primary masking method */ | |
02ab3f70 MD |
745 | |
746 | disable_irq_nosync(irq); | |
73505b44 | 747 | set_irq_chip_and_handler_name(irq, &d->chip, |
02ab3f70 | 748 | handle_level_irq, "level"); |
680c4598 | 749 | set_irq_chip_data(irq, (void *)data[primary]); |
02ab3f70 | 750 | |
7f3edee8 MD |
751 | /* set priority level |
752 | * - this needs to be at least 2 for 5-bit priorities on 7780 | |
753 | */ | |
754 | intc_prio_level[irq] = 2; | |
73505b44 | 755 | |
680c4598 MD |
756 | /* enable secondary masking method if present */ |
757 | if (data[!primary]) | |
73505b44 MD |
758 | _intc_enable(irq, data[!primary]); |
759 | ||
760 | /* add irq to d->prio list if priority is available */ | |
761 | if (data[1]) { | |
3d37d94e MD |
762 | hp = d->prio + d->nr_prio; |
763 | hp->irq = irq; | |
764 | hp->handle = data[1]; | |
765 | ||
766 | if (primary) { | |
767 | /* | |
768 | * only secondary priority should access registers, so | |
769 | * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority() | |
770 | */ | |
771 | ||
772 | hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0); | |
773 | hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0); | |
774 | } | |
73505b44 MD |
775 | d->nr_prio++; |
776 | } | |
777 | ||
778 | /* add irq to d->sense list if sense is available */ | |
779 | data[0] = intc_sense_data(desc, d, enum_id); | |
780 | if (data[0]) { | |
781 | (d->sense + d->nr_sense)->irq = irq; | |
782 | (d->sense + d->nr_sense)->handle = data[0]; | |
783 | d->nr_sense++; | |
784 | } | |
02ab3f70 MD |
785 | |
786 | /* irq should be disabled by default */ | |
73505b44 | 787 | d->chip.mask(irq); |
d58876e2 | 788 | |
577cd758 | 789 | if (desc->hw.ack_regs) |
d58876e2 | 790 | ack_handle[irq] = intc_ack_data(desc, d, enum_id); |
65a5b28f MD |
791 | |
792 | #ifdef CONFIG_ARM | |
793 | set_irq_flags(irq, IRQF_VALID); /* Enable IRQ on ARM systems */ | |
794 | #endif | |
02ab3f70 MD |
795 | } |
796 | ||
f18d533e MD |
797 | static unsigned int __init save_reg(struct intc_desc_int *d, |
798 | unsigned int cnt, | |
799 | unsigned long value, | |
800 | unsigned int smp) | |
801 | { | |
802 | if (value) { | |
803 | d->reg[cnt] = value; | |
804 | #ifdef CONFIG_SMP | |
805 | d->smp[cnt] = smp; | |
806 | #endif | |
807 | return 1; | |
808 | } | |
809 | ||
810 | return 0; | |
811 | } | |
812 | ||
05ecd5a1 | 813 | static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc) |
bdaa6e80 | 814 | { |
05ecd5a1 | 815 | generic_handle_irq((unsigned int)get_irq_data(irq)); |
bdaa6e80 | 816 | } |
f18d533e | 817 | |
02ab3f70 MD |
818 | void __init register_intc_controller(struct intc_desc *desc) |
819 | { | |
54ff328b | 820 | unsigned int i, k, smp; |
577cd758 | 821 | struct intc_hw_desc *hw = &desc->hw; |
73505b44 MD |
822 | struct intc_desc_int *d; |
823 | ||
11b6aa95 | 824 | d = kzalloc(sizeof(*d), GFP_NOWAIT); |
73505b44 | 825 | |
2dcec7a9 MD |
826 | INIT_LIST_HEAD(&d->list); |
827 | list_add(&d->list, &intc_list); | |
828 | ||
577cd758 MD |
829 | d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0; |
830 | d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0; | |
831 | d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0; | |
832 | d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0; | |
9b798d50 | 833 | |
11b6aa95 | 834 | d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT); |
f18d533e | 835 | #ifdef CONFIG_SMP |
11b6aa95 | 836 | d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT); |
f18d533e | 837 | #endif |
73505b44 MD |
838 | k = 0; |
839 | ||
577cd758 MD |
840 | if (hw->mask_regs) { |
841 | for (i = 0; i < hw->nr_mask_regs; i++) { | |
842 | smp = IS_SMP(hw->mask_regs[i]); | |
843 | k += save_reg(d, k, hw->mask_regs[i].set_reg, smp); | |
844 | k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp); | |
73505b44 MD |
845 | } |
846 | } | |
847 | ||
577cd758 MD |
848 | if (hw->prio_regs) { |
849 | d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio), | |
850 | GFP_NOWAIT); | |
73505b44 | 851 | |
577cd758 MD |
852 | for (i = 0; i < hw->nr_prio_regs; i++) { |
853 | smp = IS_SMP(hw->prio_regs[i]); | |
854 | k += save_reg(d, k, hw->prio_regs[i].set_reg, smp); | |
855 | k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp); | |
73505b44 MD |
856 | } |
857 | } | |
858 | ||
577cd758 MD |
859 | if (hw->sense_regs) { |
860 | d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense), | |
861 | GFP_NOWAIT); | |
73505b44 | 862 | |
577cd758 MD |
863 | for (i = 0; i < hw->nr_sense_regs; i++) |
864 | k += save_reg(d, k, hw->sense_regs[i].reg, 0); | |
73505b44 MD |
865 | } |
866 | ||
73505b44 MD |
867 | d->chip.name = desc->name; |
868 | d->chip.mask = intc_disable; | |
869 | d->chip.unmask = intc_enable; | |
870 | d->chip.mask_ack = intc_disable; | |
f7dd2548 MD |
871 | d->chip.enable = intc_enable; |
872 | d->chip.disable = intc_disable; | |
873 | d->chip.shutdown = intc_disable; | |
73505b44 | 874 | d->chip.set_type = intc_set_sense; |
2dcec7a9 | 875 | d->chip.set_wake = intc_set_wake; |
a8941dad PM |
876 | #ifdef CONFIG_SMP |
877 | d->chip.set_affinity = intc_set_affinity; | |
878 | #endif | |
02ab3f70 | 879 | |
577cd758 MD |
880 | if (hw->ack_regs) { |
881 | for (i = 0; i < hw->nr_ack_regs; i++) | |
882 | k += save_reg(d, k, hw->ack_regs[i].set_reg, 0); | |
d58876e2 MD |
883 | |
884 | d->chip.mask_ack = intc_mask_ack; | |
885 | } | |
d58876e2 | 886 | |
d85429a3 MD |
887 | /* disable bits matching force_disable before registering irqs */ |
888 | if (desc->force_disable) | |
889 | intc_enable_disable_enum(desc, d, desc->force_disable, 0); | |
d5190953 MD |
890 | |
891 | /* disable bits matching force_enable before registering irqs */ | |
892 | if (desc->force_enable) | |
893 | intc_enable_disable_enum(desc, d, desc->force_enable, 0); | |
894 | ||
d58876e2 MD |
895 | BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */ |
896 | ||
bdaa6e80 | 897 | /* register the vectors one by one */ |
577cd758 MD |
898 | for (i = 0; i < hw->nr_vectors; i++) { |
899 | struct intc_vect *vect = hw->vectors + i; | |
05ff3004 PM |
900 | unsigned int irq = evt2irq(vect->vect); |
901 | struct irq_desc *irq_desc; | |
54ff328b | 902 | |
bdaa6e80 MD |
903 | if (!vect->enum_id) |
904 | continue; | |
905 | ||
54ff328b | 906 | irq_desc = irq_to_desc_alloc_node(irq, numa_node_id()); |
05ff3004 | 907 | if (unlikely(!irq_desc)) { |
1279b7f1 | 908 | pr_info("can't get irq_desc for %d\n", irq); |
05ff3004 PM |
909 | continue; |
910 | } | |
911 | ||
912 | intc_register_irq(desc, d, vect->enum_id, irq); | |
05ecd5a1 | 913 | |
577cd758 MD |
914 | for (k = i + 1; k < hw->nr_vectors; k++) { |
915 | struct intc_vect *vect2 = hw->vectors + k; | |
05ecd5a1 PM |
916 | unsigned int irq2 = evt2irq(vect2->vect); |
917 | ||
918 | if (vect->enum_id != vect2->enum_id) | |
919 | continue; | |
920 | ||
1279b7f1 PM |
921 | /* |
922 | * In the case of multi-evt handling and sparse | |
923 | * IRQ support, each vector still needs to have | |
924 | * its own backing irq_desc. | |
925 | */ | |
926 | irq_desc = irq_to_desc_alloc_node(irq2, numa_node_id()); | |
927 | if (unlikely(!irq_desc)) { | |
928 | pr_info("can't get irq_desc for %d\n", irq2); | |
929 | continue; | |
930 | } | |
931 | ||
05ecd5a1 PM |
932 | vect2->enum_id = 0; |
933 | ||
934 | /* redirect this interrupts to the first one */ | |
4d2185d9 | 935 | set_irq_chip(irq2, &dummy_irq_chip); |
e6f07759 | 936 | set_irq_chained_handler(irq2, intc_redirect_irq); |
05ecd5a1 PM |
937 | set_irq_data(irq2, (void *)irq); |
938 | } | |
02ab3f70 | 939 | } |
d5190953 MD |
940 | |
941 | /* enable bits matching force_enable after registering irqs */ | |
942 | if (desc->force_enable) | |
943 | intc_enable_disable_enum(desc, d, desc->force_enable, 1); | |
02ab3f70 | 944 | } |
2dcec7a9 MD |
945 | |
946 | static int intc_suspend(struct sys_device *dev, pm_message_t state) | |
947 | { | |
948 | struct intc_desc_int *d; | |
949 | struct irq_desc *desc; | |
950 | int irq; | |
951 | ||
952 | /* get intc controller associated with this sysdev */ | |
953 | d = container_of(dev, struct intc_desc_int, sysdev); | |
954 | ||
7fd87b3f FV |
955 | switch (state.event) { |
956 | case PM_EVENT_ON: | |
957 | if (d->state.event != PM_EVENT_FREEZE) | |
958 | break; | |
959 | for_each_irq_desc(irq, desc) { | |
87a705dd | 960 | if (desc->handle_irq == intc_redirect_irq) |
0a753d58 | 961 | continue; |
7fd87b3f FV |
962 | if (desc->chip != &d->chip) |
963 | continue; | |
964 | if (desc->status & IRQ_DISABLED) | |
965 | intc_disable(irq); | |
966 | else | |
967 | intc_enable(irq); | |
968 | } | |
969 | break; | |
970 | case PM_EVENT_FREEZE: | |
971 | /* nothing has to be done */ | |
972 | break; | |
973 | case PM_EVENT_SUSPEND: | |
974 | /* enable wakeup irqs belonging to this intc controller */ | |
975 | for_each_irq_desc(irq, desc) { | |
976 | if ((desc->status & IRQ_WAKEUP) && (desc->chip == &d->chip)) | |
977 | intc_enable(irq); | |
978 | } | |
979 | break; | |
2dcec7a9 | 980 | } |
7fd87b3f | 981 | d->state = state; |
2dcec7a9 MD |
982 | |
983 | return 0; | |
984 | } | |
985 | ||
7fd87b3f FV |
986 | static int intc_resume(struct sys_device *dev) |
987 | { | |
988 | return intc_suspend(dev, PMSG_ON); | |
989 | } | |
990 | ||
2dcec7a9 MD |
991 | static struct sysdev_class intc_sysdev_class = { |
992 | .name = "intc", | |
993 | .suspend = intc_suspend, | |
7fd87b3f | 994 | .resume = intc_resume, |
2dcec7a9 MD |
995 | }; |
996 | ||
997 | /* register this intc as sysdev to allow suspend/resume */ | |
998 | static int __init register_intc_sysdevs(void) | |
999 | { | |
1000 | struct intc_desc_int *d; | |
1001 | int error; | |
1002 | int id = 0; | |
1003 | ||
1004 | error = sysdev_class_register(&intc_sysdev_class); | |
1005 | if (!error) { | |
1006 | list_for_each_entry(d, &intc_list, list) { | |
1007 | d->sysdev.id = id; | |
1008 | d->sysdev.cls = &intc_sysdev_class; | |
1009 | error = sysdev_register(&d->sysdev); | |
1010 | if (error) | |
1011 | break; | |
1012 | id++; | |
1013 | } | |
1014 | } | |
1015 | ||
1016 | if (error) | |
1017 | pr_warning("intc: sysdev registration error\n"); | |
1018 | ||
1019 | return error; | |
1020 | } | |
2dcec7a9 | 1021 | device_initcall(register_intc_sysdevs); |
1ce7b039 PM |
1022 | |
1023 | /* | |
1024 | * Dynamic IRQ allocation and deallocation | |
1025 | */ | |
e9867c56 | 1026 | unsigned int create_irq_nr(unsigned int irq_want, int node) |
1ce7b039 PM |
1027 | { |
1028 | unsigned int irq = 0, new; | |
1029 | unsigned long flags; | |
1030 | struct irq_desc *desc; | |
1031 | ||
1032 | spin_lock_irqsave(&vector_lock, flags); | |
1033 | ||
1034 | /* | |
e9867c56 | 1035 | * First try the wanted IRQ |
1ce7b039 | 1036 | */ |
e9867c56 PM |
1037 | if (test_and_set_bit(irq_want, intc_irq_map) == 0) { |
1038 | new = irq_want; | |
1039 | } else { | |
1040 | /* .. then fall back to scanning. */ | |
1ce7b039 PM |
1041 | new = find_first_zero_bit(intc_irq_map, nr_irqs); |
1042 | if (unlikely(new == nr_irqs)) | |
1043 | goto out_unlock; | |
1044 | ||
1ce7b039 | 1045 | __set_bit(new, intc_irq_map); |
1ce7b039 PM |
1046 | } |
1047 | ||
e9867c56 PM |
1048 | desc = irq_to_desc_alloc_node(new, node); |
1049 | if (unlikely(!desc)) { | |
1050 | pr_info("can't get irq_desc for %d\n", new); | |
1051 | goto out_unlock; | |
1052 | } | |
1053 | ||
1054 | desc = move_irq_desc(desc, node); | |
1055 | irq = new; | |
1056 | ||
1ce7b039 PM |
1057 | out_unlock: |
1058 | spin_unlock_irqrestore(&vector_lock, flags); | |
1059 | ||
65a5b28f | 1060 | if (irq > 0) { |
1ce7b039 | 1061 | dynamic_irq_init(irq); |
65a5b28f MD |
1062 | #ifdef CONFIG_ARM |
1063 | set_irq_flags(irq, IRQF_VALID); /* Enable IRQ on ARM systems */ | |
1064 | #endif | |
1065 | } | |
1ce7b039 PM |
1066 | |
1067 | return irq; | |
1068 | } | |
1069 | ||
1070 | int create_irq(void) | |
1071 | { | |
1072 | int nid = cpu_to_node(smp_processor_id()); | |
1073 | int irq; | |
1074 | ||
e9867c56 | 1075 | irq = create_irq_nr(NR_IRQS_LEGACY, nid); |
1ce7b039 PM |
1076 | if (irq == 0) |
1077 | irq = -1; | |
1078 | ||
1079 | return irq; | |
1080 | } | |
1081 | ||
1082 | void destroy_irq(unsigned int irq) | |
1083 | { | |
1084 | unsigned long flags; | |
1085 | ||
1086 | dynamic_irq_cleanup(irq); | |
1087 | ||
1088 | spin_lock_irqsave(&vector_lock, flags); | |
1089 | __clear_bit(irq, intc_irq_map); | |
1090 | spin_unlock_irqrestore(&vector_lock, flags); | |
1091 | } | |
45b9deaf PM |
1092 | |
1093 | int reserve_irq_vector(unsigned int irq) | |
1094 | { | |
1095 | unsigned long flags; | |
1096 | int ret = 0; | |
1097 | ||
1098 | spin_lock_irqsave(&vector_lock, flags); | |
1099 | if (test_and_set_bit(irq, intc_irq_map)) | |
1100 | ret = -EBUSY; | |
1101 | spin_unlock_irqrestore(&vector_lock, flags); | |
1102 | ||
1103 | return ret; | |
1104 | } | |
1105 | ||
1106 | void reserve_irq_legacy(void) | |
1107 | { | |
1108 | unsigned long flags; | |
1109 | int i, j; | |
1110 | ||
1111 | spin_lock_irqsave(&vector_lock, flags); | |
1112 | j = find_first_bit(intc_irq_map, nr_irqs); | |
1113 | for (i = 0; i < j; i++) | |
1114 | __set_bit(i, intc_irq_map); | |
1115 | spin_unlock_irqrestore(&vector_lock, flags); | |
1116 | } |