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34aec591 RR |
1 | /* |
2 | * timbuart.c timberdale FPGA UART driver | |
3 | * Copyright (c) 2009 Intel Corporation | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
19 | /* Supports: | |
20 | * Timberdale FPGA UART | |
21 | */ | |
22 | ||
23 | #include <linux/pci.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/serial_core.h> | |
26 | #include <linux/kernel.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/ioport.h> | |
29 | ||
30 | #include "timbuart.h" | |
31 | ||
32 | struct timbuart_port { | |
33 | struct uart_port port; | |
34 | struct tasklet_struct tasklet; | |
35 | int usedma; | |
2421c48b | 36 | u32 last_ier; |
34aec591 RR |
37 | struct platform_device *dev; |
38 | }; | |
39 | ||
40 | static int baudrates[] = {9600, 19200, 38400, 57600, 115200, 230400, 460800, | |
41 | 921600, 1843200, 3250000}; | |
42 | ||
2421c48b | 43 | static void timbuart_mctrl_check(struct uart_port *port, u32 isr, u32 *ier); |
34aec591 RR |
44 | |
45 | static irqreturn_t timbuart_handleinterrupt(int irq, void *devid); | |
46 | ||
47 | static void timbuart_stop_rx(struct uart_port *port) | |
48 | { | |
49 | /* spin lock held by upper layer, disable all RX interrupts */ | |
2421c48b RR |
50 | u32 ier = ioread32(port->membase + TIMBUART_IER) & ~RXFLAGS; |
51 | iowrite32(ier, port->membase + TIMBUART_IER); | |
34aec591 RR |
52 | } |
53 | ||
54 | static void timbuart_stop_tx(struct uart_port *port) | |
55 | { | |
56 | /* spinlock held by upper layer, disable TX interrupt */ | |
2421c48b RR |
57 | u32 ier = ioread32(port->membase + TIMBUART_IER) & ~TXBAE; |
58 | iowrite32(ier, port->membase + TIMBUART_IER); | |
34aec591 RR |
59 | } |
60 | ||
61 | static void timbuart_start_tx(struct uart_port *port) | |
62 | { | |
63 | struct timbuart_port *uart = | |
64 | container_of(port, struct timbuart_port, port); | |
65 | ||
66 | /* do not transfer anything here -> fire off the tasklet */ | |
67 | tasklet_schedule(&uart->tasklet); | |
68 | } | |
69 | ||
70 | static void timbuart_flush_buffer(struct uart_port *port) | |
71 | { | |
72 | u8 ctl = ioread8(port->membase + TIMBUART_CTRL) | TIMBUART_CTRL_FLSHTX; | |
73 | ||
74 | iowrite8(ctl, port->membase + TIMBUART_CTRL); | |
2421c48b | 75 | iowrite32(TXBF, port->membase + TIMBUART_ISR); |
34aec591 RR |
76 | } |
77 | ||
78 | static void timbuart_rx_chars(struct uart_port *port) | |
79 | { | |
80 | struct tty_struct *tty = port->info->port.tty; | |
81 | ||
2421c48b | 82 | while (ioread32(port->membase + TIMBUART_ISR) & RXDP) { |
34aec591 RR |
83 | u8 ch = ioread8(port->membase + TIMBUART_RXFIFO); |
84 | port->icount.rx++; | |
85 | tty_insert_flip_char(tty, ch, TTY_NORMAL); | |
86 | } | |
87 | ||
88 | spin_unlock(&port->lock); | |
89 | tty_flip_buffer_push(port->info->port.tty); | |
90 | spin_lock(&port->lock); | |
91 | ||
92 | dev_dbg(port->dev, "%s - total read %d bytes\n", | |
93 | __func__, port->icount.rx); | |
94 | } | |
95 | ||
96 | static void timbuart_tx_chars(struct uart_port *port) | |
97 | { | |
98 | struct circ_buf *xmit = &port->info->xmit; | |
99 | ||
2421c48b | 100 | while (!(ioread32(port->membase + TIMBUART_ISR) & TXBF) && |
34aec591 RR |
101 | !uart_circ_empty(xmit)) { |
102 | iowrite8(xmit->buf[xmit->tail], | |
103 | port->membase + TIMBUART_TXFIFO); | |
104 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
105 | port->icount.tx++; | |
106 | } | |
107 | ||
108 | dev_dbg(port->dev, | |
109 | "%s - total written %d bytes, CTL: %x, RTS: %x, baud: %x\n", | |
110 | __func__, | |
111 | port->icount.tx, | |
112 | ioread8(port->membase + TIMBUART_CTRL), | |
113 | port->mctrl & TIOCM_RTS, | |
114 | ioread8(port->membase + TIMBUART_BAUDRATE)); | |
115 | } | |
116 | ||
2421c48b | 117 | static void timbuart_handle_tx_port(struct uart_port *port, u32 isr, u32 *ier) |
34aec591 RR |
118 | { |
119 | struct timbuart_port *uart = | |
120 | container_of(port, struct timbuart_port, port); | |
121 | struct circ_buf *xmit = &port->info->xmit; | |
122 | ||
123 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) | |
124 | return; | |
125 | ||
126 | if (port->x_char) | |
127 | return; | |
128 | ||
129 | if (isr & TXFLAGS) { | |
130 | timbuart_tx_chars(port); | |
131 | /* clear all TX interrupts */ | |
2421c48b | 132 | iowrite32(TXFLAGS, port->membase + TIMBUART_ISR); |
34aec591 RR |
133 | |
134 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
135 | uart_write_wakeup(port); | |
136 | } else | |
137 | /* Re-enable any tx interrupt */ | |
138 | *ier |= uart->last_ier & TXFLAGS; | |
139 | ||
140 | /* enable interrupts if there are chars in the transmit buffer, | |
141 | * Or if we delivered some bytes and want the almost empty interrupt | |
142 | * we wake up the upper layer later when we got the interrupt | |
143 | * to give it some time to go out... | |
144 | */ | |
145 | if (!uart_circ_empty(xmit)) | |
146 | *ier |= TXBAE; | |
147 | ||
148 | dev_dbg(port->dev, "%s - leaving\n", __func__); | |
149 | } | |
150 | ||
2421c48b | 151 | void timbuart_handle_rx_port(struct uart_port *port, u32 isr, u32 *ier) |
34aec591 RR |
152 | { |
153 | if (isr & RXFLAGS) { | |
154 | /* Some RX status is set */ | |
155 | if (isr & RXBF) { | |
156 | u8 ctl = ioread8(port->membase + TIMBUART_CTRL) | | |
157 | TIMBUART_CTRL_FLSHRX; | |
158 | iowrite8(ctl, port->membase + TIMBUART_CTRL); | |
159 | port->icount.overrun++; | |
160 | } else if (isr & (RXDP)) | |
161 | timbuart_rx_chars(port); | |
162 | ||
163 | /* ack all RX interrupts */ | |
2421c48b | 164 | iowrite32(RXFLAGS, port->membase + TIMBUART_ISR); |
34aec591 RR |
165 | } |
166 | ||
167 | /* always have the RX interrupts enabled */ | |
168 | *ier |= RXBAF | RXBF | RXTT; | |
169 | ||
170 | dev_dbg(port->dev, "%s - leaving\n", __func__); | |
171 | } | |
172 | ||
173 | void timbuart_tasklet(unsigned long arg) | |
174 | { | |
175 | struct timbuart_port *uart = (struct timbuart_port *)arg; | |
2421c48b | 176 | u32 isr, ier = 0; |
34aec591 RR |
177 | |
178 | spin_lock(&uart->port.lock); | |
179 | ||
2421c48b | 180 | isr = ioread32(uart->port.membase + TIMBUART_ISR); |
34aec591 RR |
181 | dev_dbg(uart->port.dev, "%s ISR: %x\n", __func__, isr); |
182 | ||
183 | if (!uart->usedma) | |
184 | timbuart_handle_tx_port(&uart->port, isr, &ier); | |
185 | ||
186 | timbuart_mctrl_check(&uart->port, isr, &ier); | |
187 | ||
188 | if (!uart->usedma) | |
189 | timbuart_handle_rx_port(&uart->port, isr, &ier); | |
190 | ||
2421c48b | 191 | iowrite32(ier, uart->port.membase + TIMBUART_IER); |
34aec591 RR |
192 | |
193 | spin_unlock(&uart->port.lock); | |
194 | dev_dbg(uart->port.dev, "%s leaving\n", __func__); | |
195 | } | |
196 | ||
197 | static unsigned int timbuart_tx_empty(struct uart_port *port) | |
198 | { | |
2421c48b | 199 | u32 isr = ioread32(port->membase + TIMBUART_ISR); |
34aec591 | 200 | |
2421c48b | 201 | return (isr & TXBE) ? TIOCSER_TEMT : 0; |
34aec591 RR |
202 | } |
203 | ||
204 | static unsigned int timbuart_get_mctrl(struct uart_port *port) | |
205 | { | |
206 | u8 cts = ioread8(port->membase + TIMBUART_CTRL); | |
207 | dev_dbg(port->dev, "%s - cts %x\n", __func__, cts); | |
208 | ||
209 | if (cts & TIMBUART_CTRL_CTS) | |
210 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
211 | else | |
212 | return TIOCM_DSR | TIOCM_CAR; | |
213 | } | |
214 | ||
215 | static void timbuart_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
216 | { | |
217 | dev_dbg(port->dev, "%s - %x\n", __func__, mctrl); | |
218 | ||
219 | if (mctrl & TIOCM_RTS) | |
220 | iowrite8(TIMBUART_CTRL_RTS, port->membase + TIMBUART_CTRL); | |
221 | else | |
222 | iowrite8(TIMBUART_CTRL_RTS, port->membase + TIMBUART_CTRL); | |
223 | } | |
224 | ||
2421c48b | 225 | static void timbuart_mctrl_check(struct uart_port *port, u32 isr, u32 *ier) |
34aec591 RR |
226 | { |
227 | unsigned int cts; | |
228 | ||
229 | if (isr & CTS_DELTA) { | |
230 | /* ack */ | |
2421c48b | 231 | iowrite32(CTS_DELTA, port->membase + TIMBUART_ISR); |
34aec591 RR |
232 | cts = timbuart_get_mctrl(port); |
233 | uart_handle_cts_change(port, cts & TIOCM_CTS); | |
234 | wake_up_interruptible(&port->info->delta_msr_wait); | |
235 | } | |
236 | ||
237 | *ier |= CTS_DELTA; | |
238 | } | |
239 | ||
240 | static void timbuart_enable_ms(struct uart_port *port) | |
241 | { | |
242 | /* N/A */ | |
243 | } | |
244 | ||
245 | static void timbuart_break_ctl(struct uart_port *port, int ctl) | |
246 | { | |
247 | /* N/A */ | |
248 | } | |
249 | ||
250 | static int timbuart_startup(struct uart_port *port) | |
251 | { | |
252 | struct timbuart_port *uart = | |
253 | container_of(port, struct timbuart_port, port); | |
254 | ||
255 | dev_dbg(port->dev, "%s\n", __func__); | |
256 | ||
257 | iowrite8(TIMBUART_CTRL_FLSHRX, port->membase + TIMBUART_CTRL); | |
2421c48b | 258 | iowrite32(0x1ff, port->membase + TIMBUART_ISR); |
34aec591 | 259 | /* Enable all but TX interrupts */ |
2421c48b | 260 | iowrite32(RXBAF | RXBF | RXTT | CTS_DELTA, |
34aec591 RR |
261 | port->membase + TIMBUART_IER); |
262 | ||
263 | return request_irq(port->irq, timbuart_handleinterrupt, IRQF_SHARED, | |
264 | "timb-uart", uart); | |
265 | } | |
266 | ||
267 | static void timbuart_shutdown(struct uart_port *port) | |
268 | { | |
269 | struct timbuart_port *uart = | |
270 | container_of(port, struct timbuart_port, port); | |
271 | dev_dbg(port->dev, "%s\n", __func__); | |
272 | free_irq(port->irq, uart); | |
2421c48b | 273 | iowrite32(0, port->membase + TIMBUART_IER); |
34aec591 RR |
274 | } |
275 | ||
276 | static int get_bindex(int baud) | |
277 | { | |
278 | int i; | |
279 | ||
280 | for (i = 0; i < ARRAY_SIZE(baudrates); i++) | |
7d55deaf | 281 | if (baud <= baudrates[i]) |
34aec591 RR |
282 | return i; |
283 | ||
284 | return -1; | |
285 | } | |
286 | ||
287 | static void timbuart_set_termios(struct uart_port *port, | |
288 | struct ktermios *termios, | |
289 | struct ktermios *old) | |
290 | { | |
291 | unsigned int baud; | |
292 | short bindex; | |
293 | unsigned long flags; | |
294 | ||
295 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); | |
296 | bindex = get_bindex(baud); | |
297 | dev_dbg(port->dev, "%s - bindex %d\n", __func__, bindex); | |
298 | ||
7d55deaf AC |
299 | if (bindex < 0) |
300 | bindex = 0; | |
301 | baud = baudrates[bindex]; | |
302 | ||
303 | /* The serial layer calls into this once with old = NULL when setting | |
304 | up initially */ | |
305 | if (old) | |
306 | tty_termios_copy_hw(termios, old); | |
307 | tty_termios_encode_baud_rate(termios, baud, baud); | |
308 | ||
309 | spin_lock_irqsave(&port->lock, flags); | |
310 | iowrite8((u8)bindex, port->membase + TIMBUART_BAUDRATE); | |
311 | uart_update_timeout(port, termios->c_cflag, baud); | |
312 | spin_unlock_irqrestore(&port->lock, flags); | |
34aec591 RR |
313 | } |
314 | ||
315 | static const char *timbuart_type(struct uart_port *port) | |
316 | { | |
317 | return port->type == PORT_UNKNOWN ? "timbuart" : NULL; | |
318 | } | |
319 | ||
320 | /* We do not request/release mappings of the registers here, | |
321 | * currently it's done in the proble function. | |
322 | */ | |
323 | static void timbuart_release_port(struct uart_port *port) | |
324 | { | |
325 | struct platform_device *pdev = to_platform_device(port->dev); | |
326 | int size = | |
327 | resource_size(platform_get_resource(pdev, IORESOURCE_MEM, 0)); | |
328 | ||
329 | if (port->flags & UPF_IOREMAP) { | |
330 | iounmap(port->membase); | |
331 | port->membase = NULL; | |
332 | } | |
333 | ||
334 | release_mem_region(port->mapbase, size); | |
335 | } | |
336 | ||
337 | static int timbuart_request_port(struct uart_port *port) | |
338 | { | |
339 | struct platform_device *pdev = to_platform_device(port->dev); | |
340 | int size = | |
341 | resource_size(platform_get_resource(pdev, IORESOURCE_MEM, 0)); | |
342 | ||
343 | if (!request_mem_region(port->mapbase, size, "timb-uart")) | |
344 | return -EBUSY; | |
345 | ||
346 | if (port->flags & UPF_IOREMAP) { | |
347 | port->membase = ioremap(port->mapbase, size); | |
348 | if (port->membase == NULL) { | |
349 | release_mem_region(port->mapbase, size); | |
350 | return -ENOMEM; | |
351 | } | |
352 | } | |
353 | ||
354 | return 0; | |
355 | } | |
356 | ||
357 | static irqreturn_t timbuart_handleinterrupt(int irq, void *devid) | |
358 | { | |
359 | struct timbuart_port *uart = (struct timbuart_port *)devid; | |
360 | ||
361 | if (ioread8(uart->port.membase + TIMBUART_IPR)) { | |
2421c48b | 362 | uart->last_ier = ioread32(uart->port.membase + TIMBUART_IER); |
34aec591 RR |
363 | |
364 | /* disable interrupts, the tasklet enables them again */ | |
2421c48b | 365 | iowrite32(0, uart->port.membase + TIMBUART_IER); |
34aec591 RR |
366 | |
367 | /* fire off bottom half */ | |
368 | tasklet_schedule(&uart->tasklet); | |
369 | ||
370 | return IRQ_HANDLED; | |
371 | } else | |
372 | return IRQ_NONE; | |
373 | } | |
374 | ||
375 | /* | |
376 | * Configure/autoconfigure the port. | |
377 | */ | |
378 | static void timbuart_config_port(struct uart_port *port, int flags) | |
379 | { | |
380 | if (flags & UART_CONFIG_TYPE) { | |
381 | port->type = PORT_TIMBUART; | |
382 | timbuart_request_port(port); | |
383 | } | |
384 | } | |
385 | ||
386 | static int timbuart_verify_port(struct uart_port *port, | |
387 | struct serial_struct *ser) | |
388 | { | |
389 | /* we don't want the core code to modify any port params */ | |
390 | return -EINVAL; | |
391 | } | |
392 | ||
393 | static struct uart_ops timbuart_ops = { | |
394 | .tx_empty = timbuart_tx_empty, | |
395 | .set_mctrl = timbuart_set_mctrl, | |
396 | .get_mctrl = timbuart_get_mctrl, | |
397 | .stop_tx = timbuart_stop_tx, | |
398 | .start_tx = timbuart_start_tx, | |
399 | .flush_buffer = timbuart_flush_buffer, | |
400 | .stop_rx = timbuart_stop_rx, | |
401 | .enable_ms = timbuart_enable_ms, | |
402 | .break_ctl = timbuart_break_ctl, | |
403 | .startup = timbuart_startup, | |
404 | .shutdown = timbuart_shutdown, | |
405 | .set_termios = timbuart_set_termios, | |
406 | .type = timbuart_type, | |
407 | .release_port = timbuart_release_port, | |
408 | .request_port = timbuart_request_port, | |
409 | .config_port = timbuart_config_port, | |
410 | .verify_port = timbuart_verify_port | |
411 | }; | |
412 | ||
413 | static struct uart_driver timbuart_driver = { | |
414 | .owner = THIS_MODULE, | |
415 | .driver_name = "timberdale_uart", | |
416 | .dev_name = "ttyTU", | |
417 | .major = TIMBUART_MAJOR, | |
418 | .minor = TIMBUART_MINOR, | |
419 | .nr = 1 | |
420 | }; | |
421 | ||
422 | static int timbuart_probe(struct platform_device *dev) | |
423 | { | |
424 | int err; | |
425 | struct timbuart_port *uart; | |
426 | struct resource *iomem; | |
427 | ||
428 | dev_dbg(&dev->dev, "%s\n", __func__); | |
429 | ||
430 | uart = kzalloc(sizeof(*uart), GFP_KERNEL); | |
431 | if (!uart) { | |
432 | err = -EINVAL; | |
433 | goto err_mem; | |
434 | } | |
435 | ||
436 | uart->usedma = 0; | |
437 | ||
438 | uart->port.uartclk = 3250000 * 16; | |
439 | uart->port.fifosize = TIMBUART_FIFO_SIZE; | |
440 | uart->port.regshift = 2; | |
441 | uart->port.iotype = UPIO_MEM; | |
442 | uart->port.ops = &timbuart_ops; | |
443 | uart->port.irq = 0; | |
444 | uart->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP; | |
445 | uart->port.line = 0; | |
446 | uart->port.dev = &dev->dev; | |
447 | ||
448 | iomem = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
449 | if (!iomem) { | |
450 | err = -ENOMEM; | |
451 | goto err_register; | |
452 | } | |
453 | uart->port.mapbase = iomem->start; | |
454 | uart->port.membase = NULL; | |
455 | ||
456 | uart->port.irq = platform_get_irq(dev, 0); | |
457 | if (uart->port.irq < 0) { | |
458 | err = -EINVAL; | |
459 | goto err_register; | |
460 | } | |
461 | ||
462 | tasklet_init(&uart->tasklet, timbuart_tasklet, (unsigned long)uart); | |
463 | ||
464 | err = uart_register_driver(&timbuart_driver); | |
465 | if (err) | |
466 | goto err_register; | |
467 | ||
468 | err = uart_add_one_port(&timbuart_driver, &uart->port); | |
469 | if (err) | |
470 | goto err_add_port; | |
471 | ||
472 | platform_set_drvdata(dev, uart); | |
473 | ||
474 | return 0; | |
475 | ||
476 | err_add_port: | |
477 | uart_unregister_driver(&timbuart_driver); | |
478 | err_register: | |
479 | kfree(uart); | |
480 | err_mem: | |
481 | printk(KERN_ERR "timberdale: Failed to register Timberdale UART: %d\n", | |
482 | err); | |
483 | ||
484 | return err; | |
485 | } | |
486 | ||
487 | static int timbuart_remove(struct platform_device *dev) | |
488 | { | |
489 | struct timbuart_port *uart = platform_get_drvdata(dev); | |
490 | ||
491 | tasklet_kill(&uart->tasklet); | |
492 | uart_remove_one_port(&timbuart_driver, &uart->port); | |
493 | uart_unregister_driver(&timbuart_driver); | |
494 | kfree(uart); | |
495 | ||
496 | return 0; | |
497 | } | |
498 | ||
499 | static struct platform_driver timbuart_platform_driver = { | |
500 | .driver = { | |
501 | .name = "timb-uart", | |
502 | .owner = THIS_MODULE, | |
503 | }, | |
504 | .probe = timbuart_probe, | |
505 | .remove = timbuart_remove, | |
506 | }; | |
507 | ||
508 | /*--------------------------------------------------------------------------*/ | |
509 | ||
510 | static int __init timbuart_init(void) | |
511 | { | |
512 | return platform_driver_register(&timbuart_platform_driver); | |
513 | } | |
514 | ||
515 | static void __exit timbuart_exit(void) | |
516 | { | |
517 | platform_driver_unregister(&timbuart_platform_driver); | |
518 | } | |
519 | ||
520 | module_init(timbuart_init); | |
521 | module_exit(timbuart_exit); | |
522 | ||
523 | MODULE_DESCRIPTION("Timberdale UART driver"); | |
524 | MODULE_LICENSE("GPL v2"); | |
525 | MODULE_ALIAS("platform:timb-uart"); | |
526 |