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sh: Rip out special unknown machvec.
[linux-block.git] / drivers / serial / sh-sci.h
CommitLineData
1da177e4
LT		 1/* $Id: sh-sci.h,v 1.4 2004/02/19 16:43:56 lethal Exp $
2 *
3 * linux/drivers/serial/sh-sci.h
4 *
5 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
6 * Copyright (C) 1999, 2000 Niibe Yutaka
7 * Copyright (C) 2000 Greg Banks
8 * Copyright (C) 2002, 2003 Paul Mundt
9 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
10 * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
11 * Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
12 */
1da177e4 13#include <linux/serial_core.h>
e108b2ca 14#include <asm/io.h>
1da177e4
LT		 15
16#if defined(__H8300H__) || defined(__H8300S__)
17#include <asm/gpio.h>
18#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
19#include <asm/regs306x.h>
20#endif
21#if defined(CONFIG_H8S2678)
22#include <asm/regs267x.h>
23#endif
24#endif
25
1da177e4 26#if defined(CONFIG_CPU_SUBTYPE_SH7708)
1da177e4
LT		 27# define SCSPTR 0xffffff7c /* 8 bit */
28# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
29# define SCI_ONLY
e108b2ca
PM		 30#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || \
31 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
32 defined(CONFIG_CPU_SUBTYPE_SH7706)
1da177e4
LT		 33# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
34# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
35# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
36# define SCI_AND_SCIF
37#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
38# define SCIF0 0xA4400000
39# define SCIF2 0xA4410000
b7a76e4b
PM		 40# define SCSMR_Ir 0xA44A0000
41# define IRDA_SCIF SCIF0
1da177e4
LT		 42# define SCPCR 0xA4000116
43# define SCPDR 0xA4000136
44
45/* Set the clock source,
46 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
47 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
48 */
49# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
50# define SCIF_ONLY
51#elif defined(CONFIG_SH_RTS7751R2D)
1da177e4
LT		 52# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
53# define SCIF_ORER 0x0001 /* overrun error bit */
54# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
55# define SCIF_ONLY
56#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751)
1da177e4
LT		 57# define SCSPTR1 0xffe0001c /* 8 bit SCI */
58# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
59# define SCIF_ORER 0x0001 /* overrun error bit */
60# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
61 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
62 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
63# define SCI_AND_SCIF
64#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
b7a76e4b
PM		 65# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
66# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
67# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
1da177e4
LT		 68# define SCIF_ORER 0x0001 /* overrun error bit */
69# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
70# define SCIF_ONLY
71#elif defined(CONFIG_CPU_SUBTYPE_SH7300)
1da177e4
LT		 72# define SCPCR 0xA4050116 /* 16 bit SCIF */
73# define SCPDR 0xA4050136 /* 16 bit SCIF */
74# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
75# define SCIF_ONLY
9465a54f 76#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
e108b2ca 77# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
9465a54f
NI		 78# define SCI_NPORTS 2
79# define SCIF_ORER 0x0001 /* overrun error bit */
80# define PACR 0xa4050100
81# define PBCR 0xa4050102
82# define SCSCR_INIT(port) 0x3B
e108b2ca 83# define SCIF_ONLY
1da177e4 84#elif defined(CONFIG_CPU_SUBTYPE_SH73180)
1da177e4
LT		 85# define SCPDR 0xA4050138 /* 16 bit SCIF */
86# define SCSPTR2 SCPDR
87# define SCIF_ORER 0x0001 /* overrun error bit */
88# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1 */
89# define SCIF_ONLY
e108b2ca
PM		 90#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
91# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
92# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
93# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
94# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
95# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
96# define SCIF_ONLY
41504c39
PM		 97#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
98# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
99# define SCSPTR0 SCPDR0
100# define SCIF_ORER 0x0001 /* overrun error bit */
101# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
102# define SCIF_ONLY
103# define PORT_PSCR 0xA405011E
1da177e4 104#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
1da177e4
LT		 105# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
106# define SCIF_ORER 0x0001 /* overrun error bit */
107# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
108# define SCIF_ONLY
109#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
1da177e4
LT		 110# define SCSPTR1 0xffe00020 /* 16 bit SCIF */
111# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
112# define SCIF_ORER 0x0001 /* overrun error bit */
113# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
114# define SCIF_ONLY
115#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
116# include <asm/hardware.h>
117# define SCIF_BASE_ADDR 0x01030000
118# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
119# define SCIF_PTR2_OFFS 0x0000020
120# define SCIF_LSR2_OFFS 0x0000024
1da177e4
LT		 121# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
122# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
123# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,
124 TE=1,RE=1,REIE=1 */
125# define SCIF_ONLY
126#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
1da177e4
LT		 127# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
128# define SCI_ONLY
129# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
130#elif defined(CONFIG_H8S2678)
1da177e4
LT		 131# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
132# define SCI_ONLY
133# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
b7a76e4b
PM		 134#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
135# define SCSPTR0 0xff923020 /* 16 bit SCIF */
136# define SCSPTR1 0xff924020 /* 16 bit SCIF */
137# define SCSPTR2 0xff925020 /* 16 bit SCIF */
138# define SCIF_ORER 0x0001 /* overrun error bit */
139# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
140# define SCIF_ONLY
141#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
142# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
143# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
e108b2ca 144# define SCIF_ORER 0x0001 /* Overrun error bit */
b7a76e4b
PM		 145# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
146# define SCIF_ONLY
32351a28
PM		 147#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
148# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
149# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
150# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
151# define SCSPTR3 0xffed0024 /* 16 bit SCIF */
152# define SCSPTR4 0xffee0024 /* 16 bit SCIF */
153# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
154# define SCIF_OPER 0x0001 /* Overrun error bit */
155# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
156# define SCIF_ONLY
9d4436a6
YS		 157#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
158# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
159# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
160# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
161# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
162# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
163# define SCIF_ONLY
164#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
165# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
166# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
167# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
168# define SCIF_ORER 0x0001 /* overrun error bit */
169# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
170# define SCIF_ONLY
1da177e4
LT		 171#else
172# error CPU subtype not defined
173#endif
174
175/* SCSCR */
176#define SCI_CTRL_FLAGS_TIE 0x80 /* all */
177#define SCI_CTRL_FLAGS_RIE 0x40 /* all */
178#define SCI_CTRL_FLAGS_TE 0x20 /* all */
179#define SCI_CTRL_FLAGS_RE 0x10 /* all */
32351a28
PM		 180#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
181 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
182 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
183 defined(CONFIG_CPU_SUBTYPE_SH7785)
1da177e4
LT		 184#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
185#else
186#define SCI_CTRL_FLAGS_REIE 0
187#endif
188/* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
189/* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
190/* SCI_CTRL_FLAGS_CKE1 0x02 * all */
191/* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
192
193/* SCxSR SCI */
194#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
195#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
196#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
197#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
198#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
199#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
200/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
201/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
202
203#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
204
205/* SCxSR SCIF */
206#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
207#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
208#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
209#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
210#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
211#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
212#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
213#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
214
215#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
216#define SCIF_ORER 0x0200
217#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
218#define SCIF_RFDC_MASK 0x007f
219#define SCIF_TXROOM_MAX 64
220#else
221#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
222#define SCIF_RFDC_MASK 0x001f
223#define SCIF_TXROOM_MAX 16
224#endif
225
226#if defined(SCI_ONLY)
227# define SCxSR_TEND(port) SCI_TEND
228# define SCxSR_ERRORS(port) SCI_ERRORS
229# define SCxSR_RDxF(port) SCI_RDRF
230# define SCxSR_TDxE(port) SCI_TDRE
231# define SCxSR_ORER(port) SCI_ORER
232# define SCxSR_FER(port) SCI_FER
233# define SCxSR_PER(port) SCI_PER
234# define SCxSR_BRK(port) 0x00
235# define SCxSR_RDxF_CLEAR(port) 0xbc
236# define SCxSR_ERROR_CLEAR(port) 0xc4
237# define SCxSR_TDxE_CLEAR(port) 0x78
b7a76e4b 238# define SCxSR_BREAK_CLEAR(port) 0xc4
1da177e4
LT		 239#elif defined(SCIF_ONLY)
240# define SCxSR_TEND(port) SCIF_TEND
241# define SCxSR_ERRORS(port) SCIF_ERRORS
242# define SCxSR_RDxF(port) SCIF_RDF
243# define SCxSR_TDxE(port) SCIF_TDFE
244#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
245# define SCxSR_ORER(port) SCIF_ORER
246#else
247# define SCxSR_ORER(port) 0x0000
248#endif
249# define SCxSR_FER(port) SCIF_FER
250# define SCxSR_PER(port) SCIF_PER
251# define SCxSR_BRK(port) SCIF_BRK
252#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
253# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc)
254# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73)
255# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf)
256# define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3)
257#else
258/* SH7705 can also use this, clearing is same between 7705 and 7709 and 7300 */
259# define SCxSR_RDxF_CLEAR(port) 0x00fc
260# define SCxSR_ERROR_CLEAR(port) 0x0073
261# define SCxSR_TDxE_CLEAR(port) 0x00df
b7a76e4b 262# define SCxSR_BREAK_CLEAR(port) 0x00e3
1da177e4
LT		 263#endif
264#else
265# define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
266# define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
267# define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
268# define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
269# define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000)
270# define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
271# define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
272# define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
273# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
274# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
275# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
276# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
277#endif
278
279/* SCFCR */
280#define SCFCR_RFRST 0x0002
281#define SCFCR_TFRST 0x0004
282#define SCFCR_TCRST 0x4000
283#define SCFCR_MCE 0x0008
284
285#define SCI_MAJOR 204
286#define SCI_MINOR_START 8
287
288/* Generic serial flags */
289#define SCI_RX_THROTTLE 0x0000001
290
291#define SCI_MAGIC 0xbabeface
292
293/*
294 * Events are used to schedule things to happen at timer-interrupt
295 * time, instead of at rs interrupt time.
296 */
297#define SCI_EVENT_WRITE_WAKEUP 0
298
1da177e4
LT		 299#define SCI_IN(size, offset) \
300 unsigned int addr = port->mapbase + (offset); \
b7a76e4b 301 if ((size) == 8) { \
1da177e4 302 return ctrl_inb(addr); \
b7a76e4b 303 } else { \
1da177e4
LT		 304 return ctrl_inw(addr); \
305 }
306#define SCI_OUT(size, offset, value) \
307 unsigned int addr = port->mapbase + (offset); \
b7a76e4b 308 if ((size) == 8) { \
1da177e4
LT		 309 ctrl_outb(value, addr); \
310 } else { \
311 ctrl_outw(value, addr); \
312 }
313
314#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
315 static inline unsigned int sci_##name##_in(struct uart_port *port) \
316 { \
b7a76e4b 317 if (port->type == PORT_SCI) { \
1da177e4
LT		 318 SCI_IN(sci_size, sci_offset) \
319 } else { \
b7a76e4b 320 SCI_IN(scif_size, scif_offset); \
1da177e4
LT		 321 } \
322 } \
323 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
324 { \
325 if (port->type == PORT_SCI) { \
326 SCI_OUT(sci_size, sci_offset, value) \
327 } else { \
328 SCI_OUT(scif_size, scif_offset, value); \
329 } \
330 }
331
332#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
333 static inline unsigned int sci_##name##_in(struct uart_port *port) \
334 { \
b7a76e4b 335 SCI_IN(scif_size, scif_offset); \
1da177e4
LT		 336 } \
337 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
338 { \
339 SCI_OUT(scif_size, scif_offset, value); \
340 }
341
342#define CPU_SCI_FNS(name, sci_offset, sci_size) \
343 static inline unsigned int sci_##name##_in(struct uart_port* port) \
344 { \
b7a76e4b 345 SCI_IN(sci_size, sci_offset); \
1da177e4
LT		 346 } \
347 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
348 { \
349 SCI_OUT(sci_size, sci_offset, value); \
350 }
351
352#ifdef CONFIG_CPU_SH3
9465a54f
NI		 353#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
354#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
355 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
356 h8_sci_offset, h8_sci_size) \
357 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
358#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
359 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
360#elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
361 defined(CONFIG_CPU_SUBTYPE_SH7705)
1da177e4
LT		 362#define SCIF_FNS(name, scif_offset, scif_size) \
363 CPU_SCIF_FNS(name, scif_offset, scif_size)
364#else
365#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
366 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
367 h8_sci_offset, h8_sci_size) \
368 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
369#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
370 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
371#endif
372#elif defined(__H8300H__) || defined(__H8300S__)
373#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
374 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
375 h8_sci_offset, h8_sci_size) \
376 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
377#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
378#else
379#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
380 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
381 h8_sci_offset, h8_sci_size) \
382 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
383#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
384 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
385#endif
386
e108b2ca 387#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
9465a54f
NI		 388 defined(CONFIG_CPU_SUBTYPE_SH7705)
389
1da177e4
LT		 390SCIF_FNS(SCSMR, 0x00, 16)
391SCIF_FNS(SCBRR, 0x04, 8)
392SCIF_FNS(SCSCR, 0x08, 16)
393SCIF_FNS(SCTDSR, 0x0c, 8)
394SCIF_FNS(SCFER, 0x10, 16)
395SCIF_FNS(SCxSR, 0x14, 16)
396SCIF_FNS(SCFCR, 0x18, 16)
397SCIF_FNS(SCFDR, 0x1c, 16)
398SCIF_FNS(SCxTDR, 0x20, 8)
399SCIF_FNS(SCxRDR, 0x24, 8)
400SCIF_FNS(SCLSR, 0x24, 16)
401#else
402/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
403/* name off sz off sz off sz off sz off sz*/
404SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
405SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
406SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
407SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
408SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
409SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
410SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
32351a28
PM		 411#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
412 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
413 defined(CONFIG_CPU_SUBTYPE_SH7785)
6fc21b82 414SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
b7a76e4b
PM		 415SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
416SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
417SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
418SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
419#else
1da177e4
LT		 420SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
421SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
422SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
423#endif
b7a76e4b 424#endif
1da177e4
LT		 425#define sci_in(port, reg) sci_##reg##_in(port)
426#define sci_out(port, reg, value) sci_##reg##_out(port, value)
427
428/* H8/300 series SCI pins assignment */
429#if defined(__H8300H__) || defined(__H8300S__)
430static const struct __attribute__((packed)) {
431 int port; /* GPIO port no */
432 unsigned short rx,tx; /* GPIO bit no */
433} h8300_sci_pins[] = {
434#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
435 { /* SCI0 */
436 .port = H8300_GPIO_P9,
437 .rx = H8300_GPIO_B2,
438 .tx = H8300_GPIO_B0,
439 },
440 { /* SCI1 */
441 .port = H8300_GPIO_P9,
442 .rx = H8300_GPIO_B3,
443 .tx = H8300_GPIO_B1,
444 },
445 { /* SCI2 */
446 .port = H8300_GPIO_PB,
447 .rx = H8300_GPIO_B7,
448 .tx = H8300_GPIO_B6,
449 }
450#elif defined(CONFIG_H8S2678)
451 { /* SCI0 */
452 .port = H8300_GPIO_P3,
453 .rx = H8300_GPIO_B2,
454 .tx = H8300_GPIO_B0,
455 },
456 { /* SCI1 */
457 .port = H8300_GPIO_P3,
458 .rx = H8300_GPIO_B3,
459 .tx = H8300_GPIO_B1,
460 },
461 { /* SCI2 */
462 .port = H8300_GPIO_P5,
463 .rx = H8300_GPIO_B1,
464 .tx = H8300_GPIO_B0,
465 }
466#endif
467};
468#endif
469
470#if defined(CONFIG_CPU_SUBTYPE_SH7708)
471static inline int sci_rxd_in(struct uart_port *port)
472{
473 if (port->mapbase == 0xfffffe80)
474 return ctrl_inb(SCSPTR)&0x01 ? 1 : 0; /* SCI */
475 return 1;
476}
e108b2ca
PM		 477#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || \
478 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
479 defined(CONFIG_CPU_SUBTYPE_SH7706)
1da177e4
LT		 480static inline int sci_rxd_in(struct uart_port *port)
481{
482 if (port->mapbase == 0xfffffe80)
483 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
484 if (port->mapbase == 0xa4000150)
485 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
486 if (port->mapbase == 0xa4000140)
487 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
488 return 1;
489}
490#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
491static inline int sci_rxd_in(struct uart_port *port)
492{
493 if (port->mapbase == SCIF0)
494 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
495 if (port->mapbase == SCIF2)
496 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
497 return 1;
498}
9465a54f 499#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
e108b2ca
PM		 500static inline int sci_rxd_in(struct uart_port *port)
501{
9465a54f
NI		 502 return sci_in(port,SCxSR)&0x0010 ? 1 : 0;
503}
504static inline void set_sh771x_scif_pfc(struct uart_port *port)
505{
506 if (port->mapbase == 0xA4400000){
507 ctrl_outw(ctrl_inw(PACR)&0xffc0,PACR);
508 ctrl_outw(ctrl_inw(PBCR)&0x0fff,PBCR);
509 return;
510 }
511 if (port->mapbase == 0xA4410000){
512 ctrl_outw(ctrl_inw(PBCR)&0xf003,PBCR);
513 return;
514 }
e108b2ca 515}
9465a54f 516
1da177e4
LT		 517#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
518 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
519 defined(CONFIG_CPU_SUBTYPE_SH4_202)
520static inline int sci_rxd_in(struct uart_port *port)
521{
522#ifndef SCIF_ONLY
523 if (port->mapbase == 0xffe00000)
524 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
525#endif
526#ifndef SCI_ONLY
527 if (port->mapbase == 0xffe80000)
528 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
529#endif
530 return 1;
531}
532#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
533static inline int sci_rxd_in(struct uart_port *port)
534{
535 if (port->mapbase == 0xfe600000)
536 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
537 if (port->mapbase == 0xfe610000)
538 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
539 if (port->mapbase == 0xfe620000)
540 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
31388750 541 return 1;
1da177e4
LT		 542}
543#elif defined(CONFIG_CPU_SUBTYPE_SH7300)
544static inline int sci_rxd_in(struct uart_port *port)
545{
546 if (port->mapbase == 0xa4430000)
547 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
548 return 1;
549}
550#elif defined(CONFIG_CPU_SUBTYPE_SH73180)
551static inline int sci_rxd_in(struct uart_port *port)
552{
553 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
554}
e108b2ca
PM		 555#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
556static inline int sci_rxd_in(struct uart_port *port)
557{
558 if (port->mapbase == 0xffe00000)
559 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
560 if (port->mapbase == 0xffe10000)
561 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
562 if (port->mapbase == 0xffe20000)
563 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
564 if (port->mapbase == 0xffe30000)
565 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
566 return 1;
567}
41504c39
PM		 568#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
569static inline int sci_rxd_in(struct uart_port *port)
570{
571 if (port->mapbase == 0xffe00000)
572 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
573 return 1;
574}
1da177e4
LT		 575#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
576static inline int sci_rxd_in(struct uart_port *port)
577{
578 if (port->mapbase == 0xffe00000)
579 return ctrl_inw(SCSPTR1)&0x0001 ? 1 : 0; /* SCIF */
580 else
581 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
582
583}
584#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
585static inline int sci_rxd_in(struct uart_port *port)
586{
587 return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */
588}
589#elif defined(__H8300H__) || defined(__H8300S__)
590static inline int sci_rxd_in(struct uart_port *port)
591{
592 int ch = (port->mapbase - SMR0) >> 3;
593 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
594}
b7a76e4b
PM		 595#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
596static inline int sci_rxd_in(struct uart_port *port)
597{
598 if (port->mapbase == 0xff923000)
599 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
600 if (port->mapbase == 0xff924000)
601 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
602 if (port->mapbase == 0xff925000)
603 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
31388750 604 return 1;
b7a76e4b
PM		 605}
606#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
607static inline int sci_rxd_in(struct uart_port *port)
608{
609 if (port->mapbase == 0xffe00000)
610 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
611 if (port->mapbase == 0xffe10000)
612 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
31388750 613 return 1;
b7a76e4b 614}
32351a28
PM		 615#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
616static inline int sci_rxd_in(struct uart_port *port)
617{
618 if (port->mapbase == 0xffea0000)
619 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
620 if (port->mapbase == 0xffeb0000)
621 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
622 if (port->mapbase == 0xffec0000)
623 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
624 if (port->mapbase == 0xffed0000)
625 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
626 if (port->mapbase == 0xffee0000)
627 return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
628 if (port->mapbase == 0xffef0000)
629 return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
630 return 1;
631}
9d4436a6
YS		 632#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
633static inline int sci_rxd_in(struct uart_port *port)
634{
635 if (port->mapbase == 0xfffe8000)
636 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
637 if (port->mapbase == 0xfffe8800)
638 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
639 if (port->mapbase == 0xfffe9000)
640 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
641 if (port->mapbase == 0xfffe9800)
642 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
31388750 643 return 1;
9d4436a6
YS		 644}
645#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
646static inline int sci_rxd_in(struct uart_port *port)
647{
648 if (port->mapbase == 0xf8400000)
649 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
650 if (port->mapbase == 0xf8410000)
651 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
652 if (port->mapbase == 0xf8420000)
653 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
31388750 654 return 1;
9d4436a6 655}
1da177e4
LT		 656#endif
657
658/*
659 * Values for the BitRate Register (SCBRR)
660 *
661 * The values are actually divisors for a frequency which can
662 * be internal to the SH3 (14.7456MHz) or derived from an external
663 * clock source. This driver assumes the internal clock is used;
664 * to support using an external clock source, config options or
665 * possibly command-line options would need to be added.
666 *
667 * Also, to support speeds below 2400 (why?) the lower 2 bits of
668 * the SCSMR register would also need to be set to non-zero values.
669 *
670 * -- Greg Banks 27Feb2000
671 *
672 * Answer: The SCBRR register is only eight bits, and the value in
673 * it gets larger with lower baud rates. At around 2400 (depending on
674 * the peripherial module clock) you run out of bits. However the
675 * lower two bits of SCSMR allow the module clock to be divided down,
676 * scaling the value which is needed in SCBRR.
677 *
678 * -- Stuart Menefy - 23 May 2000
679 *
680 * I meant, why would anyone bother with bitrates below 2400.
681 *
682 * -- Greg Banks - 7Jul2000
683 *
684 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
685 * tape reader as a console!
686 *
687 * -- Mitch Davis - 15 Jul 2000
688 */
689
32351a28
PM		 690#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
691 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
692 defined(CONFIG_CPU_SUBTYPE_SH7785)
b7a76e4b 693#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
1da177e4 694#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
b7a76e4b
PM		 695#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
696#elif defined(__H8300H__) || defined(__H8300S__)
1da177e4 697#define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
b7a76e4b
PM		 698#elif defined(CONFIG_SUPERH64)
699#define SCBRR_VALUE(bps) ((current_cpu_data.module_clock+16*bps)/(32*bps)-1)
700#else /* Generic SH */
701#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
1da177e4 702#endif
Linux 6.x block layer and io_uring tree(s)