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sh: Fix get_user()/put_user() build error.
[linux-block.git] / drivers / serial / sh-sci.h
CommitLineData
1da177e4
LT		 1/* $Id: sh-sci.h,v 1.4 2004/02/19 16:43:56 lethal Exp $
2 *
3 * linux/drivers/serial/sh-sci.h
4 *
5 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
6 * Copyright (C) 1999, 2000 Niibe Yutaka
7 * Copyright (C) 2000 Greg Banks
8 * Copyright (C) 2002, 2003 Paul Mundt
9 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
10 * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
11 * Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
d89ddd1c 12 * Removed SH7300 support (Jul 2007).
3ea6bc3d 13 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Aug 2007).
1da177e4 14 */
1da177e4 15#include <linux/serial_core.h>
e108b2ca 16#include <asm/io.h>
1da177e4 17
1da177e4 18#include <asm/gpio.h>
3ea6bc3d 19
1da177e4
LT		 20#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
21#include <asm/regs306x.h>
22#endif
23#if defined(CONFIG_H8S2678)
24#include <asm/regs267x.h>
25#endif
1da177e4 26
0fbde950
MD		 27#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
28 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
29 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
30 defined(CONFIG_CPU_SUBTYPE_SH7709)
1da177e4
LT		 31# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
32# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
33# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
34# define SCI_AND_SCIF
35#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
36# define SCIF0 0xA4400000
37# define SCIF2 0xA4410000
b7a76e4b
PM		 38# define SCSMR_Ir 0xA44A0000
39# define IRDA_SCIF SCIF0
1da177e4
LT		 40# define SCPCR 0xA4000116
41# define SCPDR 0xA4000136
42
43/* Set the clock source,
44 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
45 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
46 */
47# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
48# define SCIF_ONLY
31a49c4b
YS		 49#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
50 defined(CONFIG_CPU_SUBTYPE_SH7721)
3ea6bc3d
MB		 51# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
52# define SCIF_ONLY
53#define SCIF_ORER 0x0200 /* overrun error bit */
1da177e4 54#elif defined(CONFIG_SH_RTS7751R2D)
1da177e4
LT		 55# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
56# define SCIF_ORER 0x0001 /* overrun error bit */
57# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
58# define SCIF_ONLY
05627486
PM		 59#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
60 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
61 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
62 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
63 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
64 defined(CONFIG_CPU_SUBTYPE_SH7751R)
1da177e4
LT		 65# define SCSPTR1 0xffe0001c /* 8 bit SCI */
66# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
67# define SCIF_ORER 0x0001 /* overrun error bit */
68# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
69 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
70 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
71# define SCI_AND_SCIF
72#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
b7a76e4b
PM		 73# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
74# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
75# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
1da177e4
LT		 76# define SCIF_ORER 0x0001 /* overrun error bit */
77# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
78# define SCIF_ONLY
2b1bd1ac 79#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
e108b2ca 80# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
9465a54f
NI		 81# define SCIF_ORER 0x0001 /* overrun error bit */
82# define PACR 0xa4050100
83# define PBCR 0xa4050102
84# define SCSCR_INIT(port) 0x3B
e108b2ca 85# define SCIF_ONLY
e108b2ca
PM		 86#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
87# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
88# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
89# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
90# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
91# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
92# define SCIF_ONLY
41504c39
PM		 93#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
94# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
95# define SCSPTR0 SCPDR0
96# define SCIF_ORER 0x0001 /* overrun error bit */
97# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
98# define SCIF_ONLY
99# define PORT_PSCR 0xA405011E
1da177e4 100#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
1da177e4
LT		 101# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
102# define SCIF_ORER 0x0001 /* overrun error bit */
103# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
104# define SCIF_ONLY
1da177e4
LT		 105#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
106# include <asm/hardware.h>
107# define SCIF_BASE_ADDR 0x01030000
108# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
109# define SCIF_PTR2_OFFS 0x0000020
110# define SCIF_LSR2_OFFS 0x0000024
1da177e4
LT		 111# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
112# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
f9669187 113# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
1da177e4
LT		 114# define SCIF_ONLY
115#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
1da177e4
LT		 116# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
117# define SCI_ONLY
118# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
119#elif defined(CONFIG_H8S2678)
1da177e4
LT		 120# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
121# define SCI_ONLY
122# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
b7a76e4b
PM		 123#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
124# define SCSPTR0 0xff923020 /* 16 bit SCIF */
125# define SCSPTR1 0xff924020 /* 16 bit SCIF */
126# define SCSPTR2 0xff925020 /* 16 bit SCIF */
127# define SCIF_ORER 0x0001 /* overrun error bit */
128# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
129# define SCIF_ONLY
130#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
131# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
132# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
e108b2ca 133# define SCIF_ORER 0x0001 /* Overrun error bit */
b7a76e4b
PM		 134# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
135# define SCIF_ONLY
32351a28
PM		 136#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
137# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
138# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
139# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
140# define SCSPTR3 0xffed0024 /* 16 bit SCIF */
141# define SCSPTR4 0xffee0024 /* 16 bit SCIF */
142# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
143# define SCIF_OPER 0x0001 /* Overrun error bit */
144# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
145# define SCIF_ONLY
6d01f510 146#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
a8f67f4b
PM		 147 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
148 defined(CONFIG_CPU_SUBTYPE_SH7263)
9d4436a6
YS		 149# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
150# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
151# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
152# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
153# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
154# define SCIF_ONLY
155#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
156# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
157# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
158# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
159# define SCIF_ORER 0x0001 /* overrun error bit */
160# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
161# define SCIF_ONLY
2b1bd1ac
PM		 162#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
163# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
164# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
165# define SCSPTR2 0xffc50020 /* 16 bit SCIF */
166# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
167# define SCIF_ORER 0x0001 /* Overrun error bit */
168# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
169# define SCIF_ONLY
1da177e4
LT		 170#else
171# error CPU subtype not defined
172#endif
173
174/* SCSCR */
175#define SCI_CTRL_FLAGS_TIE 0x80 /* all */
176#define SCI_CTRL_FLAGS_RIE 0x40 /* all */
177#define SCI_CTRL_FLAGS_TE 0x20 /* all */
178#define SCI_CTRL_FLAGS_RE 0x10 /* all */
05627486
PM		 179#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
180 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
181 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
182 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
183 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
184 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
185 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
2b1bd1ac
PM		 186 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
187 defined(CONFIG_CPU_SUBTYPE_SHX3)
1da177e4
LT		 188#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
189#else
190#define SCI_CTRL_FLAGS_REIE 0
191#endif
192/* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
193/* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
194/* SCI_CTRL_FLAGS_CKE1 0x02 * all */
195/* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
196
197/* SCxSR SCI */
198#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
199#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
200#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
201#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
202#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
203#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
204/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
205/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
206
207#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
208
209/* SCxSR SCIF */
210#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
211#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
212#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
213#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
214#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
215#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
216#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
217#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
218
3ea6bc3d 219#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b
YS		 220 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
221 defined(CONFIG_CPU_SUBTYPE_SH7721)
1da177e4
LT		 222#define SCIF_ORER 0x0200
223#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
224#define SCIF_RFDC_MASK 0x007f
225#define SCIF_TXROOM_MAX 64
226#else
227#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
228#define SCIF_RFDC_MASK 0x001f
229#define SCIF_TXROOM_MAX 16
230#endif
231
232#if defined(SCI_ONLY)
233# define SCxSR_TEND(port) SCI_TEND
234# define SCxSR_ERRORS(port) SCI_ERRORS
235# define SCxSR_RDxF(port) SCI_RDRF
236# define SCxSR_TDxE(port) SCI_TDRE
237# define SCxSR_ORER(port) SCI_ORER
238# define SCxSR_FER(port) SCI_FER
239# define SCxSR_PER(port) SCI_PER
240# define SCxSR_BRK(port) 0x00
241# define SCxSR_RDxF_CLEAR(port) 0xbc
242# define SCxSR_ERROR_CLEAR(port) 0xc4
243# define SCxSR_TDxE_CLEAR(port) 0x78
b7a76e4b 244# define SCxSR_BREAK_CLEAR(port) 0xc4
1da177e4
LT		 245#elif defined(SCIF_ONLY)
246# define SCxSR_TEND(port) SCIF_TEND
247# define SCxSR_ERRORS(port) SCIF_ERRORS
248# define SCxSR_RDxF(port) SCIF_RDF
249# define SCxSR_TDxE(port) SCIF_TDFE
d89ddd1c 250#if defined(CONFIG_CPU_SUBTYPE_SH7705)
1da177e4
LT		 251# define SCxSR_ORER(port) SCIF_ORER
252#else
253# define SCxSR_ORER(port) 0x0000
254#endif
255# define SCxSR_FER(port) SCIF_FER
256# define SCxSR_PER(port) SCIF_PER
257# define SCxSR_BRK(port) SCIF_BRK
3ea6bc3d 258#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b
YS		 259 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
260 defined(CONFIG_CPU_SUBTYPE_SH7721)
1da177e4
LT		 261# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc)
262# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73)
263# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf)
264# define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3)
265#else
d89ddd1c 266/* SH7705 can also use this, clearing is same between 7705 and 7709 */
1da177e4
LT		 267# define SCxSR_RDxF_CLEAR(port) 0x00fc
268# define SCxSR_ERROR_CLEAR(port) 0x0073
269# define SCxSR_TDxE_CLEAR(port) 0x00df
b7a76e4b 270# define SCxSR_BREAK_CLEAR(port) 0x00e3
1da177e4
LT		 271#endif
272#else
273# define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
274# define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
275# define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
276# define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
277# define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000)
278# define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
279# define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
280# define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
281# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
282# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
283# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
284# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
285#endif
286
287/* SCFCR */
288#define SCFCR_RFRST 0x0002
289#define SCFCR_TFRST 0x0004
290#define SCFCR_TCRST 0x4000
291#define SCFCR_MCE 0x0008
292
293#define SCI_MAJOR 204
294#define SCI_MINOR_START 8
295
296/* Generic serial flags */
297#define SCI_RX_THROTTLE 0x0000001
298
299#define SCI_MAGIC 0xbabeface
300
301/*
302 * Events are used to schedule things to happen at timer-interrupt
303 * time, instead of at rs interrupt time.
304 */
305#define SCI_EVENT_WRITE_WAKEUP 0
306
1da177e4
LT		 307#define SCI_IN(size, offset) \
308 unsigned int addr = port->mapbase + (offset); \
b7a76e4b 309 if ((size) == 8) { \
1da177e4 310 return ctrl_inb(addr); \
b7a76e4b 311 } else { \
1da177e4
LT		 312 return ctrl_inw(addr); \
313 }
314#define SCI_OUT(size, offset, value) \
315 unsigned int addr = port->mapbase + (offset); \
b7a76e4b 316 if ((size) == 8) { \
1da177e4
LT		 317 ctrl_outb(value, addr); \
318 } else { \
319 ctrl_outw(value, addr); \
320 }
321
322#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
323 static inline unsigned int sci_##name##_in(struct uart_port *port) \
324 { \
b7a76e4b 325 if (port->type == PORT_SCI) { \
1da177e4
LT		 326 SCI_IN(sci_size, sci_offset) \
327 } else { \
b7a76e4b 328 SCI_IN(scif_size, scif_offset); \
1da177e4
LT		 329 } \
330 } \
331 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
332 { \
333 if (port->type == PORT_SCI) { \
334 SCI_OUT(sci_size, sci_offset, value) \
335 } else { \
336 SCI_OUT(scif_size, scif_offset, value); \
337 } \
338 }
339
340#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
341 static inline unsigned int sci_##name##_in(struct uart_port *port) \
342 { \
b7a76e4b 343 SCI_IN(scif_size, scif_offset); \
1da177e4
LT		 344 } \
345 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
346 { \
347 SCI_OUT(scif_size, scif_offset, value); \
348 }
349
350#define CPU_SCI_FNS(name, sci_offset, sci_size) \
351 static inline unsigned int sci_##name##_in(struct uart_port* port) \
352 { \
b7a76e4b 353 SCI_IN(sci_size, sci_offset); \
1da177e4
LT		 354 } \
355 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
356 { \
357 SCI_OUT(sci_size, sci_offset, value); \
358 }
359
360#ifdef CONFIG_CPU_SH3
9465a54f
NI		 361#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
362#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
363 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
364 h8_sci_offset, h8_sci_size) \
365 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
366#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
367 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
3ea6bc3d 368#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b
YS		 369 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
370 defined(CONFIG_CPU_SUBTYPE_SH7721)
1da177e4
LT		 371#define SCIF_FNS(name, scif_offset, scif_size) \
372 CPU_SCIF_FNS(name, scif_offset, scif_size)
373#else
374#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
375 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
376 h8_sci_offset, h8_sci_size) \
377 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
378#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
379 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
380#endif
381#elif defined(__H8300H__) || defined(__H8300S__)
382#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
383 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
384 h8_sci_offset, h8_sci_size) \
385 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
386#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
387#else
388#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
389 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
390 h8_sci_offset, h8_sci_size) \
391 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
392#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
393 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
394#endif
395
3ea6bc3d 396#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b
YS		 397 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
398 defined(CONFIG_CPU_SUBTYPE_SH7721)
9465a54f 399
1da177e4
LT		 400SCIF_FNS(SCSMR, 0x00, 16)
401SCIF_FNS(SCBRR, 0x04, 8)
402SCIF_FNS(SCSCR, 0x08, 16)
403SCIF_FNS(SCTDSR, 0x0c, 8)
404SCIF_FNS(SCFER, 0x10, 16)
405SCIF_FNS(SCxSR, 0x14, 16)
406SCIF_FNS(SCFCR, 0x18, 16)
407SCIF_FNS(SCFDR, 0x1c, 16)
408SCIF_FNS(SCxTDR, 0x20, 8)
409SCIF_FNS(SCxRDR, 0x24, 8)
410SCIF_FNS(SCLSR, 0x24, 16)
411#else
412/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
413/* name off sz off sz off sz off sz off sz*/
414SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
415SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
416SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
417SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
418SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
419SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
420SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
32351a28
PM		 421#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
422 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
423 defined(CONFIG_CPU_SUBTYPE_SH7785)
6fc21b82 424SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
b7a76e4b
PM		 425SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
426SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
427SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
428SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
429#else
1da177e4
LT		 430SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
431SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
432SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
433#endif
b7a76e4b 434#endif
1da177e4
LT		 435#define sci_in(port, reg) sci_##reg##_in(port)
436#define sci_out(port, reg, value) sci_##reg##_out(port, value)
437
438/* H8/300 series SCI pins assignment */
439#if defined(__H8300H__) || defined(__H8300S__)
440static const struct __attribute__((packed)) {
441 int port; /* GPIO port no */
442 unsigned short rx,tx; /* GPIO bit no */
443} h8300_sci_pins[] = {
444#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
445 { /* SCI0 */
446 .port = H8300_GPIO_P9,
447 .rx = H8300_GPIO_B2,
448 .tx = H8300_GPIO_B0,
449 },
450 { /* SCI1 */
451 .port = H8300_GPIO_P9,
452 .rx = H8300_GPIO_B3,
453 .tx = H8300_GPIO_B1,
454 },
455 { /* SCI2 */
456 .port = H8300_GPIO_PB,
457 .rx = H8300_GPIO_B7,
458 .tx = H8300_GPIO_B6,
459 }
460#elif defined(CONFIG_H8S2678)
461 { /* SCI0 */
462 .port = H8300_GPIO_P3,
463 .rx = H8300_GPIO_B2,
464 .tx = H8300_GPIO_B0,
465 },
466 { /* SCI1 */
467 .port = H8300_GPIO_P3,
468 .rx = H8300_GPIO_B3,
469 .tx = H8300_GPIO_B1,
470 },
471 { /* SCI2 */
472 .port = H8300_GPIO_P5,
473 .rx = H8300_GPIO_B1,
474 .tx = H8300_GPIO_B0,
475 }
476#endif
477};
478#endif
479
0fbde950
MD		 480#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
481 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
482 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
483 defined(CONFIG_CPU_SUBTYPE_SH7709)
1da177e4
LT		 484static inline int sci_rxd_in(struct uart_port *port)
485{
486 if (port->mapbase == 0xfffffe80)
487 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
488 if (port->mapbase == 0xa4000150)
489 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
490 if (port->mapbase == 0xa4000140)
491 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
492 return 1;
493}
494#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
495static inline int sci_rxd_in(struct uart_port *port)
496{
497 if (port->mapbase == SCIF0)
498 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
499 if (port->mapbase == SCIF2)
500 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
501 return 1;
502}
9465a54f 503#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
e108b2ca
PM		 504static inline int sci_rxd_in(struct uart_port *port)
505{
9465a54f
NI		 506 return sci_in(port,SCxSR)&0x0010 ? 1 : 0;
507}
508static inline void set_sh771x_scif_pfc(struct uart_port *port)
509{
510 if (port->mapbase == 0xA4400000){
511 ctrl_outw(ctrl_inw(PACR)&0xffc0,PACR);
512 ctrl_outw(ctrl_inw(PBCR)&0x0fff,PBCR);
513 return;
514 }
515 if (port->mapbase == 0xA4410000){
516 ctrl_outw(ctrl_inw(PBCR)&0xf003,PBCR);
517 return;
518 }
e108b2ca 519}
31a49c4b
YS		 520#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
521 defined(CONFIG_CPU_SUBTYPE_SH7721)
3ea6bc3d
MB		 522static inline int sci_rxd_in(struct uart_port *port)
523{
524 if (port->mapbase == 0xa4430000)
525 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
526 else if (port->mapbase == 0xa4438000)
527 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
528 return 1;
529}
05627486
PM		 530#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
531 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
532 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
533 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
534 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
535 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
1da177e4
LT		 536 defined(CONFIG_CPU_SUBTYPE_SH4_202)
537static inline int sci_rxd_in(struct uart_port *port)
538{
539#ifndef SCIF_ONLY
540 if (port->mapbase == 0xffe00000)
541 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
542#endif
543#ifndef SCI_ONLY
544 if (port->mapbase == 0xffe80000)
545 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
546#endif
547 return 1;
548}
549#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
550static inline int sci_rxd_in(struct uart_port *port)
551{
552 if (port->mapbase == 0xfe600000)
553 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
554 if (port->mapbase == 0xfe610000)
555 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
556 if (port->mapbase == 0xfe620000)
557 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
31388750 558 return 1;
1da177e4 559}
e108b2ca
PM		 560#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
561static inline int sci_rxd_in(struct uart_port *port)
562{
563 if (port->mapbase == 0xffe00000)
564 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
565 if (port->mapbase == 0xffe10000)
566 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
567 if (port->mapbase == 0xffe20000)
568 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
569 if (port->mapbase == 0xffe30000)
570 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
571 return 1;
572}
41504c39
PM		 573#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
574static inline int sci_rxd_in(struct uart_port *port)
575{
576 if (port->mapbase == 0xffe00000)
577 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
578 return 1;
579}
1da177e4
LT		 580#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
581static inline int sci_rxd_in(struct uart_port *port)
582{
583 return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */
584}
585#elif defined(__H8300H__) || defined(__H8300S__)
586static inline int sci_rxd_in(struct uart_port *port)
587{
588 int ch = (port->mapbase - SMR0) >> 3;
589 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
590}
b7a76e4b
PM		 591#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
592static inline int sci_rxd_in(struct uart_port *port)
593{
594 if (port->mapbase == 0xff923000)
595 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
596 if (port->mapbase == 0xff924000)
597 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
598 if (port->mapbase == 0xff925000)
599 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
31388750 600 return 1;
b7a76e4b
PM		 601}
602#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
603static inline int sci_rxd_in(struct uart_port *port)
604{
605 if (port->mapbase == 0xffe00000)
606 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
607 if (port->mapbase == 0xffe10000)
608 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
31388750 609 return 1;
b7a76e4b 610}
32351a28
PM		 611#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
612static inline int sci_rxd_in(struct uart_port *port)
613{
614 if (port->mapbase == 0xffea0000)
615 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
616 if (port->mapbase == 0xffeb0000)
617 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
618 if (port->mapbase == 0xffec0000)
619 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
620 if (port->mapbase == 0xffed0000)
621 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
622 if (port->mapbase == 0xffee0000)
623 return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
624 if (port->mapbase == 0xffef0000)
625 return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
626 return 1;
627}
6d01f510 628#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
a8f67f4b
PM		 629 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
630 defined(CONFIG_CPU_SUBTYPE_SH7263)
9d4436a6
YS		 631static inline int sci_rxd_in(struct uart_port *port)
632{
633 if (port->mapbase == 0xfffe8000)
634 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
635 if (port->mapbase == 0xfffe8800)
636 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
637 if (port->mapbase == 0xfffe9000)
638 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
639 if (port->mapbase == 0xfffe9800)
640 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
31388750 641 return 1;
9d4436a6
YS		 642}
643#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
644static inline int sci_rxd_in(struct uart_port *port)
645{
646 if (port->mapbase == 0xf8400000)
647 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
648 if (port->mapbase == 0xf8410000)
649 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
650 if (port->mapbase == 0xf8420000)
651 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
31388750 652 return 1;
9d4436a6 653}
2b1bd1ac
PM		 654#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
655static inline int sci_rxd_in(struct uart_port *port)
656{
657 if (port->mapbase == 0xffc30000)
658 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
659 if (port->mapbase == 0xffc40000)
660 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
661 if (port->mapbase == 0xffc50000)
662 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
663 if (port->mapbase == 0xffc60000)
664 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
1760b7d7 665 return 1;
2b1bd1ac 666}
1da177e4
LT		 667#endif
668
669/*
670 * Values for the BitRate Register (SCBRR)
671 *
672 * The values are actually divisors for a frequency which can
673 * be internal to the SH3 (14.7456MHz) or derived from an external
674 * clock source. This driver assumes the internal clock is used;
675 * to support using an external clock source, config options or
676 * possibly command-line options would need to be added.
677 *
678 * Also, to support speeds below 2400 (why?) the lower 2 bits of
679 * the SCSMR register would also need to be set to non-zero values.
680 *
681 * -- Greg Banks 27Feb2000
682 *
683 * Answer: The SCBRR register is only eight bits, and the value in
684 * it gets larger with lower baud rates. At around 2400 (depending on
685 * the peripherial module clock) you run out of bits. However the
686 * lower two bits of SCSMR allow the module clock to be divided down,
687 * scaling the value which is needed in SCBRR.
688 *
689 * -- Stuart Menefy - 23 May 2000
690 *
691 * I meant, why would anyone bother with bitrates below 2400.
692 *
693 * -- Greg Banks - 7Jul2000
694 *
695 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
696 * tape reader as a console!
697 *
698 * -- Mitch Davis - 15 Jul 2000
699 */
700
d89ddd1c 701#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
32351a28 702 defined(CONFIG_CPU_SUBTYPE_SH7785)
b7a76e4b 703#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
3ea6bc3d 704#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b
YS		 705 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
706 defined(CONFIG_CPU_SUBTYPE_SH7721)
b7a76e4b
PM		 707#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
708#elif defined(__H8300H__) || defined(__H8300S__)
1da177e4 709#define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
b7a76e4b
PM		 710#elif defined(CONFIG_SUPERH64)
711#define SCBRR_VALUE(bps) ((current_cpu_data.module_clock+16*bps)/(32*bps)-1)
712#else /* Generic SH */
713#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
1da177e4 714#endif
Linux 6.x block layer and io_uring tree(s)