projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
tty/serial: lay the foundations for the next set of reworks
[linux-2.6-block.git] / drivers / serial / sh-sci.h
CommitLineData
1da177e4 1#include <linux/serial_core.h>
e108b2ca 2#include <asm/io.h>
1da177e4 3#include <asm/gpio.h>
3ea6bc3d 4
1da177e4
LT		 5#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
6#include <asm/regs306x.h>
7#endif
8#if defined(CONFIG_H8S2678)
9#include <asm/regs267x.h>
10#endif
1da177e4 11
0fbde950
MD		 12#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
13 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
14 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
15 defined(CONFIG_CPU_SUBTYPE_SH7709)
1da177e4
LT		 16# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
17# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
18# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
19# define SCI_AND_SCIF
20#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
21# define SCIF0 0xA4400000
22# define SCIF2 0xA4410000
b7a76e4b
PM		 23# define SCSMR_Ir 0xA44A0000
24# define IRDA_SCIF SCIF0
1da177e4
LT		 25# define SCPCR 0xA4000116
26# define SCPDR 0xA4000136
27
28/* Set the clock source,
29 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
30 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
31 */
32# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
33# define SCIF_ONLY
31a49c4b
YS		 34#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
35 defined(CONFIG_CPU_SUBTYPE_SH7721)
3ea6bc3d
MB		 36# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
37# define SCIF_ONLY
38#define SCIF_ORER 0x0200 /* overrun error bit */
1da177e4 39#elif defined(CONFIG_SH_RTS7751R2D)
1da177e4
LT		 40# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
41# define SCIF_ORER 0x0001 /* overrun error bit */
42# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
43# define SCIF_ONLY
05627486
PM		 44#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
45 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
46 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
47 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
48 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
49 defined(CONFIG_CPU_SUBTYPE_SH7751R)
1da177e4
LT		 50# define SCSPTR1 0xffe0001c /* 8 bit SCI */
51# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
52# define SCIF_ORER 0x0001 /* overrun error bit */
53# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
54 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
55 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
56# define SCI_AND_SCIF
57#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
b7a76e4b
PM		 58# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
59# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
60# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
1da177e4
LT		 61# define SCIF_ORER 0x0001 /* overrun error bit */
62# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
63# define SCIF_ONLY
2b1bd1ac 64#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
e108b2ca 65# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
9465a54f
NI		 66# define SCIF_ORER 0x0001 /* overrun error bit */
67# define PACR 0xa4050100
68# define PBCR 0xa4050102
69# define SCSCR_INIT(port) 0x3B
e108b2ca 70# define SCIF_ONLY
e108b2ca
PM		 71#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
72# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
73# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
74# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
75# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
76# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
77# define SCIF_ONLY
41504c39
PM		 78#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
79# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
80# define SCSPTR0 SCPDR0
81# define SCIF_ORER 0x0001 /* overrun error bit */
82# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
83# define SCIF_ONLY
84# define PORT_PSCR 0xA405011E
9109a30e
MD		 85#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
86# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
87# define SCSPTR0 SCPDR0
88# define SCIF_ORER 0x0001 /* overrun error bit */
89# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
178dd0cd
PM		 90#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
91# define SCSPTR0 0xa4050160
92# define SCSPTR1 0xa405013e
93# define SCSPTR2 0xa4050160
94# define SCSPTR3 0xa405013e
95# define SCSPTR4 0xa4050128
96# define SCSPTR5 0xa4050128
97# define SCIF_ORER 0x0001 /* overrun error bit */
98# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
9109a30e 99# define SCIF_ONLY
1da177e4 100#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
1da177e4
LT		 101# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
102# define SCIF_ORER 0x0001 /* overrun error bit */
103# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
104# define SCIF_ONLY
1da177e4 105#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1da177e4
LT		 106# define SCIF_BASE_ADDR 0x01030000
107# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
108# define SCIF_PTR2_OFFS 0x0000020
109# define SCIF_LSR2_OFFS 0x0000024
1da177e4
LT		 110# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
111# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
f9669187 112# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
1da177e4
LT		 113# define SCIF_ONLY
114#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
1da177e4
LT		 115# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
116# define SCI_ONLY
117# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
118#elif defined(CONFIG_H8S2678)
1da177e4
LT		 119# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
120# define SCI_ONLY
121# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
7d740a06
YS		 122#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
123# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
124# define SCSPTR1 0xffe08024 /* 16 bit SCIF */
125# define SCIF_ORER 0x0001 /* overrun error bit */
126# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
127# define SCIF_ONLY
b7a76e4b
PM		 128#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
129# define SCSPTR0 0xff923020 /* 16 bit SCIF */
130# define SCSPTR1 0xff924020 /* 16 bit SCIF */
131# define SCSPTR2 0xff925020 /* 16 bit SCIF */
132# define SCIF_ORER 0x0001 /* overrun error bit */
133# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
134# define SCIF_ONLY
135#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
136# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
137# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
e108b2ca 138# define SCIF_ORER 0x0001 /* Overrun error bit */
b7a76e4b
PM		 139# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
140# define SCIF_ONLY
32351a28
PM		 141#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
142# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
143# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
144# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
145# define SCSPTR3 0xffed0024 /* 16 bit SCIF */
146# define SCSPTR4 0xffee0024 /* 16 bit SCIF */
147# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
148# define SCIF_OPER 0x0001 /* Overrun error bit */
149# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
150# define SCIF_ONLY
6d01f510 151#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
a8f67f4b
PM		 152 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
153 defined(CONFIG_CPU_SUBTYPE_SH7263)
9d4436a6
YS		 154# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
155# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
156# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
157# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
158# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
159# define SCIF_ONLY
160#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
161# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
162# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
163# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
164# define SCIF_ORER 0x0001 /* overrun error bit */
165# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
166# define SCIF_ONLY
2b1bd1ac
PM		 167#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
168# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
169# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
170# define SCSPTR2 0xffc50020 /* 16 bit SCIF */
171# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
172# define SCIF_ORER 0x0001 /* Overrun error bit */
173# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
174# define SCIF_ONLY
1da177e4
LT		 175#else
176# error CPU subtype not defined
177#endif
178
179/* SCSCR */
180#define SCI_CTRL_FLAGS_TIE 0x80 /* all */
181#define SCI_CTRL_FLAGS_RIE 0x40 /* all */
182#define SCI_CTRL_FLAGS_TE 0x20 /* all */
183#define SCI_CTRL_FLAGS_RE 0x10 /* all */
05627486
PM		 184#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
185 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
186 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
187 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
188 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
189 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
190 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
2b1bd1ac
PM		 191 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
192 defined(CONFIG_CPU_SUBTYPE_SHX3)
1da177e4
LT		 193#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
194#else
195#define SCI_CTRL_FLAGS_REIE 0
196#endif
197/* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
198/* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
199/* SCI_CTRL_FLAGS_CKE1 0x02 * all */
200/* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
201
202/* SCxSR SCI */
203#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
204#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
205#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
206#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
207#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
208#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
209/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
210/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
211
212#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
213
214/* SCxSR SCIF */
215#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
216#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
217#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
218#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
219#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
220#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
221#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
222#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
223
3ea6bc3d 224#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b
YS		 225 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
226 defined(CONFIG_CPU_SUBTYPE_SH7721)
1da177e4
LT		 227#define SCIF_ORER 0x0200
228#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
229#define SCIF_RFDC_MASK 0x007f
230#define SCIF_TXROOM_MAX 64
231#else
232#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
233#define SCIF_RFDC_MASK 0x001f
234#define SCIF_TXROOM_MAX 16
235#endif
236
237#if defined(SCI_ONLY)
238# define SCxSR_TEND(port) SCI_TEND
239# define SCxSR_ERRORS(port) SCI_ERRORS
240# define SCxSR_RDxF(port) SCI_RDRF
241# define SCxSR_TDxE(port) SCI_TDRE
242# define SCxSR_ORER(port) SCI_ORER
243# define SCxSR_FER(port) SCI_FER
244# define SCxSR_PER(port) SCI_PER
245# define SCxSR_BRK(port) 0x00
246# define SCxSR_RDxF_CLEAR(port) 0xbc
247# define SCxSR_ERROR_CLEAR(port) 0xc4
248# define SCxSR_TDxE_CLEAR(port) 0x78
b7a76e4b 249# define SCxSR_BREAK_CLEAR(port) 0xc4
1da177e4
LT		 250#elif defined(SCIF_ONLY)
251# define SCxSR_TEND(port) SCIF_TEND
252# define SCxSR_ERRORS(port) SCIF_ERRORS
253# define SCxSR_RDxF(port) SCIF_RDF
254# define SCxSR_TDxE(port) SCIF_TDFE
d89ddd1c 255#if defined(CONFIG_CPU_SUBTYPE_SH7705)
1da177e4
LT		 256# define SCxSR_ORER(port) SCIF_ORER
257#else
258# define SCxSR_ORER(port) 0x0000
259#endif
260# define SCxSR_FER(port) SCIF_FER
261# define SCxSR_PER(port) SCIF_PER
262# define SCxSR_BRK(port) SCIF_BRK
3ea6bc3d 263#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b
YS		 264 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
265 defined(CONFIG_CPU_SUBTYPE_SH7721)
1da177e4
LT		 266# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc)
267# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73)
268# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf)
269# define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3)
270#else
d89ddd1c 271/* SH7705 can also use this, clearing is same between 7705 and 7709 */
1da177e4
LT		 272# define SCxSR_RDxF_CLEAR(port) 0x00fc
273# define SCxSR_ERROR_CLEAR(port) 0x0073
274# define SCxSR_TDxE_CLEAR(port) 0x00df
b7a76e4b 275# define SCxSR_BREAK_CLEAR(port) 0x00e3
1da177e4
LT		 276#endif
277#else
278# define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
279# define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
280# define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
281# define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
282# define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000)
283# define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
284# define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
285# define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
286# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
287# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
288# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
289# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
290#endif
291
292/* SCFCR */
293#define SCFCR_RFRST 0x0002
294#define SCFCR_TFRST 0x0004
295#define SCFCR_TCRST 0x4000
296#define SCFCR_MCE 0x0008
297
298#define SCI_MAJOR 204
299#define SCI_MINOR_START 8
300
301/* Generic serial flags */
302#define SCI_RX_THROTTLE 0x0000001
303
304#define SCI_MAGIC 0xbabeface
305
306/*
307 * Events are used to schedule things to happen at timer-interrupt
308 * time, instead of at rs interrupt time.
309 */
310#define SCI_EVENT_WRITE_WAKEUP 0
311
1da177e4
LT		 312#define SCI_IN(size, offset) \
313 unsigned int addr = port->mapbase + (offset); \
b7a76e4b 314 if ((size) == 8) { \
1da177e4 315 return ctrl_inb(addr); \
b7a76e4b 316 } else { \
1da177e4
LT		 317 return ctrl_inw(addr); \
318 }
319#define SCI_OUT(size, offset, value) \
320 unsigned int addr = port->mapbase + (offset); \
b7a76e4b 321 if ((size) == 8) { \
1da177e4
LT		 322 ctrl_outb(value, addr); \
323 } else { \
324 ctrl_outw(value, addr); \
325 }
326
327#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
328 static inline unsigned int sci_##name##_in(struct uart_port *port) \
329 { \
b7a76e4b 330 if (port->type == PORT_SCI) { \
1da177e4
LT		 331 SCI_IN(sci_size, sci_offset) \
332 } else { \
b7a76e4b 333 SCI_IN(scif_size, scif_offset); \
1da177e4
LT		 334 } \
335 } \
336 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
337 { \
338 if (port->type == PORT_SCI) { \
339 SCI_OUT(sci_size, sci_offset, value) \
340 } else { \
341 SCI_OUT(scif_size, scif_offset, value); \
342 } \
343 }
344
345#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
346 static inline unsigned int sci_##name##_in(struct uart_port *port) \
347 { \
b7a76e4b 348 SCI_IN(scif_size, scif_offset); \
1da177e4
LT		 349 } \
350 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
351 { \
352 SCI_OUT(scif_size, scif_offset, value); \
353 }
354
355#define CPU_SCI_FNS(name, sci_offset, sci_size) \
356 static inline unsigned int sci_##name##_in(struct uart_port* port) \
357 { \
b7a76e4b 358 SCI_IN(sci_size, sci_offset); \
1da177e4
LT		 359 } \
360 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
361 { \
362 SCI_OUT(sci_size, sci_offset, value); \
363 }
364
365#ifdef CONFIG_CPU_SH3
9465a54f
NI		 366#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
367#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
368 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
369 h8_sci_offset, h8_sci_size) \
370 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
371#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
372 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
3ea6bc3d 373#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b
YS		 374 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
375 defined(CONFIG_CPU_SUBTYPE_SH7721)
1da177e4
LT		 376#define SCIF_FNS(name, scif_offset, scif_size) \
377 CPU_SCIF_FNS(name, scif_offset, scif_size)
378#else
379#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
380 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
381 h8_sci_offset, h8_sci_size) \
382 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
383#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
384 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
385#endif
386#elif defined(__H8300H__) || defined(__H8300S__)
387#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
388 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
389 h8_sci_offset, h8_sci_size) \
390 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
391#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
178dd0cd
PM		 392#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
393 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
394 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
395 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
396 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
1da177e4
LT		 397#else
398#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
399 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
400 h8_sci_offset, h8_sci_size) \
401 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
402#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
403 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
404#endif
405
3ea6bc3d 406#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b
YS		 407 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
408 defined(CONFIG_CPU_SUBTYPE_SH7721)
9465a54f 409
1da177e4
LT		 410SCIF_FNS(SCSMR, 0x00, 16)
411SCIF_FNS(SCBRR, 0x04, 8)
412SCIF_FNS(SCSCR, 0x08, 16)
413SCIF_FNS(SCTDSR, 0x0c, 8)
414SCIF_FNS(SCFER, 0x10, 16)
415SCIF_FNS(SCxSR, 0x14, 16)
416SCIF_FNS(SCFCR, 0x18, 16)
417SCIF_FNS(SCFDR, 0x1c, 16)
418SCIF_FNS(SCxTDR, 0x20, 8)
419SCIF_FNS(SCxRDR, 0x24, 8)
420SCIF_FNS(SCLSR, 0x24, 16)
178dd0cd
PM		 421#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
422SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
423SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
424SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
425SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
426SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
427SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
428SCIF_FNS(SCTDSR, 0x0c, 8)
429SCIF_FNS(SCFER, 0x10, 16)
430SCIF_FNS(SCFCR, 0x18, 16)
431SCIF_FNS(SCFDR, 0x1c, 16)
432SCIF_FNS(SCLSR, 0x24, 16)
1da177e4
LT		 433#else
434/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
435/* name off sz off sz off sz off sz off sz*/
436SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
437SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
438SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
439SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
440SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
441SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
442SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
32351a28 443#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
7d740a06 444 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
32351a28
PM		 445 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
446 defined(CONFIG_CPU_SUBTYPE_SH7785)
6fc21b82 447SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
b7a76e4b
PM		 448SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
449SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
450SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
451SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
452#else
1da177e4
LT		 453SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
454SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
455SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
456#endif
b7a76e4b 457#endif
1da177e4
LT		 458#define sci_in(port, reg) sci_##reg##_in(port)
459#define sci_out(port, reg, value) sci_##reg##_out(port, value)
460
461/* H8/300 series SCI pins assignment */
462#if defined(__H8300H__) || defined(__H8300S__)
463static const struct __attribute__((packed)) {
464 int port; /* GPIO port no */
465 unsigned short rx,tx; /* GPIO bit no */
466} h8300_sci_pins[] = {
467#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
468 { /* SCI0 */
469 .port = H8300_GPIO_P9,
470 .rx = H8300_GPIO_B2,
471 .tx = H8300_GPIO_B0,
472 },
473 { /* SCI1 */
474 .port = H8300_GPIO_P9,
475 .rx = H8300_GPIO_B3,
476 .tx = H8300_GPIO_B1,
477 },
478 { /* SCI2 */
479 .port = H8300_GPIO_PB,
480 .rx = H8300_GPIO_B7,
481 .tx = H8300_GPIO_B6,
482 }
483#elif defined(CONFIG_H8S2678)
484 { /* SCI0 */
485 .port = H8300_GPIO_P3,
486 .rx = H8300_GPIO_B2,
487 .tx = H8300_GPIO_B0,
488 },
489 { /* SCI1 */
490 .port = H8300_GPIO_P3,
491 .rx = H8300_GPIO_B3,
492 .tx = H8300_GPIO_B1,
493 },
494 { /* SCI2 */
495 .port = H8300_GPIO_P5,
496 .rx = H8300_GPIO_B1,
497 .tx = H8300_GPIO_B0,
498 }
499#endif
500};
501#endif
502
0fbde950
MD		 503#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
504 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
505 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
506 defined(CONFIG_CPU_SUBTYPE_SH7709)
1da177e4
LT		 507static inline int sci_rxd_in(struct uart_port *port)
508{
509 if (port->mapbase == 0xfffffe80)
510 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
511 if (port->mapbase == 0xa4000150)
512 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
513 if (port->mapbase == 0xa4000140)
514 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
515 return 1;
516}
517#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
518static inline int sci_rxd_in(struct uart_port *port)
519{
520 if (port->mapbase == SCIF0)
521 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
522 if (port->mapbase == SCIF2)
523 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
524 return 1;
525}
9465a54f 526#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
e108b2ca
PM		 527static inline int sci_rxd_in(struct uart_port *port)
528{
9465a54f
NI		 529 return sci_in(port,SCxSR)&0x0010 ? 1 : 0;
530}
531static inline void set_sh771x_scif_pfc(struct uart_port *port)
532{
533 if (port->mapbase == 0xA4400000){
534 ctrl_outw(ctrl_inw(PACR)&0xffc0,PACR);
535 ctrl_outw(ctrl_inw(PBCR)&0x0fff,PBCR);
536 return;
537 }
538 if (port->mapbase == 0xA4410000){
539 ctrl_outw(ctrl_inw(PBCR)&0xf003,PBCR);
540 return;
541 }
e108b2ca 542}
31a49c4b
YS		 543#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
544 defined(CONFIG_CPU_SUBTYPE_SH7721)
3ea6bc3d
MB		 545static inline int sci_rxd_in(struct uart_port *port)
546{
547 if (port->mapbase == 0xa4430000)
548 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
549 else if (port->mapbase == 0xa4438000)
550 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
551 return 1;
552}
05627486
PM		 553#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
554 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
555 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
556 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
557 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
558 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
1da177e4
LT		 559 defined(CONFIG_CPU_SUBTYPE_SH4_202)
560static inline int sci_rxd_in(struct uart_port *port)
561{
562#ifndef SCIF_ONLY
563 if (port->mapbase == 0xffe00000)
564 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
565#endif
566#ifndef SCI_ONLY
567 if (port->mapbase == 0xffe80000)
568 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
569#endif
570 return 1;
571}
572#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
573static inline int sci_rxd_in(struct uart_port *port)
574{
575 if (port->mapbase == 0xfe600000)
576 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
577 if (port->mapbase == 0xfe610000)
578 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
579 if (port->mapbase == 0xfe620000)
580 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
31388750 581 return 1;
1da177e4 582}
e108b2ca
PM		 583#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
584static inline int sci_rxd_in(struct uart_port *port)
585{
586 if (port->mapbase == 0xffe00000)
587 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
588 if (port->mapbase == 0xffe10000)
589 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
590 if (port->mapbase == 0xffe20000)
591 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
592 if (port->mapbase == 0xffe30000)
593 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
594 return 1;
595}
9109a30e 596#elif defined(CONFIG_CPU_SUBTYPE_SH7722) || defined(CONFIG_CPU_SUBTYPE_SH7366)
41504c39
PM		 597static inline int sci_rxd_in(struct uart_port *port)
598{
599 if (port->mapbase == 0xffe00000)
600 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
601 return 1;
602}
178dd0cd
PM		 603#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
604static inline int sci_rxd_in(struct uart_port *port)
605{
606 if (port->mapbase == 0xffe00000)
607 return ctrl_inb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */
608 if (port->mapbase == 0xffe10000)
609 return ctrl_inb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */
610 if (port->mapbase == 0xffe20000)
611 return ctrl_inb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */
612 if (port->mapbase == 0xa4e30000)
613 return ctrl_inb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */
614 if (port->mapbase == 0xa4e40000)
615 return ctrl_inb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */
616 if (port->mapbase == 0xa4e50000)
617 return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */
618 return 1;
619}
1da177e4
LT		 620#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
621static inline int sci_rxd_in(struct uart_port *port)
622{
623 return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */
624}
625#elif defined(__H8300H__) || defined(__H8300S__)
626static inline int sci_rxd_in(struct uart_port *port)
627{
628 int ch = (port->mapbase - SMR0) >> 3;
629 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
630}
7d740a06
YS		 631#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
632static inline int sci_rxd_in(struct uart_port *port)
633{
634 if (port->mapbase == 0xffe00000)
635 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
636 if (port->mapbase == 0xffe08000)
637 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
638 return 1;
639}
b7a76e4b
PM		 640#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
641static inline int sci_rxd_in(struct uart_port *port)
642{
643 if (port->mapbase == 0xff923000)
644 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
645 if (port->mapbase == 0xff924000)
646 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
647 if (port->mapbase == 0xff925000)
648 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
31388750 649 return 1;
b7a76e4b
PM		 650}
651#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
652static inline int sci_rxd_in(struct uart_port *port)
653{
654 if (port->mapbase == 0xffe00000)
655 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
656 if (port->mapbase == 0xffe10000)
657 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
31388750 658 return 1;
b7a76e4b 659}
32351a28
PM		 660#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
661static inline int sci_rxd_in(struct uart_port *port)
662{
663 if (port->mapbase == 0xffea0000)
664 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
665 if (port->mapbase == 0xffeb0000)
666 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
667 if (port->mapbase == 0xffec0000)
668 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
669 if (port->mapbase == 0xffed0000)
670 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
671 if (port->mapbase == 0xffee0000)
672 return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
673 if (port->mapbase == 0xffef0000)
674 return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
675 return 1;
676}
6d01f510 677#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
a8f67f4b
PM		 678 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
679 defined(CONFIG_CPU_SUBTYPE_SH7263)
9d4436a6
YS		 680static inline int sci_rxd_in(struct uart_port *port)
681{
682 if (port->mapbase == 0xfffe8000)
683 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
684 if (port->mapbase == 0xfffe8800)
685 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
686 if (port->mapbase == 0xfffe9000)
687 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
688 if (port->mapbase == 0xfffe9800)
689 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
31388750 690 return 1;
9d4436a6
YS		 691}
692#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
693static inline int sci_rxd_in(struct uart_port *port)
694{
695 if (port->mapbase == 0xf8400000)
696 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
697 if (port->mapbase == 0xf8410000)
698 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
699 if (port->mapbase == 0xf8420000)
700 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
31388750 701 return 1;
9d4436a6 702}
2b1bd1ac
PM		 703#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
704static inline int sci_rxd_in(struct uart_port *port)
705{
706 if (port->mapbase == 0xffc30000)
707 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
708 if (port->mapbase == 0xffc40000)
709 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
710 if (port->mapbase == 0xffc50000)
711 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
712 if (port->mapbase == 0xffc60000)
713 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
1760b7d7 714 return 1;
2b1bd1ac 715}
1da177e4
LT		 716#endif
717
718/*
719 * Values for the BitRate Register (SCBRR)
720 *
721 * The values are actually divisors for a frequency which can
722 * be internal to the SH3 (14.7456MHz) or derived from an external
723 * clock source. This driver assumes the internal clock is used;
724 * to support using an external clock source, config options or
725 * possibly command-line options would need to be added.
726 *
727 * Also, to support speeds below 2400 (why?) the lower 2 bits of
728 * the SCSMR register would also need to be set to non-zero values.
729 *
730 * -- Greg Banks 27Feb2000
731 *
732 * Answer: The SCBRR register is only eight bits, and the value in
733 * it gets larger with lower baud rates. At around 2400 (depending on
734 * the peripherial module clock) you run out of bits. However the
735 * lower two bits of SCSMR allow the module clock to be divided down,
736 * scaling the value which is needed in SCBRR.
737 *
738 * -- Stuart Menefy - 23 May 2000
739 *
740 * I meant, why would anyone bother with bitrates below 2400.
741 *
742 * -- Greg Banks - 7Jul2000
743 *
744 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
745 * tape reader as a console!
746 *
747 * -- Mitch Davis - 15 Jul 2000
748 */
749
7d740a06
YS		 750#if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
751 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
32351a28 752 defined(CONFIG_CPU_SUBTYPE_SH7785)
b7a76e4b 753#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
3ea6bc3d 754#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b
YS		 755 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
756 defined(CONFIG_CPU_SUBTYPE_SH7721)
b7a76e4b 757#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
178dd0cd
PM		 758#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
759#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(16*bps)-1)
b7a76e4b 760#elif defined(__H8300H__) || defined(__H8300S__)
1da177e4 761#define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
b7a76e4b
PM		 762#elif defined(CONFIG_SUPERH64)
763#define SCBRR_VALUE(bps) ((current_cpu_data.module_clock+16*bps)/(32*bps)-1)
764#else /* Generic SH */
765#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
1da177e4 766#endif
Linux 6.x block layer and io_uring tree(s)