Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/serial/sh-sci.c | |
3 | * | |
4 | * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) | |
5 | * | |
7ff731ae | 6 | * Copyright (C) 2002 - 2008 Paul Mundt |
3ea6bc3d | 7 | * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). |
1da177e4 LT |
8 | * |
9 | * based off of the old drivers/char/sh-sci.c by: | |
10 | * | |
11 | * Copyright (C) 1999, 2000 Niibe Yutaka | |
12 | * Copyright (C) 2000 Sugioka Toshinobu | |
13 | * Modified to support multiple serial ports. Stuart Menefy (May 2000). | |
14 | * Modified to support SecureEdge. David McCullough (2002) | |
15 | * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). | |
d89ddd1c | 16 | * Removed SH7300 support (Jul 2007). |
1da177e4 LT |
17 | * |
18 | * This file is subject to the terms and conditions of the GNU General Public | |
19 | * License. See the file "COPYING" in the main directory of this archive | |
20 | * for more details. | |
21 | */ | |
0b3d4ef6 PM |
22 | #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
23 | #define SUPPORT_SYSRQ | |
24 | #endif | |
1da177e4 LT |
25 | |
26 | #undef DEBUG | |
27 | ||
1da177e4 LT |
28 | #include <linux/module.h> |
29 | #include <linux/errno.h> | |
1da177e4 LT |
30 | #include <linux/timer.h> |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/tty.h> | |
33 | #include <linux/tty_flip.h> | |
34 | #include <linux/serial.h> | |
35 | #include <linux/major.h> | |
36 | #include <linux/string.h> | |
37 | #include <linux/sysrq.h> | |
1da177e4 LT |
38 | #include <linux/ioport.h> |
39 | #include <linux/mm.h> | |
1da177e4 LT |
40 | #include <linux/init.h> |
41 | #include <linux/delay.h> | |
42 | #include <linux/console.h> | |
e108b2ca | 43 | #include <linux/platform_device.h> |
96de1a8f | 44 | #include <linux/serial_sci.h> |
1da177e4 LT |
45 | #include <linux/notifier.h> |
46 | #include <linux/cpufreq.h> | |
85f094ec | 47 | #include <linux/clk.h> |
fa5da2f7 | 48 | #include <linux/ctype.h> |
7ff731ae | 49 | #include <linux/err.h> |
85f094ec PM |
50 | |
51 | #ifdef CONFIG_SUPERH | |
b7a76e4b | 52 | #include <asm/clock.h> |
1da177e4 LT |
53 | #include <asm/sh_bios.h> |
54 | #endif | |
55 | ||
1da177e4 LT |
56 | #include "sh-sci.h" |
57 | ||
e108b2ca PM |
58 | struct sci_port { |
59 | struct uart_port port; | |
60 | ||
61 | /* Port type */ | |
62 | unsigned int type; | |
63 | ||
64 | /* Port IRQs: ERI, RXI, TXI, BRI (optional) */ | |
32351a28 | 65 | unsigned int irqs[SCIx_NR_IRQS]; |
e108b2ca PM |
66 | |
67 | /* Port pin configuration */ | |
68 | void (*init_pins)(struct uart_port *port, | |
69 | unsigned int cflag); | |
1da177e4 | 70 | |
e108b2ca PM |
71 | /* Port enable callback */ |
72 | void (*enable)(struct uart_port *port); | |
73 | ||
74 | /* Port disable callback */ | |
75 | void (*disable)(struct uart_port *port); | |
76 | ||
77 | /* Break timer */ | |
78 | struct timer_list break_timer; | |
79 | int break_flag; | |
1534a3b3 | 80 | |
a2159b52 | 81 | #ifdef CONFIG_HAVE_CLK |
1534a3b3 | 82 | /* Port clock */ |
83 | struct clk *clk; | |
005a336e | 84 | #endif |
e108b2ca PM |
85 | }; |
86 | ||
1da177e4 | 87 | #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE |
e108b2ca PM |
88 | static struct sci_port *serial_console_port; |
89 | #endif | |
1da177e4 LT |
90 | |
91 | /* Function prototypes */ | |
b129a8cc | 92 | static void sci_stop_tx(struct uart_port *port); |
1da177e4 | 93 | |
e108b2ca | 94 | #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS |
b7a76e4b | 95 | |
e108b2ca PM |
96 | static struct sci_port sci_ports[SCI_NPORTS]; |
97 | static struct uart_driver sci_uart_driver; | |
1da177e4 | 98 | |
e7c98dc7 MT |
99 | static inline struct sci_port * |
100 | to_sci_port(struct uart_port *uart) | |
101 | { | |
102 | return container_of(uart, struct sci_port, port); | |
103 | } | |
104 | ||
07d2a1a1 | 105 | #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) |
e108b2ca PM |
106 | static inline void handle_error(struct uart_port *port) |
107 | { | |
108 | /* Clear error flags */ | |
1da177e4 LT |
109 | sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); |
110 | } | |
111 | ||
07d2a1a1 | 112 | static int sci_poll_get_char(struct uart_port *port) |
1da177e4 | 113 | { |
1da177e4 LT |
114 | unsigned short status; |
115 | int c; | |
116 | ||
e108b2ca | 117 | do { |
1da177e4 LT |
118 | status = sci_in(port, SCxSR); |
119 | if (status & SCxSR_ERRORS(port)) { | |
120 | handle_error(port); | |
121 | continue; | |
122 | } | |
123 | } while (!(status & SCxSR_RDxF(port))); | |
07d2a1a1 | 124 | |
1da177e4 | 125 | c = sci_in(port, SCxRDR); |
07d2a1a1 | 126 | |
e7c98dc7 MT |
127 | /* Dummy read */ |
128 | sci_in(port, SCxSR); | |
1da177e4 | 129 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); |
1da177e4 LT |
130 | |
131 | return c; | |
132 | } | |
1da177e4 | 133 | |
07d2a1a1 | 134 | static void sci_poll_put_char(struct uart_port *port, unsigned char c) |
1da177e4 | 135 | { |
1da177e4 LT |
136 | unsigned short status; |
137 | ||
1da177e4 LT |
138 | do { |
139 | status = sci_in(port, SCxSR); | |
140 | } while (!(status & SCxSR_TDxE(port))); | |
141 | ||
1da177e4 LT |
142 | sci_in(port, SCxSR); /* Dummy read */ |
143 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); | |
272966c0 | 144 | sci_out(port, SCxTDR, c); |
1da177e4 | 145 | } |
07d2a1a1 | 146 | #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */ |
1da177e4 LT |
147 | |
148 | #if defined(__H8300S__) | |
149 | enum { sci_disable, sci_enable }; | |
150 | ||
e7c98dc7 | 151 | static void h8300_sci_config(struct uart_port *port, unsigned int ctrl) |
1da177e4 | 152 | { |
e7c98dc7 | 153 | volatile unsigned char *mstpcrl = (volatile unsigned char *)MSTPCRL; |
1da177e4 LT |
154 | int ch = (port->mapbase - SMR0) >> 3; |
155 | unsigned char mask = 1 << (ch+1); | |
156 | ||
e7c98dc7 | 157 | if (ctrl == sci_disable) |
1da177e4 | 158 | *mstpcrl |= mask; |
e7c98dc7 | 159 | else |
1da177e4 | 160 | *mstpcrl &= ~mask; |
1da177e4 | 161 | } |
e108b2ca PM |
162 | |
163 | static inline void h8300_sci_enable(struct uart_port *port) | |
164 | { | |
165 | h8300_sci_config(port, sci_enable); | |
166 | } | |
167 | ||
168 | static inline void h8300_sci_disable(struct uart_port *port) | |
169 | { | |
170 | h8300_sci_config(port, sci_disable); | |
171 | } | |
1da177e4 LT |
172 | #endif |
173 | ||
15c73aaa | 174 | #if defined(__H8300H__) || defined(__H8300S__) |
e7c98dc7 | 175 | static void sci_init_pins_sci(struct uart_port *port, unsigned int cflag) |
1da177e4 LT |
176 | { |
177 | int ch = (port->mapbase - SMR0) >> 3; | |
178 | ||
179 | /* set DDR regs */ | |
e108b2ca PM |
180 | H8300_GPIO_DDR(h8300_sci_pins[ch].port, |
181 | h8300_sci_pins[ch].rx, | |
182 | H8300_GPIO_INPUT); | |
183 | H8300_GPIO_DDR(h8300_sci_pins[ch].port, | |
184 | h8300_sci_pins[ch].tx, | |
185 | H8300_GPIO_OUTPUT); | |
186 | ||
1da177e4 LT |
187 | /* tx mark output*/ |
188 | H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx; | |
189 | } | |
e108b2ca PM |
190 | #else |
191 | #define sci_init_pins_sci NULL | |
192 | #endif | |
193 | ||
194 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) | |
195 | static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag) | |
196 | { | |
197 | unsigned int fcr_val = 0; | |
198 | ||
199 | if (cflag & CRTSCTS) | |
200 | fcr_val |= SCFCR_MCE; | |
201 | ||
202 | sci_out(port, SCFCR, fcr_val); | |
203 | } | |
204 | #else | |
205 | #define sci_init_pins_irda NULL | |
1da177e4 | 206 | #endif |
e108b2ca | 207 | |
d89ddd1c | 208 | #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
e7c98dc7 | 209 | static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) |
9465a54f NI |
210 | { |
211 | unsigned int fcr_val = 0; | |
212 | ||
213 | set_sh771x_scif_pfc(port); | |
e7c98dc7 | 214 | if (cflag & CRTSCTS) |
9465a54f | 215 | fcr_val |= SCFCR_MCE; |
9465a54f NI |
216 | sci_out(port, SCFCR, fcr_val); |
217 | } | |
31a49c4b | 218 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721) |
3ea6bc3d MB |
219 | static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) |
220 | { | |
221 | unsigned int fcr_val = 0; | |
222 | unsigned short data; | |
223 | ||
224 | if (cflag & CRTSCTS) { | |
225 | /* enable RTS/CTS */ | |
226 | if (port->mapbase == 0xa4430000) { /* SCIF0 */ | |
227 | /* Clear PTCR bit 9-2; enable all scif pins but sck */ | |
228 | data = ctrl_inw(PORT_PTCR); | |
229 | ctrl_outw((data & 0xfc03), PORT_PTCR); | |
230 | } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ | |
231 | /* Clear PVCR bit 9-2 */ | |
232 | data = ctrl_inw(PORT_PVCR); | |
233 | ctrl_outw((data & 0xfc03), PORT_PVCR); | |
234 | } | |
235 | fcr_val |= SCFCR_MCE; | |
236 | } else { | |
237 | if (port->mapbase == 0xa4430000) { /* SCIF0 */ | |
238 | /* Clear PTCR bit 5-2; enable only tx and rx */ | |
239 | data = ctrl_inw(PORT_PTCR); | |
240 | ctrl_outw((data & 0xffc3), PORT_PTCR); | |
241 | } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ | |
242 | /* Clear PVCR bit 5-2 */ | |
243 | data = ctrl_inw(PORT_PVCR); | |
244 | ctrl_outw((data & 0xffc3), PORT_PVCR); | |
245 | } | |
246 | } | |
247 | sci_out(port, SCFCR, fcr_val); | |
248 | } | |
b7a76e4b | 249 | #elif defined(CONFIG_CPU_SH3) |
e108b2ca | 250 | /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */ |
1da177e4 LT |
251 | static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) |
252 | { | |
253 | unsigned int fcr_val = 0; | |
b7a76e4b PM |
254 | unsigned short data; |
255 | ||
256 | /* We need to set SCPCR to enable RTS/CTS */ | |
257 | data = ctrl_inw(SCPCR); | |
258 | /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/ | |
259 | ctrl_outw(data & 0x0fcf, SCPCR); | |
1da177e4 | 260 | |
1da177e4 LT |
261 | if (cflag & CRTSCTS) |
262 | fcr_val |= SCFCR_MCE; | |
263 | else { | |
1da177e4 LT |
264 | /* We need to set SCPCR to enable RTS/CTS */ |
265 | data = ctrl_inw(SCPCR); | |
266 | /* Clear out SCP7MD1,0, SCP4MD1,0, | |
267 | Set SCP6MD1,0 = {01} (output) */ | |
b7a76e4b | 268 | ctrl_outw((data & 0x0fcf) | 0x1000, SCPCR); |
1da177e4 LT |
269 | |
270 | data = ctrl_inb(SCPDR); | |
271 | /* Set /RTS2 (bit6) = 0 */ | |
b7a76e4b | 272 | ctrl_outb(data & 0xbf, SCPDR); |
1da177e4 | 273 | } |
b7a76e4b | 274 | |
1da177e4 LT |
275 | sci_out(port, SCFCR, fcr_val); |
276 | } | |
41504c39 PM |
277 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) |
278 | static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) | |
279 | { | |
280 | unsigned int fcr_val = 0; | |
346b7463 | 281 | unsigned short data; |
41504c39 | 282 | |
346b7463 MD |
283 | if (port->mapbase == 0xffe00000) { |
284 | data = ctrl_inw(PSCR); | |
285 | data &= ~0x03cf; | |
286 | if (cflag & CRTSCTS) | |
287 | fcr_val |= SCFCR_MCE; | |
288 | else | |
289 | data |= 0x0340; | |
41504c39 | 290 | |
346b7463 | 291 | ctrl_outw(data, PSCR); |
41504c39 | 292 | } |
346b7463 | 293 | /* SCIF1 and SCIF2 should be setup by board code */ |
41504c39 PM |
294 | |
295 | sci_out(port, SCFCR, fcr_val); | |
296 | } | |
178dd0cd PM |
297 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) |
298 | static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) | |
299 | { | |
300 | /* Nothing to do here.. */ | |
301 | sci_out(port, SCFCR, 0); | |
302 | } | |
1da177e4 | 303 | #else |
1da177e4 LT |
304 | /* For SH7750 */ |
305 | static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) | |
306 | { | |
307 | unsigned int fcr_val = 0; | |
308 | ||
309 | if (cflag & CRTSCTS) { | |
310 | fcr_val |= SCFCR_MCE; | |
311 | } else { | |
9109a30e | 312 | #if defined(CONFIG_CPU_SUBTYPE_SH7343) || defined(CONFIG_CPU_SUBTYPE_SH7366) |
e108b2ca | 313 | /* Nothing */ |
7d740a06 YS |
314 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ |
315 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | |
2b1bd1ac PM |
316 | defined(CONFIG_CPU_SUBTYPE_SH7785) || \ |
317 | defined(CONFIG_CPU_SUBTYPE_SHX3) | |
b7a76e4b PM |
318 | ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */ |
319 | #else | |
1da177e4 | 320 | ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */ |
b7a76e4b | 321 | #endif |
1da177e4 LT |
322 | } |
323 | sci_out(port, SCFCR, fcr_val); | |
324 | } | |
e108b2ca PM |
325 | #endif |
326 | ||
32351a28 PM |
327 | #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \ |
328 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | |
329 | defined(CONFIG_CPU_SUBTYPE_SH7785) | |
e108b2ca PM |
330 | static inline int scif_txroom(struct uart_port *port) |
331 | { | |
cae167d3 | 332 | return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff); |
e108b2ca PM |
333 | } |
334 | ||
335 | static inline int scif_rxroom(struct uart_port *port) | |
336 | { | |
cae167d3 | 337 | return sci_in(port, SCRFDR) & 0xff; |
e108b2ca | 338 | } |
c63847a3 NI |
339 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) |
340 | static inline int scif_txroom(struct uart_port *port) | |
341 | { | |
e7c98dc7 MT |
342 | if ((port->mapbase == 0xffe00000) || |
343 | (port->mapbase == 0xffe08000)) { | |
344 | /* SCIF0/1*/ | |
c63847a3 | 345 | return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff); |
e7c98dc7 MT |
346 | } else { |
347 | /* SCIF2 */ | |
c63847a3 | 348 | return SCIF2_TXROOM_MAX - (sci_in(port, SCFDR) >> 8); |
e7c98dc7 | 349 | } |
c63847a3 NI |
350 | } |
351 | ||
352 | static inline int scif_rxroom(struct uart_port *port) | |
353 | { | |
e7c98dc7 MT |
354 | if ((port->mapbase == 0xffe00000) || |
355 | (port->mapbase == 0xffe08000)) { | |
356 | /* SCIF0/1*/ | |
c63847a3 | 357 | return sci_in(port, SCRFDR) & 0xff; |
e7c98dc7 MT |
358 | } else { |
359 | /* SCIF2 */ | |
c63847a3 | 360 | return sci_in(port, SCFDR) & SCIF2_RFDC_MASK; |
e7c98dc7 | 361 | } |
c63847a3 | 362 | } |
e108b2ca PM |
363 | #else |
364 | static inline int scif_txroom(struct uart_port *port) | |
365 | { | |
366 | return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8); | |
367 | } | |
1da177e4 | 368 | |
e108b2ca PM |
369 | static inline int scif_rxroom(struct uart_port *port) |
370 | { | |
371 | return sci_in(port, SCFDR) & SCIF_RFDC_MASK; | |
372 | } | |
1da177e4 | 373 | #endif |
1da177e4 | 374 | |
e108b2ca PM |
375 | static inline int sci_txroom(struct uart_port *port) |
376 | { | |
e7c98dc7 | 377 | return (sci_in(port, SCxSR) & SCI_TDRE) != 0; |
e108b2ca PM |
378 | } |
379 | ||
380 | static inline int sci_rxroom(struct uart_port *port) | |
381 | { | |
e7c98dc7 | 382 | return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; |
e108b2ca PM |
383 | } |
384 | ||
1da177e4 LT |
385 | /* ********************************************************************** * |
386 | * the interrupt related routines * | |
387 | * ********************************************************************** */ | |
388 | ||
389 | static void sci_transmit_chars(struct uart_port *port) | |
390 | { | |
391 | struct circ_buf *xmit = &port->info->xmit; | |
392 | unsigned int stopped = uart_tx_stopped(port); | |
1da177e4 LT |
393 | unsigned short status; |
394 | unsigned short ctrl; | |
e108b2ca | 395 | int count; |
1da177e4 LT |
396 | |
397 | status = sci_in(port, SCxSR); | |
398 | if (!(status & SCxSR_TDxE(port))) { | |
1da177e4 | 399 | ctrl = sci_in(port, SCSCR); |
e7c98dc7 | 400 | if (uart_circ_empty(xmit)) |
1da177e4 | 401 | ctrl &= ~SCI_CTRL_FLAGS_TIE; |
e7c98dc7 | 402 | else |
1da177e4 | 403 | ctrl |= SCI_CTRL_FLAGS_TIE; |
1da177e4 | 404 | sci_out(port, SCSCR, ctrl); |
1da177e4 LT |
405 | return; |
406 | } | |
407 | ||
1a22f08d | 408 | if (port->type == PORT_SCI) |
e108b2ca | 409 | count = sci_txroom(port); |
1a22f08d YS |
410 | else |
411 | count = scif_txroom(port); | |
1da177e4 LT |
412 | |
413 | do { | |
414 | unsigned char c; | |
415 | ||
416 | if (port->x_char) { | |
417 | c = port->x_char; | |
418 | port->x_char = 0; | |
419 | } else if (!uart_circ_empty(xmit) && !stopped) { | |
420 | c = xmit->buf[xmit->tail]; | |
421 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
422 | } else { | |
423 | break; | |
424 | } | |
425 | ||
426 | sci_out(port, SCxTDR, c); | |
427 | ||
428 | port->icount.tx++; | |
429 | } while (--count > 0); | |
430 | ||
431 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); | |
432 | ||
433 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
434 | uart_write_wakeup(port); | |
435 | if (uart_circ_empty(xmit)) { | |
b129a8cc | 436 | sci_stop_tx(port); |
1da177e4 | 437 | } else { |
1da177e4 LT |
438 | ctrl = sci_in(port, SCSCR); |
439 | ||
1a22f08d | 440 | if (port->type != PORT_SCI) { |
1da177e4 LT |
441 | sci_in(port, SCxSR); /* Dummy read */ |
442 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); | |
443 | } | |
1da177e4 LT |
444 | |
445 | ctrl |= SCI_CTRL_FLAGS_TIE; | |
446 | sci_out(port, SCSCR, ctrl); | |
1da177e4 LT |
447 | } |
448 | } | |
449 | ||
450 | /* On SH3, SCIF may read end-of-break as a space->mark char */ | |
e7c98dc7 | 451 | #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) |
1da177e4 | 452 | |
7d12e780 | 453 | static inline void sci_receive_chars(struct uart_port *port) |
1da177e4 | 454 | { |
e7c98dc7 | 455 | struct sci_port *sci_port = to_sci_port(port); |
a88487c7 | 456 | struct tty_struct *tty = port->info->port.tty; |
1da177e4 LT |
457 | int i, count, copied = 0; |
458 | unsigned short status; | |
33f0f88f | 459 | unsigned char flag; |
1da177e4 LT |
460 | |
461 | status = sci_in(port, SCxSR); | |
462 | if (!(status & SCxSR_RDxF(port))) | |
463 | return; | |
464 | ||
465 | while (1) { | |
1a22f08d | 466 | if (port->type == PORT_SCI) |
e108b2ca | 467 | count = sci_rxroom(port); |
1a22f08d YS |
468 | else |
469 | count = scif_rxroom(port); | |
1da177e4 LT |
470 | |
471 | /* Don't copy more bytes than there is room for in the buffer */ | |
33f0f88f | 472 | count = tty_buffer_request_room(tty, count); |
1da177e4 LT |
473 | |
474 | /* If for any reason we can't copy more data, we're done! */ | |
475 | if (count == 0) | |
476 | break; | |
477 | ||
478 | if (port->type == PORT_SCI) { | |
479 | char c = sci_in(port, SCxRDR); | |
e7c98dc7 MT |
480 | if (uart_handle_sysrq_char(port, c) || |
481 | sci_port->break_flag) | |
1da177e4 | 482 | count = 0; |
e7c98dc7 | 483 | else |
e108b2ca | 484 | tty_insert_flip_char(tty, c, TTY_NORMAL); |
1da177e4 | 485 | } else { |
e7c98dc7 | 486 | for (i = 0; i < count; i++) { |
1da177e4 LT |
487 | char c = sci_in(port, SCxRDR); |
488 | status = sci_in(port, SCxSR); | |
489 | #if defined(CONFIG_CPU_SH3) | |
490 | /* Skip "chars" during break */ | |
e108b2ca | 491 | if (sci_port->break_flag) { |
1da177e4 LT |
492 | if ((c == 0) && |
493 | (status & SCxSR_FER(port))) { | |
494 | count--; i--; | |
495 | continue; | |
496 | } | |
e108b2ca | 497 | |
1da177e4 | 498 | /* Nonzero => end-of-break */ |
762c69e3 | 499 | dev_dbg(port->dev, "debounce<%02x>\n", c); |
e108b2ca PM |
500 | sci_port->break_flag = 0; |
501 | ||
1da177e4 LT |
502 | if (STEPFN(c)) { |
503 | count--; i--; | |
504 | continue; | |
505 | } | |
506 | } | |
507 | #endif /* CONFIG_CPU_SH3 */ | |
7d12e780 | 508 | if (uart_handle_sysrq_char(port, c)) { |
1da177e4 LT |
509 | count--; i--; |
510 | continue; | |
511 | } | |
512 | ||
513 | /* Store data and status */ | |
1da177e4 | 514 | if (status&SCxSR_FER(port)) { |
33f0f88f | 515 | flag = TTY_FRAME; |
762c69e3 | 516 | dev_notice(port->dev, "frame error\n"); |
1da177e4 | 517 | } else if (status&SCxSR_PER(port)) { |
33f0f88f | 518 | flag = TTY_PARITY; |
762c69e3 | 519 | dev_notice(port->dev, "parity error\n"); |
33f0f88f AC |
520 | } else |
521 | flag = TTY_NORMAL; | |
762c69e3 | 522 | |
33f0f88f | 523 | tty_insert_flip_char(tty, c, flag); |
1da177e4 LT |
524 | } |
525 | } | |
526 | ||
527 | sci_in(port, SCxSR); /* dummy read */ | |
528 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
529 | ||
1da177e4 LT |
530 | copied += count; |
531 | port->icount.rx += count; | |
532 | } | |
533 | ||
534 | if (copied) { | |
535 | /* Tell the rest of the system the news. New characters! */ | |
536 | tty_flip_buffer_push(tty); | |
537 | } else { | |
538 | sci_in(port, SCxSR); /* dummy read */ | |
539 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
540 | } | |
541 | } | |
542 | ||
543 | #define SCI_BREAK_JIFFIES (HZ/20) | |
544 | /* The sci generates interrupts during the break, | |
545 | * 1 per millisecond or so during the break period, for 9600 baud. | |
546 | * So dont bother disabling interrupts. | |
547 | * But dont want more than 1 break event. | |
548 | * Use a kernel timer to periodically poll the rx line until | |
549 | * the break is finished. | |
550 | */ | |
551 | static void sci_schedule_break_timer(struct sci_port *port) | |
552 | { | |
553 | port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES; | |
554 | add_timer(&port->break_timer); | |
555 | } | |
556 | /* Ensure that two consecutive samples find the break over. */ | |
557 | static void sci_break_timer(unsigned long data) | |
558 | { | |
e108b2ca PM |
559 | struct sci_port *port = (struct sci_port *)data; |
560 | ||
561 | if (sci_rxd_in(&port->port) == 0) { | |
1da177e4 | 562 | port->break_flag = 1; |
e108b2ca PM |
563 | sci_schedule_break_timer(port); |
564 | } else if (port->break_flag == 1) { | |
1da177e4 LT |
565 | /* break is over. */ |
566 | port->break_flag = 2; | |
e108b2ca PM |
567 | sci_schedule_break_timer(port); |
568 | } else | |
569 | port->break_flag = 0; | |
1da177e4 LT |
570 | } |
571 | ||
572 | static inline int sci_handle_errors(struct uart_port *port) | |
573 | { | |
574 | int copied = 0; | |
575 | unsigned short status = sci_in(port, SCxSR); | |
a88487c7 | 576 | struct tty_struct *tty = port->info->port.tty; |
1da177e4 | 577 | |
e108b2ca | 578 | if (status & SCxSR_ORER(port)) { |
1da177e4 | 579 | /* overrun error */ |
e108b2ca | 580 | if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) |
33f0f88f | 581 | copied++; |
762c69e3 PM |
582 | |
583 | dev_notice(port->dev, "overrun error"); | |
1da177e4 LT |
584 | } |
585 | ||
e108b2ca | 586 | if (status & SCxSR_FER(port)) { |
1da177e4 LT |
587 | if (sci_rxd_in(port) == 0) { |
588 | /* Notify of BREAK */ | |
e7c98dc7 | 589 | struct sci_port *sci_port = to_sci_port(port); |
e108b2ca PM |
590 | |
591 | if (!sci_port->break_flag) { | |
592 | sci_port->break_flag = 1; | |
593 | sci_schedule_break_timer(sci_port); | |
594 | ||
1da177e4 | 595 | /* Do sysrq handling. */ |
e108b2ca | 596 | if (uart_handle_break(port)) |
1da177e4 | 597 | return 0; |
762c69e3 PM |
598 | |
599 | dev_dbg(port->dev, "BREAK detected\n"); | |
600 | ||
e108b2ca | 601 | if (tty_insert_flip_char(tty, 0, TTY_BREAK)) |
e7c98dc7 MT |
602 | copied++; |
603 | } | |
604 | ||
e108b2ca | 605 | } else { |
1da177e4 | 606 | /* frame error */ |
e108b2ca | 607 | if (tty_insert_flip_char(tty, 0, TTY_FRAME)) |
33f0f88f | 608 | copied++; |
762c69e3 PM |
609 | |
610 | dev_notice(port->dev, "frame error\n"); | |
1da177e4 LT |
611 | } |
612 | } | |
613 | ||
e108b2ca | 614 | if (status & SCxSR_PER(port)) { |
1da177e4 | 615 | /* parity error */ |
e108b2ca PM |
616 | if (tty_insert_flip_char(tty, 0, TTY_PARITY)) |
617 | copied++; | |
762c69e3 PM |
618 | |
619 | dev_notice(port->dev, "parity error"); | |
1da177e4 LT |
620 | } |
621 | ||
33f0f88f | 622 | if (copied) |
1da177e4 | 623 | tty_flip_buffer_push(tty); |
1da177e4 LT |
624 | |
625 | return copied; | |
626 | } | |
627 | ||
d830fa45 PM |
628 | static inline int sci_handle_fifo_overrun(struct uart_port *port) |
629 | { | |
630 | struct tty_struct *tty = port->info->port.tty; | |
631 | int copied = 0; | |
632 | ||
633 | if (port->type != PORT_SCIF) | |
634 | return 0; | |
635 | ||
636 | if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) { | |
637 | sci_out(port, SCLSR, 0); | |
638 | ||
639 | tty_insert_flip_char(tty, 0, TTY_OVERRUN); | |
640 | tty_flip_buffer_push(tty); | |
641 | ||
642 | dev_notice(port->dev, "overrun error\n"); | |
643 | copied++; | |
644 | } | |
645 | ||
646 | return copied; | |
647 | } | |
648 | ||
1da177e4 LT |
649 | static inline int sci_handle_breaks(struct uart_port *port) |
650 | { | |
651 | int copied = 0; | |
652 | unsigned short status = sci_in(port, SCxSR); | |
a88487c7 | 653 | struct tty_struct *tty = port->info->port.tty; |
1da177e4 LT |
654 | struct sci_port *s = &sci_ports[port->line]; |
655 | ||
0b3d4ef6 PM |
656 | if (uart_handle_break(port)) |
657 | return 0; | |
658 | ||
b7a76e4b | 659 | if (!s->break_flag && status & SCxSR_BRK(port)) { |
1da177e4 LT |
660 | #if defined(CONFIG_CPU_SH3) |
661 | /* Debounce break */ | |
662 | s->break_flag = 1; | |
663 | #endif | |
664 | /* Notify of BREAK */ | |
e108b2ca | 665 | if (tty_insert_flip_char(tty, 0, TTY_BREAK)) |
33f0f88f | 666 | copied++; |
762c69e3 PM |
667 | |
668 | dev_dbg(port->dev, "BREAK detected\n"); | |
1da177e4 LT |
669 | } |
670 | ||
33f0f88f | 671 | if (copied) |
1da177e4 | 672 | tty_flip_buffer_push(tty); |
e108b2ca | 673 | |
d830fa45 PM |
674 | copied += sci_handle_fifo_overrun(port); |
675 | ||
1da177e4 LT |
676 | return copied; |
677 | } | |
678 | ||
7d12e780 | 679 | static irqreturn_t sci_rx_interrupt(int irq, void *port) |
1da177e4 | 680 | { |
1da177e4 LT |
681 | /* I think sci_receive_chars has to be called irrespective |
682 | * of whether the I_IXOFF is set, otherwise, how is the interrupt | |
683 | * to be disabled? | |
684 | */ | |
7d12e780 | 685 | sci_receive_chars(port); |
1da177e4 LT |
686 | |
687 | return IRQ_HANDLED; | |
688 | } | |
689 | ||
7d12e780 | 690 | static irqreturn_t sci_tx_interrupt(int irq, void *ptr) |
1da177e4 LT |
691 | { |
692 | struct uart_port *port = ptr; | |
693 | ||
e108b2ca | 694 | spin_lock_irq(&port->lock); |
1da177e4 | 695 | sci_transmit_chars(port); |
e108b2ca | 696 | spin_unlock_irq(&port->lock); |
1da177e4 LT |
697 | |
698 | return IRQ_HANDLED; | |
699 | } | |
700 | ||
7d12e780 | 701 | static irqreturn_t sci_er_interrupt(int irq, void *ptr) |
1da177e4 LT |
702 | { |
703 | struct uart_port *port = ptr; | |
704 | ||
705 | /* Handle errors */ | |
706 | if (port->type == PORT_SCI) { | |
707 | if (sci_handle_errors(port)) { | |
708 | /* discard character in rx buffer */ | |
709 | sci_in(port, SCxSR); | |
710 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
711 | } | |
712 | } else { | |
d830fa45 | 713 | sci_handle_fifo_overrun(port); |
7d12e780 | 714 | sci_rx_interrupt(irq, ptr); |
1da177e4 LT |
715 | } |
716 | ||
717 | sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); | |
718 | ||
719 | /* Kick the transmission */ | |
7d12e780 | 720 | sci_tx_interrupt(irq, ptr); |
1da177e4 LT |
721 | |
722 | return IRQ_HANDLED; | |
723 | } | |
724 | ||
7d12e780 | 725 | static irqreturn_t sci_br_interrupt(int irq, void *ptr) |
1da177e4 LT |
726 | { |
727 | struct uart_port *port = ptr; | |
728 | ||
729 | /* Handle BREAKs */ | |
730 | sci_handle_breaks(port); | |
731 | sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port)); | |
732 | ||
733 | return IRQ_HANDLED; | |
734 | } | |
735 | ||
7d12e780 | 736 | static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) |
1da177e4 | 737 | { |
a8884e34 MT |
738 | unsigned short ssr_status, scr_status; |
739 | struct uart_port *port = ptr; | |
740 | irqreturn_t ret = IRQ_NONE; | |
1da177e4 | 741 | |
e7c98dc7 MT |
742 | ssr_status = sci_in(port, SCxSR); |
743 | scr_status = sci_in(port, SCSCR); | |
1da177e4 LT |
744 | |
745 | /* Tx Interrupt */ | |
a8884e34 MT |
746 | if ((ssr_status & 0x0020) && (scr_status & SCI_CTRL_FLAGS_TIE)) |
747 | ret = sci_tx_interrupt(irq, ptr); | |
1da177e4 | 748 | /* Rx Interrupt */ |
a8884e34 MT |
749 | if ((ssr_status & 0x0002) && (scr_status & SCI_CTRL_FLAGS_RIE)) |
750 | ret = sci_rx_interrupt(irq, ptr); | |
1da177e4 | 751 | /* Error Interrupt */ |
a8884e34 MT |
752 | if ((ssr_status & 0x0080) && (scr_status & SCI_CTRL_FLAGS_REIE)) |
753 | ret = sci_er_interrupt(irq, ptr); | |
1da177e4 | 754 | /* Break Interrupt */ |
a8884e34 MT |
755 | if ((ssr_status & 0x0010) && (scr_status & SCI_CTRL_FLAGS_REIE)) |
756 | ret = sci_br_interrupt(irq, ptr); | |
1da177e4 | 757 | |
a8884e34 | 758 | return ret; |
1da177e4 LT |
759 | } |
760 | ||
027e6872 | 761 | #ifdef CONFIG_HAVE_CLK |
1da177e4 LT |
762 | /* |
763 | * Here we define a transistion notifier so that we can update all of our | |
764 | * ports' baud rate when the peripheral clock changes. | |
765 | */ | |
e108b2ca PM |
766 | static int sci_notifier(struct notifier_block *self, |
767 | unsigned long phase, void *p) | |
1da177e4 | 768 | { |
1da177e4 LT |
769 | int i; |
770 | ||
771 | if ((phase == CPUFREQ_POSTCHANGE) || | |
027e6872 | 772 | (phase == CPUFREQ_RESUMECHANGE)) |
1da177e4 | 773 | for (i = 0; i < SCI_NPORTS; i++) { |
027e6872 PM |
774 | struct sci_port *s = &sci_ports[i]; |
775 | s->port.uartclk = clk_get_rate(s->clk); | |
1da177e4 LT |
776 | } |
777 | ||
1da177e4 LT |
778 | return NOTIFY_OK; |
779 | } | |
780 | ||
781 | static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 }; | |
027e6872 | 782 | #endif |
1da177e4 LT |
783 | |
784 | static int sci_request_irq(struct sci_port *port) | |
785 | { | |
786 | int i; | |
7d12e780 | 787 | irqreturn_t (*handlers[4])(int irq, void *ptr) = { |
1da177e4 LT |
788 | sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt, |
789 | sci_br_interrupt, | |
790 | }; | |
791 | const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full", | |
792 | "SCI Transmit Data Empty", "SCI Break" }; | |
793 | ||
794 | if (port->irqs[0] == port->irqs[1]) { | |
762c69e3 | 795 | if (unlikely(!port->irqs[0])) |
1da177e4 | 796 | return -ENODEV; |
e108b2ca PM |
797 | |
798 | if (request_irq(port->irqs[0], sci_mpxed_interrupt, | |
35f3c518 | 799 | IRQF_DISABLED, "sci", port)) { |
762c69e3 | 800 | dev_err(port->port.dev, "Can't allocate IRQ\n"); |
1da177e4 LT |
801 | return -ENODEV; |
802 | } | |
803 | } else { | |
804 | for (i = 0; i < ARRAY_SIZE(handlers); i++) { | |
762c69e3 | 805 | if (unlikely(!port->irqs[i])) |
1da177e4 | 806 | continue; |
762c69e3 | 807 | |
e108b2ca | 808 | if (request_irq(port->irqs[i], handlers[i], |
35f3c518 | 809 | IRQF_DISABLED, desc[i], port)) { |
762c69e3 | 810 | dev_err(port->port.dev, "Can't allocate IRQ\n"); |
1da177e4 LT |
811 | return -ENODEV; |
812 | } | |
813 | } | |
814 | } | |
815 | ||
816 | return 0; | |
817 | } | |
818 | ||
819 | static void sci_free_irq(struct sci_port *port) | |
820 | { | |
821 | int i; | |
822 | ||
762c69e3 PM |
823 | if (port->irqs[0] == port->irqs[1]) |
824 | free_irq(port->irqs[0], port); | |
825 | else { | |
1da177e4 LT |
826 | for (i = 0; i < ARRAY_SIZE(port->irqs); i++) { |
827 | if (!port->irqs[i]) | |
828 | continue; | |
829 | ||
830 | free_irq(port->irqs[i], port); | |
831 | } | |
832 | } | |
833 | } | |
834 | ||
835 | static unsigned int sci_tx_empty(struct uart_port *port) | |
836 | { | |
837 | /* Can't detect */ | |
838 | return TIOCSER_TEMT; | |
839 | } | |
840 | ||
841 | static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
842 | { | |
843 | /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */ | |
844 | /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */ | |
845 | /* If you have signals for DTR and DCD, please implement here. */ | |
846 | } | |
847 | ||
848 | static unsigned int sci_get_mctrl(struct uart_port *port) | |
849 | { | |
850 | /* This routine is used for geting signals of: DTR, DCD, DSR, RI, | |
851 | and CTS/RTS */ | |
852 | ||
853 | return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR; | |
854 | } | |
855 | ||
b129a8cc | 856 | static void sci_start_tx(struct uart_port *port) |
1da177e4 | 857 | { |
e108b2ca | 858 | unsigned short ctrl; |
1da177e4 | 859 | |
e108b2ca PM |
860 | /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ |
861 | ctrl = sci_in(port, SCSCR); | |
862 | ctrl |= SCI_CTRL_FLAGS_TIE; | |
863 | sci_out(port, SCSCR, ctrl); | |
1da177e4 LT |
864 | } |
865 | ||
b129a8cc | 866 | static void sci_stop_tx(struct uart_port *port) |
1da177e4 | 867 | { |
1da177e4 LT |
868 | unsigned short ctrl; |
869 | ||
870 | /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ | |
1da177e4 LT |
871 | ctrl = sci_in(port, SCSCR); |
872 | ctrl &= ~SCI_CTRL_FLAGS_TIE; | |
873 | sci_out(port, SCSCR, ctrl); | |
1da177e4 LT |
874 | } |
875 | ||
876 | static void sci_start_rx(struct uart_port *port, unsigned int tty_start) | |
877 | { | |
1da177e4 LT |
878 | unsigned short ctrl; |
879 | ||
880 | /* Set RIE (Receive Interrupt Enable) bit in SCSCR */ | |
1da177e4 LT |
881 | ctrl = sci_in(port, SCSCR); |
882 | ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE; | |
883 | sci_out(port, SCSCR, ctrl); | |
1da177e4 LT |
884 | } |
885 | ||
886 | static void sci_stop_rx(struct uart_port *port) | |
887 | { | |
1da177e4 LT |
888 | unsigned short ctrl; |
889 | ||
890 | /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */ | |
1da177e4 LT |
891 | ctrl = sci_in(port, SCSCR); |
892 | ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE); | |
893 | sci_out(port, SCSCR, ctrl); | |
1da177e4 LT |
894 | } |
895 | ||
896 | static void sci_enable_ms(struct uart_port *port) | |
897 | { | |
898 | /* Nothing here yet .. */ | |
899 | } | |
900 | ||
901 | static void sci_break_ctl(struct uart_port *port, int break_state) | |
902 | { | |
903 | /* Nothing here yet .. */ | |
904 | } | |
905 | ||
906 | static int sci_startup(struct uart_port *port) | |
907 | { | |
908 | struct sci_port *s = &sci_ports[port->line]; | |
909 | ||
e108b2ca PM |
910 | if (s->enable) |
911 | s->enable(port); | |
1da177e4 | 912 | |
a2159b52 | 913 | #ifdef CONFIG_HAVE_CLK |
1534a3b3 | 914 | s->clk = clk_get(NULL, "module_clk"); |
005a336e | 915 | #endif |
1534a3b3 | 916 | |
1da177e4 | 917 | sci_request_irq(s); |
d656901b | 918 | sci_start_tx(port); |
1da177e4 LT |
919 | sci_start_rx(port, 1); |
920 | ||
921 | return 0; | |
922 | } | |
923 | ||
924 | static void sci_shutdown(struct uart_port *port) | |
925 | { | |
926 | struct sci_port *s = &sci_ports[port->line]; | |
927 | ||
928 | sci_stop_rx(port); | |
b129a8cc | 929 | sci_stop_tx(port); |
1da177e4 LT |
930 | sci_free_irq(s); |
931 | ||
e108b2ca PM |
932 | if (s->disable) |
933 | s->disable(port); | |
1534a3b3 | 934 | |
a2159b52 | 935 | #ifdef CONFIG_HAVE_CLK |
1534a3b3 | 936 | clk_put(s->clk); |
937 | s->clk = NULL; | |
005a336e | 938 | #endif |
1da177e4 LT |
939 | } |
940 | ||
606d099c AC |
941 | static void sci_set_termios(struct uart_port *port, struct ktermios *termios, |
942 | struct ktermios *old) | |
1da177e4 LT |
943 | { |
944 | struct sci_port *s = &sci_ports[port->line]; | |
945 | unsigned int status, baud, smr_val; | |
a2159b52 | 946 | int t = -1; |
1da177e4 LT |
947 | |
948 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
a2159b52 PM |
949 | if (likely(baud)) |
950 | t = SCBRR_VALUE(baud, port->uartclk); | |
e108b2ca | 951 | |
1da177e4 LT |
952 | do { |
953 | status = sci_in(port, SCxSR); | |
954 | } while (!(status & SCxSR_TEND(port))); | |
955 | ||
956 | sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ | |
957 | ||
1a22f08d | 958 | if (port->type != PORT_SCI) |
1da177e4 | 959 | sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); |
1da177e4 LT |
960 | |
961 | smr_val = sci_in(port, SCSMR) & 3; | |
962 | if ((termios->c_cflag & CSIZE) == CS7) | |
963 | smr_val |= 0x40; | |
964 | if (termios->c_cflag & PARENB) | |
965 | smr_val |= 0x20; | |
966 | if (termios->c_cflag & PARODD) | |
967 | smr_val |= 0x30; | |
968 | if (termios->c_cflag & CSTOPB) | |
969 | smr_val |= 0x08; | |
970 | ||
971 | uart_update_timeout(port, termios->c_cflag, baud); | |
972 | ||
973 | sci_out(port, SCSMR, smr_val); | |
974 | ||
1da177e4 | 975 | if (t > 0) { |
e7c98dc7 | 976 | if (t >= 256) { |
1da177e4 LT |
977 | sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1); |
978 | t >>= 2; | |
e7c98dc7 | 979 | } else |
1da177e4 | 980 | sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3); |
e7c98dc7 | 981 | |
1da177e4 LT |
982 | sci_out(port, SCBRR, t); |
983 | udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */ | |
984 | } | |
985 | ||
b7a76e4b PM |
986 | if (likely(s->init_pins)) |
987 | s->init_pins(port, termios->c_cflag); | |
988 | ||
1da177e4 LT |
989 | sci_out(port, SCSCR, SCSCR_INIT(port)); |
990 | ||
991 | if ((termios->c_cflag & CREAD) != 0) | |
e7c98dc7 | 992 | sci_start_rx(port, 0); |
1da177e4 LT |
993 | } |
994 | ||
995 | static const char *sci_type(struct uart_port *port) | |
996 | { | |
997 | switch (port->type) { | |
e7c98dc7 MT |
998 | case PORT_IRDA: |
999 | return "irda"; | |
1000 | case PORT_SCI: | |
1001 | return "sci"; | |
1002 | case PORT_SCIF: | |
1003 | return "scif"; | |
1004 | case PORT_SCIFA: | |
1005 | return "scifa"; | |
1da177e4 LT |
1006 | } |
1007 | ||
fa43972f | 1008 | return NULL; |
1da177e4 LT |
1009 | } |
1010 | ||
1011 | static void sci_release_port(struct uart_port *port) | |
1012 | { | |
1013 | /* Nothing here yet .. */ | |
1014 | } | |
1015 | ||
1016 | static int sci_request_port(struct uart_port *port) | |
1017 | { | |
1018 | /* Nothing here yet .. */ | |
1019 | return 0; | |
1020 | } | |
1021 | ||
1022 | static void sci_config_port(struct uart_port *port, int flags) | |
1023 | { | |
1024 | struct sci_port *s = &sci_ports[port->line]; | |
1025 | ||
1026 | port->type = s->type; | |
1027 | ||
e108b2ca PM |
1028 | switch (port->type) { |
1029 | case PORT_SCI: | |
1030 | s->init_pins = sci_init_pins_sci; | |
1031 | break; | |
1032 | case PORT_SCIF: | |
1a22f08d | 1033 | case PORT_SCIFA: |
e108b2ca PM |
1034 | s->init_pins = sci_init_pins_scif; |
1035 | break; | |
1036 | case PORT_IRDA: | |
1037 | s->init_pins = sci_init_pins_irda; | |
1038 | break; | |
1039 | } | |
1040 | ||
7ff731ae PM |
1041 | if (port->flags & UPF_IOREMAP && !port->membase) { |
1042 | #if defined(CONFIG_SUPERH64) | |
1da177e4 | 1043 | port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF"); |
7ff731ae PM |
1044 | port->membase = (void __iomem *)port->mapbase; |
1045 | #else | |
1046 | port->membase = ioremap_nocache(port->mapbase, 0x40); | |
1da177e4 | 1047 | #endif |
7ff731ae | 1048 | |
762c69e3 | 1049 | dev_err(port->dev, "can't remap port#%d\n", port->line); |
7ff731ae | 1050 | } |
1da177e4 LT |
1051 | } |
1052 | ||
1053 | static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) | |
1054 | { | |
1055 | struct sci_port *s = &sci_ports[port->line]; | |
1056 | ||
a62c4133 | 1057 | if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs) |
1da177e4 LT |
1058 | return -EINVAL; |
1059 | if (ser->baud_base < 2400) | |
1060 | /* No paper tape reader for Mitch.. */ | |
1061 | return -EINVAL; | |
1062 | ||
1063 | return 0; | |
1064 | } | |
1065 | ||
1066 | static struct uart_ops sci_uart_ops = { | |
1067 | .tx_empty = sci_tx_empty, | |
1068 | .set_mctrl = sci_set_mctrl, | |
1069 | .get_mctrl = sci_get_mctrl, | |
1070 | .start_tx = sci_start_tx, | |
1071 | .stop_tx = sci_stop_tx, | |
1072 | .stop_rx = sci_stop_rx, | |
1073 | .enable_ms = sci_enable_ms, | |
1074 | .break_ctl = sci_break_ctl, | |
1075 | .startup = sci_startup, | |
1076 | .shutdown = sci_shutdown, | |
1077 | .set_termios = sci_set_termios, | |
1078 | .type = sci_type, | |
1079 | .release_port = sci_release_port, | |
1080 | .request_port = sci_request_port, | |
1081 | .config_port = sci_config_port, | |
1082 | .verify_port = sci_verify_port, | |
07d2a1a1 PM |
1083 | #ifdef CONFIG_CONSOLE_POLL |
1084 | .poll_get_char = sci_poll_get_char, | |
1085 | .poll_put_char = sci_poll_put_char, | |
1086 | #endif | |
1da177e4 LT |
1087 | }; |
1088 | ||
e108b2ca PM |
1089 | static void __init sci_init_ports(void) |
1090 | { | |
1091 | static int first = 1; | |
1092 | int i; | |
1093 | ||
1094 | if (!first) | |
1095 | return; | |
1096 | ||
1097 | first = 0; | |
1098 | ||
1099 | for (i = 0; i < SCI_NPORTS; i++) { | |
1100 | sci_ports[i].port.ops = &sci_uart_ops; | |
1101 | sci_ports[i].port.iotype = UPIO_MEM; | |
1102 | sci_ports[i].port.line = i; | |
1103 | sci_ports[i].port.fifosize = 1; | |
1104 | ||
1105 | #if defined(__H8300H__) || defined(__H8300S__) | |
1106 | #ifdef __H8300S__ | |
1107 | sci_ports[i].enable = h8300_sci_enable; | |
1108 | sci_ports[i].disable = h8300_sci_disable; | |
1109 | #endif | |
1110 | sci_ports[i].port.uartclk = CONFIG_CPU_CLOCK; | |
a2159b52 | 1111 | #elif defined(CONFIG_HAVE_CLK) |
e108b2ca PM |
1112 | /* |
1113 | * XXX: We should use a proper SCI/SCIF clock | |
1114 | */ | |
1115 | { | |
1d118562 | 1116 | struct clk *clk = clk_get(NULL, "module_clk"); |
a2159b52 | 1117 | sci_ports[i].port.uartclk = clk_get_rate(clk); |
e108b2ca PM |
1118 | clk_put(clk); |
1119 | } | |
a2159b52 PM |
1120 | #else |
1121 | #error "Need a valid uartclk" | |
1da177e4 | 1122 | #endif |
e108b2ca PM |
1123 | |
1124 | sci_ports[i].break_timer.data = (unsigned long)&sci_ports[i]; | |
1125 | sci_ports[i].break_timer.function = sci_break_timer; | |
1126 | ||
1127 | init_timer(&sci_ports[i].break_timer); | |
1128 | } | |
1129 | } | |
1130 | ||
1131 | int __init early_sci_setup(struct uart_port *port) | |
1132 | { | |
1133 | if (unlikely(port->line > SCI_NPORTS)) | |
1134 | return -ENODEV; | |
1135 | ||
1136 | sci_init_ports(); | |
1137 | ||
1138 | sci_ports[port->line].port.membase = port->membase; | |
1139 | sci_ports[port->line].port.mapbase = port->mapbase; | |
1140 | sci_ports[port->line].port.type = port->type; | |
1141 | ||
1142 | return 0; | |
1143 | } | |
1da177e4 LT |
1144 | |
1145 | #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE | |
1146 | /* | |
1147 | * Print a string to the serial port trying not to disturb | |
1148 | * any possible real use of the port... | |
1149 | */ | |
1150 | static void serial_console_write(struct console *co, const char *s, | |
1151 | unsigned count) | |
1152 | { | |
07d2a1a1 PM |
1153 | struct uart_port *port = &serial_console_port->port; |
1154 | int i; | |
1155 | ||
1156 | for (i = 0; i < count; i++) { | |
1157 | if (*s == 10) | |
1158 | sci_poll_put_char(port, '\r'); | |
1159 | ||
1160 | sci_poll_put_char(port, *s++); | |
1161 | } | |
1da177e4 LT |
1162 | } |
1163 | ||
1164 | static int __init serial_console_setup(struct console *co, char *options) | |
1165 | { | |
1166 | struct uart_port *port; | |
1167 | int baud = 115200; | |
1168 | int bits = 8; | |
1169 | int parity = 'n'; | |
1170 | int flow = 'n'; | |
1171 | int ret; | |
1172 | ||
e108b2ca PM |
1173 | /* |
1174 | * Check whether an invalid uart number has been specified, and | |
1175 | * if so, search for the first available port that does have | |
1176 | * console support. | |
1177 | */ | |
1178 | if (co->index >= SCI_NPORTS) | |
1179 | co->index = 0; | |
1180 | ||
1da177e4 LT |
1181 | serial_console_port = &sci_ports[co->index]; |
1182 | port = &serial_console_port->port; | |
1da177e4 LT |
1183 | |
1184 | /* | |
e108b2ca PM |
1185 | * Also need to check port->type, we don't actually have any |
1186 | * UPIO_PORT ports, but uart_report_port() handily misreports | |
1187 | * it anyways if we don't have a port available by the time this is | |
1188 | * called. | |
1da177e4 | 1189 | */ |
e108b2ca PM |
1190 | if (!port->type) |
1191 | return -ENODEV; | |
1192 | if (!port->membase || !port->mapbase) | |
1193 | return -ENODEV; | |
1194 | ||
e108b2ca PM |
1195 | port->type = serial_console_port->type; |
1196 | ||
a2159b52 | 1197 | #ifdef CONFIG_HAVE_CLK |
005a336e PM |
1198 | if (!serial_console_port->clk) |
1199 | serial_console_port->clk = clk_get(NULL, "module_clk"); | |
1200 | #endif | |
1201 | ||
e108b2ca PM |
1202 | if (port->flags & UPF_IOREMAP) |
1203 | sci_config_port(port, 0); | |
1204 | ||
1205 | if (serial_console_port->enable) | |
1206 | serial_console_port->enable(port); | |
b7a76e4b | 1207 | |
1da177e4 LT |
1208 | if (options) |
1209 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1210 | ||
1211 | ret = uart_set_options(port, co, baud, parity, bits, flow); | |
1212 | #if defined(__H8300H__) || defined(__H8300S__) | |
1213 | /* disable rx interrupt */ | |
1214 | if (ret == 0) | |
1215 | sci_stop_rx(port); | |
1216 | #endif | |
1217 | return ret; | |
1218 | } | |
1219 | ||
1220 | static struct console serial_console = { | |
1221 | .name = "ttySC", | |
1222 | .device = uart_console_device, | |
1223 | .write = serial_console_write, | |
1224 | .setup = serial_console_setup, | |
fa5da2f7 | 1225 | .flags = CON_PRINTBUFFER, |
1da177e4 LT |
1226 | .index = -1, |
1227 | .data = &sci_uart_driver, | |
1228 | }; | |
1229 | ||
1230 | static int __init sci_console_init(void) | |
1231 | { | |
e108b2ca | 1232 | sci_init_ports(); |
1da177e4 LT |
1233 | register_console(&serial_console); |
1234 | return 0; | |
1235 | } | |
1da177e4 LT |
1236 | console_initcall(sci_console_init); |
1237 | #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ | |
1238 | ||
07d2a1a1 | 1239 | #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) |
e7c98dc7 | 1240 | #define SCI_CONSOLE (&serial_console) |
1da177e4 | 1241 | #else |
b7a76e4b | 1242 | #define SCI_CONSOLE 0 |
1da177e4 LT |
1243 | #endif |
1244 | ||
1245 | static char banner[] __initdata = | |
1246 | KERN_INFO "SuperH SCI(F) driver initialized\n"; | |
1247 | ||
1248 | static struct uart_driver sci_uart_driver = { | |
1249 | .owner = THIS_MODULE, | |
1250 | .driver_name = "sci", | |
1da177e4 LT |
1251 | .dev_name = "ttySC", |
1252 | .major = SCI_MAJOR, | |
1253 | .minor = SCI_MINOR_START, | |
e108b2ca | 1254 | .nr = SCI_NPORTS, |
1da177e4 LT |
1255 | .cons = SCI_CONSOLE, |
1256 | }; | |
1257 | ||
e108b2ca PM |
1258 | /* |
1259 | * Register a set of serial devices attached to a platform device. The | |
1260 | * list is terminated with a zero flags entry, which means we expect | |
1261 | * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need | |
1262 | * remapping (such as sh64) should also set UPF_IOREMAP. | |
1263 | */ | |
1264 | static int __devinit sci_probe(struct platform_device *dev) | |
1da177e4 | 1265 | { |
e108b2ca | 1266 | struct plat_sci_port *p = dev->dev.platform_data; |
7ff731ae | 1267 | int i, ret = -EINVAL; |
1da177e4 | 1268 | |
32351a28 | 1269 | for (i = 0; p && p->flags != 0; p++, i++) { |
e108b2ca | 1270 | struct sci_port *sciport = &sci_ports[i]; |
1da177e4 | 1271 | |
32351a28 PM |
1272 | /* Sanity check */ |
1273 | if (unlikely(i == SCI_NPORTS)) { | |
1274 | dev_notice(&dev->dev, "Attempting to register port " | |
1275 | "%d when only %d are available.\n", | |
1276 | i+1, SCI_NPORTS); | |
1277 | dev_notice(&dev->dev, "Consider bumping " | |
1278 | "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); | |
1279 | break; | |
1280 | } | |
1281 | ||
e108b2ca | 1282 | sciport->port.mapbase = p->mapbase; |
b7a76e4b | 1283 | |
7ff731ae PM |
1284 | if (p->mapbase && !p->membase) { |
1285 | if (p->flags & UPF_IOREMAP) { | |
1286 | p->membase = ioremap_nocache(p->mapbase, 0x40); | |
1287 | if (IS_ERR(p->membase)) { | |
1288 | ret = PTR_ERR(p->membase); | |
1289 | goto err_unreg; | |
1290 | } | |
1291 | } else { | |
1292 | /* | |
1293 | * For the simple (and majority of) cases | |
1294 | * where we don't need to do any remapping, | |
1295 | * just cast the cookie directly. | |
1296 | */ | |
1297 | p->membase = (void __iomem *)p->mapbase; | |
1298 | } | |
1299 | } | |
1da177e4 | 1300 | |
e108b2ca PM |
1301 | sciport->port.membase = p->membase; |
1302 | ||
1303 | sciport->port.irq = p->irqs[SCIx_TXI_IRQ]; | |
1304 | sciport->port.flags = p->flags; | |
1305 | sciport->port.dev = &dev->dev; | |
1306 | ||
1307 | sciport->type = sciport->port.type = p->type; | |
1308 | ||
1309 | memcpy(&sciport->irqs, &p->irqs, sizeof(p->irqs)); | |
1310 | ||
1311 | uart_add_one_port(&sci_uart_driver, &sciport->port); | |
1da177e4 LT |
1312 | } |
1313 | ||
027e6872 | 1314 | #ifdef CONFIG_HAVE_CLK |
1da177e4 | 1315 | cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER); |
1da177e4 LT |
1316 | #endif |
1317 | ||
1318 | #ifdef CONFIG_SH_STANDARD_BIOS | |
1319 | sh_bios_gdb_detach(); | |
1320 | #endif | |
1321 | ||
e108b2ca | 1322 | return 0; |
7ff731ae PM |
1323 | |
1324 | err_unreg: | |
1325 | for (i = i - 1; i >= 0; i--) | |
1326 | uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port); | |
1327 | ||
1328 | return ret; | |
1da177e4 LT |
1329 | } |
1330 | ||
e108b2ca PM |
1331 | static int __devexit sci_remove(struct platform_device *dev) |
1332 | { | |
1333 | int i; | |
1334 | ||
027e6872 PM |
1335 | #ifdef CONFIG_HAVE_CLK |
1336 | cpufreq_unregister_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER); | |
1337 | #endif | |
1338 | ||
e108b2ca PM |
1339 | for (i = 0; i < SCI_NPORTS; i++) |
1340 | uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port); | |
1341 | ||
1342 | return 0; | |
1343 | } | |
1344 | ||
1345 | static int sci_suspend(struct platform_device *dev, pm_message_t state) | |
1da177e4 | 1346 | { |
e108b2ca PM |
1347 | int i; |
1348 | ||
1349 | for (i = 0; i < SCI_NPORTS; i++) { | |
1350 | struct sci_port *p = &sci_ports[i]; | |
1351 | ||
1352 | if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev) | |
1353 | uart_suspend_port(&sci_uart_driver, &p->port); | |
1354 | } | |
1da177e4 | 1355 | |
e108b2ca PM |
1356 | return 0; |
1357 | } | |
1da177e4 | 1358 | |
e108b2ca PM |
1359 | static int sci_resume(struct platform_device *dev) |
1360 | { | |
1361 | int i; | |
1362 | ||
1363 | for (i = 0; i < SCI_NPORTS; i++) { | |
1364 | struct sci_port *p = &sci_ports[i]; | |
1365 | ||
1366 | if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev) | |
1367 | uart_resume_port(&sci_uart_driver, &p->port); | |
1368 | } | |
1369 | ||
1370 | return 0; | |
1371 | } | |
1372 | ||
1373 | static struct platform_driver sci_driver = { | |
1374 | .probe = sci_probe, | |
1375 | .remove = __devexit_p(sci_remove), | |
1376 | .suspend = sci_suspend, | |
1377 | .resume = sci_resume, | |
1378 | .driver = { | |
1379 | .name = "sh-sci", | |
1380 | .owner = THIS_MODULE, | |
1381 | }, | |
1382 | }; | |
1383 | ||
1384 | static int __init sci_init(void) | |
1385 | { | |
1386 | int ret; | |
1387 | ||
1388 | printk(banner); | |
1389 | ||
1390 | sci_init_ports(); | |
1391 | ||
1392 | ret = uart_register_driver(&sci_uart_driver); | |
1393 | if (likely(ret == 0)) { | |
1394 | ret = platform_driver_register(&sci_driver); | |
1395 | if (unlikely(ret)) | |
1396 | uart_unregister_driver(&sci_uart_driver); | |
1397 | } | |
1398 | ||
1399 | return ret; | |
1400 | } | |
1401 | ||
1402 | static void __exit sci_exit(void) | |
1403 | { | |
1404 | platform_driver_unregister(&sci_driver); | |
1da177e4 LT |
1405 | uart_unregister_driver(&sci_uart_driver); |
1406 | } | |
1407 | ||
1408 | module_init(sci_init); | |
1409 | module_exit(sci_exit); | |
1410 | ||
e108b2ca | 1411 | MODULE_LICENSE("GPL"); |
e169c139 | 1412 | MODULE_ALIAS("platform:sh-sci"); |