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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[linux-2.6-block.git] / drivers / serial / sh-sci.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
7ff731ae 6 * Copyright (C) 2002 - 2008 Paul Mundt
3ea6bc3d 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 16 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 17 *
18 * This file is subject to the terms and conditions of the GNU General Public
19 * License. See the file "COPYING" in the main directory of this archive
20 * for more details.
21 */
0b3d4ef6
PM		 22#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23#define SUPPORT_SYSRQ
24#endif
1da177e4
LT		 25
26#undef DEBUG
27
1da177e4
LT		 28#include <linux/module.h>
29#include <linux/errno.h>
1da177e4
LT		 30#include <linux/timer.h>
31#include <linux/interrupt.h>
32#include <linux/tty.h>
33#include <linux/tty_flip.h>
34#include <linux/serial.h>
35#include <linux/major.h>
36#include <linux/string.h>
37#include <linux/sysrq.h>
1da177e4
LT		 38#include <linux/ioport.h>
39#include <linux/mm.h>
1da177e4
LT		 40#include <linux/init.h>
41#include <linux/delay.h>
42#include <linux/console.h>
e108b2ca 43#include <linux/platform_device.h>
96de1a8f 44#include <linux/serial_sci.h>
1da177e4
LT		 45#include <linux/notifier.h>
46#include <linux/cpufreq.h>
85f094ec 47#include <linux/clk.h>
fa5da2f7 48#include <linux/ctype.h>
7ff731ae 49#include <linux/err.h>
e552de24 50#include <linux/list.h>
73a19e4c
GL		 51#include <linux/dmaengine.h>
52#include <linux/scatterlist.h>
5a0e3ad6 53#include <linux/slab.h>
85f094ec
PM		 54
55#ifdef CONFIG_SUPERH
1da177e4
LT		 56#include <asm/sh_bios.h>
57#endif
58
168f3623
YS		 59#ifdef CONFIG_H8300
60#include <asm/gpio.h>
61#endif
62
1da177e4
LT		 63#include "sh-sci.h"
64
e108b2ca
PM		 65struct sci_port {
66 struct uart_port port;
67
68 /* Port type */
69 unsigned int type;
70
71 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
32351a28 72 unsigned int irqs[SCIx_NR_IRQS];
e108b2ca 73
e108b2ca
PM		 74 /* Port enable callback */
75 void (*enable)(struct uart_port *port);
76
77 /* Port disable callback */
78 void (*disable)(struct uart_port *port);
79
80 /* Break timer */
81 struct timer_list break_timer;
82 int break_flag;
1534a3b3 83
501b825d
MD		 84 /* Interface clock */
85 struct clk *iclk;
86 /* Data clock */
87 struct clk *dclk;
edad1f20 88
e552de24 89 struct list_head node;
73a19e4c
GL		 90 struct dma_chan *chan_tx;
91 struct dma_chan *chan_rx;
92#ifdef CONFIG_SERIAL_SH_SCI_DMA
93 struct device *dma_dev;
94 enum sh_dmae_slave_chan_id slave_tx;
95 enum sh_dmae_slave_chan_id slave_rx;
96 struct dma_async_tx_descriptor *desc_tx;
97 struct dma_async_tx_descriptor *desc_rx[2];
98 dma_cookie_t cookie_tx;
99 dma_cookie_t cookie_rx[2];
100 dma_cookie_t active_rx;
101 struct scatterlist sg_tx;
102 unsigned int sg_len_tx;
103 struct scatterlist sg_rx[2];
104 size_t buf_len_rx;
105 struct sh_dmae_slave param_tx;
106 struct sh_dmae_slave param_rx;
107 struct work_struct work_tx;
108 struct work_struct work_rx;
109 struct timer_list rx_timer;
110#endif
e552de24
MD		 111};
112
113struct sh_sci_priv {
114 spinlock_t lock;
115 struct list_head ports;
e552de24 116 struct notifier_block clk_nb;
e108b2ca
PM		 117};
118
1da177e4 119/* Function prototypes */
b129a8cc 120static void sci_stop_tx(struct uart_port *port);
1da177e4 121
e108b2ca 122#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 123
e108b2ca
PM		 124static struct sci_port sci_ports[SCI_NPORTS];
125static struct uart_driver sci_uart_driver;
1da177e4 126
e7c98dc7
MT		 127static inline struct sci_port *
128to_sci_port(struct uart_port *uart)
129{
130 return container_of(uart, struct sci_port, port);
131}
132
07d2a1a1 133#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 134
135#ifdef CONFIG_CONSOLE_POLL
e108b2ca
PM		 136static inline void handle_error(struct uart_port *port)
137{
138 /* Clear error flags */
1da177e4
LT		 139 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
140}
141
07d2a1a1 142static int sci_poll_get_char(struct uart_port *port)
1da177e4 143{
1da177e4
LT		 144 unsigned short status;
145 int c;
146
e108b2ca 147 do {
1da177e4
LT		 148 status = sci_in(port, SCxSR);
149 if (status & SCxSR_ERRORS(port)) {
150 handle_error(port);
151 continue;
152 }
153 } while (!(status & SCxSR_RDxF(port)));
07d2a1a1 154
1da177e4 155 c = sci_in(port, SCxRDR);
07d2a1a1 156
e7c98dc7
MT		 157 /* Dummy read */
158 sci_in(port, SCxSR);
1da177e4 159 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 160
161 return c;
162}
1f6fd5c9 163#endif
1da177e4 164
07d2a1a1 165static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 166{
1da177e4
LT		 167 unsigned short status;
168
1da177e4
LT		 169 do {
170 status = sci_in(port, SCxSR);
171 } while (!(status & SCxSR_TDxE(port)));
172
272966c0 173 sci_out(port, SCxTDR, c);
dd0a3e77 174 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 175}
07d2a1a1 176#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 177
15c73aaa 178#if defined(__H8300H__) || defined(__H8300S__)
d5701647 179static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4
LT		 180{
181 int ch = (port->mapbase - SMR0) >> 3;
182
183 /* set DDR regs */
e108b2ca
PM		 184 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
185 h8300_sci_pins[ch].rx,
186 H8300_GPIO_INPUT);
187 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
188 h8300_sci_pins[ch].tx,
189 H8300_GPIO_OUTPUT);
190
1da177e4
LT		 191 /* tx mark output*/
192 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
193}
d5701647
PM		 194#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
195static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
e108b2ca 196{
d5701647
PM		 197 if (port->mapbase == 0xA4400000) {
198 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
199 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
200 } else if (port->mapbase == 0xA4410000)
201 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
9465a54f 202}
31a49c4b 203#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
d5701647 204static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
3ea6bc3d 205{
3ea6bc3d
MB		 206 unsigned short data;
207
208 if (cflag & CRTSCTS) {
209 /* enable RTS/CTS */
210 if (port->mapbase == 0xa4430000) { /* SCIF0 */
211 /* Clear PTCR bit 9-2; enable all scif pins but sck */
d5701647
PM		 212 data = __raw_readw(PORT_PTCR);
213 __raw_writew((data & 0xfc03), PORT_PTCR);
3ea6bc3d
MB		 214 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
215 /* Clear PVCR bit 9-2 */
d5701647
PM		 216 data = __raw_readw(PORT_PVCR);
217 __raw_writew((data & 0xfc03), PORT_PVCR);
3ea6bc3d 218 }
3ea6bc3d
MB		 219 } else {
220 if (port->mapbase == 0xa4430000) { /* SCIF0 */
221 /* Clear PTCR bit 5-2; enable only tx and rx */
d5701647
PM		 222 data = __raw_readw(PORT_PTCR);
223 __raw_writew((data & 0xffc3), PORT_PTCR);
3ea6bc3d
MB		 224 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
225 /* Clear PVCR bit 5-2 */
d5701647
PM		 226 data = __raw_readw(PORT_PVCR);
227 __raw_writew((data & 0xffc3), PORT_PVCR);
3ea6bc3d
MB		 228 }
229 }
3ea6bc3d 230}
b7a76e4b 231#elif defined(CONFIG_CPU_SH3)
e108b2ca 232/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
d5701647 233static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 234{
b7a76e4b
PM		 235 unsigned short data;
236
237 /* We need to set SCPCR to enable RTS/CTS */
d5701647 238 data = __raw_readw(SCPCR);
b7a76e4b 239 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
d5701647 240 __raw_writew(data & 0x0fcf, SCPCR);
1da177e4 241
d5701647 242 if (!(cflag & CRTSCTS)) {
1da177e4 243 /* We need to set SCPCR to enable RTS/CTS */
d5701647 244 data = __raw_readw(SCPCR);
1da177e4
LT		 245 /* Clear out SCP7MD1,0, SCP4MD1,0,
246 Set SCP6MD1,0 = {01} (output) */
d5701647 247 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
1da177e4 248
32b53076 249 data = __raw_readb(SCPDR);
1da177e4 250 /* Set /RTS2 (bit6) = 0 */
32b53076 251 __raw_writeb(data & 0xbf, SCPDR);
1da177e4 252 }
1da177e4 253}
41504c39 254#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
d5701647 255static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
41504c39 256{
346b7463 257 unsigned short data;
41504c39 258
346b7463 259 if (port->mapbase == 0xffe00000) {
d5701647 260 data = __raw_readw(PSCR);
346b7463 261 data &= ~0x03cf;
d5701647 262 if (!(cflag & CRTSCTS))
346b7463 263 data |= 0x0340;
41504c39 264
d5701647 265 __raw_writew(data, PSCR);
41504c39 266 }
178dd0cd 267}
c01f0f1a
YS		 268#elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \
269 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
7d740a06 270 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
2b1bd1ac 271 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
55ba99eb 272 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
2b1bd1ac 273 defined(CONFIG_CPU_SUBTYPE_SHX3)
d5701647
PM		 274static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
275{
276 if (!(cflag & CRTSCTS))
277 __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */
278}
b0c50ad7 279#elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A)
d5701647
PM		 280static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
281{
282 if (!(cflag & CRTSCTS))
283 __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */
284}
b7a76e4b 285#else
d5701647
PM		 286static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
287{
288 /* Nothing to do */
1da177e4 289}
e108b2ca
PM		 290#endif
291
32351a28
PM		 292#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
293 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
55ba99eb
KM		 294 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
295 defined(CONFIG_CPU_SUBTYPE_SH7786)
73a19e4c 296static int scif_txfill(struct uart_port *port)
e108b2ca 297{
73a19e4c 298 return sci_in(port, SCTFDR) & 0xff;
e108b2ca
PM		 299}
300
73a19e4c
GL		 301static int scif_txroom(struct uart_port *port)
302{
303 return SCIF_TXROOM_MAX - scif_txfill(port);
304}
305
306static int scif_rxfill(struct uart_port *port)
e108b2ca 307{
cae167d3 308 return sci_in(port, SCRFDR) & 0xff;
e108b2ca 309}
c63847a3 310#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
73a19e4c 311static int scif_txfill(struct uart_port *port)
c63847a3 312{
73a19e4c
GL		 313 if (port->mapbase == 0xffe00000 ||
314 port->mapbase == 0xffe08000)
e7c98dc7 315 /* SCIF0/1*/
73a19e4c
GL		 316 return sci_in(port, SCTFDR) & 0xff;
317 else
e7c98dc7 318 /* SCIF2 */
73a19e4c
GL		 319 return sci_in(port, SCFDR) >> 8;
320}
321
322static int scif_txroom(struct uart_port *port)
323{
324 if (port->mapbase == 0xffe00000 ||
325 port->mapbase == 0xffe08000)
326 /* SCIF0/1*/
327 return SCIF_TXROOM_MAX - scif_txfill(port);
328 else
329 /* SCIF2 */
330 return SCIF2_TXROOM_MAX - scif_txfill(port);
c63847a3
NI		 331}
332
73a19e4c 333static int scif_rxfill(struct uart_port *port)
c63847a3 334{
e7c98dc7
MT		 335 if ((port->mapbase == 0xffe00000) ||
336 (port->mapbase == 0xffe08000)) {
337 /* SCIF0/1*/
c63847a3 338 return sci_in(port, SCRFDR) & 0xff;
e7c98dc7
MT		 339 } else {
340 /* SCIF2 */
c63847a3 341 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
e7c98dc7 342 }
c63847a3 343}
e108b2ca 344#else
73a19e4c 345static int scif_txfill(struct uart_port *port)
e108b2ca 346{
73a19e4c 347 return sci_in(port, SCFDR) >> 8;
e108b2ca 348}
1da177e4 349
73a19e4c
GL		 350static int scif_txroom(struct uart_port *port)
351{
352 return SCIF_TXROOM_MAX - scif_txfill(port);
353}
354
355static int scif_rxfill(struct uart_port *port)
e108b2ca
PM		 356{
357 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
358}
1da177e4 359#endif
1da177e4 360
73a19e4c 361static int sci_txfill(struct uart_port *port)
e108b2ca 362{
73a19e4c 363 return !(sci_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 364}
365
73a19e4c
GL		 366static int sci_txroom(struct uart_port *port)
367{
368 return !sci_txfill(port);
369}
370
371static int sci_rxfill(struct uart_port *port)
e108b2ca 372{
e7c98dc7 373 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 374}
375
1da177e4
LT		 376/* ********************************************************************** *
377 * the interrupt related routines *
378 * ********************************************************************** */
379
380static void sci_transmit_chars(struct uart_port *port)
381{
ebd2c8f6 382 struct circ_buf *xmit = &port->state->xmit;
1da177e4 383 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 384 unsigned short status;
385 unsigned short ctrl;
e108b2ca 386 int count;
1da177e4
LT		 387
388 status = sci_in(port, SCxSR);
389 if (!(status & SCxSR_TDxE(port))) {
1da177e4 390 ctrl = sci_in(port, SCSCR);
e7c98dc7 391 if (uart_circ_empty(xmit))
1da177e4 392 ctrl &= ~SCI_CTRL_FLAGS_TIE;
e7c98dc7 393 else
1da177e4 394 ctrl |= SCI_CTRL_FLAGS_TIE;
1da177e4 395 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 396 return;
397 }
398
1a22f08d 399 if (port->type == PORT_SCI)
e108b2ca 400 count = sci_txroom(port);
1a22f08d
YS		 401 else
402 count = scif_txroom(port);
1da177e4
LT		 403
404 do {
405 unsigned char c;
406
407 if (port->x_char) {
408 c = port->x_char;
409 port->x_char = 0;
410 } else if (!uart_circ_empty(xmit) && !stopped) {
411 c = xmit->buf[xmit->tail];
412 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
413 } else {
414 break;
415 }
416
417 sci_out(port, SCxTDR, c);
418
419 port->icount.tx++;
420 } while (--count > 0);
421
422 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
423
424 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
425 uart_write_wakeup(port);
426 if (uart_circ_empty(xmit)) {
b129a8cc 427 sci_stop_tx(port);
1da177e4 428 } else {
1da177e4
LT		 429 ctrl = sci_in(port, SCSCR);
430
1a22f08d 431 if (port->type != PORT_SCI) {
1da177e4
LT		 432 sci_in(port, SCxSR); /* Dummy read */
433 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
434 }
1da177e4
LT		 435
436 ctrl |= SCI_CTRL_FLAGS_TIE;
437 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 438 }
439}
440
441/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 442#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 443
7d12e780 444static inline void sci_receive_chars(struct uart_port *port)
1da177e4 445{
e7c98dc7 446 struct sci_port *sci_port = to_sci_port(port);
ebd2c8f6 447 struct tty_struct *tty = port->state->port.tty;
1da177e4
LT		 448 int i, count, copied = 0;
449 unsigned short status;
33f0f88f 450 unsigned char flag;
1da177e4
LT		 451
452 status = sci_in(port, SCxSR);
453 if (!(status & SCxSR_RDxF(port)))
454 return;
455
456 while (1) {
1a22f08d 457 if (port->type == PORT_SCI)
73a19e4c 458 count = sci_rxfill(port);
1a22f08d 459 else
73a19e4c 460 count = scif_rxfill(port);
1da177e4
LT		 461
462 /* Don't copy more bytes than there is room for in the buffer */
33f0f88f 463 count = tty_buffer_request_room(tty, count);
1da177e4
LT		 464
465 /* If for any reason we can't copy more data, we're done! */
466 if (count == 0)
467 break;
468
469 if (port->type == PORT_SCI) {
470 char c = sci_in(port, SCxRDR);
e7c98dc7
MT		 471 if (uart_handle_sysrq_char(port, c) ||
472 sci_port->break_flag)
1da177e4 473 count = 0;
e7c98dc7 474 else
e108b2ca 475 tty_insert_flip_char(tty, c, TTY_NORMAL);
1da177e4 476 } else {
e7c98dc7 477 for (i = 0; i < count; i++) {
1da177e4
LT		 478 char c = sci_in(port, SCxRDR);
479 status = sci_in(port, SCxSR);
480#if defined(CONFIG_CPU_SH3)
481 /* Skip "chars" during break */
e108b2ca 482 if (sci_port->break_flag) {
1da177e4
LT		 483 if ((c == 0) &&
484 (status & SCxSR_FER(port))) {
485 count--; i--;
486 continue;
487 }
e108b2ca 488
1da177e4 489 /* Nonzero => end-of-break */
762c69e3 490 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 491 sci_port->break_flag = 0;
492
1da177e4
LT		 493 if (STEPFN(c)) {
494 count--; i--;
495 continue;
496 }
497 }
498#endif /* CONFIG_CPU_SH3 */
7d12e780 499 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 500 count--; i--;
501 continue;
502 }
503
504 /* Store data and status */
73a19e4c 505 if (status & SCxSR_FER(port)) {
33f0f88f 506 flag = TTY_FRAME;
762c69e3 507 dev_notice(port->dev, "frame error\n");
73a19e4c 508 } else if (status & SCxSR_PER(port)) {
33f0f88f 509 flag = TTY_PARITY;
762c69e3 510 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 511 } else
512 flag = TTY_NORMAL;
762c69e3 513
33f0f88f 514 tty_insert_flip_char(tty, c, flag);
1da177e4
LT		 515 }
516 }
517
518 sci_in(port, SCxSR); /* dummy read */
519 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
520
1da177e4
LT		 521 copied += count;
522 port->icount.rx += count;
523 }
524
525 if (copied) {
526 /* Tell the rest of the system the news. New characters! */
527 tty_flip_buffer_push(tty);
528 } else {
529 sci_in(port, SCxSR); /* dummy read */
530 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
531 }
532}
533
534#define SCI_BREAK_JIFFIES (HZ/20)
535/* The sci generates interrupts during the break,
536 * 1 per millisecond or so during the break period, for 9600 baud.
537 * So dont bother disabling interrupts.
538 * But dont want more than 1 break event.
539 * Use a kernel timer to periodically poll the rx line until
540 * the break is finished.
541 */
542static void sci_schedule_break_timer(struct sci_port *port)
543{
544 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
545 add_timer(&port->break_timer);
546}
547/* Ensure that two consecutive samples find the break over. */
548static void sci_break_timer(unsigned long data)
549{
e108b2ca
PM		 550 struct sci_port *port = (struct sci_port *)data;
551
552 if (sci_rxd_in(&port->port) == 0) {
1da177e4 553 port->break_flag = 1;
e108b2ca
PM		 554 sci_schedule_break_timer(port);
555 } else if (port->break_flag == 1) {
1da177e4
LT		 556 /* break is over. */
557 port->break_flag = 2;
e108b2ca
PM		 558 sci_schedule_break_timer(port);
559 } else
560 port->break_flag = 0;
1da177e4
LT		 561}
562
563static inline int sci_handle_errors(struct uart_port *port)
564{
565 int copied = 0;
566 unsigned short status = sci_in(port, SCxSR);
ebd2c8f6 567 struct tty_struct *tty = port->state->port.tty;
1da177e4 568
e108b2ca 569 if (status & SCxSR_ORER(port)) {
1da177e4 570 /* overrun error */
e108b2ca 571 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
33f0f88f 572 copied++;
762c69e3
PM		 573
574 dev_notice(port->dev, "overrun error");
1da177e4
LT		 575 }
576
e108b2ca 577 if (status & SCxSR_FER(port)) {
1da177e4
LT		 578 if (sci_rxd_in(port) == 0) {
579 /* Notify of BREAK */
e7c98dc7 580 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 581
582 if (!sci_port->break_flag) {
583 sci_port->break_flag = 1;
584 sci_schedule_break_timer(sci_port);
585
1da177e4 586 /* Do sysrq handling. */
e108b2ca 587 if (uart_handle_break(port))
1da177e4 588 return 0;
762c69e3
PM		 589
590 dev_dbg(port->dev, "BREAK detected\n");
591
e108b2ca 592 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
e7c98dc7
MT		 593 copied++;
594 }
595
e108b2ca 596 } else {
1da177e4 597 /* frame error */
e108b2ca 598 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
33f0f88f 599 copied++;
762c69e3
PM		 600
601 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 602 }
603 }
604
e108b2ca 605 if (status & SCxSR_PER(port)) {
1da177e4 606 /* parity error */
e108b2ca
PM		 607 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
608 copied++;
762c69e3
PM		 609
610 dev_notice(port->dev, "parity error");
1da177e4
LT		 611 }
612
33f0f88f 613 if (copied)
1da177e4 614 tty_flip_buffer_push(tty);
1da177e4
LT		 615
616 return copied;
617}
618
d830fa45
PM		 619static inline int sci_handle_fifo_overrun(struct uart_port *port)
620{
ebd2c8f6 621 struct tty_struct *tty = port->state->port.tty;
d830fa45
PM		 622 int copied = 0;
623
624 if (port->type != PORT_SCIF)
625 return 0;
626
627 if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
628 sci_out(port, SCLSR, 0);
629
630 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
631 tty_flip_buffer_push(tty);
632
633 dev_notice(port->dev, "overrun error\n");
634 copied++;
635 }
636
637 return copied;
638}
639
1da177e4
LT		 640static inline int sci_handle_breaks(struct uart_port *port)
641{
642 int copied = 0;
643 unsigned short status = sci_in(port, SCxSR);
ebd2c8f6 644 struct tty_struct *tty = port->state->port.tty;
a5660ada 645 struct sci_port *s = to_sci_port(port);
1da177e4 646
0b3d4ef6
PM		 647 if (uart_handle_break(port))
648 return 0;
649
b7a76e4b 650 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 651#if defined(CONFIG_CPU_SH3)
652 /* Debounce break */
653 s->break_flag = 1;
654#endif
655 /* Notify of BREAK */
e108b2ca 656 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
33f0f88f 657 copied++;
762c69e3
PM		 658
659 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 660 }
661
33f0f88f 662 if (copied)
1da177e4 663 tty_flip_buffer_push(tty);
e108b2ca 664
d830fa45
PM		 665 copied += sci_handle_fifo_overrun(port);
666
1da177e4
LT		 667 return copied;
668}
669
73a19e4c 670static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1da177e4 671{
73a19e4c
GL		 672#ifdef CONFIG_SERIAL_SH_SCI_DMA
673 struct uart_port *port = ptr;
674 struct sci_port *s = to_sci_port(port);
675
676 if (s->chan_rx) {
677 unsigned long tout;
678 u16 scr = sci_in(port, SCSCR);
679 u16 ssr = sci_in(port, SCxSR);
680
681 /* Disable future Rx interrupts */
682 sci_out(port, SCSCR, scr & ~SCI_CTRL_FLAGS_RIE);
683 /* Clear current interrupt */
684 sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
685 /* Calculate delay for 1.5 DMA buffers */
686 tout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
687 port->fifosize / 2;
c6efd46b 688 dev_dbg(port->dev, "Rx IRQ: setup timeout in %lu ms\n",
73a19e4c
GL		 689 tout * 1000 / HZ);
690 if (tout < 2)
691 tout = 2;
692 mod_timer(&s->rx_timer, jiffies + tout);
693
694 return IRQ_HANDLED;
695 }
696#endif
697
1da177e4
LT		 698 /* I think sci_receive_chars has to be called irrespective
699 * of whether the I_IXOFF is set, otherwise, how is the interrupt
700 * to be disabled?
701 */
73a19e4c 702 sci_receive_chars(ptr);
1da177e4
LT		 703
704 return IRQ_HANDLED;
705}
706
7d12e780 707static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 708{
709 struct uart_port *port = ptr;
fd78a76a 710 unsigned long flags;
1da177e4 711
fd78a76a 712 spin_lock_irqsave(&port->lock, flags);
1da177e4 713 sci_transmit_chars(port);
fd78a76a 714 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 715
716 return IRQ_HANDLED;
717}
718
7d12e780 719static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 720{
721 struct uart_port *port = ptr;
722
723 /* Handle errors */
724 if (port->type == PORT_SCI) {
725 if (sci_handle_errors(port)) {
726 /* discard character in rx buffer */
727 sci_in(port, SCxSR);
728 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
729 }
730 } else {
d830fa45 731 sci_handle_fifo_overrun(port);
7d12e780 732 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 733 }
734
735 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
736
737 /* Kick the transmission */
7d12e780 738 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 739
740 return IRQ_HANDLED;
741}
742
7d12e780 743static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 744{
745 struct uart_port *port = ptr;
746
747 /* Handle BREAKs */
748 sci_handle_breaks(port);
749 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
750
751 return IRQ_HANDLED;
752}
753
7d12e780 754static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 755{
44e18e9e 756 unsigned short ssr_status, scr_status, err_enabled;
a8884e34 757 struct uart_port *port = ptr;
73a19e4c 758 struct sci_port *s = to_sci_port(port);
a8884e34 759 irqreturn_t ret = IRQ_NONE;
1da177e4 760
e7c98dc7
MT		 761 ssr_status = sci_in(port, SCxSR);
762 scr_status = sci_in(port, SCSCR);
44e18e9e 763 err_enabled = scr_status & (SCI_CTRL_FLAGS_REIE | SCI_CTRL_FLAGS_RIE);
1da177e4
LT		 764
765 /* Tx Interrupt */
73a19e4c
GL		 766 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCI_CTRL_FLAGS_TIE) &&
767 !s->chan_tx)
a8884e34 768 ret = sci_tx_interrupt(irq, ptr);
73a19e4c
GL		 769 /*
770 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
771 * DR flags
772 */
773 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
774 (scr_status & SCI_CTRL_FLAGS_RIE))
a8884e34 775 ret = sci_rx_interrupt(irq, ptr);
1da177e4 776 /* Error Interrupt */
dd4da3a5 777 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
a8884e34 778 ret = sci_er_interrupt(irq, ptr);
1da177e4 779 /* Break Interrupt */
dd4da3a5 780 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
a8884e34 781 ret = sci_br_interrupt(irq, ptr);
1da177e4 782
a8884e34 783 return ret;
1da177e4
LT		 784}
785
1da177e4
LT		 786/*
787 * Here we define a transistion notifier so that we can update all of our
788 * ports' baud rate when the peripheral clock changes.
789 */
e108b2ca
PM		 790static int sci_notifier(struct notifier_block *self,
791 unsigned long phase, void *p)
1da177e4 792{
e552de24
MD		 793 struct sh_sci_priv *priv = container_of(self,
794 struct sh_sci_priv, clk_nb);
795 struct sci_port *sci_port;
796 unsigned long flags;
1da177e4
LT		 797
798 if ((phase == CPUFREQ_POSTCHANGE) ||
e552de24
MD		 799 (phase == CPUFREQ_RESUMECHANGE)) {
800 spin_lock_irqsave(&priv->lock, flags);
801 list_for_each_entry(sci_port, &priv->ports, node)
501b825d 802 sci_port->port.uartclk = clk_get_rate(sci_port->dclk);
e552de24
MD		 803 spin_unlock_irqrestore(&priv->lock, flags);
804 }
1da177e4 805
1da177e4
LT		 806 return NOTIFY_OK;
807}
501b825d
MD		 808
809static void sci_clk_enable(struct uart_port *port)
810{
811 struct sci_port *sci_port = to_sci_port(port);
812
813 clk_enable(sci_port->dclk);
814 sci_port->port.uartclk = clk_get_rate(sci_port->dclk);
815
816 if (sci_port->iclk)
817 clk_enable(sci_port->iclk);
818}
819
820static void sci_clk_disable(struct uart_port *port)
821{
822 struct sci_port *sci_port = to_sci_port(port);
823
824 if (sci_port->iclk)
825 clk_disable(sci_port->iclk);
826
827 clk_disable(sci_port->dclk);
828}
1da177e4
LT		 829
830static int sci_request_irq(struct sci_port *port)
831{
832 int i;
7d12e780 833 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
1da177e4
LT		 834 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
835 sci_br_interrupt,
836 };
837 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
838 "SCI Transmit Data Empty", "SCI Break" };
839
840 if (port->irqs[0] == port->irqs[1]) {
762c69e3 841 if (unlikely(!port->irqs[0]))
1da177e4 842 return -ENODEV;
e108b2ca
PM		 843
844 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
35f3c518 845 IRQF_DISABLED, "sci", port)) {
762c69e3 846 dev_err(port->port.dev, "Can't allocate IRQ\n");
1da177e4
LT		 847 return -ENODEV;
848 }
849 } else {
850 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
762c69e3 851 if (unlikely(!port->irqs[i]))
1da177e4 852 continue;
762c69e3 853
e108b2ca 854 if (request_irq(port->irqs[i], handlers[i],
35f3c518 855 IRQF_DISABLED, desc[i], port)) {
762c69e3 856 dev_err(port->port.dev, "Can't allocate IRQ\n");
1da177e4
LT		 857 return -ENODEV;
858 }
859 }
860 }
861
862 return 0;
863}
864
865static void sci_free_irq(struct sci_port *port)
866{
867 int i;
868
762c69e3
PM		 869 if (port->irqs[0] == port->irqs[1])
870 free_irq(port->irqs[0], port);
871 else {
1da177e4
LT		 872 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
873 if (!port->irqs[i])
874 continue;
875
876 free_irq(port->irqs[i], port);
877 }
878 }
879}
880
881static unsigned int sci_tx_empty(struct uart_port *port)
882{
b1516803 883 unsigned short status = sci_in(port, SCxSR);
73a19e4c
GL		 884 unsigned short in_tx_fifo = scif_txfill(port);
885
886 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 887}
888
889static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
890{
891 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
892 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
893 /* If you have signals for DTR and DCD, please implement here. */
894}
895
896static unsigned int sci_get_mctrl(struct uart_port *port)
897{
73a19e4c 898 /* This routine is used for getting signals of: DTR, DCD, DSR, RI,
1da177e4
LT		 899 and CTS/RTS */
900
901 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
902}
903
73a19e4c
GL		 904#ifdef CONFIG_SERIAL_SH_SCI_DMA
905static void sci_dma_tx_complete(void *arg)
906{
907 struct sci_port *s = arg;
908 struct uart_port *port = &s->port;
909 struct circ_buf *xmit = &port->state->xmit;
910 unsigned long flags;
911
912 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
913
914 spin_lock_irqsave(&port->lock, flags);
915
916 xmit->tail += s->sg_tx.length;
917 xmit->tail &= UART_XMIT_SIZE - 1;
918
919 port->icount.tx += s->sg_tx.length;
920
921 async_tx_ack(s->desc_tx);
922 s->cookie_tx = -EINVAL;
923 s->desc_tx = NULL;
924
925 spin_unlock_irqrestore(&port->lock, flags);
926
927 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
928 uart_write_wakeup(port);
929
930 if (uart_circ_chars_pending(xmit))
931 schedule_work(&s->work_tx);
932}
933
934/* Locking: called with port lock held */
935static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty,
936 size_t count)
937{
938 struct uart_port *port = &s->port;
939 int i, active, room;
940
941 room = tty_buffer_request_room(tty, count);
942
943 if (s->active_rx == s->cookie_rx[0]) {
944 active = 0;
945 } else if (s->active_rx == s->cookie_rx[1]) {
946 active = 1;
947 } else {
948 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
949 return 0;
950 }
951
952 if (room < count)
953 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
954 count - room);
955 if (!room)
956 return room;
957
958 for (i = 0; i < room; i++)
959 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
960 TTY_NORMAL);
961
962 port->icount.rx += room;
963
964 return room;
965}
966
967static void sci_dma_rx_complete(void *arg)
968{
969 struct sci_port *s = arg;
970 struct uart_port *port = &s->port;
971 struct tty_struct *tty = port->state->port.tty;
972 unsigned long flags;
973 int count;
974
975 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
976
977 spin_lock_irqsave(&port->lock, flags);
978
979 count = sci_dma_rx_push(s, tty, s->buf_len_rx);
980
981 mod_timer(&s->rx_timer, jiffies + msecs_to_jiffies(5));
982
983 spin_unlock_irqrestore(&port->lock, flags);
984
985 if (count)
986 tty_flip_buffer_push(tty);
987
988 schedule_work(&s->work_rx);
989}
990
991static void sci_start_rx(struct uart_port *port);
992static void sci_start_tx(struct uart_port *port);
993
994static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
995{
996 struct dma_chan *chan = s->chan_rx;
997 struct uart_port *port = &s->port;
73a19e4c
GL		 998
999 s->chan_rx = NULL;
1000 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1001 dma_release_channel(chan);
1002 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1003 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1004 if (enable_pio)
1005 sci_start_rx(port);
1006}
1007
1008static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1009{
1010 struct dma_chan *chan = s->chan_tx;
1011 struct uart_port *port = &s->port;
73a19e4c
GL		 1012
1013 s->chan_tx = NULL;
1014 s->cookie_tx = -EINVAL;
1015 dma_release_channel(chan);
1016 if (enable_pio)
1017 sci_start_tx(port);
1018}
1019
1020static void sci_submit_rx(struct sci_port *s)
1021{
1022 struct dma_chan *chan = s->chan_rx;
1023 int i;
1024
1025 for (i = 0; i < 2; i++) {
1026 struct scatterlist *sg = &s->sg_rx[i];
1027 struct dma_async_tx_descriptor *desc;
1028
1029 desc = chan->device->device_prep_slave_sg(chan,
1030 sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT);
1031
1032 if (desc) {
1033 s->desc_rx[i] = desc;
1034 desc->callback = sci_dma_rx_complete;
1035 desc->callback_param = s;
1036 s->cookie_rx[i] = desc->tx_submit(desc);
1037 }
1038
1039 if (!desc || s->cookie_rx[i] < 0) {
1040 if (i) {
1041 async_tx_ack(s->desc_rx[0]);
1042 s->cookie_rx[0] = -EINVAL;
1043 }
1044 if (desc) {
1045 async_tx_ack(desc);
1046 s->cookie_rx[i] = -EINVAL;
1047 }
1048 dev_warn(s->port.dev,
1049 "failed to re-start DMA, using PIO\n");
1050 sci_rx_dma_release(s, true);
1051 return;
1052 }
1053 }
1054
1055 s->active_rx = s->cookie_rx[0];
1056
1057 dma_async_issue_pending(chan);
1058}
1059
1060static void work_fn_rx(struct work_struct *work)
1061{
1062 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1063 struct uart_port *port = &s->port;
1064 struct dma_async_tx_descriptor *desc;
1065 int new;
1066
1067 if (s->active_rx == s->cookie_rx[0]) {
1068 new = 0;
1069 } else if (s->active_rx == s->cookie_rx[1]) {
1070 new = 1;
1071 } else {
1072 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1073 return;
1074 }
1075 desc = s->desc_rx[new];
1076
1077 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1078 DMA_SUCCESS) {
1079 /* Handle incomplete DMA receive */
1080 struct tty_struct *tty = port->state->port.tty;
1081 struct dma_chan *chan = s->chan_rx;
1082 struct sh_desc *sh_desc = container_of(desc, struct sh_desc,
1083 async_tx);
1084 unsigned long flags;
1085 int count;
1086
1087 chan->device->device_terminate_all(chan);
1088 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1089 sh_desc->partial, sh_desc->cookie);
1090
1091 spin_lock_irqsave(&port->lock, flags);
1092 count = sci_dma_rx_push(s, tty, sh_desc->partial);
1093 spin_unlock_irqrestore(&port->lock, flags);
1094
1095 if (count)
1096 tty_flip_buffer_push(tty);
1097
1098 sci_submit_rx(s);
1099
1100 return;
1101 }
1102
1103 s->cookie_rx[new] = desc->tx_submit(desc);
1104 if (s->cookie_rx[new] < 0) {
1105 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1106 sci_rx_dma_release(s, true);
1107 return;
1108 }
1109
1110 dev_dbg(port->dev, "%s: cookie %d #%d\n", __func__,
1111 s->cookie_rx[new], new);
1112
1113 s->active_rx = s->cookie_rx[!new];
1114}
1115
1116static void work_fn_tx(struct work_struct *work)
1117{
1118 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1119 struct dma_async_tx_descriptor *desc;
1120 struct dma_chan *chan = s->chan_tx;
1121 struct uart_port *port = &s->port;
1122 struct circ_buf *xmit = &port->state->xmit;
1123 struct scatterlist *sg = &s->sg_tx;
1124
1125 /*
1126 * DMA is idle now.
1127 * Port xmit buffer is already mapped, and it is one page... Just adjust
1128 * offsets and lengths. Since it is a circular buffer, we have to
1129 * transmit till the end, and then the rest. Take the port lock to get a
1130 * consistent xmit buffer state.
1131 */
1132 spin_lock_irq(&port->lock);
1133 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1134 sg->dma_address = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1135 sg->offset;
1136 sg->length = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1137 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1138 sg->dma_length = sg->length;
1139 spin_unlock_irq(&port->lock);
1140
1141 BUG_ON(!sg->length);
1142
1143 desc = chan->device->device_prep_slave_sg(chan,
1144 sg, s->sg_len_tx, DMA_TO_DEVICE,
1145 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1146 if (!desc) {
1147 /* switch to PIO */
1148 sci_tx_dma_release(s, true);
1149 return;
1150 }
1151
1152 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1153
1154 spin_lock_irq(&port->lock);
1155 s->desc_tx = desc;
1156 desc->callback = sci_dma_tx_complete;
1157 desc->callback_param = s;
1158 spin_unlock_irq(&port->lock);
1159 s->cookie_tx = desc->tx_submit(desc);
1160 if (s->cookie_tx < 0) {
1161 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1162 /* switch to PIO */
1163 sci_tx_dma_release(s, true);
1164 return;
1165 }
1166
1167 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1168 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1169
1170 dma_async_issue_pending(chan);
1171}
1172#endif
1173
b129a8cc 1174static void sci_start_tx(struct uart_port *port)
1da177e4 1175{
e108b2ca 1176 unsigned short ctrl;
1da177e4 1177
73a19e4c
GL		 1178#ifdef CONFIG_SERIAL_SH_SCI_DMA
1179 struct sci_port *s = to_sci_port(port);
1180
1181 if (s->chan_tx) {
1182 if (!uart_circ_empty(&s->port.state->xmit) && s->cookie_tx < 0)
1183 schedule_work(&s->work_tx);
1184
1185 return;
1186 }
1187#endif
1188
e108b2ca
PM		 1189 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1190 ctrl = sci_in(port, SCSCR);
1191 ctrl |= SCI_CTRL_FLAGS_TIE;
1192 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1193}
1194
b129a8cc 1195static void sci_stop_tx(struct uart_port *port)
1da177e4 1196{
1da177e4
LT		 1197 unsigned short ctrl;
1198
1199 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1da177e4
LT		 1200 ctrl = sci_in(port, SCSCR);
1201 ctrl &= ~SCI_CTRL_FLAGS_TIE;
1202 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1203}
1204
73a19e4c 1205static void sci_start_rx(struct uart_port *port)
1da177e4 1206{
73a19e4c 1207 unsigned short ctrl = SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
1da177e4
LT		 1208
1209 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
73a19e4c 1210 ctrl |= sci_in(port, SCSCR);
1da177e4 1211 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1212}
1213
1214static void sci_stop_rx(struct uart_port *port)
1215{
1da177e4
LT		 1216 unsigned short ctrl;
1217
1218 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
1da177e4
LT		 1219 ctrl = sci_in(port, SCSCR);
1220 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
1221 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1222}
1223
1224static void sci_enable_ms(struct uart_port *port)
1225{
1226 /* Nothing here yet .. */
1227}
1228
1229static void sci_break_ctl(struct uart_port *port, int break_state)
1230{
1231 /* Nothing here yet .. */
1232}
1233
73a19e4c
GL		 1234#ifdef CONFIG_SERIAL_SH_SCI_DMA
1235static bool filter(struct dma_chan *chan, void *slave)
1236{
1237 struct sh_dmae_slave *param = slave;
1238
1239 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1240 param->slave_id);
1241
1242 if (param->dma_dev == chan->device->dev) {
1243 chan->private = param;
1244 return true;
1245 } else {
1246 return false;
1247 }
1248}
1249
1250static void rx_timer_fn(unsigned long arg)
1251{
1252 struct sci_port *s = (struct sci_port *)arg;
1253 struct uart_port *port = &s->port;
1254
1255 u16 scr = sci_in(port, SCSCR);
1256 sci_out(port, SCSCR, scr | SCI_CTRL_FLAGS_RIE);
1257 dev_dbg(port->dev, "DMA Rx timed out\n");
1258 schedule_work(&s->work_rx);
1259}
1260
1261static void sci_request_dma(struct uart_port *port)
1262{
1263 struct sci_port *s = to_sci_port(port);
1264 struct sh_dmae_slave *param;
1265 struct dma_chan *chan;
1266 dma_cap_mask_t mask;
1267 int nent;
1268
1269 dev_dbg(port->dev, "%s: port %d DMA %p\n", __func__,
1270 port->line, s->dma_dev);
1271
1272 if (!s->dma_dev)
1273 return;
1274
1275 dma_cap_zero(mask);
1276 dma_cap_set(DMA_SLAVE, mask);
1277
1278 param = &s->param_tx;
1279
1280 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1281 param->slave_id = s->slave_tx;
1282 param->dma_dev = s->dma_dev;
1283
1284 s->cookie_tx = -EINVAL;
1285 chan = dma_request_channel(mask, filter, param);
1286 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1287 if (chan) {
1288 s->chan_tx = chan;
1289 sg_init_table(&s->sg_tx, 1);
1290 /* UART circular tx buffer is an aligned page. */
1291 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1292 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1293 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1294 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1295 if (!nent)
1296 sci_tx_dma_release(s, false);
1297 else
1298 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1299 sg_dma_len(&s->sg_tx),
1300 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1301
1302 s->sg_len_tx = nent;
1303
1304 INIT_WORK(&s->work_tx, work_fn_tx);
1305 }
1306
1307 param = &s->param_rx;
1308
1309 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1310 param->slave_id = s->slave_rx;
1311 param->dma_dev = s->dma_dev;
1312
1313 chan = dma_request_channel(mask, filter, param);
1314 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1315 if (chan) {
1316 dma_addr_t dma[2];
1317 void *buf[2];
1318 int i;
1319
1320 s->chan_rx = chan;
1321
1322 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1323 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1324 &dma[0], GFP_KERNEL);
1325
1326 if (!buf[0]) {
1327 dev_warn(port->dev,
1328 "failed to allocate dma buffer, using PIO\n");
1329 sci_rx_dma_release(s, true);
1330 return;
1331 }
1332
1333 buf[1] = buf[0] + s->buf_len_rx;
1334 dma[1] = dma[0] + s->buf_len_rx;
1335
1336 for (i = 0; i < 2; i++) {
1337 struct scatterlist *sg = &s->sg_rx[i];
1338
1339 sg_init_table(sg, 1);
1340 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1341 (int)buf[i] & ~PAGE_MASK);
1342 sg->dma_address = dma[i];
1343 sg->dma_length = sg->length;
1344 }
1345
1346 INIT_WORK(&s->work_rx, work_fn_rx);
1347 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1348
1349 sci_submit_rx(s);
1350 }
1351}
1352
1353static void sci_free_dma(struct uart_port *port)
1354{
1355 struct sci_port *s = to_sci_port(port);
1356
1357 if (!s->dma_dev)
1358 return;
1359
1360 if (s->chan_tx)
1361 sci_tx_dma_release(s, false);
1362 if (s->chan_rx)
1363 sci_rx_dma_release(s, false);
1364}
1365#endif
1366
1da177e4
LT		 1367static int sci_startup(struct uart_port *port)
1368{
a5660ada 1369 struct sci_port *s = to_sci_port(port);
1da177e4 1370
73a19e4c
GL		 1371 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1372
e108b2ca
PM		 1373 if (s->enable)
1374 s->enable(port);
1da177e4
LT		 1375
1376 sci_request_irq(s);
73a19e4c
GL		 1377#ifdef CONFIG_SERIAL_SH_SCI_DMA
1378 sci_request_dma(port);
1379#endif
d656901b 1380 sci_start_tx(port);
73a19e4c 1381 sci_start_rx(port);
1da177e4
LT		 1382
1383 return 0;
1384}
1385
1386static void sci_shutdown(struct uart_port *port)
1387{
a5660ada 1388 struct sci_port *s = to_sci_port(port);
1da177e4 1389
73a19e4c
GL		 1390 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1391
1da177e4 1392 sci_stop_rx(port);
b129a8cc 1393 sci_stop_tx(port);
73a19e4c
GL		 1394#ifdef CONFIG_SERIAL_SH_SCI_DMA
1395 sci_free_dma(port);
1396#endif
1da177e4
LT		 1397 sci_free_irq(s);
1398
e108b2ca
PM		 1399 if (s->disable)
1400 s->disable(port);
1da177e4
LT		 1401}
1402
606d099c
AC		 1403static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1404 struct ktermios *old)
1da177e4 1405{
154280fd 1406 unsigned int status, baud, smr_val, max_baud;
a2159b52 1407 int t = -1;
1da177e4 1408
154280fd
MD		 1409 /*
1410 * earlyprintk comes here early on with port->uartclk set to zero.
1411 * the clock framework is not up and running at this point so here
1412 * we assume that 115200 is the maximum baud rate. please note that
1413 * the baud rate is not programmed during earlyprintk - it is assumed
1414 * that the previous boot loader has enabled required clocks and
1415 * setup the baud rate generator hardware for us already.
1416 */
1417 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1418
1419 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1420 if (likely(baud && port->uartclk))
a2159b52 1421 t = SCBRR_VALUE(baud, port->uartclk);
e108b2ca 1422
1da177e4
LT		 1423 do {
1424 status = sci_in(port, SCxSR);
1425 } while (!(status & SCxSR_TEND(port)));
1426
1427 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1428
1a22f08d 1429 if (port->type != PORT_SCI)
1da177e4 1430 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1da177e4
LT		 1431
1432 smr_val = sci_in(port, SCSMR) & 3;
1433 if ((termios->c_cflag & CSIZE) == CS7)
1434 smr_val |= 0x40;
1435 if (termios->c_cflag & PARENB)
1436 smr_val |= 0x20;
1437 if (termios->c_cflag & PARODD)
1438 smr_val |= 0x30;
1439 if (termios->c_cflag & CSTOPB)
1440 smr_val |= 0x08;
1441
1442 uart_update_timeout(port, termios->c_cflag, baud);
1443
1444 sci_out(port, SCSMR, smr_val);
1445
73a19e4c
GL		 1446 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t,
1447 SCSCR_INIT(port));
1448
1da177e4 1449 if (t > 0) {
e7c98dc7 1450 if (t >= 256) {
1da177e4
LT		 1451 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1452 t >>= 2;
e7c98dc7 1453 } else
1da177e4 1454 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
e7c98dc7 1455
1da177e4
LT		 1456 sci_out(port, SCBRR, t);
1457 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1458 }
1459
d5701647
PM		 1460 sci_init_pins(port, termios->c_cflag);
1461 sci_out(port, SCFCR, (termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0);
b7a76e4b 1462
1da177e4
LT		 1463 sci_out(port, SCSCR, SCSCR_INIT(port));
1464
1465 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 1466 sci_start_rx(port);
1da177e4
LT		 1467}
1468
1469static const char *sci_type(struct uart_port *port)
1470{
1471 switch (port->type) {
e7c98dc7
MT		 1472 case PORT_IRDA:
1473 return "irda";
1474 case PORT_SCI:
1475 return "sci";
1476 case PORT_SCIF:
1477 return "scif";
1478 case PORT_SCIFA:
1479 return "scifa";
1da177e4
LT		 1480 }
1481
fa43972f 1482 return NULL;
1da177e4
LT		 1483}
1484
1485static void sci_release_port(struct uart_port *port)
1486{
1487 /* Nothing here yet .. */
1488}
1489
1490static int sci_request_port(struct uart_port *port)
1491{
1492 /* Nothing here yet .. */
1493 return 0;
1494}
1495
1496static void sci_config_port(struct uart_port *port, int flags)
1497{
a5660ada 1498 struct sci_port *s = to_sci_port(port);
1da177e4
LT		 1499
1500 port->type = s->type;
1501
08f8cb31
MD		 1502 if (port->membase)
1503 return;
1504
1505 if (port->flags & UPF_IOREMAP) {
7ff731ae 1506 port->membase = ioremap_nocache(port->mapbase, 0x40);
08f8cb31
MD		 1507
1508 if (IS_ERR(port->membase))
1509 dev_err(port->dev, "can't remap port#%d\n", port->line);
1510 } else {
1511 /*
1512 * For the simple (and majority of) cases where we don't
1513 * need to do any remapping, just cast the cookie
1514 * directly.
1515 */
1516 port->membase = (void __iomem *)port->mapbase;
7ff731ae 1517 }
1da177e4
LT		 1518}
1519
1520static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1521{
a5660ada 1522 struct sci_port *s = to_sci_port(port);
1da177e4 1523
a62c4133 1524 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1da177e4
LT		 1525 return -EINVAL;
1526 if (ser->baud_base < 2400)
1527 /* No paper tape reader for Mitch.. */
1528 return -EINVAL;
1529
1530 return 0;
1531}
1532
1533static struct uart_ops sci_uart_ops = {
1534 .tx_empty = sci_tx_empty,
1535 .set_mctrl = sci_set_mctrl,
1536 .get_mctrl = sci_get_mctrl,
1537 .start_tx = sci_start_tx,
1538 .stop_tx = sci_stop_tx,
1539 .stop_rx = sci_stop_rx,
1540 .enable_ms = sci_enable_ms,
1541 .break_ctl = sci_break_ctl,
1542 .startup = sci_startup,
1543 .shutdown = sci_shutdown,
1544 .set_termios = sci_set_termios,
1545 .type = sci_type,
1546 .release_port = sci_release_port,
1547 .request_port = sci_request_port,
1548 .config_port = sci_config_port,
1549 .verify_port = sci_verify_port,
07d2a1a1
PM		 1550#ifdef CONFIG_CONSOLE_POLL
1551 .poll_get_char = sci_poll_get_char,
1552 .poll_put_char = sci_poll_put_char,
1553#endif
1da177e4
LT		 1554};
1555
501b825d
MD		 1556static void __devinit sci_init_single(struct platform_device *dev,
1557 struct sci_port *sci_port,
08f8cb31
MD		 1558 unsigned int index,
1559 struct plat_sci_port *p)
e108b2ca 1560{
73a19e4c
GL		 1561 struct uart_port *port = &sci_port->port;
1562
1563 port->ops = &sci_uart_ops;
1564 port->iotype = UPIO_MEM;
1565 port->line = index;
75136d48
MP		 1566
1567 switch (p->type) {
1568 case PORT_SCIFA:
73a19e4c 1569 port->fifosize = 64;
75136d48
MP		 1570 break;
1571 case PORT_SCIF:
73a19e4c 1572 port->fifosize = 16;
75136d48
MP		 1573 break;
1574 default:
73a19e4c 1575 port->fifosize = 1;
75136d48
MP		 1576 break;
1577 }
7b6fd3bf
MD		 1578
1579 if (dev) {
1580 sci_port->iclk = p->clk ? clk_get(&dev->dev, p->clk) : NULL;
1581 sci_port->dclk = clk_get(&dev->dev, "peripheral_clk");
1582 sci_port->enable = sci_clk_enable;
1583 sci_port->disable = sci_clk_disable;
73a19e4c 1584 port->dev = &dev->dev;
7b6fd3bf 1585 }
e108b2ca 1586
7ed7e071
MD		 1587 sci_port->break_timer.data = (unsigned long)sci_port;
1588 sci_port->break_timer.function = sci_break_timer;
1589 init_timer(&sci_port->break_timer);
1590
73a19e4c
GL		 1591 port->mapbase = p->mapbase;
1592 port->membase = p->membase;
7ed7e071 1593
73a19e4c
GL		 1594 port->irq = p->irqs[SCIx_TXI_IRQ];
1595 port->flags = p->flags;
1596 sci_port->type = port->type = p->type;
1597
1598#ifdef CONFIG_SERIAL_SH_SCI_DMA
1599 sci_port->dma_dev = p->dma_dev;
1600 sci_port->slave_tx = p->dma_slave_tx;
1601 sci_port->slave_rx = p->dma_slave_rx;
1602
1603 dev_dbg(port->dev, "%s: DMA device %p, tx %d, rx %d\n", __func__,
1604 p->dma_dev, p->dma_slave_tx, p->dma_slave_rx);
1605#endif
7ed7e071
MD		 1606
1607 memcpy(&sci_port->irqs, &p->irqs, sizeof(p->irqs));
e108b2ca
PM		 1608}
1609
1da177e4 1610#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 1611static struct tty_driver *serial_console_device(struct console *co, int *index)
1612{
1613 struct uart_driver *p = &sci_uart_driver;
1614 *index = co->index;
1615 return p->tty_driver;
1616}
1617
1618static void serial_console_putchar(struct uart_port *port, int ch)
1619{
1620 sci_poll_put_char(port, ch);
1621}
1622
1da177e4
LT		 1623/*
1624 * Print a string to the serial port trying not to disturb
1625 * any possible real use of the port...
1626 */
1627static void serial_console_write(struct console *co, const char *s,
1628 unsigned count)
1629{
dc8e6f5b 1630 struct uart_port *port = co->data;
501b825d 1631 struct sci_port *sci_port = to_sci_port(port);
973e5d52 1632 unsigned short bits;
07d2a1a1 1633
501b825d
MD		 1634 if (sci_port->enable)
1635 sci_port->enable(port);
1636
1637 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 1638
1639 /* wait until fifo is empty and last bit has been transmitted */
1640 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
1641 while ((sci_in(port, SCxSR) & bits) != bits)
1642 cpu_relax();
501b825d 1643
345e5a76 1644 if (sci_port->disable)
501b825d 1645 sci_port->disable(port);
1da177e4
LT		 1646}
1647
7b6fd3bf 1648static int __devinit serial_console_setup(struct console *co, char *options)
1da177e4 1649{
dc8e6f5b 1650 struct sci_port *sci_port;
1da177e4
LT		 1651 struct uart_port *port;
1652 int baud = 115200;
1653 int bits = 8;
1654 int parity = 'n';
1655 int flow = 'n';
1656 int ret;
1657
e108b2ca
PM		 1658 /*
1659 * Check whether an invalid uart number has been specified, and
1660 * if so, search for the first available port that does have
1661 * console support.
1662 */
1663 if (co->index >= SCI_NPORTS)
1664 co->index = 0;
1665
7b6fd3bf
MD		 1666 if (co->data) {
1667 port = co->data;
1668 sci_port = to_sci_port(port);
1669 } else {
1670 sci_port = &sci_ports[co->index];
1671 port = &sci_port->port;
1672 co->data = port;
1673 }
1da177e4
LT		 1674
1675 /*
e108b2ca
PM		 1676 * Also need to check port->type, we don't actually have any
1677 * UPIO_PORT ports, but uart_report_port() handily misreports
1678 * it anyways if we don't have a port available by the time this is
1679 * called.
1da177e4 1680 */
e108b2ca
PM		 1681 if (!port->type)
1682 return -ENODEV;
e108b2ca 1683
08f8cb31 1684 sci_config_port(port, 0);
e108b2ca 1685
dc8e6f5b
MD		 1686 if (sci_port->enable)
1687 sci_port->enable(port);
b7a76e4b 1688
1da177e4
LT		 1689 if (options)
1690 uart_parse_options(options, &baud, &parity, &bits, &flow);
1691
1692 ret = uart_set_options(port, co, baud, parity, bits, flow);
1693#if defined(__H8300H__) || defined(__H8300S__)
1694 /* disable rx interrupt */
1695 if (ret == 0)
1696 sci_stop_rx(port);
1697#endif
501b825d 1698 /* TODO: disable clock */
1da177e4
LT		 1699 return ret;
1700}
1701
1702static struct console serial_console = {
1703 .name = "ttySC",
dc8e6f5b 1704 .device = serial_console_device,
1da177e4
LT		 1705 .write = serial_console_write,
1706 .setup = serial_console_setup,
fa5da2f7 1707 .flags = CON_PRINTBUFFER,
1da177e4 1708 .index = -1,
1da177e4
LT		 1709};
1710
1711static int __init sci_console_init(void)
1712{
1713 register_console(&serial_console);
1714 return 0;
1715}
1da177e4 1716console_initcall(sci_console_init);
7b6fd3bf
MD		 1717
1718static struct sci_port early_serial_port;
1719static struct console early_serial_console = {
1720 .name = "early_ttySC",
1721 .write = serial_console_write,
1722 .flags = CON_PRINTBUFFER,
1723};
1724static char early_serial_buf[32];
1725
1da177e4
LT		 1726#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1727
07d2a1a1 1728#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
e7c98dc7 1729#define SCI_CONSOLE (&serial_console)
1da177e4 1730#else
b7a76e4b 1731#define SCI_CONSOLE 0
1da177e4
LT		 1732#endif
1733
1734static char banner[] __initdata =
1735 KERN_INFO "SuperH SCI(F) driver initialized\n";
1736
1737static struct uart_driver sci_uart_driver = {
1738 .owner = THIS_MODULE,
1739 .driver_name = "sci",
1da177e4
LT		 1740 .dev_name = "ttySC",
1741 .major = SCI_MAJOR,
1742 .minor = SCI_MINOR_START,
e108b2ca 1743 .nr = SCI_NPORTS,
1da177e4
LT		 1744 .cons = SCI_CONSOLE,
1745};
1746
e552de24 1747
54507f6e 1748static int sci_remove(struct platform_device *dev)
e552de24
MD		 1749{
1750 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1751 struct sci_port *p;
1752 unsigned long flags;
1753
e552de24 1754 cpufreq_unregister_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
e552de24
MD		 1755
1756 spin_lock_irqsave(&priv->lock, flags);
1757 list_for_each_entry(p, &priv->ports, node)
1758 uart_remove_one_port(&sci_uart_driver, &p->port);
e552de24
MD		 1759 spin_unlock_irqrestore(&priv->lock, flags);
1760
1761 kfree(priv);
1762 return 0;
1763}
1764
0ee70712
MD		 1765static int __devinit sci_probe_single(struct platform_device *dev,
1766 unsigned int index,
1767 struct plat_sci_port *p,
1768 struct sci_port *sciport)
1769{
1770 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1771 unsigned long flags;
1772 int ret;
1773
1774 /* Sanity check */
1775 if (unlikely(index >= SCI_NPORTS)) {
1776 dev_notice(&dev->dev, "Attempting to register port "
1777 "%d when only %d are available.\n",
1778 index+1, SCI_NPORTS);
1779 dev_notice(&dev->dev, "Consider bumping "
1780 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1781 return 0;
1782 }
1783
501b825d 1784 sci_init_single(dev, sciport, index, p);
0ee70712
MD		 1785
1786 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
08f8cb31 1787 if (ret)
0ee70712 1788 return ret;
0ee70712
MD		 1789
1790 INIT_LIST_HEAD(&sciport->node);
1791
1792 spin_lock_irqsave(&priv->lock, flags);
1793 list_add(&sciport->node, &priv->ports);
1794 spin_unlock_irqrestore(&priv->lock, flags);
1795
1796 return 0;
1797}
1798
e108b2ca
PM		 1799/*
1800 * Register a set of serial devices attached to a platform device. The
1801 * list is terminated with a zero flags entry, which means we expect
1802 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1803 * remapping (such as sh64) should also set UPF_IOREMAP.
1804 */
1805static int __devinit sci_probe(struct platform_device *dev)
1da177e4 1806{
e108b2ca 1807 struct plat_sci_port *p = dev->dev.platform_data;
e552de24 1808 struct sh_sci_priv *priv;
7ff731ae 1809 int i, ret = -EINVAL;
e552de24 1810
7b6fd3bf
MD		 1811#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1812 if (is_early_platform_device(dev)) {
1813 if (dev->id == -1)
1814 return -ENOTSUPP;
1815 early_serial_console.index = dev->id;
1816 early_serial_console.data = &early_serial_port.port;
1817 sci_init_single(NULL, &early_serial_port, dev->id, p);
1818 serial_console_setup(&early_serial_console, early_serial_buf);
1819 if (!strstr(early_serial_buf, "keep"))
1820 early_serial_console.flags |= CON_BOOT;
1821 register_console(&early_serial_console);
1822 return 0;
1823 }
1824#endif
1825
e552de24
MD		 1826 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1827 if (!priv)
1828 return -ENOMEM;
1829
1830 INIT_LIST_HEAD(&priv->ports);
1831 spin_lock_init(&priv->lock);
1832 platform_set_drvdata(dev, priv);
1833
e552de24
MD		 1834 priv->clk_nb.notifier_call = sci_notifier;
1835 cpufreq_register_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
1da177e4 1836
0ee70712
MD		 1837 if (dev->id != -1) {
1838 ret = sci_probe_single(dev, dev->id, p, &sci_ports[dev->id]);
1839 if (ret)
e552de24 1840 goto err_unreg;
0ee70712
MD		 1841 } else {
1842 for (i = 0; p && p->flags != 0; p++, i++) {
1843 ret = sci_probe_single(dev, i, p, &sci_ports[i]);
1844 if (ret)
1845 goto err_unreg;
e552de24 1846 }
e552de24 1847 }
1da177e4
LT		 1848
1849#ifdef CONFIG_SH_STANDARD_BIOS
1850 sh_bios_gdb_detach();
1851#endif
1852
e108b2ca 1853 return 0;
7ff731ae
PM		 1854
1855err_unreg:
e552de24 1856 sci_remove(dev);
7ff731ae 1857 return ret;
1da177e4
LT		 1858}
1859
6daa79b3 1860static int sci_suspend(struct device *dev)
1da177e4 1861{
6daa79b3 1862 struct sh_sci_priv *priv = dev_get_drvdata(dev);
e552de24
MD		 1863 struct sci_port *p;
1864 unsigned long flags;
e108b2ca 1865
e552de24
MD		 1866 spin_lock_irqsave(&priv->lock, flags);
1867 list_for_each_entry(p, &priv->ports, node)
1868 uart_suspend_port(&sci_uart_driver, &p->port);
e552de24 1869 spin_unlock_irqrestore(&priv->lock, flags);
1da177e4 1870
e108b2ca
PM		 1871 return 0;
1872}
1da177e4 1873
6daa79b3 1874static int sci_resume(struct device *dev)
e108b2ca 1875{
6daa79b3 1876 struct sh_sci_priv *priv = dev_get_drvdata(dev);
e552de24
MD		 1877 struct sci_port *p;
1878 unsigned long flags;
e108b2ca 1879
e552de24
MD		 1880 spin_lock_irqsave(&priv->lock, flags);
1881 list_for_each_entry(p, &priv->ports, node)
1882 uart_resume_port(&sci_uart_driver, &p->port);
e552de24 1883 spin_unlock_irqrestore(&priv->lock, flags);
e108b2ca
PM		 1884
1885 return 0;
1886}
1887
47145210 1888static const struct dev_pm_ops sci_dev_pm_ops = {
6daa79b3
PM		 1889 .suspend = sci_suspend,
1890 .resume = sci_resume,
1891};
1892
e108b2ca
PM		 1893static struct platform_driver sci_driver = {
1894 .probe = sci_probe,
b9e39c89 1895 .remove = sci_remove,
e108b2ca
PM		 1896 .driver = {
1897 .name = "sh-sci",
1898 .owner = THIS_MODULE,
6daa79b3 1899 .pm = &sci_dev_pm_ops,
e108b2ca
PM		 1900 },
1901};
1902
1903static int __init sci_init(void)
1904{
1905 int ret;
1906
1907 printk(banner);
1908
e108b2ca
PM		 1909 ret = uart_register_driver(&sci_uart_driver);
1910 if (likely(ret == 0)) {
1911 ret = platform_driver_register(&sci_driver);
1912 if (unlikely(ret))
1913 uart_unregister_driver(&sci_uart_driver);
1914 }
1915
1916 return ret;
1917}
1918
1919static void __exit sci_exit(void)
1920{
1921 platform_driver_unregister(&sci_driver);
1da177e4
LT		 1922 uart_unregister_driver(&sci_uart_driver);
1923}
1924
7b6fd3bf
MD		 1925#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1926early_platform_init_buffer("earlyprintk", &sci_driver,
1927 early_serial_buf, ARRAY_SIZE(early_serial_buf));
1928#endif
1da177e4
LT		 1929module_init(sci_init);
1930module_exit(sci_exit);
1931
e108b2ca 1932MODULE_LICENSE("GPL");
e169c139 1933MODULE_ALIAS("platform:sh-sci");
Linux 6.x block layer and io_uring tree(s)