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serial: sh-sci: Provide a helper for muxed IRQs.
[linux-block.git] / drivers / serial / sh-sci.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
f43dc23d 6 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 16 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 17 *
18 * This file is subject to the terms and conditions of the GNU General Public
19 * License. See the file "COPYING" in the main directory of this archive
20 * for more details.
21 */
0b3d4ef6
PM		 22#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23#define SUPPORT_SYSRQ
24#endif
1da177e4
LT		 25
26#undef DEBUG
27
1da177e4
LT		 28#include <linux/module.h>
29#include <linux/errno.h>
1da177e4
LT		 30#include <linux/timer.h>
31#include <linux/interrupt.h>
32#include <linux/tty.h>
33#include <linux/tty_flip.h>
34#include <linux/serial.h>
35#include <linux/major.h>
36#include <linux/string.h>
37#include <linux/sysrq.h>
1da177e4
LT		 38#include <linux/ioport.h>
39#include <linux/mm.h>
1da177e4
LT		 40#include <linux/init.h>
41#include <linux/delay.h>
42#include <linux/console.h>
e108b2ca 43#include <linux/platform_device.h>
96de1a8f 44#include <linux/serial_sci.h>
1da177e4
LT		 45#include <linux/notifier.h>
46#include <linux/cpufreq.h>
85f094ec 47#include <linux/clk.h>
fa5da2f7 48#include <linux/ctype.h>
7ff731ae 49#include <linux/err.h>
e552de24 50#include <linux/list.h>
73a19e4c
GL		 51#include <linux/dmaengine.h>
52#include <linux/scatterlist.h>
5a0e3ad6 53#include <linux/slab.h>
85f094ec
PM		 54
55#ifdef CONFIG_SUPERH
1da177e4
LT		 56#include <asm/sh_bios.h>
57#endif
58
168f3623
YS		 59#ifdef CONFIG_H8300
60#include <asm/gpio.h>
61#endif
62
1da177e4
LT		 63#include "sh-sci.h"
64
e108b2ca
PM		 65struct sci_port {
66 struct uart_port port;
67
68 /* Port type */
69 unsigned int type;
70
71 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
32351a28 72 unsigned int irqs[SCIx_NR_IRQS];
e108b2ca 73
e108b2ca
PM		 74 /* Port enable callback */
75 void (*enable)(struct uart_port *port);
76
77 /* Port disable callback */
78 void (*disable)(struct uart_port *port);
79
80 /* Break timer */
81 struct timer_list break_timer;
82 int break_flag;
1534a3b3 83
00b9de9c
PM		 84 /* SCSCR initialization */
85 unsigned int scscr;
86
26c92f37
PM		 87 /* SCBRR calculation algo */
88 unsigned int scbrr_algo_id;
89
501b825d
MD		 90 /* Interface clock */
91 struct clk *iclk;
c7ed1ab3
PM		 92 /* Function clock */
93 struct clk *fclk;
edad1f20 94
e552de24 95 struct list_head node;
f43dc23d 96
73a19e4c
GL		 97 struct dma_chan *chan_tx;
98 struct dma_chan *chan_rx;
f43dc23d 99
73a19e4c
GL		 100#ifdef CONFIG_SERIAL_SH_SCI_DMA
101 struct device *dma_dev;
4bab9d42
MD		 102 unsigned int slave_tx;
103 unsigned int slave_rx;
73a19e4c
GL		 104 struct dma_async_tx_descriptor *desc_tx;
105 struct dma_async_tx_descriptor *desc_rx[2];
106 dma_cookie_t cookie_tx;
107 dma_cookie_t cookie_rx[2];
108 dma_cookie_t active_rx;
109 struct scatterlist sg_tx;
110 unsigned int sg_len_tx;
111 struct scatterlist sg_rx[2];
112 size_t buf_len_rx;
113 struct sh_dmae_slave param_tx;
114 struct sh_dmae_slave param_rx;
115 struct work_struct work_tx;
116 struct work_struct work_rx;
117 struct timer_list rx_timer;
3089f381 118 unsigned int rx_timeout;
73a19e4c 119#endif
e552de24
MD		 120};
121
122struct sh_sci_priv {
123 spinlock_t lock;
124 struct list_head ports;
e552de24 125 struct notifier_block clk_nb;
e108b2ca
PM		 126};
127
1da177e4 128/* Function prototypes */
b129a8cc 129static void sci_stop_tx(struct uart_port *port);
1da177e4 130
e108b2ca 131#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 132
e108b2ca
PM		 133static struct sci_port sci_ports[SCI_NPORTS];
134static struct uart_driver sci_uart_driver;
1da177e4 135
e7c98dc7
MT		 136static inline struct sci_port *
137to_sci_port(struct uart_port *uart)
138{
139 return container_of(uart, struct sci_port, port);
140}
141
07d2a1a1 142#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 143
144#ifdef CONFIG_CONSOLE_POLL
e108b2ca
PM		 145static inline void handle_error(struct uart_port *port)
146{
147 /* Clear error flags */
1da177e4
LT		 148 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
149}
150
07d2a1a1 151static int sci_poll_get_char(struct uart_port *port)
1da177e4 152{
1da177e4
LT		 153 unsigned short status;
154 int c;
155
e108b2ca 156 do {
1da177e4
LT		 157 status = sci_in(port, SCxSR);
158 if (status & SCxSR_ERRORS(port)) {
159 handle_error(port);
160 continue;
161 }
3f255eb3
JW		 162 break;
163 } while (1);
164
165 if (!(status & SCxSR_RDxF(port)))
166 return NO_POLL_CHAR;
07d2a1a1 167
1da177e4 168 c = sci_in(port, SCxRDR);
07d2a1a1 169
e7c98dc7
MT		 170 /* Dummy read */
171 sci_in(port, SCxSR);
1da177e4 172 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 173
174 return c;
175}
1f6fd5c9 176#endif
1da177e4 177
07d2a1a1 178static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 179{
1da177e4
LT		 180 unsigned short status;
181
1da177e4
LT		 182 do {
183 status = sci_in(port, SCxSR);
184 } while (!(status & SCxSR_TDxE(port)));
185
272966c0 186 sci_out(port, SCxTDR, c);
dd0a3e77 187 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 188}
07d2a1a1 189#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 190
15c73aaa 191#if defined(__H8300H__) || defined(__H8300S__)
d5701647 192static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4
LT		 193{
194 int ch = (port->mapbase - SMR0) >> 3;
195
196 /* set DDR regs */
e108b2ca
PM		 197 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
198 h8300_sci_pins[ch].rx,
199 H8300_GPIO_INPUT);
200 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
201 h8300_sci_pins[ch].tx,
202 H8300_GPIO_OUTPUT);
203
1da177e4
LT		 204 /* tx mark output*/
205 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
206}
d5701647
PM		 207#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
208static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
e108b2ca 209{
d5701647
PM		 210 if (port->mapbase == 0xA4400000) {
211 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
212 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
213 } else if (port->mapbase == 0xA4410000)
214 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
9465a54f 215}
31a49c4b 216#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
d5701647 217static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
3ea6bc3d 218{
3ea6bc3d
MB		 219 unsigned short data;
220
221 if (cflag & CRTSCTS) {
222 /* enable RTS/CTS */
223 if (port->mapbase == 0xa4430000) { /* SCIF0 */
224 /* Clear PTCR bit 9-2; enable all scif pins but sck */
d5701647
PM		 225 data = __raw_readw(PORT_PTCR);
226 __raw_writew((data & 0xfc03), PORT_PTCR);
3ea6bc3d
MB		 227 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
228 /* Clear PVCR bit 9-2 */
d5701647
PM		 229 data = __raw_readw(PORT_PVCR);
230 __raw_writew((data & 0xfc03), PORT_PVCR);
3ea6bc3d 231 }
3ea6bc3d
MB		 232 } else {
233 if (port->mapbase == 0xa4430000) { /* SCIF0 */
234 /* Clear PTCR bit 5-2; enable only tx and rx */
d5701647
PM		 235 data = __raw_readw(PORT_PTCR);
236 __raw_writew((data & 0xffc3), PORT_PTCR);
3ea6bc3d
MB		 237 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
238 /* Clear PVCR bit 5-2 */
d5701647
PM		 239 data = __raw_readw(PORT_PVCR);
240 __raw_writew((data & 0xffc3), PORT_PVCR);
3ea6bc3d
MB		 241 }
242 }
3ea6bc3d 243}
b7a76e4b 244#elif defined(CONFIG_CPU_SH3)
e108b2ca 245/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
d5701647 246static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 247{
b7a76e4b
PM		 248 unsigned short data;
249
250 /* We need to set SCPCR to enable RTS/CTS */
d5701647 251 data = __raw_readw(SCPCR);
b7a76e4b 252 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
d5701647 253 __raw_writew(data & 0x0fcf, SCPCR);
1da177e4 254
d5701647 255 if (!(cflag & CRTSCTS)) {
1da177e4 256 /* We need to set SCPCR to enable RTS/CTS */
d5701647 257 data = __raw_readw(SCPCR);
1da177e4
LT		 258 /* Clear out SCP7MD1,0, SCP4MD1,0,
259 Set SCP6MD1,0 = {01} (output) */
d5701647 260 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
1da177e4 261
32b53076 262 data = __raw_readb(SCPDR);
1da177e4 263 /* Set /RTS2 (bit6) = 0 */
32b53076 264 __raw_writeb(data & 0xbf, SCPDR);
1da177e4 265 }
1da177e4 266}
41504c39 267#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
d5701647 268static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
41504c39 269{
346b7463 270 unsigned short data;
41504c39 271
346b7463 272 if (port->mapbase == 0xffe00000) {
d5701647 273 data = __raw_readw(PSCR);
346b7463 274 data &= ~0x03cf;
d5701647 275 if (!(cflag & CRTSCTS))
346b7463 276 data |= 0x0340;
41504c39 277
d5701647 278 __raw_writew(data, PSCR);
41504c39 279 }
178dd0cd 280}
c01f0f1a
YS		 281#elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \
282 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
7d740a06 283 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
2b1bd1ac 284 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
55ba99eb 285 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
2b1bd1ac 286 defined(CONFIG_CPU_SUBTYPE_SHX3)
d5701647
PM		 287static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
288{
289 if (!(cflag & CRTSCTS))
290 __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */
291}
b0c50ad7 292#elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A)
d5701647
PM		 293static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
294{
295 if (!(cflag & CRTSCTS))
296 __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */
297}
b7a76e4b 298#else
d5701647
PM		 299static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
300{
301 /* Nothing to do */
1da177e4 302}
e108b2ca
PM		 303#endif
304
32351a28
PM		 305#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
306 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
55ba99eb
KM		 307 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
308 defined(CONFIG_CPU_SUBTYPE_SH7786)
73a19e4c 309static int scif_txfill(struct uart_port *port)
e108b2ca 310{
73a19e4c 311 return sci_in(port, SCTFDR) & 0xff;
e108b2ca
PM		 312}
313
73a19e4c 314static int scif_txroom(struct uart_port *port)
e108b2ca 315{
73a19e4c 316 return SCIF_TXROOM_MAX - scif_txfill(port);
e108b2ca
PM		 317}
318
73a19e4c 319static int scif_rxfill(struct uart_port *port)
e108b2ca 320{
cae167d3 321 return sci_in(port, SCRFDR) & 0xff;
e108b2ca 322}
c63847a3 323#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
73a19e4c 324static int scif_txfill(struct uart_port *port)
c63847a3 325{
73a19e4c
GL		 326 if (port->mapbase == 0xffe00000 ||
327 port->mapbase == 0xffe08000)
e7c98dc7 328 /* SCIF0/1*/
73a19e4c
GL		 329 return sci_in(port, SCTFDR) & 0xff;
330 else
e7c98dc7 331 /* SCIF2 */
73a19e4c 332 return sci_in(port, SCFDR) >> 8;
c63847a3
NI		 333}
334
73a19e4c
GL		 335static int scif_txroom(struct uart_port *port)
336{
337 if (port->mapbase == 0xffe00000 ||
338 port->mapbase == 0xffe08000)
339 /* SCIF0/1*/
340 return SCIF_TXROOM_MAX - scif_txfill(port);
341 else
342 /* SCIF2 */
343 return SCIF2_TXROOM_MAX - scif_txfill(port);
c63847a3
NI		 344}
345
73a19e4c 346static int scif_rxfill(struct uart_port *port)
c63847a3 347{
e7c98dc7
MT		 348 if ((port->mapbase == 0xffe00000) ||
349 (port->mapbase == 0xffe08000)) {
350 /* SCIF0/1*/
c63847a3 351 return sci_in(port, SCRFDR) & 0xff;
e7c98dc7
MT		 352 } else {
353 /* SCIF2 */
c63847a3 354 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
e7c98dc7 355 }
c63847a3 356}
d1d4b10c
GL		 357#elif defined(CONFIG_ARCH_SH7372)
358static int scif_txfill(struct uart_port *port)
359{
360 if (port->type == PORT_SCIFA)
361 return sci_in(port, SCFDR) >> 8;
362 else
363 return sci_in(port, SCTFDR);
364}
365
366static int scif_txroom(struct uart_port *port)
367{
368 return port->fifosize - scif_txfill(port);
369}
370
371static int scif_rxfill(struct uart_port *port)
372{
373 if (port->type == PORT_SCIFA)
374 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
375 else
376 return sci_in(port, SCRFDR);
377}
e108b2ca 378#else
73a19e4c 379static int scif_txfill(struct uart_port *port)
e108b2ca 380{
73a19e4c 381 return sci_in(port, SCFDR) >> 8;
e108b2ca 382}
1da177e4 383
73a19e4c 384static int scif_txroom(struct uart_port *port)
e108b2ca 385{
73a19e4c 386 return SCIF_TXROOM_MAX - scif_txfill(port);
e108b2ca 387}
1da177e4 388
73a19e4c 389static int scif_rxfill(struct uart_port *port)
e108b2ca
PM		 390{
391 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
392}
1da177e4 393#endif
1da177e4 394
73a19e4c 395static int sci_txfill(struct uart_port *port)
e108b2ca 396{
73a19e4c 397 return !(sci_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 398}
399
73a19e4c
GL		 400static int sci_txroom(struct uart_port *port)
401{
402 return !sci_txfill(port);
403}
404
405static int sci_rxfill(struct uart_port *port)
e108b2ca 406{
e7c98dc7 407 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 408}
409
1da177e4
LT		 410/* ********************************************************************** *
411 * the interrupt related routines *
412 * ********************************************************************** */
413
414static void sci_transmit_chars(struct uart_port *port)
415{
ebd2c8f6 416 struct circ_buf *xmit = &port->state->xmit;
1da177e4 417 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 418 unsigned short status;
419 unsigned short ctrl;
e108b2ca 420 int count;
1da177e4
LT		 421
422 status = sci_in(port, SCxSR);
423 if (!(status & SCxSR_TDxE(port))) {
1da177e4 424 ctrl = sci_in(port, SCSCR);
e7c98dc7 425 if (uart_circ_empty(xmit))
8e698614 426 ctrl &= ~SCSCR_TIE;
e7c98dc7 427 else
8e698614 428 ctrl |= SCSCR_TIE;
1da177e4 429 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 430 return;
431 }
432
1a22f08d 433 if (port->type == PORT_SCI)
e108b2ca 434 count = sci_txroom(port);
1a22f08d
YS		 435 else
436 count = scif_txroom(port);
1da177e4
LT		 437
438 do {
439 unsigned char c;
440
441 if (port->x_char) {
442 c = port->x_char;
443 port->x_char = 0;
444 } else if (!uart_circ_empty(xmit) && !stopped) {
445 c = xmit->buf[xmit->tail];
446 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
447 } else {
448 break;
449 }
450
451 sci_out(port, SCxTDR, c);
452
453 port->icount.tx++;
454 } while (--count > 0);
455
456 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
457
458 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
459 uart_write_wakeup(port);
460 if (uart_circ_empty(xmit)) {
b129a8cc 461 sci_stop_tx(port);
1da177e4 462 } else {
1da177e4
LT		 463 ctrl = sci_in(port, SCSCR);
464
1a22f08d 465 if (port->type != PORT_SCI) {
1da177e4
LT		 466 sci_in(port, SCxSR); /* Dummy read */
467 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
468 }
1da177e4 469
8e698614 470 ctrl |= SCSCR_TIE;
1da177e4 471 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 472 }
473}
474
475/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 476#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 477
7d12e780 478static inline void sci_receive_chars(struct uart_port *port)
1da177e4 479{
e7c98dc7 480 struct sci_port *sci_port = to_sci_port(port);
ebd2c8f6 481 struct tty_struct *tty = port->state->port.tty;
1da177e4
LT		 482 int i, count, copied = 0;
483 unsigned short status;
33f0f88f 484 unsigned char flag;
1da177e4
LT		 485
486 status = sci_in(port, SCxSR);
487 if (!(status & SCxSR_RDxF(port)))
488 return;
489
490 while (1) {
1a22f08d 491 if (port->type == PORT_SCI)
73a19e4c 492 count = sci_rxfill(port);
1a22f08d 493 else
73a19e4c 494 count = scif_rxfill(port);
1da177e4
LT		 495
496 /* Don't copy more bytes than there is room for in the buffer */
33f0f88f 497 count = tty_buffer_request_room(tty, count);
1da177e4
LT		 498
499 /* If for any reason we can't copy more data, we're done! */
500 if (count == 0)
501 break;
502
503 if (port->type == PORT_SCI) {
504 char c = sci_in(port, SCxRDR);
e7c98dc7
MT		 505 if (uart_handle_sysrq_char(port, c) ||
506 sci_port->break_flag)
1da177e4 507 count = 0;
e7c98dc7 508 else
e108b2ca 509 tty_insert_flip_char(tty, c, TTY_NORMAL);
1da177e4 510 } else {
e7c98dc7 511 for (i = 0; i < count; i++) {
1da177e4
LT		 512 char c = sci_in(port, SCxRDR);
513 status = sci_in(port, SCxSR);
514#if defined(CONFIG_CPU_SH3)
515 /* Skip "chars" during break */
e108b2ca 516 if (sci_port->break_flag) {
1da177e4
LT		 517 if ((c == 0) &&
518 (status & SCxSR_FER(port))) {
519 count--; i--;
520 continue;
521 }
e108b2ca 522
1da177e4 523 /* Nonzero => end-of-break */
762c69e3 524 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 525 sci_port->break_flag = 0;
526
1da177e4
LT		 527 if (STEPFN(c)) {
528 count--; i--;
529 continue;
530 }
531 }
532#endif /* CONFIG_CPU_SH3 */
7d12e780 533 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 534 count--; i--;
535 continue;
536 }
537
538 /* Store data and status */
73a19e4c 539 if (status & SCxSR_FER(port)) {
33f0f88f 540 flag = TTY_FRAME;
762c69e3 541 dev_notice(port->dev, "frame error\n");
73a19e4c 542 } else if (status & SCxSR_PER(port)) {
33f0f88f 543 flag = TTY_PARITY;
762c69e3 544 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 545 } else
546 flag = TTY_NORMAL;
762c69e3 547
33f0f88f 548 tty_insert_flip_char(tty, c, flag);
1da177e4
LT		 549 }
550 }
551
552 sci_in(port, SCxSR); /* dummy read */
553 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
554
1da177e4
LT		 555 copied += count;
556 port->icount.rx += count;
557 }
558
559 if (copied) {
560 /* Tell the rest of the system the news. New characters! */
561 tty_flip_buffer_push(tty);
562 } else {
563 sci_in(port, SCxSR); /* dummy read */
564 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
565 }
566}
567
568#define SCI_BREAK_JIFFIES (HZ/20)
569/* The sci generates interrupts during the break,
570 * 1 per millisecond or so during the break period, for 9600 baud.
571 * So dont bother disabling interrupts.
572 * But dont want more than 1 break event.
573 * Use a kernel timer to periodically poll the rx line until
574 * the break is finished.
575 */
576static void sci_schedule_break_timer(struct sci_port *port)
577{
578 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
579 add_timer(&port->break_timer);
580}
581/* Ensure that two consecutive samples find the break over. */
582static void sci_break_timer(unsigned long data)
583{
e108b2ca
PM		 584 struct sci_port *port = (struct sci_port *)data;
585
586 if (sci_rxd_in(&port->port) == 0) {
1da177e4 587 port->break_flag = 1;
e108b2ca
PM		 588 sci_schedule_break_timer(port);
589 } else if (port->break_flag == 1) {
1da177e4
LT		 590 /* break is over. */
591 port->break_flag = 2;
e108b2ca
PM		 592 sci_schedule_break_timer(port);
593 } else
594 port->break_flag = 0;
1da177e4
LT		 595}
596
597static inline int sci_handle_errors(struct uart_port *port)
598{
599 int copied = 0;
600 unsigned short status = sci_in(port, SCxSR);
ebd2c8f6 601 struct tty_struct *tty = port->state->port.tty;
1da177e4 602
e108b2ca 603 if (status & SCxSR_ORER(port)) {
1da177e4 604 /* overrun error */
e108b2ca 605 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
33f0f88f 606 copied++;
762c69e3
PM		 607
608 dev_notice(port->dev, "overrun error");
1da177e4
LT		 609 }
610
e108b2ca 611 if (status & SCxSR_FER(port)) {
1da177e4
LT		 612 if (sci_rxd_in(port) == 0) {
613 /* Notify of BREAK */
e7c98dc7 614 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 615
616 if (!sci_port->break_flag) {
617 sci_port->break_flag = 1;
618 sci_schedule_break_timer(sci_port);
619
1da177e4 620 /* Do sysrq handling. */
e108b2ca 621 if (uart_handle_break(port))
1da177e4 622 return 0;
762c69e3
PM		 623
624 dev_dbg(port->dev, "BREAK detected\n");
625
e108b2ca 626 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
e7c98dc7
MT		 627 copied++;
628 }
629
e108b2ca 630 } else {
1da177e4 631 /* frame error */
e108b2ca 632 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
33f0f88f 633 copied++;
762c69e3
PM		 634
635 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 636 }
637 }
638
e108b2ca 639 if (status & SCxSR_PER(port)) {
1da177e4 640 /* parity error */
e108b2ca
PM		 641 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
642 copied++;
762c69e3
PM		 643
644 dev_notice(port->dev, "parity error");
1da177e4
LT		 645 }
646
33f0f88f 647 if (copied)
1da177e4 648 tty_flip_buffer_push(tty);
1da177e4
LT		 649
650 return copied;
651}
652
d830fa45
PM		 653static inline int sci_handle_fifo_overrun(struct uart_port *port)
654{
ebd2c8f6 655 struct tty_struct *tty = port->state->port.tty;
d830fa45
PM		 656 int copied = 0;
657
658 if (port->type != PORT_SCIF)
659 return 0;
660
661 if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
662 sci_out(port, SCLSR, 0);
663
664 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
665 tty_flip_buffer_push(tty);
666
667 dev_notice(port->dev, "overrun error\n");
668 copied++;
669 }
670
671 return copied;
672}
673
1da177e4
LT		 674static inline int sci_handle_breaks(struct uart_port *port)
675{
676 int copied = 0;
677 unsigned short status = sci_in(port, SCxSR);
ebd2c8f6 678 struct tty_struct *tty = port->state->port.tty;
a5660ada 679 struct sci_port *s = to_sci_port(port);
1da177e4 680
0b3d4ef6
PM		 681 if (uart_handle_break(port))
682 return 0;
683
b7a76e4b 684 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 685#if defined(CONFIG_CPU_SH3)
686 /* Debounce break */
687 s->break_flag = 1;
688#endif
689 /* Notify of BREAK */
e108b2ca 690 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
33f0f88f 691 copied++;
762c69e3
PM		 692
693 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 694 }
695
33f0f88f 696 if (copied)
1da177e4 697 tty_flip_buffer_push(tty);
e108b2ca 698
d830fa45
PM		 699 copied += sci_handle_fifo_overrun(port);
700
1da177e4
LT		 701 return copied;
702}
703
73a19e4c 704static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1da177e4 705{
73a19e4c
GL		 706#ifdef CONFIG_SERIAL_SH_SCI_DMA
707 struct uart_port *port = ptr;
708 struct sci_port *s = to_sci_port(port);
709
710 if (s->chan_rx) {
73a19e4c
GL		 711 u16 scr = sci_in(port, SCSCR);
712 u16 ssr = sci_in(port, SCxSR);
713
714 /* Disable future Rx interrupts */
d1d4b10c 715 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 716 disable_irq_nosync(irq);
717 scr |= 0x4000;
718 } else {
f43dc23d 719 scr &= ~SCSCR_RIE;
3089f381
GL		 720 }
721 sci_out(port, SCSCR, scr);
73a19e4c
GL		 722 /* Clear current interrupt */
723 sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
3089f381
GL		 724 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
725 jiffies, s->rx_timeout);
726 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 727
728 return IRQ_HANDLED;
729 }
730#endif
731
1da177e4
LT		 732 /* I think sci_receive_chars has to be called irrespective
733 * of whether the I_IXOFF is set, otherwise, how is the interrupt
734 * to be disabled?
735 */
73a19e4c 736 sci_receive_chars(ptr);
1da177e4
LT		 737
738 return IRQ_HANDLED;
739}
740
7d12e780 741static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 742{
743 struct uart_port *port = ptr;
fd78a76a 744 unsigned long flags;
1da177e4 745
fd78a76a 746 spin_lock_irqsave(&port->lock, flags);
1da177e4 747 sci_transmit_chars(port);
fd78a76a 748 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 749
750 return IRQ_HANDLED;
751}
752
7d12e780 753static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 754{
755 struct uart_port *port = ptr;
756
757 /* Handle errors */
758 if (port->type == PORT_SCI) {
759 if (sci_handle_errors(port)) {
760 /* discard character in rx buffer */
761 sci_in(port, SCxSR);
762 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
763 }
764 } else {
d830fa45 765 sci_handle_fifo_overrun(port);
7d12e780 766 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 767 }
768
769 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
770
771 /* Kick the transmission */
7d12e780 772 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 773
774 return IRQ_HANDLED;
775}
776
7d12e780 777static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 778{
779 struct uart_port *port = ptr;
780
781 /* Handle BREAKs */
782 sci_handle_breaks(port);
783 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
784
785 return IRQ_HANDLED;
786}
787
f43dc23d
PM		 788static inline unsigned long port_rx_irq_mask(struct uart_port *port)
789{
790 /*
791 * Not all ports (such as SCIFA) will support REIE. Rather than
792 * special-casing the port type, we check the port initialization
793 * IRQ enable mask to see whether the IRQ is desired at all. If
794 * it's unset, it's logically inferred that there's no point in
795 * testing for it.
796 */
4ae26f46 797 return SCSCR_RIE | (to_sci_port(port)->scscr & SCSCR_REIE);
f43dc23d
PM		 798}
799
7d12e780 800static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 801{
44e18e9e 802 unsigned short ssr_status, scr_status, err_enabled;
a8884e34 803 struct uart_port *port = ptr;
73a19e4c 804 struct sci_port *s = to_sci_port(port);
a8884e34 805 irqreturn_t ret = IRQ_NONE;
1da177e4 806
e7c98dc7
MT		 807 ssr_status = sci_in(port, SCxSR);
808 scr_status = sci_in(port, SCSCR);
f43dc23d 809 err_enabled = scr_status & port_rx_irq_mask(port);
1da177e4
LT		 810
811 /* Tx Interrupt */
f43dc23d 812 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
73a19e4c 813 !s->chan_tx)
a8884e34 814 ret = sci_tx_interrupt(irq, ptr);
f43dc23d 815
73a19e4c
GL		 816 /*
817 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
818 * DR flags
819 */
820 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
f43dc23d 821 (scr_status & SCSCR_RIE))
a8884e34 822 ret = sci_rx_interrupt(irq, ptr);
f43dc23d 823
1da177e4 824 /* Error Interrupt */
dd4da3a5 825 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
a8884e34 826 ret = sci_er_interrupt(irq, ptr);
f43dc23d 827
1da177e4 828 /* Break Interrupt */
dd4da3a5 829 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
a8884e34 830 ret = sci_br_interrupt(irq, ptr);
1da177e4 831
a8884e34 832 return ret;
1da177e4
LT		 833}
834
1da177e4
LT		 835/*
836 * Here we define a transistion notifier so that we can update all of our
837 * ports' baud rate when the peripheral clock changes.
838 */
e108b2ca
PM		 839static int sci_notifier(struct notifier_block *self,
840 unsigned long phase, void *p)
1da177e4 841{
e552de24
MD		 842 struct sh_sci_priv *priv = container_of(self,
843 struct sh_sci_priv, clk_nb);
844 struct sci_port *sci_port;
845 unsigned long flags;
1da177e4
LT		 846
847 if ((phase == CPUFREQ_POSTCHANGE) ||
e552de24
MD		 848 (phase == CPUFREQ_RESUMECHANGE)) {
849 spin_lock_irqsave(&priv->lock, flags);
850 list_for_each_entry(sci_port, &priv->ports, node)
c7ed1ab3 851 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
e552de24
MD		 852 spin_unlock_irqrestore(&priv->lock, flags);
853 }
1da177e4 854
1da177e4
LT		 855 return NOTIFY_OK;
856}
501b825d
MD		 857
858static void sci_clk_enable(struct uart_port *port)
859{
860 struct sci_port *sci_port = to_sci_port(port);
861
c7ed1ab3
PM		 862 clk_enable(sci_port->iclk);
863 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
864 clk_enable(sci_port->fclk);
501b825d
MD		 865}
866
867static void sci_clk_disable(struct uart_port *port)
868{
869 struct sci_port *sci_port = to_sci_port(port);
870
c7ed1ab3
PM		 871 clk_disable(sci_port->fclk);
872 clk_disable(sci_port->iclk);
501b825d 873}
1da177e4
LT		 874
875static int sci_request_irq(struct sci_port *port)
876{
877 int i;
7d12e780 878 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
1da177e4
LT		 879 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
880 sci_br_interrupt,
881 };
882 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
883 "SCI Transmit Data Empty", "SCI Break" };
884
885 if (port->irqs[0] == port->irqs[1]) {
762c69e3 886 if (unlikely(!port->irqs[0]))
1da177e4 887 return -ENODEV;
e108b2ca
PM		 888
889 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
35f3c518 890 IRQF_DISABLED, "sci", port)) {
762c69e3 891 dev_err(port->port.dev, "Can't allocate IRQ\n");
1da177e4
LT		 892 return -ENODEV;
893 }
894 } else {
895 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
762c69e3 896 if (unlikely(!port->irqs[i]))
1da177e4 897 continue;
762c69e3 898
e108b2ca 899 if (request_irq(port->irqs[i], handlers[i],
35f3c518 900 IRQF_DISABLED, desc[i], port)) {
762c69e3 901 dev_err(port->port.dev, "Can't allocate IRQ\n");
1da177e4
LT		 902 return -ENODEV;
903 }
904 }
905 }
906
907 return 0;
908}
909
910static void sci_free_irq(struct sci_port *port)
911{
912 int i;
913
762c69e3
PM		 914 if (port->irqs[0] == port->irqs[1])
915 free_irq(port->irqs[0], port);
916 else {
1da177e4
LT		 917 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
918 if (!port->irqs[i])
919 continue;
920
921 free_irq(port->irqs[i], port);
922 }
923 }
924}
925
926static unsigned int sci_tx_empty(struct uart_port *port)
927{
b1516803 928 unsigned short status = sci_in(port, SCxSR);
73a19e4c
GL		 929 unsigned short in_tx_fifo = scif_txfill(port);
930
931 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 932}
933
934static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
935{
936 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
937 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
938 /* If you have signals for DTR and DCD, please implement here. */
939}
940
941static unsigned int sci_get_mctrl(struct uart_port *port)
942{
73a19e4c 943 /* This routine is used for getting signals of: DTR, DCD, DSR, RI,
1da177e4
LT		 944 and CTS/RTS */
945
946 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
947}
948
73a19e4c
GL		 949#ifdef CONFIG_SERIAL_SH_SCI_DMA
950static void sci_dma_tx_complete(void *arg)
951{
952 struct sci_port *s = arg;
953 struct uart_port *port = &s->port;
954 struct circ_buf *xmit = &port->state->xmit;
955 unsigned long flags;
956
957 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
958
959 spin_lock_irqsave(&port->lock, flags);
960
f354a381 961 xmit->tail += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 962 xmit->tail &= UART_XMIT_SIZE - 1;
963
f354a381 964 port->icount.tx += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 965
966 async_tx_ack(s->desc_tx);
967 s->cookie_tx = -EINVAL;
968 s->desc_tx = NULL;
969
73a19e4c
GL		 970 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
971 uart_write_wakeup(port);
972
3089f381 973 if (!uart_circ_empty(xmit)) {
73a19e4c 974 schedule_work(&s->work_tx);
d1d4b10c 975 } else if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 976 u16 ctrl = sci_in(port, SCSCR);
f43dc23d 977 sci_out(port, SCSCR, ctrl & ~SCSCR_TIE);
3089f381
GL		 978 }
979
980 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 981}
982
983/* Locking: called with port lock held */
984static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty,
985 size_t count)
986{
987 struct uart_port *port = &s->port;
988 int i, active, room;
989
990 room = tty_buffer_request_room(tty, count);
991
992 if (s->active_rx == s->cookie_rx[0]) {
993 active = 0;
994 } else if (s->active_rx == s->cookie_rx[1]) {
995 active = 1;
996 } else {
997 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
998 return 0;
999 }
1000
1001 if (room < count)
1002 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
1003 count - room);
1004 if (!room)
1005 return room;
1006
1007 for (i = 0; i < room; i++)
1008 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1009 TTY_NORMAL);
1010
1011 port->icount.rx += room;
1012
1013 return room;
1014}
1015
1016static void sci_dma_rx_complete(void *arg)
1017{
1018 struct sci_port *s = arg;
1019 struct uart_port *port = &s->port;
1020 struct tty_struct *tty = port->state->port.tty;
1021 unsigned long flags;
1022 int count;
1023
3089f381 1024 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
73a19e4c
GL		 1025
1026 spin_lock_irqsave(&port->lock, flags);
1027
1028 count = sci_dma_rx_push(s, tty, s->buf_len_rx);
1029
3089f381 1030 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 1031
1032 spin_unlock_irqrestore(&port->lock, flags);
1033
1034 if (count)
1035 tty_flip_buffer_push(tty);
1036
1037 schedule_work(&s->work_rx);
1038}
1039
1040static void sci_start_rx(struct uart_port *port);
1041static void sci_start_tx(struct uart_port *port);
1042
1043static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1044{
1045 struct dma_chan *chan = s->chan_rx;
1046 struct uart_port *port = &s->port;
73a19e4c
GL		 1047
1048 s->chan_rx = NULL;
1049 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1050 dma_release_channel(chan);
85b8e3ff
GL		 1051 if (sg_dma_address(&s->sg_rx[0]))
1052 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1053 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
73a19e4c
GL		 1054 if (enable_pio)
1055 sci_start_rx(port);
1056}
1057
1058static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1059{
1060 struct dma_chan *chan = s->chan_tx;
1061 struct uart_port *port = &s->port;
73a19e4c
GL		 1062
1063 s->chan_tx = NULL;
1064 s->cookie_tx = -EINVAL;
1065 dma_release_channel(chan);
1066 if (enable_pio)
1067 sci_start_tx(port);
1068}
1069
1070static void sci_submit_rx(struct sci_port *s)
1071{
1072 struct dma_chan *chan = s->chan_rx;
1073 int i;
1074
1075 for (i = 0; i < 2; i++) {
1076 struct scatterlist *sg = &s->sg_rx[i];
1077 struct dma_async_tx_descriptor *desc;
1078
1079 desc = chan->device->device_prep_slave_sg(chan,
1080 sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT);
1081
1082 if (desc) {
1083 s->desc_rx[i] = desc;
1084 desc->callback = sci_dma_rx_complete;
1085 desc->callback_param = s;
1086 s->cookie_rx[i] = desc->tx_submit(desc);
1087 }
1088
1089 if (!desc || s->cookie_rx[i] < 0) {
1090 if (i) {
1091 async_tx_ack(s->desc_rx[0]);
1092 s->cookie_rx[0] = -EINVAL;
1093 }
1094 if (desc) {
1095 async_tx_ack(desc);
1096 s->cookie_rx[i] = -EINVAL;
1097 }
1098 dev_warn(s->port.dev,
1099 "failed to re-start DMA, using PIO\n");
1100 sci_rx_dma_release(s, true);
1101 return;
1102 }
3089f381
GL		 1103 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1104 s->cookie_rx[i], i);
73a19e4c
GL		 1105 }
1106
1107 s->active_rx = s->cookie_rx[0];
1108
1109 dma_async_issue_pending(chan);
1110}
1111
1112static void work_fn_rx(struct work_struct *work)
1113{
1114 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1115 struct uart_port *port = &s->port;
1116 struct dma_async_tx_descriptor *desc;
1117 int new;
1118
1119 if (s->active_rx == s->cookie_rx[0]) {
1120 new = 0;
1121 } else if (s->active_rx == s->cookie_rx[1]) {
1122 new = 1;
1123 } else {
1124 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1125 return;
1126 }
1127 desc = s->desc_rx[new];
1128
1129 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1130 DMA_SUCCESS) {
1131 /* Handle incomplete DMA receive */
1132 struct tty_struct *tty = port->state->port.tty;
1133 struct dma_chan *chan = s->chan_rx;
1134 struct sh_desc *sh_desc = container_of(desc, struct sh_desc,
1135 async_tx);
1136 unsigned long flags;
1137 int count;
1138
05827630 1139 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
73a19e4c
GL		 1140 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1141 sh_desc->partial, sh_desc->cookie);
1142
1143 spin_lock_irqsave(&port->lock, flags);
1144 count = sci_dma_rx_push(s, tty, sh_desc->partial);
1145 spin_unlock_irqrestore(&port->lock, flags);
1146
1147 if (count)
1148 tty_flip_buffer_push(tty);
1149
1150 sci_submit_rx(s);
1151
1152 return;
1153 }
1154
1155 s->cookie_rx[new] = desc->tx_submit(desc);
1156 if (s->cookie_rx[new] < 0) {
1157 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1158 sci_rx_dma_release(s, true);
1159 return;
1160 }
1161
73a19e4c 1162 s->active_rx = s->cookie_rx[!new];
3089f381
GL		 1163
1164 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1165 s->cookie_rx[new], new, s->active_rx);
73a19e4c
GL		 1166}
1167
1168static void work_fn_tx(struct work_struct *work)
1169{
1170 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1171 struct dma_async_tx_descriptor *desc;
1172 struct dma_chan *chan = s->chan_tx;
1173 struct uart_port *port = &s->port;
1174 struct circ_buf *xmit = &port->state->xmit;
1175 struct scatterlist *sg = &s->sg_tx;
1176
1177 /*
1178 * DMA is idle now.
1179 * Port xmit buffer is already mapped, and it is one page... Just adjust
1180 * offsets and lengths. Since it is a circular buffer, we have to
1181 * transmit till the end, and then the rest. Take the port lock to get a
1182 * consistent xmit buffer state.
1183 */
1184 spin_lock_irq(&port->lock);
1185 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
f354a381 1186 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
73a19e4c 1187 sg->offset;
f354a381 1188 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
73a19e4c 1189 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
73a19e4c
GL		 1190 spin_unlock_irq(&port->lock);
1191
f354a381 1192 BUG_ON(!sg_dma_len(sg));
73a19e4c
GL		 1193
1194 desc = chan->device->device_prep_slave_sg(chan,
1195 sg, s->sg_len_tx, DMA_TO_DEVICE,
1196 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1197 if (!desc) {
1198 /* switch to PIO */
1199 sci_tx_dma_release(s, true);
1200 return;
1201 }
1202
1203 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1204
1205 spin_lock_irq(&port->lock);
1206 s->desc_tx = desc;
1207 desc->callback = sci_dma_tx_complete;
1208 desc->callback_param = s;
1209 spin_unlock_irq(&port->lock);
1210 s->cookie_tx = desc->tx_submit(desc);
1211 if (s->cookie_tx < 0) {
1212 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1213 /* switch to PIO */
1214 sci_tx_dma_release(s, true);
1215 return;
1216 }
1217
1218 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1219 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1220
1221 dma_async_issue_pending(chan);
1222}
1223#endif
1224
b129a8cc 1225static void sci_start_tx(struct uart_port *port)
1da177e4 1226{
3089f381 1227 struct sci_port *s = to_sci_port(port);
e108b2ca 1228 unsigned short ctrl;
1da177e4 1229
73a19e4c 1230#ifdef CONFIG_SERIAL_SH_SCI_DMA
d1d4b10c 1231 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 1232 u16 new, scr = sci_in(port, SCSCR);
1233 if (s->chan_tx)
1234 new = scr | 0x8000;
1235 else
1236 new = scr & ~0x8000;
1237 if (new != scr)
1238 sci_out(port, SCSCR, new);
73a19e4c 1239 }
f43dc23d 1240
3089f381
GL		 1241 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1242 s->cookie_tx < 0)
1243 schedule_work(&s->work_tx);
73a19e4c 1244#endif
f43dc23d 1245
d1d4b10c 1246 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 1247 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1248 ctrl = sci_in(port, SCSCR);
f43dc23d 1249 sci_out(port, SCSCR, ctrl | SCSCR_TIE);
3089f381 1250 }
1da177e4
LT		 1251}
1252
b129a8cc 1253static void sci_stop_tx(struct uart_port *port)
1da177e4 1254{
1da177e4
LT		 1255 unsigned short ctrl;
1256
1257 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1da177e4 1258 ctrl = sci_in(port, SCSCR);
f43dc23d 1259
d1d4b10c 1260 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1261 ctrl &= ~0x8000;
f43dc23d 1262
8e698614 1263 ctrl &= ~SCSCR_TIE;
f43dc23d 1264
1da177e4 1265 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1266}
1267
73a19e4c 1268static void sci_start_rx(struct uart_port *port)
1da177e4 1269{
1da177e4
LT		 1270 unsigned short ctrl;
1271
f43dc23d 1272 ctrl = sci_in(port, SCSCR) | port_rx_irq_mask(port);
1da177e4 1273
d1d4b10c 1274 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1275 ctrl &= ~0x4000;
f43dc23d 1276
1da177e4 1277 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1278}
1279
1280static void sci_stop_rx(struct uart_port *port)
1281{
1da177e4
LT		 1282 unsigned short ctrl;
1283
1da177e4 1284 ctrl = sci_in(port, SCSCR);
f43dc23d 1285
d1d4b10c 1286 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1287 ctrl &= ~0x4000;
f43dc23d
PM		 1288
1289 ctrl &= ~port_rx_irq_mask(port);
1290
1da177e4 1291 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1292}
1293
1294static void sci_enable_ms(struct uart_port *port)
1295{
1296 /* Nothing here yet .. */
1297}
1298
1299static void sci_break_ctl(struct uart_port *port, int break_state)
1300{
1301 /* Nothing here yet .. */
1302}
1303
73a19e4c
GL		 1304#ifdef CONFIG_SERIAL_SH_SCI_DMA
1305static bool filter(struct dma_chan *chan, void *slave)
1306{
1307 struct sh_dmae_slave *param = slave;
1308
1309 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1310 param->slave_id);
1311
1312 if (param->dma_dev == chan->device->dev) {
1313 chan->private = param;
1314 return true;
1315 } else {
1316 return false;
1317 }
1318}
1319
1320static void rx_timer_fn(unsigned long arg)
1321{
1322 struct sci_port *s = (struct sci_port *)arg;
1323 struct uart_port *port = &s->port;
73a19e4c 1324 u16 scr = sci_in(port, SCSCR);
3089f381 1325
d1d4b10c 1326 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 1327 scr &= ~0x4000;
1328 enable_irq(s->irqs[1]);
1329 }
f43dc23d 1330 sci_out(port, SCSCR, scr | SCSCR_RIE);
73a19e4c
GL		 1331 dev_dbg(port->dev, "DMA Rx timed out\n");
1332 schedule_work(&s->work_rx);
1333}
1334
1335static void sci_request_dma(struct uart_port *port)
1336{
1337 struct sci_port *s = to_sci_port(port);
1338 struct sh_dmae_slave *param;
1339 struct dma_chan *chan;
1340 dma_cap_mask_t mask;
1341 int nent;
1342
1343 dev_dbg(port->dev, "%s: port %d DMA %p\n", __func__,
1344 port->line, s->dma_dev);
1345
1346 if (!s->dma_dev)
1347 return;
1348
1349 dma_cap_zero(mask);
1350 dma_cap_set(DMA_SLAVE, mask);
1351
1352 param = &s->param_tx;
1353
1354 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1355 param->slave_id = s->slave_tx;
1356 param->dma_dev = s->dma_dev;
1357
1358 s->cookie_tx = -EINVAL;
1359 chan = dma_request_channel(mask, filter, param);
1360 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1361 if (chan) {
1362 s->chan_tx = chan;
1363 sg_init_table(&s->sg_tx, 1);
1364 /* UART circular tx buffer is an aligned page. */
1365 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1366 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1367 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1368 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1369 if (!nent)
1370 sci_tx_dma_release(s, false);
1371 else
1372 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1373 sg_dma_len(&s->sg_tx),
1374 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1375
1376 s->sg_len_tx = nent;
1377
1378 INIT_WORK(&s->work_tx, work_fn_tx);
1379 }
1380
1381 param = &s->param_rx;
1382
1383 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1384 param->slave_id = s->slave_rx;
1385 param->dma_dev = s->dma_dev;
1386
1387 chan = dma_request_channel(mask, filter, param);
1388 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1389 if (chan) {
1390 dma_addr_t dma[2];
1391 void *buf[2];
1392 int i;
1393
1394 s->chan_rx = chan;
1395
1396 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1397 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1398 &dma[0], GFP_KERNEL);
1399
1400 if (!buf[0]) {
1401 dev_warn(port->dev,
1402 "failed to allocate dma buffer, using PIO\n");
1403 sci_rx_dma_release(s, true);
1404 return;
1405 }
1406
1407 buf[1] = buf[0] + s->buf_len_rx;
1408 dma[1] = dma[0] + s->buf_len_rx;
1409
1410 for (i = 0; i < 2; i++) {
1411 struct scatterlist *sg = &s->sg_rx[i];
1412
1413 sg_init_table(sg, 1);
1414 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1415 (int)buf[i] & ~PAGE_MASK);
f354a381 1416 sg_dma_address(sg) = dma[i];
73a19e4c
GL		 1417 }
1418
1419 INIT_WORK(&s->work_rx, work_fn_rx);
1420 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1421
1422 sci_submit_rx(s);
1423 }
1424}
1425
1426static void sci_free_dma(struct uart_port *port)
1427{
1428 struct sci_port *s = to_sci_port(port);
1429
1430 if (!s->dma_dev)
1431 return;
1432
1433 if (s->chan_tx)
1434 sci_tx_dma_release(s, false);
1435 if (s->chan_rx)
1436 sci_rx_dma_release(s, false);
1437}
1438#endif
1439
1da177e4
LT		 1440static int sci_startup(struct uart_port *port)
1441{
a5660ada 1442 struct sci_port *s = to_sci_port(port);
1da177e4 1443
73a19e4c
GL		 1444 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1445
e108b2ca
PM		 1446 if (s->enable)
1447 s->enable(port);
1da177e4
LT		 1448
1449 sci_request_irq(s);
73a19e4c
GL		 1450#ifdef CONFIG_SERIAL_SH_SCI_DMA
1451 sci_request_dma(port);
1452#endif
d656901b 1453 sci_start_tx(port);
73a19e4c 1454 sci_start_rx(port);
1da177e4
LT		 1455
1456 return 0;
1457}
1458
1459static void sci_shutdown(struct uart_port *port)
1460{
a5660ada 1461 struct sci_port *s = to_sci_port(port);
1da177e4 1462
73a19e4c
GL		 1463 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1464
1da177e4 1465 sci_stop_rx(port);
b129a8cc 1466 sci_stop_tx(port);
73a19e4c
GL		 1467#ifdef CONFIG_SERIAL_SH_SCI_DMA
1468 sci_free_dma(port);
1469#endif
1da177e4
LT		 1470 sci_free_irq(s);
1471
e108b2ca
PM		 1472 if (s->disable)
1473 s->disable(port);
1da177e4
LT		 1474}
1475
26c92f37
PM		 1476static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1477 unsigned long freq)
1478{
1479 switch (algo_id) {
1480 case SCBRR_ALGO_1:
1481 return ((freq + 16 * bps) / (16 * bps) - 1);
1482 case SCBRR_ALGO_2:
1483 return ((freq + 16 * bps) / (32 * bps) - 1);
1484 case SCBRR_ALGO_3:
1485 return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
1486 case SCBRR_ALGO_4:
1487 return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
1488 case SCBRR_ALGO_5:
1489 return (((freq * 1000 / 32) / bps) - 1);
1490 }
1491
1492 /* Warn, but use a safe default */
1493 WARN_ON(1);
1494 return ((freq + 16 * bps) / (32 * bps) - 1);
1495}
1496
606d099c
AC		 1497static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1498 struct ktermios *old)
1da177e4 1499{
00b9de9c 1500 struct sci_port *s = to_sci_port(port);
154280fd 1501 unsigned int status, baud, smr_val, max_baud;
a2159b52 1502 int t = -1;
3089f381 1503 u16 scfcr = 0;
1da177e4 1504
154280fd
MD		 1505 /*
1506 * earlyprintk comes here early on with port->uartclk set to zero.
1507 * the clock framework is not up and running at this point so here
1508 * we assume that 115200 is the maximum baud rate. please note that
1509 * the baud rate is not programmed during earlyprintk - it is assumed
1510 * that the previous boot loader has enabled required clocks and
1511 * setup the baud rate generator hardware for us already.
1512 */
1513 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1514
154280fd
MD		 1515 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1516 if (likely(baud && port->uartclk))
26c92f37 1517 t = sci_scbrr_calc(s->scbrr_algo_id, baud, port->uartclk);
e108b2ca 1518
1da177e4
LT		 1519 do {
1520 status = sci_in(port, SCxSR);
1521 } while (!(status & SCxSR_TEND(port)));
1522
1523 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1524
1a22f08d 1525 if (port->type != PORT_SCI)
3089f381 1526 sci_out(port, SCFCR, scfcr | SCFCR_RFRST | SCFCR_TFRST);
1da177e4
LT		 1527
1528 smr_val = sci_in(port, SCSMR) & 3;
1529 if ((termios->c_cflag & CSIZE) == CS7)
1530 smr_val |= 0x40;
1531 if (termios->c_cflag & PARENB)
1532 smr_val |= 0x20;
1533 if (termios->c_cflag & PARODD)
1534 smr_val |= 0x30;
1535 if (termios->c_cflag & CSTOPB)
1536 smr_val |= 0x08;
1537
1538 uart_update_timeout(port, termios->c_cflag, baud);
1539
1540 sci_out(port, SCSMR, smr_val);
1541
73a19e4c 1542 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t,
4ae26f46 1543 s->scscr);
73a19e4c 1544
1da177e4 1545 if (t > 0) {
e7c98dc7 1546 if (t >= 256) {
1da177e4
LT		 1547 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1548 t >>= 2;
e7c98dc7 1549 } else
1da177e4 1550 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
e7c98dc7 1551
1da177e4
LT		 1552 sci_out(port, SCBRR, t);
1553 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1554 }
1555
d5701647 1556 sci_init_pins(port, termios->c_cflag);
3089f381 1557 sci_out(port, SCFCR, scfcr | ((termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0));
b7a76e4b 1558
00b9de9c 1559 sci_out(port, SCSCR, s->scscr);
1da177e4 1560
3089f381
GL		 1561#ifdef CONFIG_SERIAL_SH_SCI_DMA
1562 /*
1563 * Calculate delay for 1.5 DMA buffers: see
1564 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1565 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1566 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1567 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1568 * sizes), but it has been found out experimentally, that this is not
1569 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1570 * as a minimum seem to work perfectly.
1571 */
1572 if (s->chan_rx) {
1573 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1574 port->fifosize / 2;
1575 dev_dbg(port->dev,
1576 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1577 s->rx_timeout * 1000 / HZ, port->timeout);
1578 if (s->rx_timeout < msecs_to_jiffies(20))
1579 s->rx_timeout = msecs_to_jiffies(20);
1580 }
1581#endif
1582
1da177e4 1583 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 1584 sci_start_rx(port);
1da177e4
LT		 1585}
1586
1587static const char *sci_type(struct uart_port *port)
1588{
1589 switch (port->type) {
e7c98dc7
MT		 1590 case PORT_IRDA:
1591 return "irda";
1592 case PORT_SCI:
1593 return "sci";
1594 case PORT_SCIF:
1595 return "scif";
1596 case PORT_SCIFA:
1597 return "scifa";
d1d4b10c
GL		 1598 case PORT_SCIFB:
1599 return "scifb";
1da177e4
LT		 1600 }
1601
fa43972f 1602 return NULL;
1da177e4
LT		 1603}
1604
1605static void sci_release_port(struct uart_port *port)
1606{
1607 /* Nothing here yet .. */
1608}
1609
1610static int sci_request_port(struct uart_port *port)
1611{
1612 /* Nothing here yet .. */
1613 return 0;
1614}
1615
1616static void sci_config_port(struct uart_port *port, int flags)
1617{
a5660ada 1618 struct sci_port *s = to_sci_port(port);
1da177e4
LT		 1619
1620 port->type = s->type;
1621
08f8cb31 1622 if (port->flags & UPF_IOREMAP) {
7ff731ae 1623 port->membase = ioremap_nocache(port->mapbase, 0x40);
08f8cb31
MD		 1624
1625 if (IS_ERR(port->membase))
1626 dev_err(port->dev, "can't remap port#%d\n", port->line);
1627 } else {
1628 /*
1629 * For the simple (and majority of) cases where we don't
1630 * need to do any remapping, just cast the cookie
1631 * directly.
1632 */
1633 port->membase = (void __iomem *)port->mapbase;
7ff731ae 1634 }
1da177e4
LT		 1635}
1636
1637static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1638{
a5660ada 1639 struct sci_port *s = to_sci_port(port);
1da177e4 1640
a62c4133 1641 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1da177e4
LT		 1642 return -EINVAL;
1643 if (ser->baud_base < 2400)
1644 /* No paper tape reader for Mitch.. */
1645 return -EINVAL;
1646
1647 return 0;
1648}
1649
1650static struct uart_ops sci_uart_ops = {
1651 .tx_empty = sci_tx_empty,
1652 .set_mctrl = sci_set_mctrl,
1653 .get_mctrl = sci_get_mctrl,
1654 .start_tx = sci_start_tx,
1655 .stop_tx = sci_stop_tx,
1656 .stop_rx = sci_stop_rx,
1657 .enable_ms = sci_enable_ms,
1658 .break_ctl = sci_break_ctl,
1659 .startup = sci_startup,
1660 .shutdown = sci_shutdown,
1661 .set_termios = sci_set_termios,
1662 .type = sci_type,
1663 .release_port = sci_release_port,
1664 .request_port = sci_request_port,
1665 .config_port = sci_config_port,
1666 .verify_port = sci_verify_port,
07d2a1a1
PM		 1667#ifdef CONFIG_CONSOLE_POLL
1668 .poll_get_char = sci_poll_get_char,
1669 .poll_put_char = sci_poll_put_char,
1670#endif
1da177e4
LT		 1671};
1672
c7ed1ab3
PM		 1673static int __devinit sci_init_single(struct platform_device *dev,
1674 struct sci_port *sci_port,
1675 unsigned int index,
1676 struct plat_sci_port *p)
e108b2ca 1677{
73a19e4c 1678 struct uart_port *port = &sci_port->port;
e108b2ca 1679
73a19e4c
GL		 1680 port->ops = &sci_uart_ops;
1681 port->iotype = UPIO_MEM;
1682 port->line = index;
75136d48
MP		 1683
1684 switch (p->type) {
d1d4b10c
GL		 1685 case PORT_SCIFB:
1686 port->fifosize = 256;
1687 break;
75136d48 1688 case PORT_SCIFA:
73a19e4c 1689 port->fifosize = 64;
75136d48
MP		 1690 break;
1691 case PORT_SCIF:
73a19e4c 1692 port->fifosize = 16;
75136d48
MP		 1693 break;
1694 default:
73a19e4c 1695 port->fifosize = 1;
75136d48
MP		 1696 break;
1697 }
7b6fd3bf
MD		 1698
1699 if (dev) {
c7ed1ab3
PM		 1700 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
1701 if (IS_ERR(sci_port->iclk)) {
1702 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
1703 if (IS_ERR(sci_port->iclk)) {
1704 dev_err(&dev->dev, "can't get iclk\n");
1705 return PTR_ERR(sci_port->iclk);
1706 }
1707 }
1708
1709 /*
1710 * The function clock is optional, ignore it if we can't
1711 * find it.
1712 */
1713 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
1714 if (IS_ERR(sci_port->fclk))
1715 sci_port->fclk = NULL;
1716
7b6fd3bf
MD		 1717 sci_port->enable = sci_clk_enable;
1718 sci_port->disable = sci_clk_disable;
73a19e4c 1719 port->dev = &dev->dev;
7b6fd3bf 1720 }
e108b2ca 1721
7ed7e071
MD		 1722 sci_port->break_timer.data = (unsigned long)sci_port;
1723 sci_port->break_timer.function = sci_break_timer;
1724 init_timer(&sci_port->break_timer);
1725
73a19e4c 1726 port->mapbase = p->mapbase;
7ed7e071 1727
f43dc23d
PM		 1728 port->irq = p->irqs[SCIx_TXI_IRQ];
1729 port->flags = p->flags;
1730 sci_port->type = port->type = p->type;
00b9de9c 1731 sci_port->scscr = p->scscr;
f43dc23d 1732 sci_port->scbrr_algo_id = p->scbrr_algo_id;
73a19e4c
GL		 1733
1734#ifdef CONFIG_SERIAL_SH_SCI_DMA
1735 sci_port->dma_dev = p->dma_dev;
1736 sci_port->slave_tx = p->dma_slave_tx;
1737 sci_port->slave_rx = p->dma_slave_rx;
1738
1739 dev_dbg(port->dev, "%s: DMA device %p, tx %d, rx %d\n", __func__,
1740 p->dma_dev, p->dma_slave_tx, p->dma_slave_rx);
1741#endif
7ed7e071
MD		 1742
1743 memcpy(&sci_port->irqs, &p->irqs, sizeof(p->irqs));
c7ed1ab3 1744 return 0;
e108b2ca
PM		 1745}
1746
1da177e4 1747#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 1748static struct tty_driver *serial_console_device(struct console *co, int *index)
1749{
1750 struct uart_driver *p = &sci_uart_driver;
1751 *index = co->index;
1752 return p->tty_driver;
1753}
1754
1755static void serial_console_putchar(struct uart_port *port, int ch)
1756{
1757 sci_poll_put_char(port, ch);
1758}
1759
1da177e4
LT		 1760/*
1761 * Print a string to the serial port trying not to disturb
1762 * any possible real use of the port...
1763 */
1764static void serial_console_write(struct console *co, const char *s,
1765 unsigned count)
1766{
dc8e6f5b 1767 struct uart_port *port = co->data;
501b825d 1768 struct sci_port *sci_port = to_sci_port(port);
973e5d52 1769 unsigned short bits;
07d2a1a1 1770
501b825d
MD		 1771 if (sci_port->enable)
1772 sci_port->enable(port);
1773
1774 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 1775
1776 /* wait until fifo is empty and last bit has been transmitted */
1777 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
1778 while ((sci_in(port, SCxSR) & bits) != bits)
1779 cpu_relax();
501b825d 1780
345e5a76 1781 if (sci_port->disable)
501b825d 1782 sci_port->disable(port);
1da177e4
LT		 1783}
1784
7b6fd3bf 1785static int __devinit serial_console_setup(struct console *co, char *options)
1da177e4 1786{
dc8e6f5b 1787 struct sci_port *sci_port;
1da177e4
LT		 1788 struct uart_port *port;
1789 int baud = 115200;
1790 int bits = 8;
1791 int parity = 'n';
1792 int flow = 'n';
1793 int ret;
1794
e108b2ca
PM		 1795 /*
1796 * Check whether an invalid uart number has been specified, and
1797 * if so, search for the first available port that does have
1798 * console support.
1799 */
1800 if (co->index >= SCI_NPORTS)
1801 co->index = 0;
1802
7b6fd3bf
MD		 1803 if (co->data) {
1804 port = co->data;
1805 sci_port = to_sci_port(port);
1806 } else {
1807 sci_port = &sci_ports[co->index];
1808 port = &sci_port->port;
1809 co->data = port;
1810 }
1da177e4
LT		 1811
1812 /*
e108b2ca
PM		 1813 * Also need to check port->type, we don't actually have any
1814 * UPIO_PORT ports, but uart_report_port() handily misreports
1815 * it anyways if we don't have a port available by the time this is
1816 * called.
1da177e4 1817 */
e108b2ca
PM		 1818 if (!port->type)
1819 return -ENODEV;
e108b2ca 1820
08f8cb31 1821 sci_config_port(port, 0);
e108b2ca 1822
dc8e6f5b
MD		 1823 if (sci_port->enable)
1824 sci_port->enable(port);
b7a76e4b 1825
1da177e4
LT		 1826 if (options)
1827 uart_parse_options(options, &baud, &parity, &bits, &flow);
1828
1829 ret = uart_set_options(port, co, baud, parity, bits, flow);
1830#if defined(__H8300H__) || defined(__H8300S__)
1831 /* disable rx interrupt */
1832 if (ret == 0)
1833 sci_stop_rx(port);
1834#endif
501b825d 1835 /* TODO: disable clock */
1da177e4
LT		 1836 return ret;
1837}
1838
1839static struct console serial_console = {
1840 .name = "ttySC",
dc8e6f5b 1841 .device = serial_console_device,
1da177e4
LT		 1842 .write = serial_console_write,
1843 .setup = serial_console_setup,
fa5da2f7 1844 .flags = CON_PRINTBUFFER,
1da177e4 1845 .index = -1,
1da177e4
LT		 1846};
1847
1848static int __init sci_console_init(void)
1849{
1850 register_console(&serial_console);
1851 return 0;
1852}
1da177e4 1853console_initcall(sci_console_init);
7b6fd3bf
MD		 1854
1855static struct sci_port early_serial_port;
1856static struct console early_serial_console = {
1857 .name = "early_ttySC",
1858 .write = serial_console_write,
1859 .flags = CON_PRINTBUFFER,
1860};
1861static char early_serial_buf[32];
1862
1da177e4
LT		 1863#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1864
07d2a1a1 1865#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
e7c98dc7 1866#define SCI_CONSOLE (&serial_console)
1da177e4 1867#else
b7a76e4b 1868#define SCI_CONSOLE 0
1da177e4
LT		 1869#endif
1870
1871static char banner[] __initdata =
1872 KERN_INFO "SuperH SCI(F) driver initialized\n";
1873
1874static struct uart_driver sci_uart_driver = {
1875 .owner = THIS_MODULE,
1876 .driver_name = "sci",
1da177e4
LT		 1877 .dev_name = "ttySC",
1878 .major = SCI_MAJOR,
1879 .minor = SCI_MINOR_START,
e108b2ca 1880 .nr = SCI_NPORTS,
1da177e4
LT		 1881 .cons = SCI_CONSOLE,
1882};
1883
e552de24 1884
54507f6e 1885static int sci_remove(struct platform_device *dev)
e552de24
MD		 1886{
1887 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1888 struct sci_port *p;
1889 unsigned long flags;
1890
e552de24 1891 cpufreq_unregister_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
e552de24
MD		 1892
1893 spin_lock_irqsave(&priv->lock, flags);
c7ed1ab3 1894 list_for_each_entry(p, &priv->ports, node) {
e552de24 1895 uart_remove_one_port(&sci_uart_driver, &p->port);
c7ed1ab3
PM		 1896 clk_put(p->iclk);
1897 clk_put(p->fclk);
1898 }
e552de24
MD		 1899 spin_unlock_irqrestore(&priv->lock, flags);
1900
1901 kfree(priv);
1902 return 0;
1903}
1904
0ee70712
MD		 1905static int __devinit sci_probe_single(struct platform_device *dev,
1906 unsigned int index,
1907 struct plat_sci_port *p,
1908 struct sci_port *sciport)
1909{
1910 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1911 unsigned long flags;
1912 int ret;
1913
1914 /* Sanity check */
1915 if (unlikely(index >= SCI_NPORTS)) {
1916 dev_notice(&dev->dev, "Attempting to register port "
1917 "%d when only %d are available.\n",
1918 index+1, SCI_NPORTS);
1919 dev_notice(&dev->dev, "Consider bumping "
1920 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1921 return 0;
1922 }
1923
c7ed1ab3
PM		 1924 ret = sci_init_single(dev, sciport, index, p);
1925 if (ret)
1926 return ret;
0ee70712
MD		 1927
1928 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
08f8cb31 1929 if (ret)
0ee70712 1930 return ret;
0ee70712
MD		 1931
1932 INIT_LIST_HEAD(&sciport->node);
1933
1934 spin_lock_irqsave(&priv->lock, flags);
1935 list_add(&sciport->node, &priv->ports);
1936 spin_unlock_irqrestore(&priv->lock, flags);
1937
1938 return 0;
1939}
1940
e108b2ca
PM		 1941/*
1942 * Register a set of serial devices attached to a platform device. The
1943 * list is terminated with a zero flags entry, which means we expect
1944 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1945 * remapping (such as sh64) should also set UPF_IOREMAP.
1946 */
1947static int __devinit sci_probe(struct platform_device *dev)
1da177e4 1948{
e108b2ca 1949 struct plat_sci_port *p = dev->dev.platform_data;
e552de24 1950 struct sh_sci_priv *priv;
7ff731ae 1951 int i, ret = -EINVAL;
e552de24 1952
7b6fd3bf
MD		 1953#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1954 if (is_early_platform_device(dev)) {
1955 if (dev->id == -1)
1956 return -ENOTSUPP;
1957 early_serial_console.index = dev->id;
1958 early_serial_console.data = &early_serial_port.port;
1959 sci_init_single(NULL, &early_serial_port, dev->id, p);
1960 serial_console_setup(&early_serial_console, early_serial_buf);
1961 if (!strstr(early_serial_buf, "keep"))
1962 early_serial_console.flags |= CON_BOOT;
1963 register_console(&early_serial_console);
1964 return 0;
1965 }
1966#endif
1967
e552de24
MD		 1968 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1969 if (!priv)
1970 return -ENOMEM;
1971
1972 INIT_LIST_HEAD(&priv->ports);
1973 spin_lock_init(&priv->lock);
1974 platform_set_drvdata(dev, priv);
1975
e552de24
MD		 1976 priv->clk_nb.notifier_call = sci_notifier;
1977 cpufreq_register_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
1da177e4 1978
0ee70712
MD		 1979 if (dev->id != -1) {
1980 ret = sci_probe_single(dev, dev->id, p, &sci_ports[dev->id]);
1981 if (ret)
e552de24 1982 goto err_unreg;
0ee70712
MD		 1983 } else {
1984 for (i = 0; p && p->flags != 0; p++, i++) {
1985 ret = sci_probe_single(dev, i, p, &sci_ports[i]);
1986 if (ret)
1987 goto err_unreg;
e552de24 1988 }
e552de24 1989 }
1da177e4
LT		 1990
1991#ifdef CONFIG_SH_STANDARD_BIOS
1992 sh_bios_gdb_detach();
1993#endif
1994
e108b2ca 1995 return 0;
7ff731ae
PM		 1996
1997err_unreg:
e552de24 1998 sci_remove(dev);
7ff731ae 1999 return ret;
1da177e4
LT		 2000}
2001
6daa79b3 2002static int sci_suspend(struct device *dev)
1da177e4 2003{
6daa79b3 2004 struct sh_sci_priv *priv = dev_get_drvdata(dev);
e552de24
MD		 2005 struct sci_port *p;
2006 unsigned long flags;
e108b2ca 2007
e552de24
MD		 2008 spin_lock_irqsave(&priv->lock, flags);
2009 list_for_each_entry(p, &priv->ports, node)
2010 uart_suspend_port(&sci_uart_driver, &p->port);
e552de24 2011 spin_unlock_irqrestore(&priv->lock, flags);
1da177e4 2012
e108b2ca
PM		 2013 return 0;
2014}
1da177e4 2015
6daa79b3 2016static int sci_resume(struct device *dev)
e108b2ca 2017{
6daa79b3 2018 struct sh_sci_priv *priv = dev_get_drvdata(dev);
e552de24
MD		 2019 struct sci_port *p;
2020 unsigned long flags;
e108b2ca 2021
e552de24
MD		 2022 spin_lock_irqsave(&priv->lock, flags);
2023 list_for_each_entry(p, &priv->ports, node)
2024 uart_resume_port(&sci_uart_driver, &p->port);
e552de24 2025 spin_unlock_irqrestore(&priv->lock, flags);
e108b2ca
PM		 2026
2027 return 0;
2028}
2029
47145210 2030static const struct dev_pm_ops sci_dev_pm_ops = {
6daa79b3
PM		 2031 .suspend = sci_suspend,
2032 .resume = sci_resume,
2033};
2034
e108b2ca
PM		 2035static struct platform_driver sci_driver = {
2036 .probe = sci_probe,
b9e39c89 2037 .remove = sci_remove,
e108b2ca
PM		 2038 .driver = {
2039 .name = "sh-sci",
2040 .owner = THIS_MODULE,
6daa79b3 2041 .pm = &sci_dev_pm_ops,
e108b2ca
PM		 2042 },
2043};
2044
2045static int __init sci_init(void)
2046{
2047 int ret;
2048
2049 printk(banner);
2050
e108b2ca
PM		 2051 ret = uart_register_driver(&sci_uart_driver);
2052 if (likely(ret == 0)) {
2053 ret = platform_driver_register(&sci_driver);
2054 if (unlikely(ret))
2055 uart_unregister_driver(&sci_uart_driver);
2056 }
2057
2058 return ret;
2059}
2060
2061static void __exit sci_exit(void)
2062{
2063 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2064 uart_unregister_driver(&sci_uart_driver);
2065}
2066
7b6fd3bf
MD		 2067#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2068early_platform_init_buffer("earlyprintk", &sci_driver,
2069 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2070#endif
1da177e4
LT		 2071module_init(sci_init);
2072module_exit(sci_exit);
2073
e108b2ca 2074MODULE_LICENSE("GPL");
e169c139 2075MODULE_ALIAS("platform:sh-sci");
Linux 6.x block layer and io_uring tree(s)