Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/serial/sh-sci.c | |
3 | * | |
4 | * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) | |
5 | * | |
7ff731ae | 6 | * Copyright (C) 2002 - 2008 Paul Mundt |
3ea6bc3d | 7 | * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). |
1da177e4 LT |
8 | * |
9 | * based off of the old drivers/char/sh-sci.c by: | |
10 | * | |
11 | * Copyright (C) 1999, 2000 Niibe Yutaka | |
12 | * Copyright (C) 2000 Sugioka Toshinobu | |
13 | * Modified to support multiple serial ports. Stuart Menefy (May 2000). | |
14 | * Modified to support SecureEdge. David McCullough (2002) | |
15 | * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). | |
d89ddd1c | 16 | * Removed SH7300 support (Jul 2007). |
1da177e4 LT |
17 | * |
18 | * This file is subject to the terms and conditions of the GNU General Public | |
19 | * License. See the file "COPYING" in the main directory of this archive | |
20 | * for more details. | |
21 | */ | |
0b3d4ef6 PM |
22 | #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
23 | #define SUPPORT_SYSRQ | |
24 | #endif | |
1da177e4 LT |
25 | |
26 | #undef DEBUG | |
27 | ||
1da177e4 LT |
28 | #include <linux/module.h> |
29 | #include <linux/errno.h> | |
1da177e4 LT |
30 | #include <linux/timer.h> |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/tty.h> | |
33 | #include <linux/tty_flip.h> | |
34 | #include <linux/serial.h> | |
35 | #include <linux/major.h> | |
36 | #include <linux/string.h> | |
37 | #include <linux/sysrq.h> | |
1da177e4 LT |
38 | #include <linux/ioport.h> |
39 | #include <linux/mm.h> | |
1da177e4 LT |
40 | #include <linux/init.h> |
41 | #include <linux/delay.h> | |
42 | #include <linux/console.h> | |
e108b2ca | 43 | #include <linux/platform_device.h> |
96de1a8f | 44 | #include <linux/serial_sci.h> |
1da177e4 LT |
45 | #include <linux/notifier.h> |
46 | #include <linux/cpufreq.h> | |
85f094ec | 47 | #include <linux/clk.h> |
fa5da2f7 | 48 | #include <linux/ctype.h> |
7ff731ae | 49 | #include <linux/err.h> |
e552de24 | 50 | #include <linux/list.h> |
85f094ec PM |
51 | |
52 | #ifdef CONFIG_SUPERH | |
b7a76e4b | 53 | #include <asm/clock.h> |
1da177e4 LT |
54 | #include <asm/sh_bios.h> |
55 | #endif | |
56 | ||
168f3623 YS |
57 | #ifdef CONFIG_H8300 |
58 | #include <asm/gpio.h> | |
59 | #endif | |
60 | ||
1da177e4 LT |
61 | #include "sh-sci.h" |
62 | ||
e108b2ca PM |
63 | struct sci_port { |
64 | struct uart_port port; | |
65 | ||
66 | /* Port type */ | |
67 | unsigned int type; | |
68 | ||
69 | /* Port IRQs: ERI, RXI, TXI, BRI (optional) */ | |
32351a28 | 70 | unsigned int irqs[SCIx_NR_IRQS]; |
e108b2ca | 71 | |
e108b2ca PM |
72 | /* Port enable callback */ |
73 | void (*enable)(struct uart_port *port); | |
74 | ||
75 | /* Port disable callback */ | |
76 | void (*disable)(struct uart_port *port); | |
77 | ||
78 | /* Break timer */ | |
79 | struct timer_list break_timer; | |
80 | int break_flag; | |
1534a3b3 | 81 | |
a2159b52 | 82 | #ifdef CONFIG_HAVE_CLK |
501b825d MD |
83 | /* Interface clock */ |
84 | struct clk *iclk; | |
85 | /* Data clock */ | |
86 | struct clk *dclk; | |
e552de24 MD |
87 | #endif |
88 | struct list_head node; | |
89 | }; | |
90 | ||
91 | struct sh_sci_priv { | |
92 | spinlock_t lock; | |
93 | struct list_head ports; | |
94 | ||
95 | #ifdef CONFIG_HAVE_CLK | |
96 | struct notifier_block clk_nb; | |
005a336e | 97 | #endif |
e108b2ca PM |
98 | }; |
99 | ||
1da177e4 | 100 | /* Function prototypes */ |
b129a8cc | 101 | static void sci_stop_tx(struct uart_port *port); |
1da177e4 | 102 | |
e108b2ca | 103 | #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS |
b7a76e4b | 104 | |
e108b2ca PM |
105 | static struct sci_port sci_ports[SCI_NPORTS]; |
106 | static struct uart_driver sci_uart_driver; | |
1da177e4 | 107 | |
e7c98dc7 MT |
108 | static inline struct sci_port * |
109 | to_sci_port(struct uart_port *uart) | |
110 | { | |
111 | return container_of(uart, struct sci_port, port); | |
112 | } | |
113 | ||
07d2a1a1 | 114 | #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) |
1f6fd5c9 PM |
115 | |
116 | #ifdef CONFIG_CONSOLE_POLL | |
e108b2ca PM |
117 | static inline void handle_error(struct uart_port *port) |
118 | { | |
119 | /* Clear error flags */ | |
1da177e4 LT |
120 | sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); |
121 | } | |
122 | ||
07d2a1a1 | 123 | static int sci_poll_get_char(struct uart_port *port) |
1da177e4 | 124 | { |
1da177e4 LT |
125 | unsigned short status; |
126 | int c; | |
127 | ||
e108b2ca | 128 | do { |
1da177e4 LT |
129 | status = sci_in(port, SCxSR); |
130 | if (status & SCxSR_ERRORS(port)) { | |
131 | handle_error(port); | |
132 | continue; | |
133 | } | |
134 | } while (!(status & SCxSR_RDxF(port))); | |
07d2a1a1 | 135 | |
1da177e4 | 136 | c = sci_in(port, SCxRDR); |
07d2a1a1 | 137 | |
e7c98dc7 MT |
138 | /* Dummy read */ |
139 | sci_in(port, SCxSR); | |
1da177e4 | 140 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); |
1da177e4 LT |
141 | |
142 | return c; | |
143 | } | |
1f6fd5c9 | 144 | #endif |
1da177e4 | 145 | |
07d2a1a1 | 146 | static void sci_poll_put_char(struct uart_port *port, unsigned char c) |
1da177e4 | 147 | { |
1da177e4 LT |
148 | unsigned short status; |
149 | ||
1da177e4 LT |
150 | do { |
151 | status = sci_in(port, SCxSR); | |
152 | } while (!(status & SCxSR_TDxE(port))); | |
153 | ||
272966c0 | 154 | sci_out(port, SCxTDR, c); |
dd0a3e77 | 155 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); |
1da177e4 | 156 | } |
07d2a1a1 | 157 | #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */ |
1da177e4 LT |
158 | |
159 | #if defined(__H8300S__) | |
160 | enum { sci_disable, sci_enable }; | |
161 | ||
e7c98dc7 | 162 | static void h8300_sci_config(struct uart_port *port, unsigned int ctrl) |
1da177e4 | 163 | { |
e7c98dc7 | 164 | volatile unsigned char *mstpcrl = (volatile unsigned char *)MSTPCRL; |
1da177e4 LT |
165 | int ch = (port->mapbase - SMR0) >> 3; |
166 | unsigned char mask = 1 << (ch+1); | |
167 | ||
e7c98dc7 | 168 | if (ctrl == sci_disable) |
1da177e4 | 169 | *mstpcrl |= mask; |
e7c98dc7 | 170 | else |
1da177e4 | 171 | *mstpcrl &= ~mask; |
1da177e4 | 172 | } |
e108b2ca | 173 | |
501b825d | 174 | static void h8300_sci_enable(struct uart_port *port) |
e108b2ca PM |
175 | { |
176 | h8300_sci_config(port, sci_enable); | |
177 | } | |
178 | ||
501b825d | 179 | static void h8300_sci_disable(struct uart_port *port) |
e108b2ca PM |
180 | { |
181 | h8300_sci_config(port, sci_disable); | |
182 | } | |
1da177e4 LT |
183 | #endif |
184 | ||
15c73aaa | 185 | #if defined(__H8300H__) || defined(__H8300S__) |
d5701647 | 186 | static void sci_init_pins(struct uart_port *port, unsigned int cflag) |
1da177e4 LT |
187 | { |
188 | int ch = (port->mapbase - SMR0) >> 3; | |
189 | ||
190 | /* set DDR regs */ | |
e108b2ca PM |
191 | H8300_GPIO_DDR(h8300_sci_pins[ch].port, |
192 | h8300_sci_pins[ch].rx, | |
193 | H8300_GPIO_INPUT); | |
194 | H8300_GPIO_DDR(h8300_sci_pins[ch].port, | |
195 | h8300_sci_pins[ch].tx, | |
196 | H8300_GPIO_OUTPUT); | |
197 | ||
1da177e4 LT |
198 | /* tx mark output*/ |
199 | H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx; | |
200 | } | |
d5701647 PM |
201 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
202 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) | |
e108b2ca | 203 | { |
d5701647 PM |
204 | if (port->mapbase == 0xA4400000) { |
205 | __raw_writew(__raw_readw(PACR) & 0xffc0, PACR); | |
206 | __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR); | |
207 | } else if (port->mapbase == 0xA4410000) | |
208 | __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR); | |
9465a54f | 209 | } |
31a49c4b | 210 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721) |
d5701647 | 211 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
3ea6bc3d | 212 | { |
3ea6bc3d MB |
213 | unsigned short data; |
214 | ||
215 | if (cflag & CRTSCTS) { | |
216 | /* enable RTS/CTS */ | |
217 | if (port->mapbase == 0xa4430000) { /* SCIF0 */ | |
218 | /* Clear PTCR bit 9-2; enable all scif pins but sck */ | |
d5701647 PM |
219 | data = __raw_readw(PORT_PTCR); |
220 | __raw_writew((data & 0xfc03), PORT_PTCR); | |
3ea6bc3d MB |
221 | } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ |
222 | /* Clear PVCR bit 9-2 */ | |
d5701647 PM |
223 | data = __raw_readw(PORT_PVCR); |
224 | __raw_writew((data & 0xfc03), PORT_PVCR); | |
3ea6bc3d | 225 | } |
3ea6bc3d MB |
226 | } else { |
227 | if (port->mapbase == 0xa4430000) { /* SCIF0 */ | |
228 | /* Clear PTCR bit 5-2; enable only tx and rx */ | |
d5701647 PM |
229 | data = __raw_readw(PORT_PTCR); |
230 | __raw_writew((data & 0xffc3), PORT_PTCR); | |
3ea6bc3d MB |
231 | } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ |
232 | /* Clear PVCR bit 5-2 */ | |
d5701647 PM |
233 | data = __raw_readw(PORT_PVCR); |
234 | __raw_writew((data & 0xffc3), PORT_PVCR); | |
3ea6bc3d MB |
235 | } |
236 | } | |
3ea6bc3d | 237 | } |
b7a76e4b | 238 | #elif defined(CONFIG_CPU_SH3) |
e108b2ca | 239 | /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */ |
d5701647 | 240 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
1da177e4 | 241 | { |
b7a76e4b PM |
242 | unsigned short data; |
243 | ||
244 | /* We need to set SCPCR to enable RTS/CTS */ | |
d5701647 | 245 | data = __raw_readw(SCPCR); |
b7a76e4b | 246 | /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/ |
d5701647 | 247 | __raw_writew(data & 0x0fcf, SCPCR); |
1da177e4 | 248 | |
d5701647 | 249 | if (!(cflag & CRTSCTS)) { |
1da177e4 | 250 | /* We need to set SCPCR to enable RTS/CTS */ |
d5701647 | 251 | data = __raw_readw(SCPCR); |
1da177e4 LT |
252 | /* Clear out SCP7MD1,0, SCP4MD1,0, |
253 | Set SCP6MD1,0 = {01} (output) */ | |
d5701647 | 254 | __raw_writew((data & 0x0fcf) | 0x1000, SCPCR); |
1da177e4 LT |
255 | |
256 | data = ctrl_inb(SCPDR); | |
257 | /* Set /RTS2 (bit6) = 0 */ | |
b7a76e4b | 258 | ctrl_outb(data & 0xbf, SCPDR); |
1da177e4 | 259 | } |
1da177e4 | 260 | } |
41504c39 | 261 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) |
d5701647 | 262 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
41504c39 | 263 | { |
346b7463 | 264 | unsigned short data; |
41504c39 | 265 | |
346b7463 | 266 | if (port->mapbase == 0xffe00000) { |
d5701647 | 267 | data = __raw_readw(PSCR); |
346b7463 | 268 | data &= ~0x03cf; |
d5701647 | 269 | if (!(cflag & CRTSCTS)) |
346b7463 | 270 | data |= 0x0340; |
41504c39 | 271 | |
d5701647 | 272 | __raw_writew(data, PSCR); |
41504c39 | 273 | } |
178dd0cd | 274 | } |
7d740a06 YS |
275 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ |
276 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | |
2b1bd1ac | 277 | defined(CONFIG_CPU_SUBTYPE_SH7785) || \ |
55ba99eb | 278 | defined(CONFIG_CPU_SUBTYPE_SH7786) || \ |
2b1bd1ac | 279 | defined(CONFIG_CPU_SUBTYPE_SHX3) |
d5701647 PM |
280 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
281 | { | |
282 | if (!(cflag & CRTSCTS)) | |
283 | __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */ | |
284 | } | |
b0c50ad7 | 285 | #elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A) |
d5701647 PM |
286 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
287 | { | |
288 | if (!(cflag & CRTSCTS)) | |
289 | __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */ | |
290 | } | |
b7a76e4b | 291 | #else |
d5701647 PM |
292 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
293 | { | |
294 | /* Nothing to do */ | |
1da177e4 | 295 | } |
e108b2ca PM |
296 | #endif |
297 | ||
32351a28 PM |
298 | #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \ |
299 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | |
55ba99eb KM |
300 | defined(CONFIG_CPU_SUBTYPE_SH7785) || \ |
301 | defined(CONFIG_CPU_SUBTYPE_SH7786) | |
e108b2ca PM |
302 | static inline int scif_txroom(struct uart_port *port) |
303 | { | |
cae167d3 | 304 | return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff); |
e108b2ca PM |
305 | } |
306 | ||
307 | static inline int scif_rxroom(struct uart_port *port) | |
308 | { | |
cae167d3 | 309 | return sci_in(port, SCRFDR) & 0xff; |
e108b2ca | 310 | } |
c63847a3 NI |
311 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) |
312 | static inline int scif_txroom(struct uart_port *port) | |
313 | { | |
e7c98dc7 MT |
314 | if ((port->mapbase == 0xffe00000) || |
315 | (port->mapbase == 0xffe08000)) { | |
316 | /* SCIF0/1*/ | |
c63847a3 | 317 | return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff); |
e7c98dc7 MT |
318 | } else { |
319 | /* SCIF2 */ | |
c63847a3 | 320 | return SCIF2_TXROOM_MAX - (sci_in(port, SCFDR) >> 8); |
e7c98dc7 | 321 | } |
c63847a3 NI |
322 | } |
323 | ||
324 | static inline int scif_rxroom(struct uart_port *port) | |
325 | { | |
e7c98dc7 MT |
326 | if ((port->mapbase == 0xffe00000) || |
327 | (port->mapbase == 0xffe08000)) { | |
328 | /* SCIF0/1*/ | |
c63847a3 | 329 | return sci_in(port, SCRFDR) & 0xff; |
e7c98dc7 MT |
330 | } else { |
331 | /* SCIF2 */ | |
c63847a3 | 332 | return sci_in(port, SCFDR) & SCIF2_RFDC_MASK; |
e7c98dc7 | 333 | } |
c63847a3 | 334 | } |
e108b2ca PM |
335 | #else |
336 | static inline int scif_txroom(struct uart_port *port) | |
337 | { | |
338 | return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8); | |
339 | } | |
1da177e4 | 340 | |
e108b2ca PM |
341 | static inline int scif_rxroom(struct uart_port *port) |
342 | { | |
343 | return sci_in(port, SCFDR) & SCIF_RFDC_MASK; | |
344 | } | |
1da177e4 | 345 | #endif |
1da177e4 | 346 | |
e108b2ca PM |
347 | static inline int sci_txroom(struct uart_port *port) |
348 | { | |
e7c98dc7 | 349 | return (sci_in(port, SCxSR) & SCI_TDRE) != 0; |
e108b2ca PM |
350 | } |
351 | ||
352 | static inline int sci_rxroom(struct uart_port *port) | |
353 | { | |
e7c98dc7 | 354 | return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; |
e108b2ca PM |
355 | } |
356 | ||
1da177e4 LT |
357 | /* ********************************************************************** * |
358 | * the interrupt related routines * | |
359 | * ********************************************************************** */ | |
360 | ||
361 | static void sci_transmit_chars(struct uart_port *port) | |
362 | { | |
363 | struct circ_buf *xmit = &port->info->xmit; | |
364 | unsigned int stopped = uart_tx_stopped(port); | |
1da177e4 LT |
365 | unsigned short status; |
366 | unsigned short ctrl; | |
e108b2ca | 367 | int count; |
1da177e4 LT |
368 | |
369 | status = sci_in(port, SCxSR); | |
370 | if (!(status & SCxSR_TDxE(port))) { | |
1da177e4 | 371 | ctrl = sci_in(port, SCSCR); |
e7c98dc7 | 372 | if (uart_circ_empty(xmit)) |
1da177e4 | 373 | ctrl &= ~SCI_CTRL_FLAGS_TIE; |
e7c98dc7 | 374 | else |
1da177e4 | 375 | ctrl |= SCI_CTRL_FLAGS_TIE; |
1da177e4 | 376 | sci_out(port, SCSCR, ctrl); |
1da177e4 LT |
377 | return; |
378 | } | |
379 | ||
1a22f08d | 380 | if (port->type == PORT_SCI) |
e108b2ca | 381 | count = sci_txroom(port); |
1a22f08d YS |
382 | else |
383 | count = scif_txroom(port); | |
1da177e4 LT |
384 | |
385 | do { | |
386 | unsigned char c; | |
387 | ||
388 | if (port->x_char) { | |
389 | c = port->x_char; | |
390 | port->x_char = 0; | |
391 | } else if (!uart_circ_empty(xmit) && !stopped) { | |
392 | c = xmit->buf[xmit->tail]; | |
393 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
394 | } else { | |
395 | break; | |
396 | } | |
397 | ||
398 | sci_out(port, SCxTDR, c); | |
399 | ||
400 | port->icount.tx++; | |
401 | } while (--count > 0); | |
402 | ||
403 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); | |
404 | ||
405 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
406 | uart_write_wakeup(port); | |
407 | if (uart_circ_empty(xmit)) { | |
b129a8cc | 408 | sci_stop_tx(port); |
1da177e4 | 409 | } else { |
1da177e4 LT |
410 | ctrl = sci_in(port, SCSCR); |
411 | ||
1a22f08d | 412 | if (port->type != PORT_SCI) { |
1da177e4 LT |
413 | sci_in(port, SCxSR); /* Dummy read */ |
414 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); | |
415 | } | |
1da177e4 LT |
416 | |
417 | ctrl |= SCI_CTRL_FLAGS_TIE; | |
418 | sci_out(port, SCSCR, ctrl); | |
1da177e4 LT |
419 | } |
420 | } | |
421 | ||
422 | /* On SH3, SCIF may read end-of-break as a space->mark char */ | |
e7c98dc7 | 423 | #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) |
1da177e4 | 424 | |
7d12e780 | 425 | static inline void sci_receive_chars(struct uart_port *port) |
1da177e4 | 426 | { |
e7c98dc7 | 427 | struct sci_port *sci_port = to_sci_port(port); |
a88487c7 | 428 | struct tty_struct *tty = port->info->port.tty; |
1da177e4 LT |
429 | int i, count, copied = 0; |
430 | unsigned short status; | |
33f0f88f | 431 | unsigned char flag; |
1da177e4 LT |
432 | |
433 | status = sci_in(port, SCxSR); | |
434 | if (!(status & SCxSR_RDxF(port))) | |
435 | return; | |
436 | ||
437 | while (1) { | |
1a22f08d | 438 | if (port->type == PORT_SCI) |
e108b2ca | 439 | count = sci_rxroom(port); |
1a22f08d YS |
440 | else |
441 | count = scif_rxroom(port); | |
1da177e4 LT |
442 | |
443 | /* Don't copy more bytes than there is room for in the buffer */ | |
33f0f88f | 444 | count = tty_buffer_request_room(tty, count); |
1da177e4 LT |
445 | |
446 | /* If for any reason we can't copy more data, we're done! */ | |
447 | if (count == 0) | |
448 | break; | |
449 | ||
450 | if (port->type == PORT_SCI) { | |
451 | char c = sci_in(port, SCxRDR); | |
e7c98dc7 MT |
452 | if (uart_handle_sysrq_char(port, c) || |
453 | sci_port->break_flag) | |
1da177e4 | 454 | count = 0; |
e7c98dc7 | 455 | else |
e108b2ca | 456 | tty_insert_flip_char(tty, c, TTY_NORMAL); |
1da177e4 | 457 | } else { |
e7c98dc7 | 458 | for (i = 0; i < count; i++) { |
1da177e4 LT |
459 | char c = sci_in(port, SCxRDR); |
460 | status = sci_in(port, SCxSR); | |
461 | #if defined(CONFIG_CPU_SH3) | |
462 | /* Skip "chars" during break */ | |
e108b2ca | 463 | if (sci_port->break_flag) { |
1da177e4 LT |
464 | if ((c == 0) && |
465 | (status & SCxSR_FER(port))) { | |
466 | count--; i--; | |
467 | continue; | |
468 | } | |
e108b2ca | 469 | |
1da177e4 | 470 | /* Nonzero => end-of-break */ |
762c69e3 | 471 | dev_dbg(port->dev, "debounce<%02x>\n", c); |
e108b2ca PM |
472 | sci_port->break_flag = 0; |
473 | ||
1da177e4 LT |
474 | if (STEPFN(c)) { |
475 | count--; i--; | |
476 | continue; | |
477 | } | |
478 | } | |
479 | #endif /* CONFIG_CPU_SH3 */ | |
7d12e780 | 480 | if (uart_handle_sysrq_char(port, c)) { |
1da177e4 LT |
481 | count--; i--; |
482 | continue; | |
483 | } | |
484 | ||
485 | /* Store data and status */ | |
1da177e4 | 486 | if (status&SCxSR_FER(port)) { |
33f0f88f | 487 | flag = TTY_FRAME; |
762c69e3 | 488 | dev_notice(port->dev, "frame error\n"); |
1da177e4 | 489 | } else if (status&SCxSR_PER(port)) { |
33f0f88f | 490 | flag = TTY_PARITY; |
762c69e3 | 491 | dev_notice(port->dev, "parity error\n"); |
33f0f88f AC |
492 | } else |
493 | flag = TTY_NORMAL; | |
762c69e3 | 494 | |
33f0f88f | 495 | tty_insert_flip_char(tty, c, flag); |
1da177e4 LT |
496 | } |
497 | } | |
498 | ||
499 | sci_in(port, SCxSR); /* dummy read */ | |
500 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
501 | ||
1da177e4 LT |
502 | copied += count; |
503 | port->icount.rx += count; | |
504 | } | |
505 | ||
506 | if (copied) { | |
507 | /* Tell the rest of the system the news. New characters! */ | |
508 | tty_flip_buffer_push(tty); | |
509 | } else { | |
510 | sci_in(port, SCxSR); /* dummy read */ | |
511 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
512 | } | |
513 | } | |
514 | ||
515 | #define SCI_BREAK_JIFFIES (HZ/20) | |
516 | /* The sci generates interrupts during the break, | |
517 | * 1 per millisecond or so during the break period, for 9600 baud. | |
518 | * So dont bother disabling interrupts. | |
519 | * But dont want more than 1 break event. | |
520 | * Use a kernel timer to periodically poll the rx line until | |
521 | * the break is finished. | |
522 | */ | |
523 | static void sci_schedule_break_timer(struct sci_port *port) | |
524 | { | |
525 | port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES; | |
526 | add_timer(&port->break_timer); | |
527 | } | |
528 | /* Ensure that two consecutive samples find the break over. */ | |
529 | static void sci_break_timer(unsigned long data) | |
530 | { | |
e108b2ca PM |
531 | struct sci_port *port = (struct sci_port *)data; |
532 | ||
533 | if (sci_rxd_in(&port->port) == 0) { | |
1da177e4 | 534 | port->break_flag = 1; |
e108b2ca PM |
535 | sci_schedule_break_timer(port); |
536 | } else if (port->break_flag == 1) { | |
1da177e4 LT |
537 | /* break is over. */ |
538 | port->break_flag = 2; | |
e108b2ca PM |
539 | sci_schedule_break_timer(port); |
540 | } else | |
541 | port->break_flag = 0; | |
1da177e4 LT |
542 | } |
543 | ||
544 | static inline int sci_handle_errors(struct uart_port *port) | |
545 | { | |
546 | int copied = 0; | |
547 | unsigned short status = sci_in(port, SCxSR); | |
a88487c7 | 548 | struct tty_struct *tty = port->info->port.tty; |
1da177e4 | 549 | |
e108b2ca | 550 | if (status & SCxSR_ORER(port)) { |
1da177e4 | 551 | /* overrun error */ |
e108b2ca | 552 | if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) |
33f0f88f | 553 | copied++; |
762c69e3 PM |
554 | |
555 | dev_notice(port->dev, "overrun error"); | |
1da177e4 LT |
556 | } |
557 | ||
e108b2ca | 558 | if (status & SCxSR_FER(port)) { |
1da177e4 LT |
559 | if (sci_rxd_in(port) == 0) { |
560 | /* Notify of BREAK */ | |
e7c98dc7 | 561 | struct sci_port *sci_port = to_sci_port(port); |
e108b2ca PM |
562 | |
563 | if (!sci_port->break_flag) { | |
564 | sci_port->break_flag = 1; | |
565 | sci_schedule_break_timer(sci_port); | |
566 | ||
1da177e4 | 567 | /* Do sysrq handling. */ |
e108b2ca | 568 | if (uart_handle_break(port)) |
1da177e4 | 569 | return 0; |
762c69e3 PM |
570 | |
571 | dev_dbg(port->dev, "BREAK detected\n"); | |
572 | ||
e108b2ca | 573 | if (tty_insert_flip_char(tty, 0, TTY_BREAK)) |
e7c98dc7 MT |
574 | copied++; |
575 | } | |
576 | ||
e108b2ca | 577 | } else { |
1da177e4 | 578 | /* frame error */ |
e108b2ca | 579 | if (tty_insert_flip_char(tty, 0, TTY_FRAME)) |
33f0f88f | 580 | copied++; |
762c69e3 PM |
581 | |
582 | dev_notice(port->dev, "frame error\n"); | |
1da177e4 LT |
583 | } |
584 | } | |
585 | ||
e108b2ca | 586 | if (status & SCxSR_PER(port)) { |
1da177e4 | 587 | /* parity error */ |
e108b2ca PM |
588 | if (tty_insert_flip_char(tty, 0, TTY_PARITY)) |
589 | copied++; | |
762c69e3 PM |
590 | |
591 | dev_notice(port->dev, "parity error"); | |
1da177e4 LT |
592 | } |
593 | ||
33f0f88f | 594 | if (copied) |
1da177e4 | 595 | tty_flip_buffer_push(tty); |
1da177e4 LT |
596 | |
597 | return copied; | |
598 | } | |
599 | ||
d830fa45 PM |
600 | static inline int sci_handle_fifo_overrun(struct uart_port *port) |
601 | { | |
602 | struct tty_struct *tty = port->info->port.tty; | |
603 | int copied = 0; | |
604 | ||
605 | if (port->type != PORT_SCIF) | |
606 | return 0; | |
607 | ||
608 | if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) { | |
609 | sci_out(port, SCLSR, 0); | |
610 | ||
611 | tty_insert_flip_char(tty, 0, TTY_OVERRUN); | |
612 | tty_flip_buffer_push(tty); | |
613 | ||
614 | dev_notice(port->dev, "overrun error\n"); | |
615 | copied++; | |
616 | } | |
617 | ||
618 | return copied; | |
619 | } | |
620 | ||
1da177e4 LT |
621 | static inline int sci_handle_breaks(struct uart_port *port) |
622 | { | |
623 | int copied = 0; | |
624 | unsigned short status = sci_in(port, SCxSR); | |
a88487c7 | 625 | struct tty_struct *tty = port->info->port.tty; |
a5660ada | 626 | struct sci_port *s = to_sci_port(port); |
1da177e4 | 627 | |
0b3d4ef6 PM |
628 | if (uart_handle_break(port)) |
629 | return 0; | |
630 | ||
b7a76e4b | 631 | if (!s->break_flag && status & SCxSR_BRK(port)) { |
1da177e4 LT |
632 | #if defined(CONFIG_CPU_SH3) |
633 | /* Debounce break */ | |
634 | s->break_flag = 1; | |
635 | #endif | |
636 | /* Notify of BREAK */ | |
e108b2ca | 637 | if (tty_insert_flip_char(tty, 0, TTY_BREAK)) |
33f0f88f | 638 | copied++; |
762c69e3 PM |
639 | |
640 | dev_dbg(port->dev, "BREAK detected\n"); | |
1da177e4 LT |
641 | } |
642 | ||
33f0f88f | 643 | if (copied) |
1da177e4 | 644 | tty_flip_buffer_push(tty); |
e108b2ca | 645 | |
d830fa45 PM |
646 | copied += sci_handle_fifo_overrun(port); |
647 | ||
1da177e4 LT |
648 | return copied; |
649 | } | |
650 | ||
7d12e780 | 651 | static irqreturn_t sci_rx_interrupt(int irq, void *port) |
1da177e4 | 652 | { |
1da177e4 LT |
653 | /* I think sci_receive_chars has to be called irrespective |
654 | * of whether the I_IXOFF is set, otherwise, how is the interrupt | |
655 | * to be disabled? | |
656 | */ | |
7d12e780 | 657 | sci_receive_chars(port); |
1da177e4 LT |
658 | |
659 | return IRQ_HANDLED; | |
660 | } | |
661 | ||
7d12e780 | 662 | static irqreturn_t sci_tx_interrupt(int irq, void *ptr) |
1da177e4 LT |
663 | { |
664 | struct uart_port *port = ptr; | |
665 | ||
e108b2ca | 666 | spin_lock_irq(&port->lock); |
1da177e4 | 667 | sci_transmit_chars(port); |
e108b2ca | 668 | spin_unlock_irq(&port->lock); |
1da177e4 LT |
669 | |
670 | return IRQ_HANDLED; | |
671 | } | |
672 | ||
7d12e780 | 673 | static irqreturn_t sci_er_interrupt(int irq, void *ptr) |
1da177e4 LT |
674 | { |
675 | struct uart_port *port = ptr; | |
676 | ||
677 | /* Handle errors */ | |
678 | if (port->type == PORT_SCI) { | |
679 | if (sci_handle_errors(port)) { | |
680 | /* discard character in rx buffer */ | |
681 | sci_in(port, SCxSR); | |
682 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
683 | } | |
684 | } else { | |
d830fa45 | 685 | sci_handle_fifo_overrun(port); |
7d12e780 | 686 | sci_rx_interrupt(irq, ptr); |
1da177e4 LT |
687 | } |
688 | ||
689 | sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); | |
690 | ||
691 | /* Kick the transmission */ | |
7d12e780 | 692 | sci_tx_interrupt(irq, ptr); |
1da177e4 LT |
693 | |
694 | return IRQ_HANDLED; | |
695 | } | |
696 | ||
7d12e780 | 697 | static irqreturn_t sci_br_interrupt(int irq, void *ptr) |
1da177e4 LT |
698 | { |
699 | struct uart_port *port = ptr; | |
700 | ||
701 | /* Handle BREAKs */ | |
702 | sci_handle_breaks(port); | |
703 | sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port)); | |
704 | ||
705 | return IRQ_HANDLED; | |
706 | } | |
707 | ||
7d12e780 | 708 | static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) |
1da177e4 | 709 | { |
44e18e9e | 710 | unsigned short ssr_status, scr_status, err_enabled; |
a8884e34 MT |
711 | struct uart_port *port = ptr; |
712 | irqreturn_t ret = IRQ_NONE; | |
1da177e4 | 713 | |
e7c98dc7 MT |
714 | ssr_status = sci_in(port, SCxSR); |
715 | scr_status = sci_in(port, SCSCR); | |
44e18e9e | 716 | err_enabled = scr_status & (SCI_CTRL_FLAGS_REIE | SCI_CTRL_FLAGS_RIE); |
1da177e4 LT |
717 | |
718 | /* Tx Interrupt */ | |
dd4da3a5 | 719 | if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCI_CTRL_FLAGS_TIE)) |
a8884e34 | 720 | ret = sci_tx_interrupt(irq, ptr); |
1da177e4 | 721 | /* Rx Interrupt */ |
dd4da3a5 | 722 | if ((ssr_status & SCxSR_RDxF(port)) && (scr_status & SCI_CTRL_FLAGS_RIE)) |
a8884e34 | 723 | ret = sci_rx_interrupt(irq, ptr); |
1da177e4 | 724 | /* Error Interrupt */ |
dd4da3a5 | 725 | if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) |
a8884e34 | 726 | ret = sci_er_interrupt(irq, ptr); |
1da177e4 | 727 | /* Break Interrupt */ |
dd4da3a5 | 728 | if ((ssr_status & SCxSR_BRK(port)) && err_enabled) |
a8884e34 | 729 | ret = sci_br_interrupt(irq, ptr); |
1da177e4 | 730 | |
a8884e34 | 731 | return ret; |
1da177e4 LT |
732 | } |
733 | ||
027e6872 | 734 | #ifdef CONFIG_HAVE_CLK |
1da177e4 LT |
735 | /* |
736 | * Here we define a transistion notifier so that we can update all of our | |
737 | * ports' baud rate when the peripheral clock changes. | |
738 | */ | |
e108b2ca PM |
739 | static int sci_notifier(struct notifier_block *self, |
740 | unsigned long phase, void *p) | |
1da177e4 | 741 | { |
e552de24 MD |
742 | struct sh_sci_priv *priv = container_of(self, |
743 | struct sh_sci_priv, clk_nb); | |
744 | struct sci_port *sci_port; | |
745 | unsigned long flags; | |
1da177e4 LT |
746 | |
747 | if ((phase == CPUFREQ_POSTCHANGE) || | |
e552de24 MD |
748 | (phase == CPUFREQ_RESUMECHANGE)) { |
749 | spin_lock_irqsave(&priv->lock, flags); | |
750 | list_for_each_entry(sci_port, &priv->ports, node) | |
501b825d | 751 | sci_port->port.uartclk = clk_get_rate(sci_port->dclk); |
e552de24 MD |
752 | |
753 | spin_unlock_irqrestore(&priv->lock, flags); | |
754 | } | |
1da177e4 | 755 | |
1da177e4 LT |
756 | return NOTIFY_OK; |
757 | } | |
501b825d MD |
758 | |
759 | static void sci_clk_enable(struct uart_port *port) | |
760 | { | |
761 | struct sci_port *sci_port = to_sci_port(port); | |
762 | ||
763 | clk_enable(sci_port->dclk); | |
764 | sci_port->port.uartclk = clk_get_rate(sci_port->dclk); | |
765 | ||
766 | if (sci_port->iclk) | |
767 | clk_enable(sci_port->iclk); | |
768 | } | |
769 | ||
770 | static void sci_clk_disable(struct uart_port *port) | |
771 | { | |
772 | struct sci_port *sci_port = to_sci_port(port); | |
773 | ||
774 | if (sci_port->iclk) | |
775 | clk_disable(sci_port->iclk); | |
776 | ||
777 | clk_disable(sci_port->dclk); | |
778 | } | |
027e6872 | 779 | #endif |
1da177e4 LT |
780 | |
781 | static int sci_request_irq(struct sci_port *port) | |
782 | { | |
783 | int i; | |
7d12e780 | 784 | irqreturn_t (*handlers[4])(int irq, void *ptr) = { |
1da177e4 LT |
785 | sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt, |
786 | sci_br_interrupt, | |
787 | }; | |
788 | const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full", | |
789 | "SCI Transmit Data Empty", "SCI Break" }; | |
790 | ||
791 | if (port->irqs[0] == port->irqs[1]) { | |
762c69e3 | 792 | if (unlikely(!port->irqs[0])) |
1da177e4 | 793 | return -ENODEV; |
e108b2ca PM |
794 | |
795 | if (request_irq(port->irqs[0], sci_mpxed_interrupt, | |
35f3c518 | 796 | IRQF_DISABLED, "sci", port)) { |
762c69e3 | 797 | dev_err(port->port.dev, "Can't allocate IRQ\n"); |
1da177e4 LT |
798 | return -ENODEV; |
799 | } | |
800 | } else { | |
801 | for (i = 0; i < ARRAY_SIZE(handlers); i++) { | |
762c69e3 | 802 | if (unlikely(!port->irqs[i])) |
1da177e4 | 803 | continue; |
762c69e3 | 804 | |
e108b2ca | 805 | if (request_irq(port->irqs[i], handlers[i], |
35f3c518 | 806 | IRQF_DISABLED, desc[i], port)) { |
762c69e3 | 807 | dev_err(port->port.dev, "Can't allocate IRQ\n"); |
1da177e4 LT |
808 | return -ENODEV; |
809 | } | |
810 | } | |
811 | } | |
812 | ||
813 | return 0; | |
814 | } | |
815 | ||
816 | static void sci_free_irq(struct sci_port *port) | |
817 | { | |
818 | int i; | |
819 | ||
762c69e3 PM |
820 | if (port->irqs[0] == port->irqs[1]) |
821 | free_irq(port->irqs[0], port); | |
822 | else { | |
1da177e4 LT |
823 | for (i = 0; i < ARRAY_SIZE(port->irqs); i++) { |
824 | if (!port->irqs[i]) | |
825 | continue; | |
826 | ||
827 | free_irq(port->irqs[i], port); | |
828 | } | |
829 | } | |
830 | } | |
831 | ||
832 | static unsigned int sci_tx_empty(struct uart_port *port) | |
833 | { | |
834 | /* Can't detect */ | |
835 | return TIOCSER_TEMT; | |
836 | } | |
837 | ||
838 | static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
839 | { | |
840 | /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */ | |
841 | /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */ | |
842 | /* If you have signals for DTR and DCD, please implement here. */ | |
843 | } | |
844 | ||
845 | static unsigned int sci_get_mctrl(struct uart_port *port) | |
846 | { | |
847 | /* This routine is used for geting signals of: DTR, DCD, DSR, RI, | |
848 | and CTS/RTS */ | |
849 | ||
850 | return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR; | |
851 | } | |
852 | ||
b129a8cc | 853 | static void sci_start_tx(struct uart_port *port) |
1da177e4 | 854 | { |
e108b2ca | 855 | unsigned short ctrl; |
1da177e4 | 856 | |
e108b2ca PM |
857 | /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ |
858 | ctrl = sci_in(port, SCSCR); | |
859 | ctrl |= SCI_CTRL_FLAGS_TIE; | |
860 | sci_out(port, SCSCR, ctrl); | |
1da177e4 LT |
861 | } |
862 | ||
b129a8cc | 863 | static void sci_stop_tx(struct uart_port *port) |
1da177e4 | 864 | { |
1da177e4 LT |
865 | unsigned short ctrl; |
866 | ||
867 | /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ | |
1da177e4 LT |
868 | ctrl = sci_in(port, SCSCR); |
869 | ctrl &= ~SCI_CTRL_FLAGS_TIE; | |
870 | sci_out(port, SCSCR, ctrl); | |
1da177e4 LT |
871 | } |
872 | ||
873 | static void sci_start_rx(struct uart_port *port, unsigned int tty_start) | |
874 | { | |
1da177e4 LT |
875 | unsigned short ctrl; |
876 | ||
877 | /* Set RIE (Receive Interrupt Enable) bit in SCSCR */ | |
1da177e4 LT |
878 | ctrl = sci_in(port, SCSCR); |
879 | ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE; | |
880 | sci_out(port, SCSCR, ctrl); | |
1da177e4 LT |
881 | } |
882 | ||
883 | static void sci_stop_rx(struct uart_port *port) | |
884 | { | |
1da177e4 LT |
885 | unsigned short ctrl; |
886 | ||
887 | /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */ | |
1da177e4 LT |
888 | ctrl = sci_in(port, SCSCR); |
889 | ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE); | |
890 | sci_out(port, SCSCR, ctrl); | |
1da177e4 LT |
891 | } |
892 | ||
893 | static void sci_enable_ms(struct uart_port *port) | |
894 | { | |
895 | /* Nothing here yet .. */ | |
896 | } | |
897 | ||
898 | static void sci_break_ctl(struct uart_port *port, int break_state) | |
899 | { | |
900 | /* Nothing here yet .. */ | |
901 | } | |
902 | ||
903 | static int sci_startup(struct uart_port *port) | |
904 | { | |
a5660ada | 905 | struct sci_port *s = to_sci_port(port); |
1da177e4 | 906 | |
e108b2ca PM |
907 | if (s->enable) |
908 | s->enable(port); | |
1da177e4 LT |
909 | |
910 | sci_request_irq(s); | |
d656901b | 911 | sci_start_tx(port); |
1da177e4 LT |
912 | sci_start_rx(port, 1); |
913 | ||
914 | return 0; | |
915 | } | |
916 | ||
917 | static void sci_shutdown(struct uart_port *port) | |
918 | { | |
a5660ada | 919 | struct sci_port *s = to_sci_port(port); |
1da177e4 LT |
920 | |
921 | sci_stop_rx(port); | |
b129a8cc | 922 | sci_stop_tx(port); |
1da177e4 LT |
923 | sci_free_irq(s); |
924 | ||
e108b2ca PM |
925 | if (s->disable) |
926 | s->disable(port); | |
1da177e4 LT |
927 | } |
928 | ||
606d099c AC |
929 | static void sci_set_termios(struct uart_port *port, struct ktermios *termios, |
930 | struct ktermios *old) | |
1da177e4 | 931 | { |
1da177e4 | 932 | unsigned int status, baud, smr_val; |
a2159b52 | 933 | int t = -1; |
1da177e4 LT |
934 | |
935 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
a2159b52 PM |
936 | if (likely(baud)) |
937 | t = SCBRR_VALUE(baud, port->uartclk); | |
e108b2ca | 938 | |
1da177e4 LT |
939 | do { |
940 | status = sci_in(port, SCxSR); | |
941 | } while (!(status & SCxSR_TEND(port))); | |
942 | ||
943 | sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ | |
944 | ||
1a22f08d | 945 | if (port->type != PORT_SCI) |
1da177e4 | 946 | sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); |
1da177e4 LT |
947 | |
948 | smr_val = sci_in(port, SCSMR) & 3; | |
949 | if ((termios->c_cflag & CSIZE) == CS7) | |
950 | smr_val |= 0x40; | |
951 | if (termios->c_cflag & PARENB) | |
952 | smr_val |= 0x20; | |
953 | if (termios->c_cflag & PARODD) | |
954 | smr_val |= 0x30; | |
955 | if (termios->c_cflag & CSTOPB) | |
956 | smr_val |= 0x08; | |
957 | ||
958 | uart_update_timeout(port, termios->c_cflag, baud); | |
959 | ||
960 | sci_out(port, SCSMR, smr_val); | |
961 | ||
1da177e4 | 962 | if (t > 0) { |
e7c98dc7 | 963 | if (t >= 256) { |
1da177e4 LT |
964 | sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1); |
965 | t >>= 2; | |
e7c98dc7 | 966 | } else |
1da177e4 | 967 | sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3); |
e7c98dc7 | 968 | |
1da177e4 LT |
969 | sci_out(port, SCBRR, t); |
970 | udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */ | |
971 | } | |
972 | ||
d5701647 PM |
973 | sci_init_pins(port, termios->c_cflag); |
974 | sci_out(port, SCFCR, (termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0); | |
b7a76e4b | 975 | |
1da177e4 LT |
976 | sci_out(port, SCSCR, SCSCR_INIT(port)); |
977 | ||
978 | if ((termios->c_cflag & CREAD) != 0) | |
e7c98dc7 | 979 | sci_start_rx(port, 0); |
1da177e4 LT |
980 | } |
981 | ||
982 | static const char *sci_type(struct uart_port *port) | |
983 | { | |
984 | switch (port->type) { | |
e7c98dc7 MT |
985 | case PORT_IRDA: |
986 | return "irda"; | |
987 | case PORT_SCI: | |
988 | return "sci"; | |
989 | case PORT_SCIF: | |
990 | return "scif"; | |
991 | case PORT_SCIFA: | |
992 | return "scifa"; | |
1da177e4 LT |
993 | } |
994 | ||
fa43972f | 995 | return NULL; |
1da177e4 LT |
996 | } |
997 | ||
998 | static void sci_release_port(struct uart_port *port) | |
999 | { | |
1000 | /* Nothing here yet .. */ | |
1001 | } | |
1002 | ||
1003 | static int sci_request_port(struct uart_port *port) | |
1004 | { | |
1005 | /* Nothing here yet .. */ | |
1006 | return 0; | |
1007 | } | |
1008 | ||
1009 | static void sci_config_port(struct uart_port *port, int flags) | |
1010 | { | |
a5660ada | 1011 | struct sci_port *s = to_sci_port(port); |
1da177e4 LT |
1012 | |
1013 | port->type = s->type; | |
1014 | ||
08f8cb31 MD |
1015 | if (port->membase) |
1016 | return; | |
1017 | ||
1018 | if (port->flags & UPF_IOREMAP) { | |
7ff731ae | 1019 | port->membase = ioremap_nocache(port->mapbase, 0x40); |
08f8cb31 MD |
1020 | |
1021 | if (IS_ERR(port->membase)) | |
1022 | dev_err(port->dev, "can't remap port#%d\n", port->line); | |
1023 | } else { | |
1024 | /* | |
1025 | * For the simple (and majority of) cases where we don't | |
1026 | * need to do any remapping, just cast the cookie | |
1027 | * directly. | |
1028 | */ | |
1029 | port->membase = (void __iomem *)port->mapbase; | |
7ff731ae | 1030 | } |
1da177e4 LT |
1031 | } |
1032 | ||
1033 | static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) | |
1034 | { | |
a5660ada | 1035 | struct sci_port *s = to_sci_port(port); |
1da177e4 | 1036 | |
a62c4133 | 1037 | if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs) |
1da177e4 LT |
1038 | return -EINVAL; |
1039 | if (ser->baud_base < 2400) | |
1040 | /* No paper tape reader for Mitch.. */ | |
1041 | return -EINVAL; | |
1042 | ||
1043 | return 0; | |
1044 | } | |
1045 | ||
1046 | static struct uart_ops sci_uart_ops = { | |
1047 | .tx_empty = sci_tx_empty, | |
1048 | .set_mctrl = sci_set_mctrl, | |
1049 | .get_mctrl = sci_get_mctrl, | |
1050 | .start_tx = sci_start_tx, | |
1051 | .stop_tx = sci_stop_tx, | |
1052 | .stop_rx = sci_stop_rx, | |
1053 | .enable_ms = sci_enable_ms, | |
1054 | .break_ctl = sci_break_ctl, | |
1055 | .startup = sci_startup, | |
1056 | .shutdown = sci_shutdown, | |
1057 | .set_termios = sci_set_termios, | |
1058 | .type = sci_type, | |
1059 | .release_port = sci_release_port, | |
1060 | .request_port = sci_request_port, | |
1061 | .config_port = sci_config_port, | |
1062 | .verify_port = sci_verify_port, | |
07d2a1a1 PM |
1063 | #ifdef CONFIG_CONSOLE_POLL |
1064 | .poll_get_char = sci_poll_get_char, | |
1065 | .poll_put_char = sci_poll_put_char, | |
1066 | #endif | |
1da177e4 LT |
1067 | }; |
1068 | ||
501b825d MD |
1069 | static void __devinit sci_init_single(struct platform_device *dev, |
1070 | struct sci_port *sci_port, | |
08f8cb31 MD |
1071 | unsigned int index, |
1072 | struct plat_sci_port *p) | |
e108b2ca | 1073 | { |
7ed7e071 MD |
1074 | sci_port->port.ops = &sci_uart_ops; |
1075 | sci_port->port.iotype = UPIO_MEM; | |
1076 | sci_port->port.line = index; | |
1077 | sci_port->port.fifosize = 1; | |
e108b2ca PM |
1078 | |
1079 | #if defined(__H8300H__) || defined(__H8300S__) | |
1080 | #ifdef __H8300S__ | |
7ed7e071 MD |
1081 | sci_port->enable = h8300_sci_enable; |
1082 | sci_port->disable = h8300_sci_disable; | |
e108b2ca | 1083 | #endif |
7ed7e071 | 1084 | sci_port->port.uartclk = CONFIG_CPU_CLOCK; |
a2159b52 | 1085 | #elif defined(CONFIG_HAVE_CLK) |
501b825d | 1086 | sci_port->iclk = p->clk ? clk_get(&dev->dev, p->clk) : NULL; |
af777ce4 | 1087 | sci_port->dclk = clk_get(&dev->dev, "peripheral_clk"); |
501b825d MD |
1088 | sci_port->enable = sci_clk_enable; |
1089 | sci_port->disable = sci_clk_disable; | |
a2159b52 PM |
1090 | #else |
1091 | #error "Need a valid uartclk" | |
1da177e4 | 1092 | #endif |
e108b2ca | 1093 | |
7ed7e071 MD |
1094 | sci_port->break_timer.data = (unsigned long)sci_port; |
1095 | sci_port->break_timer.function = sci_break_timer; | |
1096 | init_timer(&sci_port->break_timer); | |
1097 | ||
1098 | sci_port->port.mapbase = p->mapbase; | |
7ed7e071 MD |
1099 | sci_port->port.membase = p->membase; |
1100 | ||
1101 | sci_port->port.irq = p->irqs[SCIx_TXI_IRQ]; | |
1102 | sci_port->port.flags = p->flags; | |
501b825d | 1103 | sci_port->port.dev = &dev->dev; |
7ed7e071 MD |
1104 | sci_port->type = sci_port->port.type = p->type; |
1105 | ||
1106 | memcpy(&sci_port->irqs, &p->irqs, sizeof(p->irqs)); | |
501b825d | 1107 | |
e108b2ca PM |
1108 | } |
1109 | ||
1da177e4 | 1110 | #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE |
dc8e6f5b MD |
1111 | static struct tty_driver *serial_console_device(struct console *co, int *index) |
1112 | { | |
1113 | struct uart_driver *p = &sci_uart_driver; | |
1114 | *index = co->index; | |
1115 | return p->tty_driver; | |
1116 | } | |
1117 | ||
1118 | static void serial_console_putchar(struct uart_port *port, int ch) | |
1119 | { | |
1120 | sci_poll_put_char(port, ch); | |
1121 | } | |
1122 | ||
1da177e4 LT |
1123 | /* |
1124 | * Print a string to the serial port trying not to disturb | |
1125 | * any possible real use of the port... | |
1126 | */ | |
1127 | static void serial_console_write(struct console *co, const char *s, | |
1128 | unsigned count) | |
1129 | { | |
dc8e6f5b | 1130 | struct uart_port *port = co->data; |
501b825d | 1131 | struct sci_port *sci_port = to_sci_port(port); |
973e5d52 | 1132 | unsigned short bits; |
07d2a1a1 | 1133 | |
501b825d MD |
1134 | if (sci_port->enable) |
1135 | sci_port->enable(port); | |
1136 | ||
1137 | uart_console_write(port, s, count, serial_console_putchar); | |
973e5d52 MD |
1138 | |
1139 | /* wait until fifo is empty and last bit has been transmitted */ | |
1140 | bits = SCxSR_TDxE(port) | SCxSR_TEND(port); | |
1141 | while ((sci_in(port, SCxSR) & bits) != bits) | |
1142 | cpu_relax(); | |
501b825d MD |
1143 | |
1144 | if (sci_port->disable); | |
1145 | sci_port->disable(port); | |
1da177e4 LT |
1146 | } |
1147 | ||
1148 | static int __init serial_console_setup(struct console *co, char *options) | |
1149 | { | |
dc8e6f5b | 1150 | struct sci_port *sci_port; |
1da177e4 LT |
1151 | struct uart_port *port; |
1152 | int baud = 115200; | |
1153 | int bits = 8; | |
1154 | int parity = 'n'; | |
1155 | int flow = 'n'; | |
1156 | int ret; | |
1157 | ||
e108b2ca PM |
1158 | /* |
1159 | * Check whether an invalid uart number has been specified, and | |
1160 | * if so, search for the first available port that does have | |
1161 | * console support. | |
1162 | */ | |
1163 | if (co->index >= SCI_NPORTS) | |
1164 | co->index = 0; | |
1165 | ||
dc8e6f5b MD |
1166 | sci_port = &sci_ports[co->index]; |
1167 | port = &sci_port->port; | |
1168 | co->data = port; | |
1da177e4 LT |
1169 | |
1170 | /* | |
e108b2ca PM |
1171 | * Also need to check port->type, we don't actually have any |
1172 | * UPIO_PORT ports, but uart_report_port() handily misreports | |
1173 | * it anyways if we don't have a port available by the time this is | |
1174 | * called. | |
1da177e4 | 1175 | */ |
e108b2ca PM |
1176 | if (!port->type) |
1177 | return -ENODEV; | |
e108b2ca | 1178 | |
08f8cb31 | 1179 | sci_config_port(port, 0); |
e108b2ca | 1180 | |
dc8e6f5b MD |
1181 | if (sci_port->enable) |
1182 | sci_port->enable(port); | |
b7a76e4b | 1183 | |
1da177e4 LT |
1184 | if (options) |
1185 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1186 | ||
1187 | ret = uart_set_options(port, co, baud, parity, bits, flow); | |
1188 | #if defined(__H8300H__) || defined(__H8300S__) | |
1189 | /* disable rx interrupt */ | |
1190 | if (ret == 0) | |
1191 | sci_stop_rx(port); | |
1192 | #endif | |
501b825d | 1193 | /* TODO: disable clock */ |
1da177e4 LT |
1194 | return ret; |
1195 | } | |
1196 | ||
1197 | static struct console serial_console = { | |
1198 | .name = "ttySC", | |
dc8e6f5b | 1199 | .device = serial_console_device, |
1da177e4 LT |
1200 | .write = serial_console_write, |
1201 | .setup = serial_console_setup, | |
fa5da2f7 | 1202 | .flags = CON_PRINTBUFFER, |
1da177e4 | 1203 | .index = -1, |
1da177e4 LT |
1204 | }; |
1205 | ||
1206 | static int __init sci_console_init(void) | |
1207 | { | |
1208 | register_console(&serial_console); | |
1209 | return 0; | |
1210 | } | |
1da177e4 LT |
1211 | console_initcall(sci_console_init); |
1212 | #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ | |
1213 | ||
07d2a1a1 | 1214 | #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) |
e7c98dc7 | 1215 | #define SCI_CONSOLE (&serial_console) |
1da177e4 | 1216 | #else |
b7a76e4b | 1217 | #define SCI_CONSOLE 0 |
1da177e4 LT |
1218 | #endif |
1219 | ||
1220 | static char banner[] __initdata = | |
1221 | KERN_INFO "SuperH SCI(F) driver initialized\n"; | |
1222 | ||
1223 | static struct uart_driver sci_uart_driver = { | |
1224 | .owner = THIS_MODULE, | |
1225 | .driver_name = "sci", | |
1da177e4 LT |
1226 | .dev_name = "ttySC", |
1227 | .major = SCI_MAJOR, | |
1228 | .minor = SCI_MINOR_START, | |
e108b2ca | 1229 | .nr = SCI_NPORTS, |
1da177e4 LT |
1230 | .cons = SCI_CONSOLE, |
1231 | }; | |
1232 | ||
e552de24 | 1233 | |
54507f6e | 1234 | static int sci_remove(struct platform_device *dev) |
e552de24 MD |
1235 | { |
1236 | struct sh_sci_priv *priv = platform_get_drvdata(dev); | |
1237 | struct sci_port *p; | |
1238 | unsigned long flags; | |
1239 | ||
1240 | #ifdef CONFIG_HAVE_CLK | |
1241 | cpufreq_unregister_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER); | |
1242 | #endif | |
1243 | ||
1244 | spin_lock_irqsave(&priv->lock, flags); | |
1245 | list_for_each_entry(p, &priv->ports, node) | |
1246 | uart_remove_one_port(&sci_uart_driver, &p->port); | |
1247 | ||
1248 | spin_unlock_irqrestore(&priv->lock, flags); | |
1249 | ||
1250 | kfree(priv); | |
1251 | return 0; | |
1252 | } | |
1253 | ||
0ee70712 MD |
1254 | static int __devinit sci_probe_single(struct platform_device *dev, |
1255 | unsigned int index, | |
1256 | struct plat_sci_port *p, | |
1257 | struct sci_port *sciport) | |
1258 | { | |
1259 | struct sh_sci_priv *priv = platform_get_drvdata(dev); | |
1260 | unsigned long flags; | |
1261 | int ret; | |
1262 | ||
1263 | /* Sanity check */ | |
1264 | if (unlikely(index >= SCI_NPORTS)) { | |
1265 | dev_notice(&dev->dev, "Attempting to register port " | |
1266 | "%d when only %d are available.\n", | |
1267 | index+1, SCI_NPORTS); | |
1268 | dev_notice(&dev->dev, "Consider bumping " | |
1269 | "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); | |
1270 | return 0; | |
1271 | } | |
1272 | ||
501b825d | 1273 | sci_init_single(dev, sciport, index, p); |
0ee70712 MD |
1274 | |
1275 | ret = uart_add_one_port(&sci_uart_driver, &sciport->port); | |
08f8cb31 | 1276 | if (ret) |
0ee70712 | 1277 | return ret; |
0ee70712 MD |
1278 | |
1279 | INIT_LIST_HEAD(&sciport->node); | |
1280 | ||
1281 | spin_lock_irqsave(&priv->lock, flags); | |
1282 | list_add(&sciport->node, &priv->ports); | |
1283 | spin_unlock_irqrestore(&priv->lock, flags); | |
1284 | ||
1285 | return 0; | |
1286 | } | |
1287 | ||
e108b2ca PM |
1288 | /* |
1289 | * Register a set of serial devices attached to a platform device. The | |
1290 | * list is terminated with a zero flags entry, which means we expect | |
1291 | * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need | |
1292 | * remapping (such as sh64) should also set UPF_IOREMAP. | |
1293 | */ | |
1294 | static int __devinit sci_probe(struct platform_device *dev) | |
1da177e4 | 1295 | { |
e108b2ca | 1296 | struct plat_sci_port *p = dev->dev.platform_data; |
e552de24 | 1297 | struct sh_sci_priv *priv; |
7ff731ae | 1298 | int i, ret = -EINVAL; |
e552de24 MD |
1299 | |
1300 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
1301 | if (!priv) | |
1302 | return -ENOMEM; | |
1303 | ||
1304 | INIT_LIST_HEAD(&priv->ports); | |
1305 | spin_lock_init(&priv->lock); | |
1306 | platform_set_drvdata(dev, priv); | |
1307 | ||
1308 | #ifdef CONFIG_HAVE_CLK | |
1309 | priv->clk_nb.notifier_call = sci_notifier; | |
1310 | cpufreq_register_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER); | |
1311 | #endif | |
1da177e4 | 1312 | |
0ee70712 MD |
1313 | if (dev->id != -1) { |
1314 | ret = sci_probe_single(dev, dev->id, p, &sci_ports[dev->id]); | |
1315 | if (ret) | |
e552de24 | 1316 | goto err_unreg; |
0ee70712 MD |
1317 | } else { |
1318 | for (i = 0; p && p->flags != 0; p++, i++) { | |
1319 | ret = sci_probe_single(dev, i, p, &sci_ports[i]); | |
1320 | if (ret) | |
1321 | goto err_unreg; | |
e552de24 | 1322 | } |
e552de24 | 1323 | } |
1da177e4 LT |
1324 | |
1325 | #ifdef CONFIG_SH_STANDARD_BIOS | |
1326 | sh_bios_gdb_detach(); | |
1327 | #endif | |
1328 | ||
e108b2ca | 1329 | return 0; |
7ff731ae PM |
1330 | |
1331 | err_unreg: | |
e552de24 | 1332 | sci_remove(dev); |
7ff731ae | 1333 | return ret; |
1da177e4 LT |
1334 | } |
1335 | ||
6daa79b3 | 1336 | static int sci_suspend(struct device *dev) |
1da177e4 | 1337 | { |
6daa79b3 | 1338 | struct sh_sci_priv *priv = dev_get_drvdata(dev); |
e552de24 MD |
1339 | struct sci_port *p; |
1340 | unsigned long flags; | |
e108b2ca | 1341 | |
e552de24 MD |
1342 | spin_lock_irqsave(&priv->lock, flags); |
1343 | list_for_each_entry(p, &priv->ports, node) | |
1344 | uart_suspend_port(&sci_uart_driver, &p->port); | |
e552de24 | 1345 | spin_unlock_irqrestore(&priv->lock, flags); |
1da177e4 | 1346 | |
e108b2ca PM |
1347 | return 0; |
1348 | } | |
1da177e4 | 1349 | |
6daa79b3 | 1350 | static int sci_resume(struct device *dev) |
e108b2ca | 1351 | { |
6daa79b3 | 1352 | struct sh_sci_priv *priv = dev_get_drvdata(dev); |
e552de24 MD |
1353 | struct sci_port *p; |
1354 | unsigned long flags; | |
e108b2ca | 1355 | |
e552de24 MD |
1356 | spin_lock_irqsave(&priv->lock, flags); |
1357 | list_for_each_entry(p, &priv->ports, node) | |
1358 | uart_resume_port(&sci_uart_driver, &p->port); | |
e552de24 | 1359 | spin_unlock_irqrestore(&priv->lock, flags); |
e108b2ca PM |
1360 | |
1361 | return 0; | |
1362 | } | |
1363 | ||
6daa79b3 PM |
1364 | static struct dev_pm_ops sci_dev_pm_ops = { |
1365 | .suspend = sci_suspend, | |
1366 | .resume = sci_resume, | |
1367 | }; | |
1368 | ||
e108b2ca PM |
1369 | static struct platform_driver sci_driver = { |
1370 | .probe = sci_probe, | |
1371 | .remove = __devexit_p(sci_remove), | |
e108b2ca PM |
1372 | .driver = { |
1373 | .name = "sh-sci", | |
1374 | .owner = THIS_MODULE, | |
6daa79b3 | 1375 | .pm = &sci_dev_pm_ops, |
e108b2ca PM |
1376 | }, |
1377 | }; | |
1378 | ||
1379 | static int __init sci_init(void) | |
1380 | { | |
1381 | int ret; | |
1382 | ||
1383 | printk(banner); | |
1384 | ||
e108b2ca PM |
1385 | ret = uart_register_driver(&sci_uart_driver); |
1386 | if (likely(ret == 0)) { | |
1387 | ret = platform_driver_register(&sci_driver); | |
1388 | if (unlikely(ret)) | |
1389 | uart_unregister_driver(&sci_uart_driver); | |
1390 | } | |
1391 | ||
1392 | return ret; | |
1393 | } | |
1394 | ||
1395 | static void __exit sci_exit(void) | |
1396 | { | |
1397 | platform_driver_unregister(&sci_driver); | |
1da177e4 LT |
1398 | uart_unregister_driver(&sci_uart_driver); |
1399 | } | |
1400 | ||
1401 | module_init(sci_init); | |
1402 | module_exit(sci_exit); | |
1403 | ||
e108b2ca | 1404 | MODULE_LICENSE("GPL"); |
e169c139 | 1405 | MODULE_ALIAS("platform:sh-sci"); |