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3c6a4832 TM |
1 | /* |
2 | *Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD. | |
3 | * | |
4 | *This program is free software; you can redistribute it and/or modify | |
5 | *it under the terms of the GNU General Public License as published by | |
6 | *the Free Software Foundation; version 2 of the License. | |
7 | * | |
8 | *This program is distributed in the hope that it will be useful, | |
9 | *but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | *GNU General Public License for more details. | |
12 | * | |
13 | *You should have received a copy of the GNU General Public License | |
14 | *along with this program; if not, write to the Free Software | |
15 | *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. | |
16 | */ | |
17 | #include <linux/serial_reg.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/pci.h> | |
21 | #include <linux/serial_core.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/io.h> | |
24 | ||
25 | #include <linux/dmaengine.h> | |
26 | #include <linux/pch_dma.h> | |
27 | ||
28 | enum { | |
29 | PCH_UART_HANDLED_RX_INT_SHIFT, | |
30 | PCH_UART_HANDLED_TX_INT_SHIFT, | |
31 | PCH_UART_HANDLED_RX_ERR_INT_SHIFT, | |
32 | PCH_UART_HANDLED_RX_TRG_INT_SHIFT, | |
33 | PCH_UART_HANDLED_MS_INT_SHIFT, | |
34 | }; | |
35 | ||
36 | enum { | |
37 | PCH_UART_8LINE, | |
38 | PCH_UART_2LINE, | |
39 | }; | |
40 | ||
41 | #define PCH_UART_DRIVER_DEVICE "ttyPCH" | |
42 | ||
43 | #define PCH_UART_NR_GE_256FIFO 1 | |
44 | #define PCH_UART_NR_GE_64FIFO 3 | |
45 | #define PCH_UART_NR_GE (PCH_UART_NR_GE_256FIFO+PCH_UART_NR_GE_64FIFO) | |
46 | #define PCH_UART_NR PCH_UART_NR_GE | |
47 | ||
48 | #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1)) | |
49 | #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1)) | |
50 | #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\ | |
51 | PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1)) | |
52 | #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\ | |
53 | PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1)) | |
54 | #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1)) | |
55 | ||
56 | #define PCH_UART_RBR 0x00 | |
57 | #define PCH_UART_THR 0x00 | |
58 | ||
59 | #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\ | |
60 | PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI) | |
61 | #define PCH_UART_IER_ERBFI 0x00000001 | |
62 | #define PCH_UART_IER_ETBEI 0x00000002 | |
63 | #define PCH_UART_IER_ELSI 0x00000004 | |
64 | #define PCH_UART_IER_EDSSI 0x00000008 | |
65 | ||
66 | #define PCH_UART_IIR_IP 0x00000001 | |
67 | #define PCH_UART_IIR_IID 0x00000006 | |
68 | #define PCH_UART_IIR_MSI 0x00000000 | |
69 | #define PCH_UART_IIR_TRI 0x00000002 | |
70 | #define PCH_UART_IIR_RRI 0x00000004 | |
71 | #define PCH_UART_IIR_REI 0x00000006 | |
72 | #define PCH_UART_IIR_TOI 0x00000008 | |
73 | #define PCH_UART_IIR_FIFO256 0x00000020 | |
74 | #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256 | |
75 | #define PCH_UART_IIR_FE 0x000000C0 | |
76 | ||
77 | #define PCH_UART_FCR_FIFOE 0x00000001 | |
78 | #define PCH_UART_FCR_RFR 0x00000002 | |
79 | #define PCH_UART_FCR_TFR 0x00000004 | |
80 | #define PCH_UART_FCR_DMS 0x00000008 | |
81 | #define PCH_UART_FCR_FIFO256 0x00000020 | |
82 | #define PCH_UART_FCR_RFTL 0x000000C0 | |
83 | ||
84 | #define PCH_UART_FCR_RFTL1 0x00000000 | |
85 | #define PCH_UART_FCR_RFTL64 0x00000040 | |
86 | #define PCH_UART_FCR_RFTL128 0x00000080 | |
87 | #define PCH_UART_FCR_RFTL224 0x000000C0 | |
88 | #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64 | |
89 | #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128 | |
90 | #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224 | |
91 | #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64 | |
92 | #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128 | |
93 | #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224 | |
94 | #define PCH_UART_FCR_RFTL_SHIFT 6 | |
95 | ||
96 | #define PCH_UART_LCR_WLS 0x00000003 | |
97 | #define PCH_UART_LCR_STB 0x00000004 | |
98 | #define PCH_UART_LCR_PEN 0x00000008 | |
99 | #define PCH_UART_LCR_EPS 0x00000010 | |
100 | #define PCH_UART_LCR_SP 0x00000020 | |
101 | #define PCH_UART_LCR_SB 0x00000040 | |
102 | #define PCH_UART_LCR_DLAB 0x00000080 | |
103 | #define PCH_UART_LCR_NP 0x00000000 | |
104 | #define PCH_UART_LCR_OP PCH_UART_LCR_PEN | |
105 | #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS) | |
106 | #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP) | |
107 | #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\ | |
108 | PCH_UART_LCR_SP) | |
109 | ||
110 | #define PCH_UART_LCR_5BIT 0x00000000 | |
111 | #define PCH_UART_LCR_6BIT 0x00000001 | |
112 | #define PCH_UART_LCR_7BIT 0x00000002 | |
113 | #define PCH_UART_LCR_8BIT 0x00000003 | |
114 | ||
115 | #define PCH_UART_MCR_DTR 0x00000001 | |
116 | #define PCH_UART_MCR_RTS 0x00000002 | |
117 | #define PCH_UART_MCR_OUT 0x0000000C | |
118 | #define PCH_UART_MCR_LOOP 0x00000010 | |
119 | #define PCH_UART_MCR_AFE 0x00000020 | |
120 | ||
121 | #define PCH_UART_LSR_DR 0x00000001 | |
122 | #define PCH_UART_LSR_ERR (1<<7) | |
123 | ||
124 | #define PCH_UART_MSR_DCTS 0x00000001 | |
125 | #define PCH_UART_MSR_DDSR 0x00000002 | |
126 | #define PCH_UART_MSR_TERI 0x00000004 | |
127 | #define PCH_UART_MSR_DDCD 0x00000008 | |
128 | #define PCH_UART_MSR_CTS 0x00000010 | |
129 | #define PCH_UART_MSR_DSR 0x00000020 | |
130 | #define PCH_UART_MSR_RI 0x00000040 | |
131 | #define PCH_UART_MSR_DCD 0x00000080 | |
132 | #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\ | |
133 | PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD) | |
134 | ||
135 | #define PCH_UART_DLL 0x00 | |
136 | #define PCH_UART_DLM 0x01 | |
137 | ||
138 | #define DIV_ROUND(a, b) (((a) + ((b)/2)) / (b)) | |
139 | ||
140 | #define PCH_UART_IID_RLS (PCH_UART_IIR_REI) | |
141 | #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI) | |
142 | #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI) | |
143 | #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI) | |
144 | #define PCH_UART_IID_MS (PCH_UART_IIR_MSI) | |
145 | ||
146 | #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP) | |
147 | #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP) | |
148 | #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP) | |
149 | #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P) | |
150 | #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P) | |
151 | #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT) | |
152 | #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT) | |
153 | #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT) | |
154 | #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT) | |
155 | #define PCH_UART_HAL_STB1 0 | |
156 | #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB) | |
157 | ||
158 | #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR) | |
159 | #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR) | |
160 | #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \ | |
161 | PCH_UART_HAL_CLR_RX_FIFO) | |
162 | ||
163 | #define PCH_UART_HAL_DMA_MODE0 0 | |
164 | #define PCH_UART_HAL_FIFO_DIS 0 | |
165 | #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE) | |
166 | #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \ | |
167 | PCH_UART_FCR_FIFO256) | |
168 | #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256) | |
169 | #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1) | |
170 | #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64) | |
171 | #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128) | |
172 | #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224) | |
173 | #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16) | |
174 | #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32) | |
175 | #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56) | |
176 | #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4) | |
177 | #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8) | |
178 | #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14) | |
179 | #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64) | |
180 | #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128) | |
181 | #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224) | |
182 | ||
183 | #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI) | |
184 | #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI) | |
185 | #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI) | |
186 | #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI) | |
187 | #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK) | |
188 | ||
189 | #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR) | |
190 | #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS) | |
191 | #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT) | |
192 | #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP) | |
193 | #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE) | |
194 | ||
195 | struct pch_uart_buffer { | |
196 | unsigned char *buf; | |
197 | int size; | |
198 | }; | |
199 | ||
200 | struct eg20t_port { | |
201 | struct uart_port port; | |
202 | int port_type; | |
203 | void __iomem *membase; | |
204 | resource_size_t mapbase; | |
205 | unsigned int iobase; | |
206 | struct pci_dev *pdev; | |
207 | int fifo_size; | |
208 | int base_baud; | |
209 | int start_tx; | |
210 | int start_rx; | |
211 | int tx_empty; | |
212 | int int_dis_flag; | |
213 | int trigger; | |
214 | int trigger_level; | |
215 | struct pch_uart_buffer rxbuf; | |
216 | unsigned int dmsr; | |
217 | unsigned int fcr; | |
218 | unsigned int use_dma; | |
219 | unsigned int use_dma_flag; | |
220 | struct dma_async_tx_descriptor *desc_tx; | |
221 | struct dma_async_tx_descriptor *desc_rx; | |
222 | struct pch_dma_slave param_tx; | |
223 | struct pch_dma_slave param_rx; | |
224 | struct dma_chan *chan_tx; | |
225 | struct dma_chan *chan_rx; | |
226 | struct scatterlist sg_tx; | |
227 | struct scatterlist sg_rx; | |
228 | int tx_dma_use; | |
229 | void *rx_buf_virt; | |
230 | dma_addr_t rx_buf_dma; | |
231 | }; | |
232 | ||
233 | static unsigned int default_baud = 9600; | |
234 | static const int trigger_level_256[4] = { 1, 64, 128, 224 }; | |
235 | static const int trigger_level_64[4] = { 1, 16, 32, 56 }; | |
236 | static const int trigger_level_16[4] = { 1, 4, 8, 14 }; | |
237 | static const int trigger_level_1[4] = { 1, 1, 1, 1 }; | |
238 | ||
239 | static void pch_uart_hal_request(struct pci_dev *pdev, int fifosize, | |
240 | int base_baud) | |
241 | { | |
242 | struct eg20t_port *priv = pci_get_drvdata(pdev); | |
243 | ||
244 | priv->trigger_level = 1; | |
245 | priv->fcr = 0; | |
246 | } | |
247 | ||
248 | static unsigned int get_msr(struct eg20t_port *priv, void __iomem *base) | |
249 | { | |
250 | unsigned int msr = ioread8(base + UART_MSR); | |
251 | priv->dmsr |= msr & PCH_UART_MSR_DELTA; | |
252 | ||
253 | return msr; | |
254 | } | |
255 | ||
256 | static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv, | |
257 | unsigned int flag) | |
258 | { | |
259 | u8 ier = ioread8(priv->membase + UART_IER); | |
260 | ier |= flag & PCH_UART_IER_MASK; | |
261 | iowrite8(ier, priv->membase + UART_IER); | |
262 | } | |
263 | ||
264 | static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv, | |
265 | unsigned int flag) | |
266 | { | |
267 | u8 ier = ioread8(priv->membase + UART_IER); | |
268 | ier &= ~(flag & PCH_UART_IER_MASK); | |
269 | iowrite8(ier, priv->membase + UART_IER); | |
270 | } | |
271 | ||
272 | static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud, | |
273 | unsigned int parity, unsigned int bits, | |
274 | unsigned int stb) | |
275 | { | |
276 | unsigned int dll, dlm, lcr; | |
277 | int div; | |
278 | ||
279 | div = DIV_ROUND(priv->base_baud / 16, baud); | |
280 | if (div < 0 || USHRT_MAX <= div) { | |
281 | pr_err("Invalid Baud(div=0x%x)\n", div); | |
282 | return -EINVAL; | |
283 | } | |
284 | ||
285 | dll = (unsigned int)div & 0x00FFU; | |
286 | dlm = ((unsigned int)div >> 8) & 0x00FFU; | |
287 | ||
288 | if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) { | |
289 | pr_err("Invalid parity(0x%x)\n", parity); | |
290 | return -EINVAL; | |
291 | } | |
292 | ||
293 | if (bits & ~PCH_UART_LCR_WLS) { | |
294 | pr_err("Invalid bits(0x%x)\n", bits); | |
295 | return -EINVAL; | |
296 | } | |
297 | ||
298 | if (stb & ~PCH_UART_LCR_STB) { | |
299 | pr_err("Invalid STB(0x%x)\n", stb); | |
300 | return -EINVAL; | |
301 | } | |
302 | ||
303 | lcr = parity; | |
304 | lcr |= bits; | |
305 | lcr |= stb; | |
306 | ||
307 | pr_debug("%s:baud = %d, div = %04x, lcr = %02x (%lu)\n", | |
308 | __func__, baud, div, lcr, jiffies); | |
309 | iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); | |
310 | iowrite8(dll, priv->membase + PCH_UART_DLL); | |
311 | iowrite8(dlm, priv->membase + PCH_UART_DLM); | |
312 | iowrite8(lcr, priv->membase + UART_LCR); | |
313 | ||
314 | return 0; | |
315 | } | |
316 | ||
317 | static int pch_uart_hal_fifo_reset(struct eg20t_port *priv, | |
318 | unsigned int flag) | |
319 | { | |
320 | if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) { | |
321 | pr_err("%s:Invalid flag(0x%x)\n", __func__, flag); | |
322 | return -EINVAL; | |
323 | } | |
324 | ||
325 | iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); | |
326 | iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag, | |
327 | priv->membase + UART_FCR); | |
328 | iowrite8(priv->fcr, priv->membase + UART_FCR); | |
329 | ||
330 | return 0; | |
331 | } | |
332 | ||
333 | static int pch_uart_hal_set_fifo(struct eg20t_port *priv, | |
334 | unsigned int dmamode, | |
335 | unsigned int fifo_size, unsigned int trigger) | |
336 | { | |
337 | u8 fcr; | |
338 | ||
339 | if (dmamode & ~PCH_UART_FCR_DMS) { | |
340 | pr_err("%s:Invalid DMA Mode(0x%x)\n", __func__, dmamode); | |
341 | return -EINVAL; | |
342 | } | |
343 | ||
344 | if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) { | |
345 | pr_err("%s:Invalid FIFO SIZE(0x%x)\n", __func__, fifo_size); | |
346 | return -EINVAL; | |
347 | } | |
348 | ||
349 | if (trigger & ~PCH_UART_FCR_RFTL) { | |
350 | pr_err("%s:Invalid TRIGGER(0x%x)\n", __func__, trigger); | |
351 | return -EINVAL; | |
352 | } | |
353 | ||
354 | switch (priv->fifo_size) { | |
355 | case 256: | |
356 | priv->trigger_level = | |
357 | trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT]; | |
358 | break; | |
359 | case 64: | |
360 | priv->trigger_level = | |
361 | trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT]; | |
362 | break; | |
363 | case 16: | |
364 | priv->trigger_level = | |
365 | trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT]; | |
366 | break; | |
367 | default: | |
368 | priv->trigger_level = | |
369 | trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT]; | |
370 | break; | |
371 | } | |
372 | fcr = | |
373 | dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR; | |
374 | iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR); | |
375 | iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR, | |
376 | priv->membase + UART_FCR); | |
377 | iowrite8(fcr, priv->membase + UART_FCR); | |
378 | priv->fcr = fcr; | |
379 | ||
380 | return 0; | |
381 | } | |
382 | ||
383 | static u8 pch_uart_hal_get_modem(struct eg20t_port *priv) | |
384 | { | |
385 | priv->dmsr = 0; | |
386 | return get_msr(priv, priv->membase); | |
387 | } | |
388 | ||
389 | static int pch_uart_hal_write(struct eg20t_port *priv, | |
390 | const unsigned char *buf, int tx_size) | |
391 | { | |
392 | int i; | |
393 | unsigned int thr; | |
394 | ||
395 | for (i = 0; i < tx_size;) { | |
396 | thr = buf[i++]; | |
397 | iowrite8(thr, priv->membase + PCH_UART_THR); | |
398 | } | |
399 | return i; | |
400 | } | |
401 | ||
402 | static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf, | |
403 | int rx_size) | |
404 | { | |
405 | int i; | |
406 | u8 rbr, lsr; | |
407 | ||
408 | lsr = ioread8(priv->membase + UART_LSR); | |
409 | for (i = 0, lsr = ioread8(priv->membase + UART_LSR); | |
410 | i < rx_size && lsr & UART_LSR_DR; | |
411 | lsr = ioread8(priv->membase + UART_LSR)) { | |
412 | rbr = ioread8(priv->membase + PCH_UART_RBR); | |
413 | buf[i++] = rbr; | |
414 | } | |
415 | return i; | |
416 | } | |
417 | ||
418 | static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv) | |
419 | { | |
420 | unsigned int iir; | |
421 | int ret; | |
422 | ||
423 | iir = ioread8(priv->membase + UART_IIR); | |
424 | ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP)); | |
425 | return ret; | |
426 | } | |
427 | ||
428 | static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv) | |
429 | { | |
430 | return ioread8(priv->membase + UART_LSR); | |
431 | } | |
432 | ||
433 | static void pch_uart_hal_set_break(struct eg20t_port *priv, int on) | |
434 | { | |
435 | unsigned int lcr; | |
436 | ||
437 | lcr = ioread8(priv->membase + UART_LCR); | |
438 | if (on) | |
439 | lcr |= PCH_UART_LCR_SB; | |
440 | else | |
441 | lcr &= ~PCH_UART_LCR_SB; | |
442 | ||
443 | iowrite8(lcr, priv->membase + UART_LCR); | |
444 | } | |
445 | ||
446 | static int push_rx(struct eg20t_port *priv, const unsigned char *buf, | |
447 | int size) | |
448 | { | |
449 | struct uart_port *port; | |
450 | struct tty_struct *tty; | |
451 | ||
452 | port = &priv->port; | |
453 | tty = tty_port_tty_get(&port->state->port); | |
454 | if (!tty) { | |
455 | pr_debug("%s:tty is busy now", __func__); | |
456 | return -EBUSY; | |
457 | } | |
458 | ||
459 | tty_insert_flip_string(tty, buf, size); | |
460 | tty_flip_buffer_push(tty); | |
461 | tty_kref_put(tty); | |
462 | ||
463 | return 0; | |
464 | } | |
465 | ||
466 | static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf) | |
467 | { | |
468 | int ret; | |
469 | struct uart_port *port = &priv->port; | |
470 | ||
471 | if (port->x_char) { | |
472 | pr_debug("%s:X character send %02x (%lu)\n", __func__, | |
473 | port->x_char, jiffies); | |
474 | buf[0] = port->x_char; | |
475 | port->x_char = 0; | |
476 | ret = 1; | |
477 | } else { | |
478 | ret = 0; | |
479 | } | |
480 | ||
481 | return ret; | |
482 | } | |
483 | ||
484 | static int dma_push_rx(struct eg20t_port *priv, int size) | |
485 | { | |
486 | struct tty_struct *tty; | |
487 | int room; | |
488 | struct uart_port *port = &priv->port; | |
489 | ||
490 | port = &priv->port; | |
491 | tty = tty_port_tty_get(&port->state->port); | |
492 | if (!tty) { | |
493 | pr_debug("%s:tty is busy now", __func__); | |
494 | return 0; | |
495 | } | |
496 | ||
497 | room = tty_buffer_request_room(tty, size); | |
498 | ||
499 | if (room < size) | |
500 | dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", | |
501 | size - room); | |
502 | if (!room) | |
503 | return room; | |
504 | ||
505 | tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size); | |
506 | ||
507 | port->icount.rx += room; | |
508 | tty_kref_put(tty); | |
509 | ||
510 | return room; | |
511 | } | |
512 | ||
513 | static void pch_free_dma(struct uart_port *port) | |
514 | { | |
515 | struct eg20t_port *priv; | |
516 | priv = container_of(port, struct eg20t_port, port); | |
517 | ||
518 | if (priv->chan_tx) { | |
519 | dma_release_channel(priv->chan_tx); | |
520 | priv->chan_tx = NULL; | |
521 | } | |
522 | if (priv->chan_rx) { | |
523 | dma_release_channel(priv->chan_rx); | |
524 | priv->chan_rx = NULL; | |
525 | } | |
526 | if (sg_dma_address(&priv->sg_rx)) | |
527 | dma_free_coherent(port->dev, port->fifosize, | |
528 | sg_virt(&priv->sg_rx), | |
529 | sg_dma_address(&priv->sg_rx)); | |
530 | ||
531 | return; | |
532 | } | |
533 | ||
534 | static bool filter(struct dma_chan *chan, void *slave) | |
535 | { | |
536 | struct pch_dma_slave *param = slave; | |
537 | ||
538 | if ((chan->chan_id == param->chan_id) && (param->dma_dev == | |
539 | chan->device->dev)) { | |
540 | chan->private = param; | |
541 | return true; | |
542 | } else { | |
543 | return false; | |
544 | } | |
545 | } | |
546 | ||
547 | static void pch_request_dma(struct uart_port *port) | |
548 | { | |
549 | dma_cap_mask_t mask; | |
550 | struct dma_chan *chan; | |
551 | struct pci_dev *dma_dev; | |
552 | struct pch_dma_slave *param; | |
553 | struct eg20t_port *priv = | |
554 | container_of(port, struct eg20t_port, port); | |
555 | dma_cap_zero(mask); | |
556 | dma_cap_set(DMA_SLAVE, mask); | |
557 | ||
558 | dma_dev = pci_get_bus_and_slot(2, PCI_DEVFN(0xa, 0)); /* Get DMA's dev | |
559 | information */ | |
560 | /* Set Tx DMA */ | |
561 | param = &priv->param_tx; | |
562 | param->dma_dev = &dma_dev->dev; | |
563 | param->chan_id = priv->port.line; | |
564 | param->tx_reg = port->mapbase + UART_TX; | |
565 | chan = dma_request_channel(mask, filter, param); | |
566 | if (!chan) { | |
567 | pr_err("%s:dma_request_channel FAILS(Tx)\n", __func__); | |
568 | return; | |
569 | } | |
570 | priv->chan_tx = chan; | |
571 | ||
572 | /* Set Rx DMA */ | |
573 | param = &priv->param_rx; | |
574 | param->dma_dev = &dma_dev->dev; | |
575 | param->chan_id = priv->port.line + 1; /* Rx = Tx + 1 */ | |
576 | param->rx_reg = port->mapbase + UART_RX; | |
577 | chan = dma_request_channel(mask, filter, param); | |
578 | if (!chan) { | |
579 | pr_err("%s:dma_request_channel FAILS(Rx)\n", __func__); | |
580 | dma_release_channel(priv->chan_tx); | |
581 | return; | |
582 | } | |
583 | ||
584 | /* Get Consistent memory for DMA */ | |
585 | priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize, | |
586 | &priv->rx_buf_dma, GFP_KERNEL); | |
587 | priv->chan_rx = chan; | |
588 | } | |
589 | ||
590 | static void pch_dma_rx_complete(void *arg) | |
591 | { | |
592 | struct eg20t_port *priv = arg; | |
593 | struct uart_port *port = &priv->port; | |
594 | struct tty_struct *tty = tty_port_tty_get(&port->state->port); | |
595 | ||
596 | if (!tty) { | |
597 | pr_debug("%s:tty is busy now", __func__); | |
598 | return; | |
599 | } | |
600 | ||
601 | if (dma_push_rx(priv, priv->trigger_level)) | |
602 | tty_flip_buffer_push(tty); | |
603 | ||
604 | tty_kref_put(tty); | |
605 | } | |
606 | ||
607 | static void pch_dma_tx_complete(void *arg) | |
608 | { | |
609 | struct eg20t_port *priv = arg; | |
610 | struct uart_port *port = &priv->port; | |
611 | struct circ_buf *xmit = &port->state->xmit; | |
612 | ||
613 | xmit->tail += sg_dma_len(&priv->sg_tx); | |
614 | xmit->tail &= UART_XMIT_SIZE - 1; | |
615 | port->icount.tx += sg_dma_len(&priv->sg_tx); | |
616 | ||
617 | async_tx_ack(priv->desc_tx); | |
618 | priv->tx_dma_use = 0; | |
619 | } | |
620 | ||
621 | static int pop_tx(struct eg20t_port *priv, unsigned char *buf, int size) | |
622 | { | |
623 | int count = 0; | |
624 | struct uart_port *port = &priv->port; | |
625 | struct circ_buf *xmit = &port->state->xmit; | |
626 | ||
627 | if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size) | |
628 | goto pop_tx_end; | |
629 | ||
630 | do { | |
631 | int cnt_to_end = | |
632 | CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); | |
633 | int sz = min(size - count, cnt_to_end); | |
634 | memcpy(&buf[count], &xmit->buf[xmit->tail], sz); | |
635 | xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1); | |
636 | count += sz; | |
637 | } while (!uart_circ_empty(xmit) && count < size); | |
638 | ||
639 | pop_tx_end: | |
640 | pr_debug("%d characters. Remained %d characters. (%lu)\n", | |
641 | count, size - count, jiffies); | |
642 | ||
643 | return count; | |
644 | } | |
645 | ||
646 | static int handle_rx_to(struct eg20t_port *priv) | |
647 | { | |
648 | struct pch_uart_buffer *buf; | |
649 | int rx_size; | |
650 | int ret; | |
651 | if (!priv->start_rx) { | |
652 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT); | |
653 | return 0; | |
654 | } | |
655 | buf = &priv->rxbuf; | |
656 | do { | |
657 | rx_size = pch_uart_hal_read(priv, buf->buf, buf->size); | |
658 | ret = push_rx(priv, buf->buf, rx_size); | |
659 | if (ret) | |
660 | return 0; | |
661 | } while (rx_size == buf->size); | |
662 | ||
663 | return PCH_UART_HANDLED_RX_INT; | |
664 | } | |
665 | ||
666 | static int handle_rx(struct eg20t_port *priv) | |
667 | { | |
668 | return handle_rx_to(priv); | |
669 | } | |
670 | ||
671 | static int dma_handle_rx(struct eg20t_port *priv) | |
672 | { | |
673 | struct uart_port *port = &priv->port; | |
674 | struct dma_async_tx_descriptor *desc; | |
675 | struct scatterlist *sg; | |
676 | ||
677 | priv = container_of(port, struct eg20t_port, port); | |
678 | sg = &priv->sg_rx; | |
679 | ||
680 | sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */ | |
681 | ||
682 | sg_dma_len(sg) = priv->fifo_size; | |
683 | ||
684 | sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt), | |
685 | sg_dma_len(sg), (int)priv->rx_buf_virt & ~PAGE_MASK); | |
686 | ||
687 | sg_dma_address(sg) = priv->rx_buf_dma; | |
688 | ||
689 | desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx, | |
690 | sg, 1, DMA_FROM_DEVICE, | |
691 | DMA_PREP_INTERRUPT); | |
692 | if (!desc) | |
693 | return 0; | |
694 | ||
695 | priv->desc_rx = desc; | |
696 | desc->callback = pch_dma_rx_complete; | |
697 | desc->callback_param = priv; | |
698 | desc->tx_submit(desc); | |
699 | dma_async_issue_pending(priv->chan_rx); | |
700 | ||
701 | return PCH_UART_HANDLED_RX_INT; | |
702 | } | |
703 | ||
704 | static unsigned int handle_tx(struct eg20t_port *priv) | |
705 | { | |
706 | struct uart_port *port = &priv->port; | |
707 | struct circ_buf *xmit = &port->state->xmit; | |
708 | int ret; | |
709 | int fifo_size; | |
710 | int tx_size; | |
711 | int size; | |
712 | int tx_empty; | |
713 | ||
714 | if (!priv->start_tx) { | |
715 | pr_info("%s:Tx isn't started. (%lu)\n", __func__, jiffies); | |
716 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); | |
717 | priv->tx_empty = 1; | |
718 | return 0; | |
719 | } | |
720 | ||
721 | fifo_size = max(priv->fifo_size, 1); | |
722 | tx_empty = 1; | |
723 | if (pop_tx_x(priv, xmit->buf)) { | |
724 | pch_uart_hal_write(priv, xmit->buf, 1); | |
725 | port->icount.tx++; | |
726 | tx_empty = 0; | |
727 | fifo_size--; | |
728 | } | |
729 | size = min(xmit->head - xmit->tail, fifo_size); | |
730 | tx_size = pop_tx(priv, xmit->buf, size); | |
731 | if (tx_size > 0) { | |
732 | ret = pch_uart_hal_write(priv, xmit->buf, tx_size); | |
733 | port->icount.tx += ret; | |
734 | tx_empty = 0; | |
735 | } | |
736 | ||
737 | priv->tx_empty = tx_empty; | |
738 | ||
739 | if (tx_empty) | |
740 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); | |
741 | ||
742 | return PCH_UART_HANDLED_TX_INT; | |
743 | } | |
744 | ||
745 | static unsigned int dma_handle_tx(struct eg20t_port *priv) | |
746 | { | |
747 | struct uart_port *port = &priv->port; | |
748 | struct circ_buf *xmit = &port->state->xmit; | |
749 | struct scatterlist *sg = &priv->sg_tx; | |
750 | int nent; | |
751 | int fifo_size; | |
752 | int tx_empty; | |
753 | struct dma_async_tx_descriptor *desc; | |
754 | ||
755 | if (!priv->start_tx) { | |
756 | pr_info("%s:Tx isn't started. (%lu)\n", __func__, jiffies); | |
757 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); | |
758 | priv->tx_empty = 1; | |
759 | return 0; | |
760 | } | |
761 | ||
762 | fifo_size = max(priv->fifo_size, 1); | |
763 | tx_empty = 1; | |
764 | if (pop_tx_x(priv, xmit->buf)) { | |
765 | pch_uart_hal_write(priv, xmit->buf, 1); | |
766 | port->icount.tx++; | |
767 | tx_empty = 0; | |
768 | fifo_size--; | |
769 | } | |
770 | ||
771 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); | |
772 | ||
773 | priv->tx_dma_use = 1; | |
774 | ||
775 | sg_init_table(&priv->sg_tx, 1); /* Initialize SG table */ | |
776 | ||
777 | sg_set_page(&priv->sg_tx, virt_to_page(xmit->buf), | |
778 | UART_XMIT_SIZE, (int)xmit->buf & ~PAGE_MASK); | |
779 | ||
780 | nent = dma_map_sg(port->dev, &priv->sg_tx, 1, DMA_TO_DEVICE); | |
781 | if (!nent) { | |
782 | pr_err("%s:dma_map_sg Failed\n", __func__); | |
783 | return 0; | |
784 | } | |
785 | ||
786 | sg->offset = xmit->tail & (UART_XMIT_SIZE - 1); | |
787 | sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) + | |
788 | sg->offset; | |
789 | sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, | |
790 | UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head, | |
791 | xmit->tail, UART_XMIT_SIZE)); | |
792 | ||
793 | desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx, | |
794 | sg, nent, DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
795 | if (!desc) { | |
796 | pr_err("%s:device_prep_slave_sg Failed\n", __func__); | |
797 | return 0; | |
798 | } | |
799 | ||
800 | dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE); | |
801 | ||
802 | priv->desc_tx = desc; | |
803 | desc->callback = pch_dma_tx_complete; | |
804 | desc->callback_param = priv; | |
805 | ||
806 | desc->tx_submit(desc); | |
807 | ||
808 | dma_async_issue_pending(priv->chan_tx); | |
809 | ||
810 | return PCH_UART_HANDLED_TX_INT; | |
811 | } | |
812 | ||
813 | static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr) | |
814 | { | |
815 | u8 fcr = ioread8(priv->membase + UART_FCR); | |
816 | ||
817 | /* Reset FIFO */ | |
818 | fcr |= UART_FCR_CLEAR_RCVR; | |
819 | iowrite8(fcr, priv->membase + UART_FCR); | |
820 | ||
821 | if (lsr & PCH_UART_LSR_ERR) | |
822 | dev_err(&priv->pdev->dev, "Error data in FIFO\n"); | |
823 | ||
824 | if (lsr & UART_LSR_FE) | |
825 | dev_err(&priv->pdev->dev, "Framing Error\n"); | |
826 | ||
827 | if (lsr & UART_LSR_PE) | |
828 | dev_err(&priv->pdev->dev, "Parity Error\n"); | |
829 | ||
830 | if (lsr & UART_LSR_OE) | |
831 | dev_err(&priv->pdev->dev, "Overrun Error\n"); | |
832 | } | |
833 | ||
834 | static irqreturn_t pch_uart_interrupt(int irq, void *dev_id) | |
835 | { | |
836 | struct eg20t_port *priv = dev_id; | |
837 | unsigned int handled; | |
838 | u8 lsr; | |
839 | int ret = 0; | |
840 | unsigned int iid; | |
841 | unsigned long flags; | |
842 | ||
843 | spin_lock_irqsave(&priv->port.lock, flags); | |
844 | handled = 0; | |
845 | while ((iid = pch_uart_hal_get_iid(priv)) > 1) { | |
846 | switch (iid) { | |
847 | case PCH_UART_IID_RLS: /* Receiver Line Status */ | |
848 | lsr = pch_uart_hal_get_line_status(priv); | |
849 | if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE | | |
850 | UART_LSR_PE | UART_LSR_OE)) { | |
851 | pch_uart_err_ir(priv, lsr); | |
852 | ret = PCH_UART_HANDLED_RX_ERR_INT; | |
853 | } | |
854 | break; | |
855 | case PCH_UART_IID_RDR: /* Received Data Ready */ | |
856 | if (priv->use_dma) | |
857 | ret = dma_handle_rx(priv); | |
858 | else | |
859 | ret = handle_rx(priv); | |
860 | break; | |
861 | case PCH_UART_IID_RDR_TO: /* Received Data Ready | |
862 | (FIFO Timeout) */ | |
863 | ret = handle_rx_to(priv); | |
864 | break; | |
865 | case PCH_UART_IID_THRE: /* Transmitter Holding Register | |
866 | Empty */ | |
867 | if (priv->use_dma) | |
868 | ret = dma_handle_tx(priv); | |
869 | else | |
870 | ret = handle_tx(priv); | |
871 | break; | |
872 | case PCH_UART_IID_MS: /* Modem Status */ | |
873 | ret = PCH_UART_HANDLED_MS_INT; | |
874 | break; | |
875 | default: /* Never junp to this label */ | |
876 | pr_err("%s:iid=%d (%lu)\n", __func__, iid, jiffies); | |
877 | ret = -1; | |
878 | break; | |
879 | } | |
880 | handled |= (unsigned int)ret; | |
881 | } | |
882 | if (handled == 0 && iid <= 1) { | |
883 | if (priv->int_dis_flag) | |
884 | priv->int_dis_flag = 0; | |
885 | } | |
886 | ||
887 | spin_unlock_irqrestore(&priv->port.lock, flags); | |
888 | return IRQ_RETVAL(handled); | |
889 | } | |
890 | ||
891 | /* This function tests whether the transmitter fifo and shifter for the port | |
892 | described by 'port' is empty. */ | |
893 | static unsigned int pch_uart_tx_empty(struct uart_port *port) | |
894 | { | |
895 | struct eg20t_port *priv; | |
896 | int ret; | |
897 | priv = container_of(port, struct eg20t_port, port); | |
898 | if (priv->tx_empty) | |
899 | ret = TIOCSER_TEMT; | |
900 | else | |
901 | ret = 0; | |
902 | ||
903 | return ret; | |
904 | } | |
905 | ||
906 | /* Returns the current state of modem control inputs. */ | |
907 | static unsigned int pch_uart_get_mctrl(struct uart_port *port) | |
908 | { | |
909 | struct eg20t_port *priv; | |
910 | u8 modem; | |
911 | unsigned int ret = 0; | |
912 | ||
913 | priv = container_of(port, struct eg20t_port, port); | |
914 | modem = pch_uart_hal_get_modem(priv); | |
915 | ||
916 | if (modem & UART_MSR_DCD) | |
917 | ret |= TIOCM_CAR; | |
918 | ||
919 | if (modem & UART_MSR_RI) | |
920 | ret |= TIOCM_RNG; | |
921 | ||
922 | if (modem & UART_MSR_DSR) | |
923 | ret |= TIOCM_DSR; | |
924 | ||
925 | if (modem & UART_MSR_CTS) | |
926 | ret |= TIOCM_CTS; | |
927 | ||
928 | return ret; | |
929 | } | |
930 | ||
931 | static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
932 | { | |
933 | u32 mcr = 0; | |
934 | unsigned int dat; | |
935 | struct eg20t_port *priv = container_of(port, struct eg20t_port, port); | |
936 | ||
937 | if (mctrl & TIOCM_DTR) | |
938 | mcr |= UART_MCR_DTR; | |
939 | if (mctrl & TIOCM_RTS) | |
940 | mcr |= UART_MCR_RTS; | |
941 | if (mctrl & TIOCM_LOOP) | |
942 | mcr |= UART_MCR_LOOP; | |
943 | ||
944 | if (mctrl) { | |
945 | dat = pch_uart_get_mctrl(port); | |
946 | dat |= mcr; | |
947 | iowrite8(dat, priv->membase + UART_MCR); | |
948 | } | |
949 | } | |
950 | ||
951 | static void pch_uart_stop_tx(struct uart_port *port) | |
952 | { | |
953 | struct eg20t_port *priv; | |
954 | priv = container_of(port, struct eg20t_port, port); | |
955 | priv->start_tx = 0; | |
956 | priv->tx_dma_use = 0; | |
957 | } | |
958 | ||
959 | static void pch_uart_start_tx(struct uart_port *port) | |
960 | { | |
961 | struct eg20t_port *priv; | |
962 | ||
963 | priv = container_of(port, struct eg20t_port, port); | |
964 | ||
965 | if (priv->use_dma) | |
966 | if (priv->tx_dma_use) | |
967 | return; | |
968 | ||
969 | priv->start_tx = 1; | |
970 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); | |
971 | } | |
972 | ||
973 | static void pch_uart_stop_rx(struct uart_port *port) | |
974 | { | |
975 | struct eg20t_port *priv; | |
976 | priv = container_of(port, struct eg20t_port, port); | |
977 | priv->start_rx = 0; | |
978 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT); | |
979 | priv->int_dis_flag = 1; | |
980 | } | |
981 | ||
982 | /* Enable the modem status interrupts. */ | |
983 | static void pch_uart_enable_ms(struct uart_port *port) | |
984 | { | |
985 | struct eg20t_port *priv; | |
986 | priv = container_of(port, struct eg20t_port, port); | |
987 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT); | |
988 | } | |
989 | ||
990 | /* Control the transmission of a break signal. */ | |
991 | static void pch_uart_break_ctl(struct uart_port *port, int ctl) | |
992 | { | |
993 | struct eg20t_port *priv; | |
994 | unsigned long flags; | |
995 | ||
996 | priv = container_of(port, struct eg20t_port, port); | |
997 | spin_lock_irqsave(&port->lock, flags); | |
998 | pch_uart_hal_set_break(priv, ctl); | |
999 | spin_unlock_irqrestore(&port->lock, flags); | |
1000 | } | |
1001 | ||
1002 | /* Grab any interrupt resources and initialise any low level driver state. */ | |
1003 | static int pch_uart_startup(struct uart_port *port) | |
1004 | { | |
1005 | struct eg20t_port *priv; | |
1006 | int ret; | |
1007 | int fifo_size; | |
1008 | int trigger_level; | |
1009 | ||
1010 | priv = container_of(port, struct eg20t_port, port); | |
1011 | priv->tx_empty = 1; | |
1012 | port->uartclk = priv->base_baud; | |
1013 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); | |
1014 | ret = pch_uart_hal_set_line(priv, default_baud, | |
1015 | PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT, | |
1016 | PCH_UART_HAL_STB1); | |
1017 | if (ret) | |
1018 | return ret; | |
1019 | ||
1020 | switch (priv->fifo_size) { | |
1021 | case 256: | |
1022 | fifo_size = PCH_UART_HAL_FIFO256; | |
1023 | break; | |
1024 | case 64: | |
1025 | fifo_size = PCH_UART_HAL_FIFO64; | |
1026 | break; | |
1027 | case 16: | |
1028 | fifo_size = PCH_UART_HAL_FIFO16; | |
1029 | case 1: | |
1030 | default: | |
1031 | fifo_size = PCH_UART_HAL_FIFO_DIS; | |
1032 | break; | |
1033 | } | |
1034 | ||
1035 | switch (priv->trigger) { | |
1036 | case PCH_UART_HAL_TRIGGER1: | |
1037 | trigger_level = 1; | |
1038 | break; | |
1039 | case PCH_UART_HAL_TRIGGER_L: | |
1040 | trigger_level = priv->fifo_size / 4; | |
1041 | break; | |
1042 | case PCH_UART_HAL_TRIGGER_M: | |
1043 | trigger_level = priv->fifo_size / 2; | |
1044 | break; | |
1045 | case PCH_UART_HAL_TRIGGER_H: | |
1046 | default: | |
1047 | trigger_level = priv->fifo_size - (priv->fifo_size / 8); | |
1048 | break; | |
1049 | } | |
1050 | ||
1051 | priv->trigger_level = trigger_level; | |
1052 | ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, | |
1053 | fifo_size, priv->trigger); | |
1054 | if (ret < 0) | |
1055 | return ret; | |
1056 | ||
1057 | ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED, | |
1058 | KBUILD_MODNAME, priv); | |
1059 | if (ret < 0) | |
1060 | return ret; | |
1061 | ||
1062 | if (priv->use_dma) | |
1063 | pch_request_dma(port); | |
1064 | ||
1065 | priv->start_rx = 1; | |
1066 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT); | |
1067 | uart_update_timeout(port, CS8, default_baud); | |
1068 | ||
1069 | return 0; | |
1070 | } | |
1071 | ||
1072 | static void pch_uart_shutdown(struct uart_port *port) | |
1073 | { | |
1074 | struct eg20t_port *priv; | |
1075 | int ret; | |
1076 | ||
1077 | priv = container_of(port, struct eg20t_port, port); | |
1078 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); | |
1079 | pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO); | |
1080 | ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, | |
1081 | PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1); | |
1082 | if (ret) | |
1083 | pr_err("pch_uart_hal_set_fifo Failed(ret=%d)\n", ret); | |
1084 | ||
1085 | if (priv->use_dma_flag) | |
1086 | pch_free_dma(port); | |
1087 | ||
1088 | free_irq(priv->port.irq, priv); | |
1089 | } | |
1090 | ||
1091 | /* Change the port parameters, including word length, parity, stop | |
1092 | *bits. Update read_status_mask and ignore_status_mask to indicate | |
1093 | *the types of events we are interested in receiving. */ | |
1094 | static void pch_uart_set_termios(struct uart_port *port, | |
1095 | struct ktermios *termios, struct ktermios *old) | |
1096 | { | |
1097 | int baud; | |
1098 | int rtn; | |
1099 | unsigned int parity, bits, stb; | |
1100 | struct eg20t_port *priv; | |
1101 | unsigned long flags; | |
1102 | ||
1103 | priv = container_of(port, struct eg20t_port, port); | |
1104 | switch (termios->c_cflag & CSIZE) { | |
1105 | case CS5: | |
1106 | bits = PCH_UART_HAL_5BIT; | |
1107 | break; | |
1108 | case CS6: | |
1109 | bits = PCH_UART_HAL_6BIT; | |
1110 | break; | |
1111 | case CS7: | |
1112 | bits = PCH_UART_HAL_7BIT; | |
1113 | break; | |
1114 | default: /* CS8 */ | |
1115 | bits = PCH_UART_HAL_8BIT; | |
1116 | break; | |
1117 | } | |
1118 | if (termios->c_cflag & CSTOPB) | |
1119 | stb = PCH_UART_HAL_STB2; | |
1120 | else | |
1121 | stb = PCH_UART_HAL_STB1; | |
1122 | ||
1123 | if (termios->c_cflag & PARENB) { | |
1124 | if (!(termios->c_cflag & PARODD)) | |
1125 | parity = PCH_UART_HAL_PARITY_ODD; | |
1126 | else | |
1127 | parity = PCH_UART_HAL_PARITY_EVEN; | |
1128 | ||
1129 | } else { | |
1130 | parity = PCH_UART_HAL_PARITY_NONE; | |
1131 | } | |
1132 | termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ | |
1133 | ||
1134 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); | |
1135 | ||
1136 | spin_lock_irqsave(&port->lock, flags); | |
1137 | ||
1138 | uart_update_timeout(port, termios->c_cflag, baud); | |
1139 | rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb); | |
1140 | if (rtn) | |
1141 | goto out; | |
1142 | ||
1143 | /* Don't rewrite B0 */ | |
1144 | if (tty_termios_baud_rate(termios)) | |
1145 | tty_termios_encode_baud_rate(termios, baud, baud); | |
1146 | ||
1147 | out: | |
1148 | spin_unlock_irqrestore(&port->lock, flags); | |
1149 | } | |
1150 | ||
1151 | static const char *pch_uart_type(struct uart_port *port) | |
1152 | { | |
1153 | return KBUILD_MODNAME; | |
1154 | } | |
1155 | ||
1156 | static void pch_uart_release_port(struct uart_port *port) | |
1157 | { | |
1158 | struct eg20t_port *priv; | |
1159 | ||
1160 | priv = container_of(port, struct eg20t_port, port); | |
1161 | pci_iounmap(priv->pdev, priv->membase); | |
1162 | pci_release_regions(priv->pdev); | |
1163 | } | |
1164 | ||
1165 | static int pch_uart_request_port(struct uart_port *port) | |
1166 | { | |
1167 | struct eg20t_port *priv; | |
1168 | int ret; | |
1169 | void __iomem *membase; | |
1170 | ||
1171 | priv = container_of(port, struct eg20t_port, port); | |
1172 | ret = pci_request_regions(priv->pdev, KBUILD_MODNAME); | |
1173 | if (ret < 0) | |
1174 | return -EBUSY; | |
1175 | ||
1176 | membase = pci_iomap(priv->pdev, 1, 0); | |
1177 | if (!membase) { | |
1178 | pci_release_regions(priv->pdev); | |
1179 | return -EBUSY; | |
1180 | } | |
1181 | priv->membase = port->membase = membase; | |
1182 | ||
1183 | return 0; | |
1184 | } | |
1185 | ||
1186 | static void pch_uart_config_port(struct uart_port *port, int type) | |
1187 | { | |
1188 | struct eg20t_port *priv; | |
1189 | ||
1190 | priv = container_of(port, struct eg20t_port, port); | |
1191 | if (type & UART_CONFIG_TYPE) { | |
1192 | port->type = priv->port_type; | |
1193 | pch_uart_request_port(port); | |
1194 | } | |
1195 | } | |
1196 | ||
1197 | static int pch_uart_verify_port(struct uart_port *port, | |
1198 | struct serial_struct *serinfo) | |
1199 | { | |
1200 | struct eg20t_port *priv; | |
1201 | ||
1202 | priv = container_of(port, struct eg20t_port, port); | |
1203 | if (serinfo->flags & UPF_LOW_LATENCY) { | |
1204 | pr_info("PCH UART : Use PIO Mode (without DMA)\n"); | |
1205 | priv->use_dma = 0; | |
1206 | serinfo->flags &= ~UPF_LOW_LATENCY; | |
1207 | } else { | |
1208 | #ifndef CONFIG_PCH_DMA | |
1209 | pr_err("%s : PCH DMA is not Loaded.\n", __func__); | |
1210 | return -EOPNOTSUPP; | |
1211 | #endif | |
1212 | priv->use_dma = 1; | |
1213 | priv->use_dma_flag = 1; | |
1214 | pr_info("PCH UART : Use DMA Mode\n"); | |
1215 | } | |
1216 | ||
1217 | return 0; | |
1218 | } | |
1219 | ||
1220 | static struct uart_ops pch_uart_ops = { | |
1221 | .tx_empty = pch_uart_tx_empty, | |
1222 | .set_mctrl = pch_uart_set_mctrl, | |
1223 | .get_mctrl = pch_uart_get_mctrl, | |
1224 | .stop_tx = pch_uart_stop_tx, | |
1225 | .start_tx = pch_uart_start_tx, | |
1226 | .stop_rx = pch_uart_stop_rx, | |
1227 | .enable_ms = pch_uart_enable_ms, | |
1228 | .break_ctl = pch_uart_break_ctl, | |
1229 | .startup = pch_uart_startup, | |
1230 | .shutdown = pch_uart_shutdown, | |
1231 | .set_termios = pch_uart_set_termios, | |
1232 | /* .pm = pch_uart_pm, Not supported yet */ | |
1233 | /* .set_wake = pch_uart_set_wake, Not supported yet */ | |
1234 | .type = pch_uart_type, | |
1235 | .release_port = pch_uart_release_port, | |
1236 | .request_port = pch_uart_request_port, | |
1237 | .config_port = pch_uart_config_port, | |
1238 | .verify_port = pch_uart_verify_port | |
1239 | }; | |
1240 | ||
1241 | static struct uart_driver pch_uart_driver = { | |
1242 | .owner = THIS_MODULE, | |
1243 | .driver_name = KBUILD_MODNAME, | |
1244 | .dev_name = PCH_UART_DRIVER_DEVICE, | |
1245 | .major = 0, | |
1246 | .minor = 0, | |
1247 | .nr = PCH_UART_NR, | |
1248 | }; | |
1249 | ||
1250 | static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev, | |
1251 | int port_type) | |
1252 | { | |
1253 | struct eg20t_port *priv; | |
1254 | int ret; | |
1255 | unsigned int iobase; | |
1256 | unsigned int mapbase; | |
1257 | unsigned int rxbuf; | |
1258 | int fifosize, base_baud; | |
1259 | static int num; | |
1260 | ||
1261 | priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL); | |
1262 | if (priv == NULL) | |
1263 | goto init_port_alloc_err; | |
1264 | ||
1265 | rxbuf = __get_free_page(GFP_KERNEL); | |
1266 | if (!rxbuf) | |
1267 | goto init_port_free_txbuf; | |
1268 | ||
1269 | switch (port_type) { | |
1270 | case PORT_UNKNOWN: | |
1271 | fifosize = 256; /* UART0 */ | |
1272 | base_baud = 1843200; /* 1.8432MHz */ | |
1273 | break; | |
1274 | case PORT_8250: | |
1275 | fifosize = 64; /* UART1~3 */ | |
1276 | base_baud = 1843200; /* 1.8432MHz */ | |
1277 | break; | |
1278 | default: | |
1279 | dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type); | |
1280 | goto init_port_hal_free; | |
1281 | } | |
1282 | ||
1283 | iobase = pci_resource_start(pdev, 0); | |
1284 | mapbase = pci_resource_start(pdev, 1); | |
1285 | priv->mapbase = mapbase; | |
1286 | priv->iobase = iobase; | |
1287 | priv->pdev = pdev; | |
1288 | priv->tx_empty = 1; | |
1289 | priv->rxbuf.buf = (unsigned char *)rxbuf; | |
1290 | priv->rxbuf.size = PAGE_SIZE; | |
1291 | ||
1292 | priv->fifo_size = fifosize; | |
1293 | priv->base_baud = base_baud; | |
1294 | priv->port_type = PORT_MAX_8250 + port_type + 1; | |
1295 | priv->port.dev = &pdev->dev; | |
1296 | priv->port.iobase = iobase; | |
1297 | priv->port.membase = NULL; | |
1298 | priv->port.mapbase = mapbase; | |
1299 | priv->port.irq = pdev->irq; | |
1300 | priv->port.iotype = UPIO_PORT; | |
1301 | priv->port.ops = &pch_uart_ops; | |
1302 | priv->port.flags = UPF_BOOT_AUTOCONF; | |
1303 | priv->port.fifosize = fifosize; | |
1304 | priv->port.line = num++; | |
1305 | priv->trigger = PCH_UART_HAL_TRIGGER_M; | |
1306 | ||
1307 | pci_set_drvdata(pdev, priv); | |
1308 | pch_uart_hal_request(pdev, fifosize, base_baud); | |
1309 | ret = uart_add_one_port(&pch_uart_driver, &priv->port); | |
1310 | if (ret < 0) | |
1311 | goto init_port_hal_free; | |
1312 | ||
1313 | return priv; | |
1314 | ||
1315 | init_port_hal_free: | |
1316 | free_page(rxbuf); | |
1317 | init_port_free_txbuf: | |
1318 | kfree(priv); | |
1319 | init_port_alloc_err: | |
1320 | ||
1321 | return NULL; | |
1322 | } | |
1323 | ||
1324 | static void pch_uart_exit_port(struct eg20t_port *priv) | |
1325 | { | |
1326 | uart_remove_one_port(&pch_uart_driver, &priv->port); | |
1327 | pci_set_drvdata(priv->pdev, NULL); | |
1328 | free_page((unsigned int)priv->rxbuf.buf); | |
1329 | } | |
1330 | ||
1331 | static void pch_uart_pci_remove(struct pci_dev *pdev) | |
1332 | { | |
1333 | struct eg20t_port *priv; | |
1334 | ||
1335 | priv = (struct eg20t_port *)pci_get_drvdata(pdev); | |
1336 | pch_uart_exit_port(priv); | |
1337 | pci_disable_device(pdev); | |
1338 | kfree(priv); | |
1339 | return; | |
1340 | } | |
1341 | #ifdef CONFIG_PM | |
1342 | static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state) | |
1343 | { | |
1344 | struct eg20t_port *priv = pci_get_drvdata(pdev); | |
1345 | ||
1346 | uart_suspend_port(&pch_uart_driver, &priv->port); | |
1347 | ||
1348 | pci_save_state(pdev); | |
1349 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
1350 | return 0; | |
1351 | } | |
1352 | ||
1353 | static int pch_uart_pci_resume(struct pci_dev *pdev) | |
1354 | { | |
1355 | struct eg20t_port *priv = pci_get_drvdata(pdev); | |
1356 | int ret; | |
1357 | ||
1358 | pci_set_power_state(pdev, PCI_D0); | |
1359 | pci_restore_state(pdev); | |
1360 | ||
1361 | ret = pci_enable_device(pdev); | |
1362 | if (ret) { | |
1363 | dev_err(&pdev->dev, | |
1364 | "%s-pci_enable_device failed(ret=%d) ", __func__, ret); | |
1365 | return ret; | |
1366 | } | |
1367 | ||
1368 | uart_resume_port(&pch_uart_driver, &priv->port); | |
1369 | ||
1370 | return 0; | |
1371 | } | |
1372 | #else | |
1373 | #define pch_uart_pci_suspend NULL | |
1374 | #define pch_uart_pci_resume NULL | |
1375 | #endif | |
1376 | ||
1377 | static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = { | |
1378 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811), | |
1379 | .driver_data = PCH_UART_8LINE}, | |
1380 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812), | |
1381 | .driver_data = PCH_UART_2LINE}, | |
1382 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813), | |
1383 | .driver_data = PCH_UART_2LINE}, | |
1384 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814), | |
1385 | .driver_data = PCH_UART_2LINE}, | |
1386 | {0,}, | |
1387 | }; | |
1388 | ||
1389 | static int __devinit pch_uart_pci_probe(struct pci_dev *pdev, | |
1390 | const struct pci_device_id *id) | |
1391 | { | |
1392 | int ret; | |
1393 | struct eg20t_port *priv; | |
1394 | ||
1395 | ret = pci_enable_device(pdev); | |
1396 | if (ret < 0) | |
1397 | goto probe_error; | |
1398 | ||
1399 | priv = pch_uart_init_port(pdev, id->driver_data); | |
1400 | if (!priv) { | |
1401 | ret = -EBUSY; | |
1402 | goto probe_disable_device; | |
1403 | } | |
1404 | pci_set_drvdata(pdev, priv); | |
1405 | ||
1406 | return ret; | |
1407 | ||
1408 | probe_disable_device: | |
1409 | pci_disable_device(pdev); | |
1410 | probe_error: | |
1411 | return ret; | |
1412 | } | |
1413 | ||
1414 | static struct pci_driver pch_uart_pci_driver = { | |
1415 | .name = "pch_uart", | |
1416 | .id_table = pch_uart_pci_id, | |
1417 | .probe = pch_uart_pci_probe, | |
1418 | .remove = __devexit_p(pch_uart_pci_remove), | |
1419 | .suspend = pch_uart_pci_suspend, | |
1420 | .resume = pch_uart_pci_resume, | |
1421 | }; | |
1422 | ||
1423 | static int __init pch_uart_module_init(void) | |
1424 | { | |
1425 | int ret; | |
1426 | ||
1427 | /* register as UART driver */ | |
1428 | ret = uart_register_driver(&pch_uart_driver); | |
1429 | if (ret < 0) | |
1430 | return ret; | |
1431 | ||
1432 | /* register as PCI driver */ | |
1433 | ret = pci_register_driver(&pch_uart_pci_driver); | |
1434 | if (ret < 0) | |
1435 | uart_unregister_driver(&pch_uart_driver); | |
1436 | ||
1437 | return ret; | |
1438 | } | |
1439 | module_init(pch_uart_module_init); | |
1440 | ||
1441 | static void __exit pch_uart_module_exit(void) | |
1442 | { | |
1443 | pci_unregister_driver(&pch_uart_pci_driver); | |
1444 | uart_unregister_driver(&pch_uart_driver); | |
1445 | } | |
1446 | module_exit(pch_uart_module_exit); | |
1447 | ||
1448 | MODULE_LICENSE("GPL v2"); | |
1449 | MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver"); | |
1450 | module_param(default_baud, uint, S_IRUGO); |